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build/patch/u-boot/v2023.07.02/board_radxa-zero/001-HACK-fix-meson-mmc-core-phase-in-the-tuning-process.patch
2024-12-05 00:22:43 +01:00

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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: ZHANG Yuntian <95260730+RadxaYuntian@users.noreply.github.com>
Date: Mon, 21 Aug 2023 15:28:09 +0800
Subject: HACK: fix meson mmc core phase in the tuning process
This is needed to use with Samsung eMMC module.
Tested with Samsung, Foresee, and YMTC eMMC modules on Radxa Zero.
Idea taken from the following patch and comments:
https://patchwork.ozlabs.org/project/uboot/patch/20191126211206.4537-2-linux.amoon@gmail.com/
---
drivers/mmc/meson_gx_mmc.c | 5 +++--
drivers/mmc/meson_gx_mmc.h | 4 ++++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 111111111111..222222222222 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -71,10 +71,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
meson_mmc_clk |= CLK_CO_PHASE_270;
else
- meson_mmc_clk |= CLK_CO_PHASE_180;
+ meson_mmc_clk |= CLK_CO_PHASE_090;
- /* 180 phase tx clock */
+ /* 000 phase tx & rx clock */
meson_mmc_clk |= CLK_TX_PHASE_000;
+ meson_mmc_clk |= CLK_RX_PHASE_000;
/* clock settings */
meson_mmc_clk |= clk_src;
diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h
index 111111111111..222222222222 100644
--- a/drivers/mmc/meson_gx_mmc.h
+++ b/drivers/mmc/meson_gx_mmc.h
@@ -33,6 +33,10 @@ enum meson_gx_mmc_compatible {
#define CLK_TX_PHASE_090 (1 << 10)
#define CLK_TX_PHASE_180 (2 << 10)
#define CLK_TX_PHASE_270 (3 << 10)
+#define CLK_RX_PHASE_000 (0 << 12)
+#define CLK_RX_PHASE_090 (1 << 12)
+#define CLK_RX_PHASE_180 (2 << 12)
+#define CLK_RX_PHASE_270 (3 << 12)
#define CLK_ALWAYS_ON BIT(24)
#define MESON_SD_EMMC_CFG 0x44
--
Armbian