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Move OPi5 Plus uboot to Radxa git tree

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This commit is contained in:
Muhammed Efe Cetin
2024-07-03 16:38:43 +03:00
committed by Igor
parent 35f6fd3238
commit ee62433116
3 changed files with 546 additions and 15 deletions
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255
patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/orangepi-5-plus-rk3588_defconfig Normal file
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CONFIG_ARM=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_ROCKCHIP_USB_BOOT=y
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_ROCKCHIP_HWID_DTB=y
CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_NEW_IDB=y
CONFIG_LOADER_INI="RK3588MINIALL.ini"
CONFIG_TRUST_INI="RK3588TRUST.ini"
CONFIG_PSTORE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RK3588=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rk3588-orangepi-5-plus"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_HW_CRYPTO=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_FIT_HW_CRYPTO=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_AVB=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
CONFIG_SPL_MMC_WRITE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ATF=y
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
CONFIG_FASTBOOT_BUF_SIZE=0x07000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_BOOT_ANDROID=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTP_BOOTM=y
CONFIG_CMD_TFTP_FLASH=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_MTD_BLK=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
# CONFIG_NET_TFTP_VARS is not set
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SARADC_ROCKCHIP is not set
CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_SCMI=y
CONFIG_SPL_CLK_SCMI=y
CONFIG_DM_CRYPTO=y
CONFIG_SPL_DM_CRYPTO=y
CONFIG_ROCKCHIP_CRYPTO_V2=y
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_SCMI_FIRMWARE=y
CONFIG_SPL_SCMI_FIRMWARE=y
CONFIG_GPIO_HOG=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEY=y
CONFIG_RK8XX_PWRKEY=y
CONFIG_ADC_KEY=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_MISC_DECOMPRESS=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=80000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_POWER_FG_CW201X=y
CONFIG_POWER_FG_CW221X=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_SPI_RK8XX=y
CONFIG_DM_POWER_DELIVERY=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_HUSB311=y
CONFIG_TYPEC_FUSB302=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK860X=y
CONFIG_REGULATOR_RK806=y
CONFIG_CHARGER_BQ25700=y
CONFIG_CHARGER_BQ25890=y
CONFIG_CHARGER_SC8551=y
CONFIG_CHARGER_SGM41542=y
CONFIG_DM_CHARGE_DISPLAY=y
CONFIG_CHARGE_ANIMATION=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_MAXIM_MAX96745=y
CONFIG_DRM_MAXIM_MAX96752F=y
CONFIG_DRM_MAXIM_MAX96755F=y
CONFIG_DRM_PANEL_MAXIM_DESERIALIZER=y
CONFIG_DRM_ROHM_BU18XL82=y
CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
CONFIG_DRM_ROCKCHIP_DW_DP=y
CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_LIB_RAND=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_N_SIZE=0x200
CONFIG_RSA_E_SIZE=0x10
CONFIG_RSA_C_SIZE=0x20
CONFIG_XBC=y
CONFIG_LZ4=y
CONFIG_LZMA=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
CONFIG_AVB_LIBAVB=y
CONFIG_AVB_LIBAVB_AB=y
CONFIG_AVB_LIBAVB_ATX=y
CONFIG_AVB_LIBAVB_USER=y
CONFIG_RK_AVB_LIBAVB_USER=y
CONFIG_CMD_SETEXPR=y
CONFIG_AHCI=y
CONFIG_CMD_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_DWC_AHCI=y
CONFIG_LIBATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SCSI=y
CONFIG_MTD_BLK_U_BOOT_OFFS=0x400
CONFIG_OPTEE_CLIENT=y
CONFIG_OPTEE_V2=y

290
patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588-orangepi-5-plus.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd
*
*/
/dts-v1/;
#include "rk3588.dtsi"
#include "rk3588-u-boot.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Orange Pi 5 Plus";
compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
button-maskrom {
label = "Mask Rom";
linux,code = <KEY_SETUP>;
press-threshold-microvolt = <2000>;
};
};
adc-keys-1 {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <2000>;
};
};
vcc5v0_sys: vcc5v0-sys {
u-boot,dm-pre-reloc;
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator {
u-boot,dm-pre-reloc;
compatible = "regulator-fixed";
gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_pcie_eth";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <50000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_wf: vcc3v3-wf-regulator {
u-boot,dm-pre-reloc;
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc3v3_wf";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <50000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
u-boot,dm-pre-reloc;
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc3v3_pcie30";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <5000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb20: vcc5v0-usb20-regulator {
u-boot,dm-pre-reloc;
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb20_en>;
regulator-name = "vcc5v0_usb20";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vbus5v0_typec: vbus5v0-typec-regulator {
u-boot,dm-pre-reloc;
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
regulator-name = "vbus5v0_typec";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy0_ps {
u-boot,dm-pre-reloc;
status = "okay";
};
&combphy1_ps {
u-boot,dm-pre-reloc;
status = "okay";
};
&combphy2_psu {
u-boot,dm-pre-reloc;
status = "okay";
};
/* phy1 - M.KEY socket */
&pcie2x1l0 {
u-boot,dm-pre-reloc;
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_wf>;
status = "okay";
};
/* phy2 - right ethernet port */
&pcie2x1l1 {
u-boot,dm-pre-reloc;
reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie_eth>;
status = "okay";
};
/* phy0 - left ethernet port */
&pcie2x1l2 {
u-boot,dm-pre-reloc;
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie_eth>;
status = "okay";
};
&pcie30phy {
u-boot,dm-pre-reloc;
status = "okay";
};
&pcie3x4 {
u-boot,dm-pre-reloc;
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
status = "okay";
};
&u2phy0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&u2phy0_otg {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb2phy0_grf {
u-boot,dm-pre-reloc;
status = "okay";
};
&u2phy1 {
u-boot,dm-pre-reloc;
status = "okay";
};
&u2phy1_otg {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb2phy1_grf {
u-boot,dm-pre-reloc;
status = "okay";
};
&u2phy2 {
u-boot,dm-pre-reloc;
status = "okay";
};
&u2phy2_host {
u-boot,dm-pre-reloc;
phy-supply = <&vcc5v0_usb20>;
status = "okay";
};
&usb2phy2_grf {
u-boot,dm-pre-reloc;
status = "okay";
};
&u2phy3 {
u-boot,dm-pre-reloc;
status = "okay";
};
&u2phy3_host {
u-boot,dm-pre-reloc;
phy-supply = <&vcc5v0_usb20>;
status = "okay";
};
&usb2phy3_grf {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb_host0_ehci {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb_host0_ohci {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb_host1_ehci {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb_host1_ohci {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd3_0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd_dwc3_0 {
u-boot,dm-pre-reloc;
dr_mode = "host";
status = "okay";
};
&usbdrd3_1 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd_dwc3_1 {
u-boot,dm-pre-reloc;
dr_mode = "host";
status = "okay";
};
&pinctrl {
usb {
u-boot,dm-pre-reloc;
typec5v_pwren: typec5v-pwren {
u-boot,dm-pre-reloc;
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
usbc0_int: usbc0-int {
u-boot,dm-pre-reloc;
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
vcc5v0_usb20_en: vcc5v0-usb20-en {
u-boot,dm-pre-reloc;
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};