JDM170/build
1
0
Fork 0
mirror of https://github.com/armbian/build synced 2025-09-24 19:47:06 +07:00
Code Issues Packages Projects Releases Wiki Activity

BananaPi BPI-F3: Update u-boot and linux patching

Browse Source 
Signed-off-by: Patrick Yavitz <pyavitz@gmail.com>
This commit is contained in:
Patrick Yavitz
2024-12-26 10:50:34 -05:00
committed by c0rnelius
parent 7b6fcab372
commit df9ddaf44e
91 changed files with 337 additions and 477249 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6923
patch/atf/atf-spacemit/001-Update-for-v1.0alpha2.patch
View File

File diff suppressed because it is too large Load Diff

1201
patch/atf/atf-spacemit/002-Update-for-v1.0beta3.1.patch
View File

File diff suppressed because it is too large Load Diff

331
patch/atf/atf-spacemit/003-Update-for-v1.0rc1.patch
View File

@@ -1,331 +0,0 @@
From 41a15ab971400502e93bbbf0d7336fa81daf25c9 Mon Sep 17 00:00:00 2001
From: James Deng <james.deng@spacemit.com>
Date: Tue, 30 Apr 2024 17:48:07 +0800
Subject: Update for v1.0rc1
---
include/sbi_utils/cache/cacheflush.h | 34 +++++++++-----
lib/sbi/sbi_hsm.c | 2 +-
lib/utils/psci/psci_private.h | 2 +-
.../spacemit/plat/k1x/underly_implement.c | 37 ---------------
lib/utils/psci/spacemit/plat/plat_pm.c | 4 +-
.../generic/include/spacemit/k1x/k1x_evb.h | 44 ++++++++++++++++-
.../generic/include/spacemit/k1x/k1x_fpga.h | 47 +++++++++++++++++--
platform/generic/spacemit/spacemit_k1.c | 13 +++++
8 files changed, 126 insertions(+), 57 deletions(-)
diff --git a/include/sbi_utils/cache/cacheflush.h b/include/sbi_utils/cache/cacheflush.h
index c3e353229f75..126931b25888 100644
--- a/include/sbi_utils/cache/cacheflush.h
+++ b/include/sbi_utils/cache/cacheflush.h
@@ -167,26 +167,34 @@ static inline void __mdelay(void)
cpu_relax();
}
-static inline void csi_flush_l2_cache(void)
+static inline void csi_flush_l2_cache(bool hw)
{
unsigned int hartid = current_hartid();
uintptr_t *cr =(MPIDR_AFFLVL1_VAL(hartid) == 0) ? (uintptr_t *)CLUSTER0_L2_CACHE_FLUSH_REG_BASE :
(uintptr_t *)CLUSTER1_L2_CACHE_FLUSH_REG_BASE;
- /* flush l2 cache */
- writel(readl(cr) | (1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
- /* k1pro */
- if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
- while (readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET));
- else /* k1x */ {
- /* clear the request */
- while (1) {
- if ((readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET)) == 0)
- break;
- __mdelay();
+ if (!hw) {
+ writel(0x0, cr);
+ /* flush l2 cache */
+ writel(readl(cr) | (1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
+ /* k1pro */
+ if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
+ while (readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET));
+ else /* k1x */ {
+ /* clear the request */
+ while (1) {
+ if ((readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET)) == 0)
+ break;
+ __mdelay();
+ }
+ writel(readl(cr) & ~(1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
}
- writel(readl(cr) & ~(1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
+ } else {
+ /* k1pro */
+ if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
+ return /* do nothing */;
+ writel((1 << L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET) | (1 << L2_CACHE_FLUSH_HW_EN_BIT_OFFSET), cr);
}
}
#endif
diff --git a/lib/sbi/sbi_hsm.c b/lib/sbi/sbi_hsm.c
index acd3c9e04c87..51c982ad7b78 100644
--- a/lib/sbi/sbi_hsm.c
+++ b/lib/sbi/sbi_hsm.c
@@ -183,7 +183,7 @@ void __noreturn sbi_hsm_hart_start_finish(struct sbi_scratch *scratch,
* */
if (cool_boot) {
csi_flush_dcache_all();
- csi_flush_l2_cache();
+ csi_flush_l2_cache(0);
}
sbi_hart_switch_mode(hartid, next_arg1, next_addr, next_mode, false);
diff --git a/lib/utils/psci/psci_private.h b/lib/utils/psci/psci_private.h
index c768d3f379ab..0a3f260f5c39 100644
--- a/lib/utils/psci/psci_private.h
+++ b/lib/utils/psci/psci_private.h
@@ -182,7 +182,7 @@ static inline void psci_do_pwrdown_cache_maintenance(int hartid, uintptr_t scrat
/* disable the tcm */
csr_write(CSR_TCMCFG, 0);
#endif
- csi_flush_l2_cache();
+ csi_flush_l2_cache(0);
}
/* disable dcache */
diff --git a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
index 279e6d5dc741..73feec440d27 100644
--- a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+++ b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
@@ -5,43 +5,6 @@
#include <sbi/sbi_console.h>
#include <spacemit/spacemit_config.h>
-#define C1_CPU_RESET_BASE_ADDR (0xD4282B24)
-
-#define PMU_CAP_CORE0_IDLE_CFG (0xd4282924)
-#define PMU_CAP_CORE1_IDLE_CFG (0xd4282928)
-#define PMU_CAP_CORE2_IDLE_CFG (0xd4282960)
-#define PMU_CAP_CORE3_IDLE_CFG (0xd4282964)
-#define PMU_CAP_CORE4_IDLE_CFG (0xd4282b04)
-#define PMU_CAP_CORE5_IDLE_CFG (0xd4282b08)
-#define PMU_CAP_CORE6_IDLE_CFG (0xd4282b0c)
-#define PMU_CAP_CORE7_IDLE_CFG (0xd4282b10)
-
-#define PMU_C0_CAPMP_IDLE_CFG0 (0xd4282920)
-#define PMU_C0_CAPMP_IDLE_CFG1 (0xd42828e4)
-#define PMU_C0_CAPMP_IDLE_CFG2 (0xd4282950)
-#define PMU_C0_CAPMP_IDLE_CFG3 (0xd4282954)
-#define PMU_C1_CAPMP_IDLE_CFG0 (0xd4282b14)
-#define PMU_C1_CAPMP_IDLE_CFG1 (0xd4282b18)
-#define PMU_C1_CAPMP_IDLE_CFG2 (0xd4282b1c)
-#define PMU_C1_CAPMP_IDLE_CFG3 (0xd4282b20)
-
-#define PMU_ACPR_CLUSTER0_REG (0xd4051090)
-#define PMU_ACPR_CLUSTER1_REG (0xd4051094)
-#define PMU_ACPR_UNKONW_REG (0xd4050038)
-
-
-#define CPU_PWR_DOWN_VALUE (0x3)
-#define CLUSTER_PWR_DOWN_VALUE (0x3)
-#define CLUSTER_AXISDO_OFFSET (31)
-#define CLUSTER_DDRSD_OFFSET (27)
-#define CLUSTER_APBSD_OFFSET (26)
-#define CLUSTER_VCXOSD_OFFSET (19)
-#define CLUSTER_BIT29_OFFSET (29)
-#define CLUSTER_BIT14_OFFSET (14)
-#define CLUSTER_BIT30_OFFSET (30)
-#define CLUSTER_BIT25_OFFSET (25)
-#define CLUSTER_BIT13_OFFSET (13)
-
struct pmu_cap_wakeup {
unsigned int pmu_cap_core0_wakeup;
unsigned int pmu_cap_core1_wakeup;
diff --git a/lib/utils/psci/spacemit/plat/plat_pm.c b/lib/utils/psci/spacemit/plat/plat_pm.c
index da6f958157fa..a5b91270834f 100644
--- a/lib/utils/psci/spacemit/plat/plat_pm.c
+++ b/lib/utils/psci/spacemit/plat/plat_pm.c
@@ -7,6 +7,7 @@
#include <sbi/sbi_console.h>
#include <sbi_utils/psci/plat/arm/common/arm_def.h>
#include <sbi_utils/irqchip/fdt_irqchip_plic.h>
+#include <sbi_utils/cache/cacheflush.h>
#include "underly_implement.h"
#define CORE_PWR_STATE(state) \
@@ -81,6 +82,7 @@ static void spacemit_pwr_domain_off(const psci_power_state_t *target_state)
#endif
cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(hartid));
spacemit_cluster_off(hartid);
+ csi_flush_l2_cache(1);
}
if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
@@ -180,8 +182,8 @@ static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
csr_write(CSR_TCMCFG, 0);
#endif
cci_disable_snoop_dvm_reqs(clusterid);
-
spacemit_cluster_off(hartid);
+ csi_flush_l2_cache(1);
}
if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
diff --git a/platform/generic/include/spacemit/k1x/k1x_evb.h b/platform/generic/include/spacemit/k1x/k1x_evb.h
index b951105e0c04..5f5b672a61a6 100644
--- a/platform/generic/include/spacemit/k1x/k1x_evb.h
+++ b/platform/generic/include/spacemit/k1x/k1x_evb.h
@@ -24,6 +24,45 @@
#define C1_RVBADDR_LO_ADDR (0xD4282C00 + 0x2B0)
#define C1_RVBADDR_HI_ADDR (0xD4282C00 + 0X2B4)
+#define C1_CPU_RESET_BASE_ADDR (0xD4282B24)
+
+#define PMU_CAP_CORE0_IDLE_CFG (0xd4282924)
+#define PMU_CAP_CORE1_IDLE_CFG (0xd4282928)
+#define PMU_CAP_CORE2_IDLE_CFG (0xd4282960)
+#define PMU_CAP_CORE3_IDLE_CFG (0xd4282964)
+#define PMU_CAP_CORE4_IDLE_CFG (0xd4282b04)
+#define PMU_CAP_CORE5_IDLE_CFG (0xd4282b08)
+#define PMU_CAP_CORE6_IDLE_CFG (0xd4282b0c)
+#define PMU_CAP_CORE7_IDLE_CFG (0xd4282b10)
+
+#define PMU_C0_CAPMP_IDLE_CFG0 (0xd4282920)
+#define PMU_C0_CAPMP_IDLE_CFG1 (0xd42828e4)
+#define PMU_C0_CAPMP_IDLE_CFG2 (0xd4282950)
+#define PMU_C0_CAPMP_IDLE_CFG3 (0xd4282954)
+#define PMU_C1_CAPMP_IDLE_CFG0 (0xd4282b14)
+#define PMU_C1_CAPMP_IDLE_CFG1 (0xd4282b18)
+#define PMU_C1_CAPMP_IDLE_CFG2 (0xd4282b1c)
+#define PMU_C1_CAPMP_IDLE_CFG3 (0xd4282b20)
+
+#define PMU_ACPR_CLUSTER0_REG (0xd4051090)
+#define PMU_ACPR_CLUSTER1_REG (0xd4051094)
+#define PMU_ACPR_UNKONW_REG (0xd4050038)
+
+
+#define CPU_PWR_DOWN_VALUE (0x3)
+#define CLUSTER_PWR_DOWN_VALUE (0x3)
+#define CLUSTER_AXISDO_OFFSET (31)
+#define CLUSTER_DDRSD_OFFSET (27)
+#define CLUSTER_APBSD_OFFSET (26)
+#define CLUSTER_VCXOSD_OFFSET (19)
+#define CLUSTER_BIT29_OFFSET (29)
+#define CLUSTER_BIT14_OFFSET (14)
+#define CLUSTER_BIT30_OFFSET (30)
+#define CLUSTER_BIT25_OFFSET (25)
+#define CLUSTER_BIT13_OFFSET (13)
+
+#define L2_HARDWARE_CACHE_FLUSH_EN (13)
+
/***************************mailbox***************************/
#define SCMI_MAILBOX_SHARE_MEM (0x2f902080)
#define PLAT_MAILBOX_REG_BASE (0x2f824000)
@@ -66,7 +105,10 @@
#define CLUSTER0_L2_CACHE_FLUSH_REG_BASE (0xD84401B0)
#define CLUSTER1_L2_CACHE_FLUSH_REG_BASE (0xD84401B4)
-#define L2_CACHE_FLUSH_REQUEST_BIT_OFFSET (0x1)
+#define L2_CACHE_FLUSH_REQUEST_BIT_OFFSET (0x1) /* sw flush l2 cache */
#define L2_CACHE_FLUSH_DONE_BIT_OFFSET (0x3)
+#define L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET (0)
+#define L2_CACHE_FLUSH_HW_EN_BIT_OFFSET (0x2)
+
#endif /* __K1X_EVB_CONFIG_H__ */
diff --git a/platform/generic/include/spacemit/k1x/k1x_fpga.h b/platform/generic/include/spacemit/k1x/k1x_fpga.h
index 4748c86b69c2..3d8964c861c4 100644
--- a/platform/generic/include/spacemit/k1x/k1x_fpga.h
+++ b/platform/generic/include/spacemit/k1x/k1x_fpga.h
@@ -24,13 +24,51 @@
#define C1_RVBADDR_LO_ADDR (0xD4282C00 + 0x2B0)
#define C1_RVBADDR_HI_ADDR (0xD4282C00 + 0X2B4)
+#define C1_CPU_RESET_BASE_ADDR (0xD4282B24)
+
+#define PMU_CAP_CORE0_IDLE_CFG (0xd4282924)
+#define PMU_CAP_CORE1_IDLE_CFG (0xd4282928)
+#define PMU_CAP_CORE2_IDLE_CFG (0xd4282960)
+#define PMU_CAP_CORE3_IDLE_CFG (0xd4282964)
+#define PMU_CAP_CORE4_IDLE_CFG (0xd4282b04)
+#define PMU_CAP_CORE5_IDLE_CFG (0xd4282b08)
+#define PMU_CAP_CORE6_IDLE_CFG (0xd4282b0c)
+#define PMU_CAP_CORE7_IDLE_CFG (0xd4282b10)
+
+#define PMU_C0_CAPMP_IDLE_CFG0 (0xd4282920)
+#define PMU_C0_CAPMP_IDLE_CFG1 (0xd42828e4)
+#define PMU_C0_CAPMP_IDLE_CFG2 (0xd4282950)
+#define PMU_C0_CAPMP_IDLE_CFG3 (0xd4282954)
+#define PMU_C1_CAPMP_IDLE_CFG0 (0xd4282b14)
+#define PMU_C1_CAPMP_IDLE_CFG1 (0xd4282b18)
+#define PMU_C1_CAPMP_IDLE_CFG2 (0xd4282b1c)
+#define PMU_C1_CAPMP_IDLE_CFG3 (0xd4282b20)
+
+#define PMU_ACPR_CLUSTER0_REG (0xd4051090)
+#define PMU_ACPR_CLUSTER1_REG (0xd4051094)
+#define PMU_ACPR_UNKONW_REG (0xd4050038)
+
+
+#define CPU_PWR_DOWN_VALUE (0x3)
+#define CLUSTER_PWR_DOWN_VALUE (0x3)
+#define CLUSTER_AXISDO_OFFSET (31)
+#define CLUSTER_DDRSD_OFFSET (27)
+#define CLUSTER_APBSD_OFFSET (26)
+#define CLUSTER_VCXOSD_OFFSET (19)
+#define CLUSTER_BIT29_OFFSET (29)
+#define CLUSTER_BIT14_OFFSET (14)
+#define CLUSTER_BIT30_OFFSET (30)
+#define CLUSTER_BIT25_OFFSET (25)
+#define CLUSTER_BIT13_OFFSET (13)
+
+#define L2_HARDWARE_CACHE_FLUSH_EN (13)
+
/***************************mailbox***************************/
#define SCMI_MAILBOX_SHARE_MEM (0x2f902080)
#define PLAT_MAILBOX_REG_BASE (0x2f824000)
/****************************scmi*****************************/
-#define PLAT_SCMI_SINGLE_CLUSTER_DOMAIN_MAP {0, 1, 2, 3}
-#define PLAT_SCMI_DOUBLE_CLUSTER_DOMAIN_MAP {0, 1, 4, 5}
+#define PLAT_SCMI_DOMAIN_MAP {0, 1, 2, 3}
/*************************cpu topology************************/
#define ARM_SYSTEM_COUNT (1U)
@@ -67,7 +105,10 @@
#define CLUSTER0_L2_CACHE_FLUSH_REG_BASE (0xD84401B0)
#define CLUSTER1_L2_CACHE_FLUSH_REG_BASE (0xD84401B4)
-#define L2_CACHE_FLUSH_REQUEST_BIT_OFFSET (0x1)
+#define L2_CACHE_FLUSH_REQUEST_BIT_OFFSET (0x1) /* sw flush l2 cache */
#define L2_CACHE_FLUSH_DONE_BIT_OFFSET (0x3)
+#define L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET (0)
+#define L2_CACHE_FLUSH_HW_EN_BIT_OFFSET (0x2)
+
#endif /* __K1X_FPGA_CONFIG_H__ */
diff --git a/platform/generic/spacemit/spacemit_k1.c b/platform/generic/spacemit/spacemit_k1.c
index 38794c2dfbb5..95218846715f 100644
--- a/platform/generic/spacemit/spacemit_k1.c
+++ b/platform/generic/spacemit/spacemit_k1.c
@@ -65,6 +65,19 @@ static void wakeup_other_core(void)
unsigned char *cpu_topology = plat_get_power_domain_tree_desc();
#endif
+#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
+ /* enable the hw l2 cache flush method for each core */
+ writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG0);
+ writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG1);
+ writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG2);
+ writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG3);
+
+ writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG0);
+ writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG1);
+ writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG2);
+ writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG3);
+#endif
+
// hart0 is already boot up
for (i = 0; i < platform.hart_count; i++) {
hartid = platform.hart_index2id[i];
--
2.35.3

42
patch/atf/atf-spacemit/004-Update-for-v1.0.patch
View File

@@ -1,42 +0,0 @@
From ce6e8eec55a62d9e4cb5f5a767e50e9d0c2659ff Mon Sep 17 00:00:00 2001
From: James Deng <james.deng@spacemit.com>
Date: Thu, 30 May 2024 23:19:43 +0800
Subject: Update for v1.0
---
debian/opensbi-spacemit.postinst | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/debian/opensbi-spacemit.postinst b/debian/opensbi-spacemit.postinst
index 1f6feca80674..9ce082ef548b 100755
--- a/debian/opensbi-spacemit.postinst
+++ b/debian/opensbi-spacemit.postinst
@@ -22,9 +22,16 @@ configure)
case $ROOT in
"/dev/mmcblk0"*)
OPENSBI=/dev/mmcblk0p3
+ OPENSBI_SEEK=0
;;
"/dev/mmcblk2"*)
OPENSBI=/dev/mmcblk2p3
+ OPENSBI_SEEK=0
+ ;;
+ "/dev/nvme0n1"*)
+ OPENSBI=/dev/mtdblock0
+ # 以KB为单位
+ OPENSBI_SEEK=448
;;
*)
echo "Unsupported root=$ROOT"
@@ -37,7 +44,7 @@ configure)
fi
if [ -n "$target" ] && [ -e $OPENSBI ]; then
- dd if=/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.itb of=$OPENSBI bs=1 && sync
+ dd if=/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.itb of=$OPENSBI seek=$OPENSBI_SEEK bs=1K && sync
fi
;;
esac
--
2.35.3

86
patch/atf/atf-spacemit/005-Update-for-v1.0.3.patch
View File

@@ -1,86 +0,0 @@
From 6f1344573d4ce0638d24d960e9a7d5ff1b0426b6 Mon Sep 17 00:00:00 2001
From: James Deng <james.deng@spacemit.com>
Date: Wed, 19 Jun 2024 15:18:09 +0800
Subject: Update for v1.0.3
---
.../spacemit/plat/k1x/underly_implement.c | 24 ++++++++++++++++++-
.../generic/include/spacemit/k1x/k1x_evb.h | 4 ++--
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
index 73feec440d27..654da2d1a926 100644
--- a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+++ b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
@@ -44,6 +44,12 @@ void spacemit_top_on(u_register_t mpidr)
(1 << CLUSTER_BIT25_OFFSET) |
(1 << CLUSTER_BIT13_OFFSET));
writel(value, cluster1_acpr);
+
+ /* enable the gpio edge detected function again
+ * */
+ value = readl((unsigned int *)0xd4051000);
+ value &= ~(1 << 21);
+ writel(value, (unsigned int *)0xd4051000);
}
/* D1P & D2 ? */
@@ -60,6 +66,7 @@ void spacemit_top_off(u_register_t mpidr)
(1 << CLUSTER_DDRSD_OFFSET) |
(1 << CLUSTER_APBSD_OFFSET) |
(1 << CLUSTER_VCXOSD_OFFSET) |
+ (1 << 3) |
(1 << CLUSTER_BIT29_OFFSET) |
(1 << CLUSTER_BIT14_OFFSET) |
(1 << CLUSTER_BIT30_OFFSET) |
@@ -72,6 +79,7 @@ void spacemit_top_off(u_register_t mpidr)
(1 << CLUSTER_DDRSD_OFFSET) |
(1 << CLUSTER_APBSD_OFFSET) |
(1 << CLUSTER_VCXOSD_OFFSET) |
+ (1 << 3) |
(1 << CLUSTER_BIT29_OFFSET) |
(1 << CLUSTER_BIT14_OFFSET) |
(1 << CLUSTER_BIT30_OFFSET) |
@@ -80,9 +88,23 @@ void spacemit_top_off(u_register_t mpidr)
writel(value, cluster1_acpr);
value = readl((unsigned int *)PMU_ACPR_UNKONW_REG);
- value |= (1 << 2);
+ value |= (1 << 2) | (1 << 0);
writel(value, (unsigned int *)PMU_ACPR_UNKONW_REG);
+ /* disable the gpio edge detect function
+ * this may cause the system cann't enter D2
+ * */
+ value = readl((unsigned int *)0xd4051000);
+ value |= (1 << 21);
+ writel(value, (unsigned int *)0xd4051000);
+
+ /* enable the refbuf function which will enhance the
+ * driving capability of the internal 26M to PLL path
+ * */
+ value = readl((unsigned int *)0xd4090104);
+ value |= (1 << 22);
+ writel(value, (unsigned int *)0xd4090104);
+
/* for wakeup debug */
writel(0xffff, (unsigned int *)0xd4051030);
}
diff --git a/platform/generic/include/spacemit/k1x/k1x_evb.h b/platform/generic/include/spacemit/k1x/k1x_evb.h
index 5f5b672a61a6..10e856965618 100644
--- a/platform/generic/include/spacemit/k1x/k1x_evb.h
+++ b/platform/generic/include/spacemit/k1x/k1x_evb.h
@@ -49,8 +49,8 @@
#define PMU_ACPR_UNKONW_REG (0xd4050038)
-#define CPU_PWR_DOWN_VALUE (0x3)
-#define CLUSTER_PWR_DOWN_VALUE (0x3)
+#define CPU_PWR_DOWN_VALUE (0x1b)
+#define CLUSTER_PWR_DOWN_VALUE (0x7)
#define CLUSTER_AXISDO_OFFSET (31)
#define CLUSTER_DDRSD_OFFSET (27)
#define CLUSTER_APBSD_OFFSET (26)
--
2.35.3

94
patch/atf/atf-spacemit/006-Update-for-v1.0.7.patch
View File

@@ -1,94 +0,0 @@
From 94bf83cc0bd1c86e51f48174fa17e23427903c59 Mon Sep 17 00:00:00 2001
From: James Deng <james.deng@spacemit.com>
Date: Thu, 11 Jul 2024 14:56:36 +0800
Subject: Update for v1.0.7
---
debian/opensbi-spacemit.postinst | 24 ++++++++++++++-----
.../spacemit/plat/k1x/underly_implement.c | 13 ----------
2 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/debian/opensbi-spacemit.postinst b/debian/opensbi-spacemit.postinst
index 9ce082ef548b..dce7154ac8f4 100755
--- a/debian/opensbi-spacemit.postinst
+++ b/debian/opensbi-spacemit.postinst
@@ -4,9 +4,11 @@ set -e
case "$1" in
configure)
target=""
- if grep -q '^spacemit' /sys/firmware/devicetree/base/model; then
+ if grep -q '^spacemit' /sys/firmware/devicetree/base/model || grep -q '^spacemit' /sys/devices/soc0/family; then
target="spacemit"
else
+ echo "Neither /sys/firmware/devicetree/base/model nor /sys/devices/soc0/family starts with 'spacemit'."
+ echo "This may indicate that you are installing this package in a chroot environment."
exit 0
fi
@@ -35,17 +37,27 @@ configure)
;;
*)
echo "Unsupported root=$ROOT"
- exit 0
+ exit 1
;;
esac
else
echo "Missing root= in cmdline"
- exit 0
+ exit 1
fi
- if [ -n "$target" ] && [ -e $OPENSBI ]; then
- dd if=/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.itb of=$OPENSBI seek=$OPENSBI_SEEK bs=1K && sync
- fi
+ # 待检查文件/分区列表
+ files="/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.itb $OPENSBI"
+ for file in $files; do
+ if [ ! -e "$file" ]; then
+ # 任意不存在则退出
+ echo "Missing $file"
+ exit 1
+ fi
+ done
+
+ # 此前已经做了所有检查
+ dd if=/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.itb of=$OPENSBI seek=$OPENSBI_SEEK bs=1K && sync
+
;;
esac
diff --git a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
index 654da2d1a926..94d53bf51d0f 100644
--- a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+++ b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
@@ -44,12 +44,6 @@ void spacemit_top_on(u_register_t mpidr)
(1 << CLUSTER_BIT25_OFFSET) |
(1 << CLUSTER_BIT13_OFFSET));
writel(value, cluster1_acpr);
-
- /* enable the gpio edge detected function again
- * */
- value = readl((unsigned int *)0xd4051000);
- value &= ~(1 << 21);
- writel(value, (unsigned int *)0xd4051000);
}
/* D1P & D2 ? */
@@ -91,13 +85,6 @@ void spacemit_top_off(u_register_t mpidr)
value |= (1 << 2) | (1 << 0);
writel(value, (unsigned int *)PMU_ACPR_UNKONW_REG);
- /* disable the gpio edge detect function
- * this may cause the system cann't enter D2
- * */
- value = readl((unsigned int *)0xd4051000);
- value |= (1 << 21);
- writel(value, (unsigned int *)0xd4051000);
-
/* enable the refbuf function which will enhance the
* driving capability of the internal 26M to PLL path
* */
--
2.35.3

554
patch/atf/atf-spacemit/007-Update-for-v1.0.11.patch
View File

@@ -1,554 +0,0 @@
From 1600b3620dd8babffcfcc7d780a31723c94270bc Mon Sep 17 00:00:00 2001
From: James Deng <james.deng@spacemit.com>
Date: Thu, 1 Aug 2024 22:09:26 +0800
Subject: Update for v1.0.11
---
debian/control | 1 +
debian/rules | 10 ++
include/sbi_utils/cache/cacheflush.h | 29 ++++
lib/utils/psci/psci_main.c | 8 +-
.../spacemit/plat/k1x/underly_implement.c | 86 +++++++++++-
lib/utils/psci/spacemit/plat/plat_pm.c | 131 ++++++++++++++----
.../psci/spacemit/plat/underly_implement.h | 2 +
lib/utils/serial/fdt_serial_uart8250.c | 1 +
.../generic/include/spacemit/k1x/k1x_evb.h | 1 +
platform/generic/spacemit/spacemit_k1.c | 23 +--
10 files changed, 246 insertions(+), 46 deletions(-)
diff --git a/debian/control b/debian/control
index 6c4a1747b5f3..f0f186707ea7 100644
--- a/debian/control
+++ b/debian/control
@@ -11,6 +11,7 @@ Rules-Requires-Root: no
Vcs-Browser: https://salsa.debian.org/opensbi-team/opensbi
Vcs-Git: https://salsa.debian.org/opensbi-team/opensbi.git
Homepage: https://github.com/riscv-software-src/opensbi
+XBS-Commit-Id:
Package: opensbi-spacemit
Architecture: all
diff --git a/debian/rules b/debian/rules
index ab9cc10c406c..3d44b43fcc38 100755
--- a/debian/rules
+++ b/debian/rules
@@ -10,9 +10,19 @@ else
VERBOSE=0
endif
+# 检查是否在 Git 仓库中，并获取 commit ID
+GIT_INSIDE := $(shell git rev-parse --is-inside-work-tree 2>/dev/null)
+ifeq ($(GIT_INSIDE),true)
+ COMMIT_ID := $(shell git rev-parse --short HEAD)
+endif
+
%:
dh $@
+override_dh_auto_configure:
+ sed -i "s/XBS-Commit-Id:.*/XBS-Commit-Id: $(COMMIT_ID)/" debian/control
+ dh_auto_configure
+
override_dh_auto_build:
make \
V=$(VERBOSE) \
diff --git a/include/sbi_utils/cache/cacheflush.h b/include/sbi_utils/cache/cacheflush.h
index 126931b25888..7887eef949ab 100644
--- a/include/sbi_utils/cache/cacheflush.h
+++ b/include/sbi_utils/cache/cacheflush.h
@@ -197,4 +197,33 @@ static inline void csi_flush_l2_cache(bool hw)
writel((1 << L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET) | (1 << L2_CACHE_FLUSH_HW_EN_BIT_OFFSET), cr);
}
}
+
+static inline void csi_flush_l2_cache_hart(bool hw, int hartid)
+{
+ uintptr_t *cr =(MPIDR_AFFLVL1_VAL(hartid) == 0) ? (uintptr_t *)CLUSTER0_L2_CACHE_FLUSH_REG_BASE :
+ (uintptr_t *)CLUSTER1_L2_CACHE_FLUSH_REG_BASE;
+
+ if (!hw) {
+ writel(0x0, cr);
+ /* flush l2 cache */
+ writel(readl(cr) | (1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
+ /* k1pro */
+ if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
+ while (readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET));
+ else /* k1x */ {
+ /* clear the request */
+ while (1) {
+ if ((readl(cr) & (1 << L2_CACHE_FLUSH_DONE_BIT_OFFSET)) == 0)
+ break;
+ __mdelay();
+ }
+ writel(readl(cr) & ~(1 << L2_CACHE_FLUSH_REQUEST_BIT_OFFSET), cr);
+ }
+ } else {
+ /* k1pro */
+ if (L2_CACHE_FLUSH_REQUEST_BIT_OFFSET == L2_CACHE_FLUSH_DONE_BIT_OFFSET)
+ return /* do nothing */;
+ writel((1 << L2_CACHE_FLUSH_HW_TYPE_BIT_OFFSET) | (1 << L2_CACHE_FLUSH_HW_EN_BIT_OFFSET), cr);
+ }
+}
#endif
diff --git a/lib/utils/psci/psci_main.c b/lib/utils/psci/psci_main.c
index a3ce138c00cc..e89bb4ad3f39 100644
--- a/lib/utils/psci/psci_main.c
+++ b/lib/utils/psci/psci_main.c
@@ -81,10 +81,10 @@ int psci_cpu_off(void)
* The only error cpu_off can return is E_DENIED. So check if that's
* indeed the case.
*/
- if (rc != PSCI_E_DENIED) {
- sbi_printf("%s:%d, err\n", __func__, __LINE__);
- sbi_hart_hang();
- }
+// if (rc != PSCI_E_DENIED) {
+// sbi_printf("%s:%d, err\n", __func__, __LINE__);
+// sbi_hart_hang();
+// }
return rc;
}
diff --git a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
index 94d53bf51d0f..f87bacc7297d 100644
--- a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+++ b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
@@ -30,7 +30,8 @@ void spacemit_top_on(u_register_t mpidr)
(1 << CLUSTER_BIT14_OFFSET) |
(1 << CLUSTER_BIT30_OFFSET) |
(1 << CLUSTER_BIT25_OFFSET) |
- (1 << CLUSTER_BIT13_OFFSET));
+ (1 << CLUSTER_BIT13_OFFSET) |
+ (1 << CLUSTER_VOTE_AP_SLPEN));
writel(value, cluster0_acpr);
value = readl(cluster1_acpr);
@@ -42,7 +43,8 @@ void spacemit_top_on(u_register_t mpidr)
(1 << CLUSTER_BIT14_OFFSET) |
(1 << CLUSTER_BIT30_OFFSET) |
(1 << CLUSTER_BIT25_OFFSET) |
- (1 << CLUSTER_BIT13_OFFSET));
+ (1 << CLUSTER_BIT13_OFFSET) |
+ (1 << CLUSTER_VOTE_AP_SLPEN));
writel(value, cluster1_acpr);
}
@@ -60,7 +62,7 @@ void spacemit_top_off(u_register_t mpidr)
(1 << CLUSTER_DDRSD_OFFSET) |
(1 << CLUSTER_APBSD_OFFSET) |
(1 << CLUSTER_VCXOSD_OFFSET) |
- (1 << 3) |
+ (1 << CLUSTER_VOTE_AP_SLPEN) |
(1 << CLUSTER_BIT29_OFFSET) |
(1 << CLUSTER_BIT14_OFFSET) |
(1 << CLUSTER_BIT30_OFFSET) |
@@ -73,7 +75,7 @@ void spacemit_top_off(u_register_t mpidr)
(1 << CLUSTER_DDRSD_OFFSET) |
(1 << CLUSTER_APBSD_OFFSET) |
(1 << CLUSTER_VCXOSD_OFFSET) |
- (1 << 3) |
+ (1 << CLUSTER_VOTE_AP_SLPEN) |
(1 << CLUSTER_BIT29_OFFSET) |
(1 << CLUSTER_BIT14_OFFSET) |
(1 << CLUSTER_BIT30_OFFSET) |
@@ -279,6 +281,82 @@ void spacemit_wakeup_cpu(u_register_t mpidr)
writel(1 << target_cpu_idx, cpu_reset_base);
}
+int spacemit_core_enter_c2(u_register_t mpidr)
+{
+ unsigned int value;
+
+ /* wait the cpu enter c2 */
+ value = readl((unsigned int *)0xd4282890);
+
+ if (mpidr == 0) {
+ if (value & (1 << 6))
+ return 1;
+ } else if (mpidr == 1) {
+ if (value & (1 << 9))
+ return 1;
+ } else if (mpidr == 2) {
+ if (value & (1 << 12))
+ return 1;
+ } else if (mpidr == 3) {
+ if (value & (1 << 15))
+ return 1;
+ } else if (mpidr == 4) {
+ if (value & (1 << 22))
+ return 1;
+ } else if (mpidr == 5) {
+ if (value & (1 << 25))
+ return 1;
+ } else if (mpidr == 6) {
+ if (value & (1 << 28))
+ return 1;
+ } else if (mpidr == 7) {
+ if (value & (1 << 31))
+ return 1;
+ } else {
+ return 0;
+ }
+
+ return 0;
+}
+
+void spacemit_wait_core_enter_c2(u_register_t mpidr)
+{
+ unsigned int value;
+
+ while (1) {
+ /* wait the cpu enter c2 */
+ value = readl((unsigned int *)0xd4282890);
+
+ if (mpidr == 0) {
+ if (value & (1 << 6))
+ return;
+ } else if (mpidr == 1) {
+ if (value & (1 << 9))
+ return;
+ } else if (mpidr == 2) {
+ if (value & (1 << 12))
+ return;
+ } else if (mpidr == 3) {
+ if (value & (1 << 15))
+ return;
+ } else if (mpidr == 4) {
+ if (value & (1 << 22))
+ return;
+ } else if (mpidr == 5) {
+ if (value & (1 << 25))
+ return;
+ } else if (mpidr == 6) {
+ if (value & (1 << 28))
+ return;
+ } else if (mpidr == 7) {
+ if (value & (1 << 31))
+ return;
+ } else {
+ ;
+ }
+ }
+}
+
void spacemit_assert_cpu(u_register_t mpidr)
{
unsigned int target_cpu_idx;
diff --git a/lib/utils/psci/spacemit/plat/plat_pm.c b/lib/utils/psci/spacemit/plat/plat_pm.c
index a5b91270834f..166bc3c7be1f 100644
--- a/lib/utils/psci/spacemit/plat/plat_pm.c
+++ b/lib/utils/psci/spacemit/plat/plat_pm.c
@@ -1,14 +1,20 @@
#include <sbi/sbi_types.h>
+#include <sbi/riscv_locks.h>
#include <sbi/riscv_asm.h>
#include <sbi_utils/cci/cci.h>
#include <sbi_utils/psci/psci.h>
#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_ipi.h>
#include <sbi/sbi_hart.h>
+#include <sbi/sbi_hsm.h>
+#include <sbi/sbi_domain.h>
#include <sbi/sbi_console.h>
+#include <sbi/sbi_hartmask.h>
#include <sbi_utils/psci/plat/arm/common/arm_def.h>
#include <sbi_utils/irqchip/fdt_irqchip_plic.h>
#include <sbi_utils/cache/cacheflush.h>
#include "underly_implement.h"
+#include "../../psci_private.h"
#define CORE_PWR_STATE(state) \
((state)->pwr_domain_state[MPIDR_AFFLVL0])
@@ -20,17 +26,39 @@
/* reserved for future used */
/* unsigned long __plic_regsave_offset_ptr; */
+static spinlock_t psciipi_lock = SPIN_LOCK_INITIALIZER;
+static struct sbi_hartmask psciipi_wait_hmask = { 0 };
+
+static void wake_idle_harts(struct sbi_scratch *scratch, u32 hartid)
+{
+ spin_lock(&psciipi_lock);
+
+ /* Send an IPI to all HARTs of the cluster that waiting for waked up */
+ for (u32 i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER * PLATFORM_CLUSTER_COUNT; i++) {
+ if (i != hartid) {
+ sbi_hartmask_set_hart(i, &psciipi_wait_hmask);
+ sbi_ipi_raw_send(i);
+ }
+ }
+
+ spin_unlock(&psciipi_lock);
+}
+
static int spacemit_pwr_domain_on(u_register_t mpidr)
{
/* wakeup the cpu */
- spacemit_wakeup_cpu(mpidr);
+ if (spacemit_core_enter_c2(mpidr)) {
+ spacemit_wakeup_cpu(mpidr);
+ } else {
+ sbi_ipi_raw_send(mpidr);
+ }
return 0;
}
static void spacemit_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
- unsigned int hartid = current_hartid();
+ unsigned int hartid = current_hartid();
if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
/* D1P */
@@ -42,12 +70,12 @@ static void spacemit_pwr_domain_on_finish(const psci_power_state_t *target_state
* No need for locks as no other cpu is active at the moment.
*/
if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
- spacemit_cluster_on(hartid);
+ spacemit_cluster_on(hartid);
#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
/* disable the tcm */
csr_write(CSR_TCMCFG, 0);
#endif
- cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(hartid));
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(hartid));
#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
/* enable the tcm */
csr_write(CSR_TCMCFG, 1);
@@ -62,6 +90,7 @@ static int spacemit_pwr_domain_off_early(const psci_power_state_t *target_state)
/* clear the external irq pending */
csr_clear(CSR_MIP, MIP_MEIP);
csr_clear(CSR_MIP, MIP_SEIP);
+ csr_clear(CSR_MIP, MIP_MSIP);
/* here we clear the sstimer pending if this core have */
if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(), SBI_HART_EXT_SSTC)) {
@@ -76,28 +105,65 @@ static void spacemit_pwr_domain_off(const psci_power_state_t *target_state)
unsigned int hartid = current_hartid();
if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
-#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
- /* disable the tcm */
- csr_write(CSR_TCMCFG, 0);
-#endif
- cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(hartid));
- spacemit_cluster_off(hartid);
- csi_flush_l2_cache(1);
+ /* power-off cluster */
+ spacemit_cluster_off(hartid);
}
if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
/* D1P */
spacemit_top_off(hartid);
}
-
- spacemit_assert_cpu(hartid);
}
static void spacemit_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
{
- while (1) {
- asm volatile ("wfi");
+ int hstate;
+ unsigned long saved_mie, cmip;
+ unsigned int hartid = current_hartid();
+
+ hstate = sbi_hsm_hart_get_state(sbi_domain_thishart_ptr(), hartid);
+
+ /* Save MIE CSR */
+ saved_mie = csr_read(CSR_MIE);
+
+ /* Set MSIE and MEIE bits to receive IPI */
+ if (hstate == SBI_HSM_STATE_SUSPENDED) {
+ csr_set(CSR_MIE, MIP_MSIP | MIP_MEIP);
+
+ /* Wait for wakeup source to finish using WFI */
+ do {
+ wfi();
+ cmip = csr_read(CSR_MIP);
+ } while (!(cmip & (MIP_MSIP | MIP_MEIP)));
+ } else {
+ csr_set(CSR_MIE, MIP_MSIP);
+
+ /* Wait for wakeup source to finish using WFI */
+ do {
+ wfi();
+ cmip = csr_read(CSR_MIP);
+ } while (!(cmip & (MIP_MSIP)));
+
+ spin_lock(&psciipi_lock);
+
+ if (sbi_hartmask_test_hart(hartid, &psciipi_wait_hmask)) {
+ sbi_ipi_raw_clear(hartid);
+ /* Restore MIE CSR */
+ csr_write(CSR_MIE, saved_mie);
+
+ spin_unlock(&psciipi_lock);
+
+ spacemit_assert_cpu(hartid);
+
+ while (1)
+ asm volatile ("wfi");
+ }
+
+ spin_unlock(&psciipi_lock);
}
+
+ /* Restore MIE CSR */
+ csr_write(CSR_MIE, saved_mie);
}
static void spacemit_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
@@ -158,9 +224,8 @@ static int spacemit_validate_power_state(unsigned int power_state,
static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
{
- unsigned int clusterid;
unsigned int hartid = current_hartid();
-
+
/*
* CSS currently supports retention only at cpu level. Just return
* as nothing is to be done for retention.
@@ -168,30 +233,40 @@ static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
if (CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
return;
-
if (CORE_PWR_STATE(target_state) != ARM_LOCAL_STATE_OFF) {
sbi_printf("%s:%d\n", __func__, __LINE__);
sbi_hart_hang();
}
- /* Cluster is to be turned off, so disable coherency */
- if (CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
- clusterid = MPIDR_AFFLVL1_VAL(hartid);
+ /* power-off cluster */
+ if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
+ spacemit_cluster_off(hartid);
+
+ if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
/* disable the tcm */
csr_write(CSR_TCMCFG, 0);
#endif
- cci_disable_snoop_dvm_reqs(clusterid);
- spacemit_cluster_off(hartid);
- csi_flush_l2_cache(1);
- }
+ wake_idle_harts(NULL, hartid);
- if (SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
/* D1P & D2 */
+ csi_flush_l2_cache_hart(0, 0);
+ csi_flush_l2_cache_hart(0, PLATFORM_MAX_CPUS_PER_CLUSTER);
+
+ cci_disable_snoop_dvm_reqs(0);
+ cci_disable_snoop_dvm_reqs(1);
+
+ /* assert othter cpu & wait other cpu enter c2 */
+ for (u32 i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER * PLATFORM_CLUSTER_COUNT; i++) {
+ if (i != hartid) {
+ spacemit_wait_core_enter_c2(i);
+ }
+ }
+
+ spacemit_assert_cpu(hartid);
+
spacemit_top_off(hartid);
}
-
- spacemit_assert_cpu(hartid);
}
static void spacemit_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
diff --git a/lib/utils/psci/spacemit/plat/underly_implement.h b/lib/utils/psci/spacemit/plat/underly_implement.h
index dd6c972325bb..7c11db518a3f 100644
--- a/lib/utils/psci/spacemit/plat/underly_implement.h
+++ b/lib/utils/psci/spacemit/plat/underly_implement.h
@@ -9,6 +9,8 @@ void spacemit_cluster_on(u_register_t mpidr);
void spacemit_cluster_off(u_register_t mpidr);
void spacemit_wakeup_cpu(u_register_t mpidr);
void spacemit_assert_cpu(u_register_t mpidr);
+int spacemit_core_enter_c2(u_register_t mpidr);
+void spacemit_wait_core_enter_c2(u_register_t mpidr);
void spacemit_deassert_cpu(void);
#endif
diff --git a/lib/utils/serial/fdt_serial_uart8250.c b/lib/utils/serial/fdt_serial_uart8250.c
index 7b5d6a4c2f18..51ea91c7665f 100644
--- a/lib/utils/serial/fdt_serial_uart8250.c
+++ b/lib/utils/serial/fdt_serial_uart8250.c
@@ -30,6 +30,7 @@ static const struct fdt_match serial_uart8250_match[] = {
{ .compatible = "ns16550" },
{ .compatible = "ns16550a" },
{ .compatible = "snps,dw-apb-uart" },
+ { .compatible = "spacemit,pxa-uart" },
{ },
};
diff --git a/platform/generic/include/spacemit/k1x/k1x_evb.h b/platform/generic/include/spacemit/k1x/k1x_evb.h
index 10e856965618..e7381ca245da 100644
--- a/platform/generic/include/spacemit/k1x/k1x_evb.h
+++ b/platform/generic/include/spacemit/k1x/k1x_evb.h
@@ -60,6 +60,7 @@
#define CLUSTER_BIT30_OFFSET (30)
#define CLUSTER_BIT25_OFFSET (25)
#define CLUSTER_BIT13_OFFSET (13)
+#define CLUSTER_VOTE_AP_SLPEN (3)
#define L2_HARDWARE_CACHE_FLUSH_EN (13)
diff --git a/platform/generic/spacemit/spacemit_k1.c b/platform/generic/spacemit/spacemit_k1.c
index 95218846715f..2f9deb1a7940 100644
--- a/platform/generic/spacemit/spacemit_k1.c
+++ b/platform/generic/spacemit/spacemit_k1.c
@@ -67,15 +67,15 @@ static void wakeup_other_core(void)
#if defined(CONFIG_PLATFORM_SPACEMIT_K1X)
/* enable the hw l2 cache flush method for each core */
- writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG0);
- writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG1);
- writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG2);
- writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG3);
-
- writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG0);
- writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG1);
- writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG2);
- writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG3);
+ /* writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG0); */
+ /* writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG1); */
+ /* writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG2); */
+ /* writel(readl((u32 *)PMU_C0_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C0_CAPMP_IDLE_CFG3); */
+
+ /* writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG0) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG0); */
+ /* writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG1) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG1); */
+ /* writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG2) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG2); */
+ /* writel(readl((u32 *)PMU_C1_CAPMP_IDLE_CFG3) | (1 << L2_HARDWARE_CACHE_FLUSH_EN), (u32 *)PMU_C1_CAPMP_IDLE_CFG3); */
#endif
// hart0 is already boot up
@@ -188,7 +188,8 @@ static int spacemit_hart_start(unsigned int hartid, unsigned long saddr)
static int spacemit_hart_stop(void)
{
psci_cpu_off();
- return 0;
+
+ return SBI_ENOTSUPP;
}
static int spacemit_hart_suspend(unsigned int suspend_type)
@@ -265,6 +266,8 @@ static bool spacemit_cold_boot_allowed(u32 hartid, const struct fdt_match *match
static const struct fdt_match spacemit_k1_match[] = {
{ .compatible = "spacemit,k1-pro" },
{ .compatible = "spacemit,k1x" },
+ { .compatible = "spacemit,k1-x" },
+ { .compatible = "spacemit,k1" },
{ },
};
--
2.35.3

26
patch/atf/atf-spacemit/008-Update-for-v1.0.13.patch
View File

@@ -1,26 +0,0 @@
From a26e37daaeb01f027e4753f854716f0f15eb3d13 Mon Sep 17 00:00:00 2001
From: James Deng <james.deng@spacemit.com>
Date: Fri, 16 Aug 2024 23:44:13 +0800
Subject: Update for v1.0.13
---
lib/utils/psci/spacemit/plat/plat_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/utils/psci/spacemit/plat/plat_pm.c b/lib/utils/psci/spacemit/plat/plat_pm.c
index 166bc3c7be1f..32aec9d308ab 100644
--- a/lib/utils/psci/spacemit/plat/plat_pm.c
+++ b/lib/utils/psci/spacemit/plat/plat_pm.c
@@ -147,6 +147,9 @@ static void spacemit_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_st
spin_lock(&psciipi_lock);
if (sbi_hartmask_test_hart(hartid, &psciipi_wait_hmask)) {
+
+ sbi_hartmask_clear_hart(hartid, &psciipi_wait_hmask);
+
sbi_ipi_raw_clear(hartid);
/* Restore MIE CSR */
csr_write(CSR_MIE, saved_mie);
--
2.35.3

46
patch/atf/atf-spacemit/009-Update-for-v1.0.14.patch
View File

@@ -1,46 +0,0 @@
From 6cf0c8e6ed09841cdbff7b3788efa608ac5b08aa Mon Sep 17 00:00:00 2001
From: James Deng <james.deng@spacemit.com>
Date: Sat, 31 Aug 2024 14:23:34 +0800
Subject: Update for v1.0.14
---
debian/opensbi-spacemit.postinst | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/debian/opensbi-spacemit.postinst b/debian/opensbi-spacemit.postinst
index dce7154ac8f4..0362a598a14b 100755
--- a/debian/opensbi-spacemit.postinst
+++ b/debian/opensbi-spacemit.postinst
@@ -31,9 +31,15 @@ configure)
OPENSBI_SEEK=0
;;
"/dev/nvme0n1"*)
- OPENSBI=/dev/mtdblock0
- # 以KB为单位
- OPENSBI_SEEK=448
+ if [ ! -e "/dev/mtdblock4" ]; then
+ OPENSBI=/dev/mtdblock0
+ # 以KB为单位
+ OPENSBI_SEEK=448
+ else
+ OPENSBI=/dev/mtdblock4
+ # 以KB为单位
+ OPENSBI_SEEK=0
+ fi
;;
*)
echo "Unsupported root=$ROOT"
@@ -56,8 +62,9 @@ configure)
done
# 此前已经做了所有检查
+ set -x
dd if=/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.itb of=$OPENSBI seek=$OPENSBI_SEEK bs=1K && sync
-
+ set +x
;;
esac
--
2.35.3

108
patch/atf/atf-spacemit/010-Update-for-v1.0.15.patch
View File

@@ -1,108 +0,0 @@
From 08916e4fe06451080a8882d6955df9e5947e352e Mon Sep 17 00:00:00 2001
From: James Deng <james.deng@spacemit.com>
Date: Sat, 7 Sep 2024 21:08:45 +0800
Subject: Update for v1.0.15
---
.../spacemit/plat/k1x/underly_implement.c | 20 ++++++++++++++
lib/utils/psci/spacemit/plat/plat_pm.c | 27 +++++++++++--------
.../psci/spacemit/plat/underly_implement.h | 1 +
3 files changed, 37 insertions(+), 11 deletions(-)
diff --git a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
index f87bacc7297d..825db86dddfe 100644
--- a/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
+++ b/lib/utils/psci/spacemit/plat/k1x/underly_implement.c
@@ -319,6 +319,26 @@ int spacemit_core_enter_c2(u_register_t mpidr)
return 0;
}
+int spacemit_cluster_enter_m2(u_register_t mpidr)
+{
+ unsigned int value;
+
+ /* wait the cpu enter M2 */
+ value = readl((unsigned int *)0xd4282890);
+
+ if (mpidr == 0 || mpidr == 1 || mpidr == 2 || mpidr == 3) {
+ if (value & (1 << 3))
+ return 1;
+ } else if (mpidr == 4 || mpidr == 5 || mpidr == 6 || mpidr == 7) {
+ if (value & (1 << 19))
+ return 1;
+ } else {
+ return 0;
+ }
+
+ return 0;
+}
+
void spacemit_wait_core_enter_c2(u_register_t mpidr)
{
unsigned int value;
diff --git a/lib/utils/psci/spacemit/plat/plat_pm.c b/lib/utils/psci/spacemit/plat/plat_pm.c
index 32aec9d308ab..e3f494065f23 100644
--- a/lib/utils/psci/spacemit/plat/plat_pm.c
+++ b/lib/utils/psci/spacemit/plat/plat_pm.c
@@ -228,7 +228,7 @@ static int spacemit_validate_power_state(unsigned int power_state,
static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
{
unsigned int hartid = current_hartid();
-
+
/*
* CSS currently supports retention only at cpu level. Just return
* as nothing is to be done for retention.
@@ -250,22 +250,27 @@ static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
/* disable the tcm */
csr_write(CSR_TCMCFG, 0);
#endif
- wake_idle_harts(NULL, hartid);
+ if (!spacemit_cluster_enter_m2(PLATFORM_MAX_CPUS_PER_CLUSTER)) {
+ wake_idle_harts(NULL, hartid);
- /* D1P & D2 */
- csi_flush_l2_cache_hart(0, 0);
- csi_flush_l2_cache_hart(0, PLATFORM_MAX_CPUS_PER_CLUSTER);
+ csi_flush_l2_cache_hart(0, 0);
+ csi_flush_l2_cache_hart(0, PLATFORM_MAX_CPUS_PER_CLUSTER);
- cci_disable_snoop_dvm_reqs(0);
- cci_disable_snoop_dvm_reqs(1);
+ cci_disable_snoop_dvm_reqs(0);
+ cci_disable_snoop_dvm_reqs(1);
- /* assert othter cpu & wait other cpu enter c2 */
- for (u32 i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER * PLATFORM_CLUSTER_COUNT; i++) {
- if (i != hartid) {
- spacemit_wait_core_enter_c2(i);
+ /* assert othter cpu & wait other cpu enter c2 */
+ for (u32 i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER * PLATFORM_CLUSTER_COUNT; i++) {
+ if (i != hartid) {
+ spacemit_wait_core_enter_c2(i);
+ }
}
+ } else {
+ csi_flush_l2_cache_hart(0, 0);
+ cci_disable_snoop_dvm_reqs(0);
}
+
spacemit_assert_cpu(hartid);
spacemit_top_off(hartid);
diff --git a/lib/utils/psci/spacemit/plat/underly_implement.h b/lib/utils/psci/spacemit/plat/underly_implement.h
index 7c11db518a3f..80f1377d1116 100644
--- a/lib/utils/psci/spacemit/plat/underly_implement.h
+++ b/lib/utils/psci/spacemit/plat/underly_implement.h
@@ -10,6 +10,7 @@ void spacemit_cluster_off(u_register_t mpidr);
void spacemit_wakeup_cpu(u_register_t mpidr);
void spacemit_assert_cpu(u_register_t mpidr);
int spacemit_core_enter_c2(u_register_t mpidr);
+int spacemit_cluster_enter_m2(u_register_t mpidr);
void spacemit_wait_core_enter_c2(u_register_t mpidr);
void spacemit_deassert_cpu(void);
--
2.35.3