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sunxi-6.16: remove unused megous patches
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@@ -0,0 +1,178 @@
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From 54669ac67e47835b8cc3eea215026385a0050567 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Sun, 29 Sep 2024 22:04:33 +1300
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Subject: drm: sun4i: de2/de3: Change CSC argument
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Currently, CSC module takes care only for converting YUV to RGB.
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However, DE3 is more suited to work in YUV color space. Change CSC mode
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argument to format type to be more neutral. New argument only tells
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layer format type and doesn't imply output type.
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This commit doesn't make any functional change.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Signed-off-by: Ryan Walklin <ryan@testtoast.com>
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Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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---
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drivers/gpu/drm/sun4i/sun8i_csc.c | 22 +++++++++++-----------
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drivers/gpu/drm/sun4i/sun8i_csc.h | 10 +++++-----
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drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 16 ++++++++--------
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3 files changed, 24 insertions(+), 24 deletions(-)
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diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
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index 58480d8e4f70..6ebd1c3aa3ab 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
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@@ -108,7 +108,7 @@ static const u32 yuv2rgb_de3[2][3][12] = {
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};
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static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
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- enum sun8i_csc_mode mode,
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+ enum format_type fmt_type,
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enum drm_color_encoding encoding,
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enum drm_color_range range)
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{
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@@ -118,12 +118,12 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
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table = yuv2rgb[range][encoding];
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- switch (mode) {
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- case SUN8I_CSC_MODE_YUV2RGB:
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+ switch (fmt_type) {
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+ case FORMAT_TYPE_YUV:
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base_reg = SUN8I_CSC_COEFF(base, 0);
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regmap_bulk_write(map, base_reg, table, 12);
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break;
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- case SUN8I_CSC_MODE_YVU2RGB:
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+ case FORMAT_TYPE_YVU:
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for (i = 0; i < 12; i++) {
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if ((i & 3) == 1)
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base_reg = SUN8I_CSC_COEFF(base, i + 1);
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@@ -141,7 +141,7 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
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}
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static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
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- enum sun8i_csc_mode mode,
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+ enum format_type fmt_type,
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enum drm_color_encoding encoding,
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enum drm_color_range range)
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{
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@@ -151,12 +151,12 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
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table = yuv2rgb_de3[range][encoding];
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- switch (mode) {
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- case SUN8I_CSC_MODE_YUV2RGB:
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+ switch (fmt_type) {
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+ case FORMAT_TYPE_YUV:
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addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0);
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regmap_bulk_write(map, addr, table, 12);
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break;
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- case SUN8I_CSC_MODE_YVU2RGB:
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+ case FORMAT_TYPE_YVU:
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for (i = 0; i < 12; i++) {
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if ((i & 3) == 1)
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addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE,
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@@ -206,7 +206,7 @@ static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable)
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}
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void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
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- enum sun8i_csc_mode mode,
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+ enum format_type fmt_type,
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enum drm_color_encoding encoding,
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enum drm_color_range range)
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{
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@@ -214,14 +214,14 @@ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
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if (mixer->cfg->is_de3) {
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sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer,
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- mode, encoding, range);
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+ fmt_type, encoding, range);
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return;
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}
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base = ccsc_base[mixer->cfg->ccsc][layer];
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sun8i_csc_set_coefficients(mixer->engine.regs, base,
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- mode, encoding, range);
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+ fmt_type, encoding, range);
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}
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void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
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diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h
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index 828b86fd0cab..7322770f39f0 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_csc.h
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+++ b/drivers/gpu/drm/sun4i/sun8i_csc.h
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@@ -22,14 +22,14 @@ struct sun8i_mixer;
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#define SUN8I_CSC_CTRL_EN BIT(0)
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-enum sun8i_csc_mode {
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- SUN8I_CSC_MODE_OFF,
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- SUN8I_CSC_MODE_YUV2RGB,
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- SUN8I_CSC_MODE_YVU2RGB,
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+enum format_type {
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+ FORMAT_TYPE_RGB,
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+ FORMAT_TYPE_YUV,
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+ FORMAT_TYPE_YVU,
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};
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void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
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- enum sun8i_csc_mode mode,
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+ enum format_type fmt_type,
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enum drm_color_encoding encoding,
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enum drm_color_range range);
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void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable);
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diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
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index 9c09d9c08496..8a80934e928f 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
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@@ -193,19 +193,19 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
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return 0;
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}
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-static u32 sun8i_vi_layer_get_csc_mode(const struct drm_format_info *format)
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+static u32 sun8i_vi_layer_get_format_type(const struct drm_format_info *format)
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{
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if (!format->is_yuv)
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- return SUN8I_CSC_MODE_OFF;
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+ return FORMAT_TYPE_RGB;
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switch (format->format) {
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case DRM_FORMAT_YVU411:
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case DRM_FORMAT_YVU420:
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case DRM_FORMAT_YVU422:
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case DRM_FORMAT_YVU444:
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- return SUN8I_CSC_MODE_YVU2RGB;
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+ return FORMAT_TYPE_YVU;
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default:
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- return SUN8I_CSC_MODE_YUV2RGB;
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+ return FORMAT_TYPE_YUV;
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}
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}
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@@ -213,7 +213,7 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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- u32 val, ch_base, csc_mode, hw_fmt;
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+ u32 val, ch_base, fmt_type, hw_fmt;
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const struct drm_format_info *fmt;
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int ret;
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@@ -231,9 +231,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
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- csc_mode = sun8i_vi_layer_get_csc_mode(fmt);
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- if (csc_mode != SUN8I_CSC_MODE_OFF) {
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- sun8i_csc_set_ccsc_coefficients(mixer, channel, csc_mode,
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+ fmt_type = sun8i_vi_layer_get_format_type(fmt);
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+ if (fmt_type != FORMAT_TYPE_RGB) {
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+ sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_type,
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state->color_encoding,
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state->color_range);
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sun8i_csc_enable_ccsc(mixer, channel, true);
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--
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2.35.3
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