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u-boot-sunxi: Fix incorrect ram detection

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Also updated orangepi3-lts support patch from Jernej's patch from LibreELEC
This commit is contained in:
Gunjan Gupta
2023-09-12 18:44:48 +05:30
committed by Igor
parent 9def9f6b4a
commit 889183b78c
2 changed files with 244 additions and 66 deletions
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265
patch/u-boot/u-boot-sunxi/board_orangepi3-lts/0001-add-orange-pi-3-lts-support.patch
View File

@@ -1,25 +1,22 @@
From ff63ede2a38b16f2438c4c33f49796c639735753 Mon Sep 17 00:00:00 2001 From 65a3bafb3f5a8c83b678b59cb4b7bb87d12e7cd0 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com> From: Jernej Skrabec <jernej.skrabec@gmail.com>
Date: Fri, 1 Apr 2022 21:58:07 +0100 Date: Tue, 7 Feb 2023 17:43:14 +0100
Subject: [PATCH] add orange pi 3 lts support Subject: [PATCH] sunxi: Add OrangePi 3 LTS board
+ Set dcdcd to 980mv
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
--- ---
arch/arm/dts/Makefile | 1 + arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun50i-h6-orangepi-3-lts.dts | 179 ++++++++++++++++++++++ arch/arm/dts/sun50i-h6-orangepi-3-lts.dts | 313 ++++++++++++++++++++++
configs/orangepi_3_lts_defconfig | 18 +++ configs/orangepi_3_lts_defconfig | 19 ++
3 files changed, 198 insertions(+) 3 files changed, 333 insertions(+)
create mode 100644 arch/arm/dts/sun50i-h6-orangepi-3-lts.dts create mode 100644 arch/arm/dts/sun50i-h6-orangepi-3-lts.dts
create mode 100644 configs/orangepi_3_lts_defconfig create mode 100644 configs/orangepi_3_lts_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 028dc4a4..b129fcce 100644 index 965895bc2a3c..501400635fa9 100644
--- a/arch/arm/dts/Makefile --- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile
@@ -649,6 +649,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ @@ -702,6 +702,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
dtb-$(CONFIG_MACH_SUN50I_H6) += \ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-beelink-gs1.dtb \ sun50i-h6-beelink-gs1.dtb \
sun50i-h6-orangepi-3.dtb \ sun50i-h6-orangepi-3.dtb \
@@ -29,19 +26,19 @@ index 028dc4a4..b129fcce 100644
sun50i-h6-pine-h64.dtb \ sun50i-h6-pine-h64.dtb \
diff --git a/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts b/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts diff --git a/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts b/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts
new file mode 100644 new file mode 100644
index 00000000..94e3c5b5 index 000000000000..6a5df1103a90
--- /dev/null --- /dev/null
+++ b/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts
@@ -0,0 +1,180 @@ @@ -0,0 +1,313 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* +// Copyright (C) 2023 Jernej Skrabec <jernej.skrabec@gmail.com>
+ * Copyright (C) 2018 Amarula Solutions +// Based on sun50i-h6-orangepi-3.dts, which is:
+ * Author: Jagan Teki <jagan@amarulasolutions.com> +// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
+ */
+ +
+/dts-v1/; +/dts-v1/;
+ +
+#include "sun50i-h6.dtsi" +#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+ +
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/gpio/gpio.h>
+ +
@@ -50,13 +47,86 @@ index 00000000..94e3c5b5
+ compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6"; + compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
+ +
+ aliases { + aliases {
+ serial0 = &uart0;
+ ethernet0 = &emac; + ethernet0 = &emac;
+ serial0 = &uart0;
+ }; + };
+ +
+ chosen { + chosen {
+ stdout-path = "serial0:115200n8"; + stdout-path = "serial0:115200n8";
+ }; + };
+
+ connector {
+ compatible = "hdmi-connector";
+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "orangepi:red:power";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ default-state = "on";
+ };
+
+ led-1 {
+ label = "orangepi:green:status";
+ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <150000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
+&de {
+ status = "okay";
+};
+
+&dwc3 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+}; +};
+ +
+&emac { +&emac {
@@ -64,38 +134,73 @@ index 00000000..94e3c5b5
+ pinctrl-0 = <&ext_rgmii_pins>; + pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii"; + phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>; + phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <&reg_aldo2>; + phy-supply = <&reg_gmac_3v3>;
+ allwinner,rx-delay-ps = <200>; + allwinner,rx-delay-ps = <200>;
+ allwinner,tx-delay-ps = <200>; + allwinner,tx-delay-ps = <300>;
+ status = "okay"; + status = "okay";
+}; +};
+ +
+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
+&hdmi {
+ hvcc-supply = <&reg_bldo2>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mdio { +&mdio {
+ ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>; + reg = <1>;
+
+ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+ reset-assert-us = <15000>;
+ reset-deassert-us = <40000>;
+ }; + };
+}; +};
+ +
+&mmc0 { +&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_cldo1>; + vmmc-supply = <&reg_cldo1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>; + bus-width = <4>;
+ status = "okay"; + status = "okay";
+}; +};
+ +
+&mmc2 { +&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_cldo1>; + vmmc-supply = <&reg_cldo1>;
+ non-removable; + vqmmc-supply = <&reg_bldo2>;
+ cap-mmc-hw-reset; + cap-mmc-hw-reset;
+ non-removable;
+ bus-width = <8>; + bus-width = <8>;
+ status = "okay"; + status = "okay";
+}; +};
+ +
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pc-supply = <&reg_bldo2>;
+ vcc-pd-supply = <&reg_cldo1>;
+ vcc-pg-supply = <&reg_bldo3>;
+};
+
+&r_ir {
+ status = "okay";
+};
+
+&r_i2c { +&r_i2c {
+ status = "okay"; + status = "okay";
+ +
@@ -103,52 +208,58 @@ index 00000000..94e3c5b5
+ compatible = "x-powers,axp805", "x-powers,axp806"; + compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x36>; + reg = <0x36>;
+ interrupt-parent = <&r_intc>; + interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller; + interrupt-controller;
+ #interrupt-cells = <1>; + #interrupt-cells = <1>;
+ x-powers,self-working-mode; + x-powers,self-working-mode;
+ vina-supply = <&reg_vcc5v>;
+ vinb-supply = <&reg_vcc5v>;
+ vinc-supply = <&reg_vcc5v>;
+ vind-supply = <&reg_vcc5v>;
+ vine-supply = <&reg_vcc5v>;
+ aldoin-supply = <&reg_vcc5v>;
+ bldoin-supply = <&reg_vcc5v>;
+ cldoin-supply = <&reg_vcc5v>;
+ +
+ regulators { + regulators {
+ reg_aldo1: aldo1 { + reg_aldo1: aldo1 {
+ regulator-always-on; + regulator-always-on;
+ regulator-min-microvolt = <3300000>; + regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl"; + regulator-name = "vcc-pl-led-ir";
+ }; + };
+ +
+ reg_aldo2: aldo2 { + reg_aldo2: aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>; + regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-ac200"; + regulator-name = "vcc33-audio-tv-ephy-mac";
+ }; + };
+ +
+ /* ALDO3 is shorted to CLDO1 */
+ reg_aldo3: aldo3 { + reg_aldo3: aldo3 {
+ regulator-always-on; + regulator-always-on;
+ regulator-min-microvolt = <3300000>; + regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc25-dram"; + regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
+ }; + };
+ +
+ reg_bldo1: bldo1 { + reg_bldo1: bldo1 {
+ regulator-always-on; + regulator-always-on;
+ regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>; + regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-bias-pll"; + regulator-name = "vcc18-dram-bias-pll";
+ }; + };
+ +
+ reg_bldo2: bldo2 { + reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>; + regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-efuse-pcie-hdmi-io"; + regulator-name = "vcc-efuse-pcie-hdmi-pc";
+ }; + };
+ +
+ reg_bldo3: bldo3 { + reg_bldo3: bldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>; + regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dcxoio"; + regulator-name = "vcc-pm-pg-dcxoio-wifi";
+ }; + };
+ +
+ bldo4 { + bldo4 {
@@ -159,38 +270,37 @@ index 00000000..94e3c5b5
+ regulator-always-on; + regulator-always-on;
+ regulator-min-microvolt = <3300000>; + regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3"; + regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
+ }; + };
+ +
+ reg_cldo2: cldo2 { + cldo2 {
+ regulator-min-microvolt = <3300000>; + /* unused */
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+ }; + };
+ +
+ reg_cldo3: cldo3 { + cldo3 {
+ regulator-min-microvolt = <3300000>; + /* unused */
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+ }; + };
+ +
+ reg_dcdca: dcdca { + reg_dcdca: dcdca {
+ regulator-always-on; + regulator-always-on;
+ regulator-min-microvolt = <810000>; + regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1080000>; + regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
+ regulator-name = "vdd-cpu"; + regulator-name = "vdd-cpu";
+ }; + };
+ +
+ reg_dcdcc: dcdcc { + reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
+ regulator-min-microvolt = <810000>; + regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>; + regulator-max-microvolt = <1080000>;
+ regulator-ramp-delay = <2500>;
+ regulator-name = "vdd-gpu"; + regulator-name = "vdd-gpu";
+ }; + };
+ +
+ reg_dcdcd: dcdcd { + reg_dcdcd: dcdcd {
+ regulator-always-on; + regulator-always-on;
+ regulator-min-microvolt = <980000>; + regulator-min-microvolt = <960000>;
+ regulator-max-microvolt = <980000>; + regulator-max-microvolt = <960000>;
+ regulator-name = "vdd-sys"; + regulator-name = "vdd-sys";
+ }; + };
+ +
@@ -208,33 +318,56 @@ index 00000000..94e3c5b5
+ }; + };
+}; +};
+ +
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&uart0 { +&uart0 {
+ pinctrl-names = "default"; + pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>; + pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay"; + status = "okay";
+}; +};
+
+&usb2otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
+ usb0_vbus-supply = <&reg_vcc5v>;
+ usb3_vbus-supply = <&reg_vcc5v>;
+ status = "okay";
+};
+
+&usb3phy {
+ status = "okay";
+};
diff --git a/configs/orangepi_3_lts_defconfig b/configs/orangepi_3_lts_defconfig diff --git a/configs/orangepi_3_lts_defconfig b/configs/orangepi_3_lts_defconfig
new file mode 100644 new file mode 100644
index 00000000..f119c349 index 000000000000..41a9af4ef67a
--- /dev/null --- /dev/null
+++ b/configs/orangepi_3_lts_defconfig +++ b/configs/orangepi_3_lts_defconfig
@@ -0,0 +1,19 @@ @@ -0,0 +1,19 @@
+CONFIG_ARM=y +CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3-lts"
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H6=y +CONFIG_MACH_SUN50I_H6=y
+CONFIG_SUNXI_DRAM_H6_LPDDR3=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+CONFIG_SUNXI_DRAM_DDR3=n +CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_HDMI_DDC_EN="PH2"
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3-lts"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y +CONFIG_SPL_STACK=0x118000
+CONFIG_SPL_I2C=y +CONFIG_SYS_PBSIZE=1024
+CONFIG_R_I2C_ENABLE=y +CONFIG_SYS_BOOTM_LEN=0x2000000
+# CONFIG_CMD_FLASH is not set +CONFIG_PHY_SUN50I_USB3=y
+# CONFIG_CMD_FPGA is not set +CONFIG_USB_XHCI_HCD=y
+# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_USB_XHCI_DWC3=y
+# CONFIG_SPL_ISO_PARTITION is not set +CONFIG_USB_EHCI_HCD=y
+# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
--
2.39.1

45
patch/u-boot/u-boot-sunxi/unreliable-dram.patch Normal file
View File

@@ -0,0 +1,45 @@
From 04751c559bf01f6a3098fb92c7c25c9feb293b74 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 29 Jul 2019 01:39:42 +0200
Subject: [PATCH] Fix unreliable detection of DRAM size on Orange Pi 3
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Orange Pi 3 has 2 GiB of DRAM, that sometime get misdetected
as 4 GiB, due to false negative result from mctl_mem_matches()
when detecting number of column address bits. This leads to
u-boot detecting more address bits than there are and the
boot process hangs shortly after.
In mctl_mem_matches() we need to wait for each write to finish,
separately. Without this, the check is not reliable for some
unknown reason, probably having to do with unpredictable memory
access ordering.
Patch was made with help from André Przywara, who noticed that
my original idea about detection failing due to read-back from
cache without involving DRAM was false, because data cache is
still of at the time of the DRAM size autodetection.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Cc: André Przywara <andre.przywara@arm.com>
---
arch/arm/mach-sunxi/dram_helpers.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index cdf2750f1c..16938fab21 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -34,6 +34,7 @@ bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
writel(0, CFG_SYS_SDRAM_BASE);
+ dsb();
writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
dsb();
/* Check if the same value is actually observed when reading back */
--
2.34.1