Cleanup u-boot configurations for rockchip64 derivatives (#3150)

* Cleanup u-boot configurations for rockchip64 derivatives

* Bring separate BOOT_USE_* variables into BOOT_SCENARIO

* Revert BOOTDIR change in rockchip64

* Bump RK3568 BL31 to v1.35

config/boards/khadas-edge.conf

@@ -5,4 +5,5 @@ BOOTCONFIG="khadas-edge-v-rk3399_defconfig"
 KERNEL_TARGET="current,edge"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
+BOOT_SUPPORT_SPI=yes
 ASOUND_STATE="asound.state.rk3399"

config/boards/pinebook-pro.csc

@@ -7,4 +7,5 @@ KERNEL_TARGET="legacy,current,edge"
 FULL_DESKTOP="yes"
 PACKAGE_LIST_DESKTOP_BOARD="xfce4-power-manager"
 BOOT_LOGO="desktop"
+BOOT_SCENARIO="blobless"
 ASOUND_STATE="asound.state.pinebook-pro"

config/boards/roc-rk3399-pc.csc

@@ -6,3 +6,5 @@ KERNEL_TARGET="legacy,current,edge"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
 BOOT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
+BOOT_SCENARIO="blobless"
+BOOT_SUPPORT_SPI=yes

config/boards/rock-3a.csc

@@ -6,5 +6,4 @@ KERNEL_TARGET="legacy"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
 BOOT_FDT_FILE="rockchip/rk3568-rock-3-a.dtb"
-BOOT_USE_SPL_BLOBS=yes
-BOOT_SOC=rk3568
+BOOT_SCENARIO="spl-blobs"

config/boards/rock64.csc

@@ -4,3 +4,4 @@ BOARDFAMILY="rockchip64"
 BOOTCONFIG="rock64-rk3328_defconfig"
 KERNEL_TARGET="legacy,current,edge"
 FULL_DESKTOP="yes"
+BOOT_SCENARIO="blobless"

config/boards/rockpi-4a.conf

@@ -6,3 +6,5 @@ KERNEL_TARGET="legacy,current,edge"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
 BOOT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
+BOOT_SUPPORT_SPI=yes
+DDR_BLOB="rk33/rk3399_ddr_933MHz_v1.20.bin"

config/boards/rockpi-4b.conf

@@ -6,3 +6,5 @@ KERNEL_TARGET="legacy,current,edge"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
 BOOT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb"
+BOOT_SUPPORT_SPI=yes
+DDR_BLOB="rk33/rk3399_ddr_933MHz_v1.20.bin"

config/boards/rockpi-4c.conf

@@ -6,3 +6,4 @@ KERNEL_TARGET="legacy,current,edge"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
 BOOT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"
+BOOT_SUPPORT_SPI=yes

config/boards/rockpi-n10.csc

@@ -6,3 +6,4 @@ KERNEL_TARGET="current,edge"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
 BOOT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb"
+BOOT_SUPPORT_SPI=yes

config/boards/rockpro64.conf

@@ -5,3 +5,5 @@ BOOTCONFIG="rockpro64-rk3399_defconfig"
 KERNEL_TARGET="legacy,current,edge"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
+BOOT_SCENARIO="tpl-spl-blob"
+BOOT_SUPPORT_SPI=yes

config/boards/station-p1.wip

@@ -6,6 +6,7 @@ KERNEL_TARGET="legacy,current,edge"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
 BOOT_FDT_FILE="rockchip/rk3399-roc-pc-plus.dtb"
+BOOT_SUPPORT_SPI=yes
 SRC_EXTLINUX="yes"
 SRC_CMDLINE="console=uart8250,mmio32,0xff1a0000 console=tty0"
 ASOUND_STATE="asound.state.station-p1"

config/boards/tinkerboard-2.wip

@@ -6,3 +6,4 @@ KERNEL_TARGET="current,edge"
 FULL_DESKTOP="yes"
 BOOT_LOGO="desktop"
 BOOT_FDT_FILE="rockchip/rk3399-tinker-2.dtb"
+BOOT_SCENARIO="blobless"

config/boards/virtual-qemu.wip

@@ -27,7 +27,7 @@ BOOTCONFIG="qemu_arm64_defconfig"
 ATF_COMPILE="no"
 BOOTBRANCH='tag:v2021.04'
 USE_OVERLAYFS='no'
-BOOT_USE_MAINLINE_ATF=yes
+BOOT_SCENARIO="blobless"
 BOOT_SOC=qemu
 EXTRAWIFI='no'
 ROOTFS_TYPE="ext4"
@@ -47,5 +47,3 @@ post_build_image_modify() {
     display_alert "failsafe applied" "This post_build_image_modify function should not have been executed" "warn"
   fi
 }
-
-

config/sources/families/include/rockchip64_common.inc

@@ -9,6 +9,7 @@ OVERLAY_PREFIX='rockchip'
 SERIALCON=${SERIALCON:=$([ $BRANCH == "legacy" ] && echo "ttyFIQ0:1500000" || echo "ttyS2:1500000")}
 GOVERNOR="ondemand"
 BOOTBRANCH="tag:v2020.10"
+BOOTPATCHDIR="u-boot-rockchip64"
 PACKAGE_LIST_FAMILY="ethtool"
 
 RKBIN_DIR="$SRC/cache/sources/rkbin-tools"
@@ -25,8 +26,9 @@ else
 	PKG_PREFIX=""
 fi
 
+BOOT_SOC=`expr $BOOTCONFIG : '.*\(rk[[:digit:]]\+.*\)_.*'`
 
-if [[ $BOOTCONFIG == *3399* ]]; then
+if [[ $BOOT_SOC == rk3399 ]]; then
 
 	CPUMIN=${CPUMIN:="408000"}
 	CPUMAX=${CPUMAX:="2016000"}
@@ -38,75 +40,31 @@ else # rk3308, rk3328
 
 fi
 
-if [[ $BOARD == nanopi-r2s || $BOARD == nanopi-r2c || $BOARD == nanopineo3 || $BOARD == orangepi-r1plus || $BOARD == renegade || $BOARD == rockpi-e || $BOARD == station-m1 || $BOARD == z28pro ]]; then
+if [[ $BOOT_SOC == rk3328 ]]; then
 
-	BOOT_USE_BLOBS=yes
-	BOOT_SOC=rk3328
+	BOOT_SCENARIO="${BOOT_SCENARIO:=only-blobs}"
 	DDR_BLOB='rk33/rk3328_ddr_333MHz_v1.16.bin'
 	MINILOADER_BLOB='rk33/rk322xh_miniloader_v2.50.bin'
 	BL31_BLOB='rk33/rk322xh_bl31_v1.44.elf'
 
-elif [[ $BOARD == rock64 ]]; then
+elif [[ $BOOT_SOC == rk3399 ]]; then
 
-	BOOT_USE_MAINLINE_ATF=yes
-	BOOT_SOC=rk3328
-
-elif [[ $BOOTCONFIG == *3328* ]]; then
-
-	BOOT_RK3328_USE_AYUFAN_ATF=yes
-
-elif [[ $BOARD == pinebook-pro || $BOARD == tinkerboard-2 ]]; then
-
-	BOOT_USE_MAINLINE_ATF=yes
-	BOOT_SOC=rk3399
+	BOOT_SCENARIO="${BOOT_SCENARIO:=only-blobs}"
+	DDR_BLOB='rk33/rk3399_ddr_933MHz_v1.25.bin'
+	MINILOADER_BLOB='rk33/rk3399_miniloader_v1.26.bin'
+	BL31_BLOB='rk33/rk3399_bl31_v1.35.elf'
 	ATFPATCHDIR='atf-rk3399'
 
-elif [[ $BOARD == khadas-edge ]]; then
+elif [[ $BOOT_SOC == rk3399pro ]]; then
 
-	BOOT_USE_BLOBS=yes
-	BOOT_SUPPORT_SPI=yes
-	BOOT_SOC=rk3399
-	DDR_BLOB='rk33/rk3399_ddr_800MHz_v1.25.bin'
-	MINILOADER_BLOB='rk33/rk3399_miniloader_v1.26.bin'
-	BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
-
-elif [[ $BOARD == rockpi-4* ]]; then
-
-	BOOT_USE_BLOBS=yes
-	BOOT_SUPPORT_SPI=yes
-	BOOT_SOC=rk3399
-	DDR_BLOB='rk33/rk3399_ddr_933MHz_v1.20.bin' # 1GB model does not boot with later versions
-	MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin'
-	BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
-
-elif [[ $BOARD == station-p1 || $BOARD == firefly-rk3399 ]]; then
-
-	BOOT_USE_BLOBS=yes
-	BOOT_SUPPORT_SPI=yes
-	BOOT_SOC=rk3399
-	DDR_BLOB='rk33/rk3399_ddr_933MHz_v1.24.bin'
-	MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin'
-	BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
-
-elif [[ $BOARD == rockpi-n10* ]]; then
-
-	BOOT_USE_BLOBS=yes
-	BOOT_SUPPORT_SPI=yes
-	BOOT_SOC=rk3399pro
+	BOOT_SCENARIO="${BOOT_SCENARIO:=only-blobs}"
 	DDR_BLOB='rk33/rk3399pro_npu_ddr_933MHz_v1.02.bin'
 	MINILOADER_BLOB='rk33/rk3399pro_miniloader_v1.26.bin'
 	BL31_BLOB='rk33/rk3399pro_bl31_v1.35.elf'
 
-elif [[ $BOARD == rockpro64 ]]; then
-
-	BOOT_USE_TPL_SPL_BLOB=yes
-	BOOT_SUPPORT_SPI=yes
-	BOOT_SOC=rk3399
-	BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
-
 elif [[ $BOARD == rockpi-s ]]; then
 
-	BOOT_USE_BLOBS=yes
+	BOOT_SCENARIO="${BOOT_SCENARIO:=only-blobs}"
 	BOOT_SOC=rk3308
 	DDR_BLOB='rk33/rk3308_ddr_589MHz_uart2_m1_v1.30.bin'
 	MINILOADER_BLOB='rk33/rk3308_miniloader_v1.22.bin'
@@ -117,11 +75,6 @@ elif [[ $BOARD == rockpi-s ]]; then
 		MINILOADER_BLOB='rk33/rk3308_miniloader_sd_nand_v1.13.bin'
 		BL31_BLOB='rk33/rk3308_bl31_v2.10.elf'
 	fi
-
-else
-
-	ATFPATCHDIR='atf-rk3399'
-
 fi
 
 case $BRANCH in
@@ -147,7 +100,7 @@ esac
 
 prepare_boot_configuration()
 {
-	if [[ $BOOT_USE_MAINLINE_ATF == yes ]]; then
+	if [[ $BOOT_SCENARIO == "blobless" ]]; then
 
 		UBOOT_TARGET_MAP="BL31=bl31.bin idbloader.img u-boot.itb;;idbloader.img u-boot.itb"
 		ATFSOURCE='https://github.com/ARM-software/arm-trusted-firmware'
@@ -158,45 +111,24 @@ prepare_boot_configuration()
 		ATF_TARGET_MAP="M0_CROSS_COMPILE=arm-linux-gnueabi- PLAT=$BOOT_SOC bl31;;build/$BOOT_SOC/release/bl31/bl31.elf:bl31.bin"
 		ATF_TOOLCHAIN2="arm-linux-gnueabi-:> 5.0"
 
-	elif [[ $BOOT_USE_TPL_SPL_BLOB == yes ]]; then
+	elif [[ $BOOT_SCENARIO == "tpl-spl-blob" ]]; then
 
 		UBOOT_TARGET_MAP="BL31=$RKBIN_DIR/$BL31_BLOB idbloader.img u-boot.itb;;idbloader.img u-boot.itb"
 		ATFSOURCE=''
 		ATF_COMPILE='no'
 
-	elif [[ $BOOT_USE_SPL_BLOBS == yes ]]; then
+	elif [[ $BOOT_SCENARIO == "spl-blobs" ]]; then
 
 		UBOOT_TARGET_MAP="BL31=$RKBIN_DIR/$BL31_BLOB spl/u-boot-spl.bin u-boot.dtb u-boot.itb;;idbloader.img u-boot.itb"
 		ATFSOURCE=''
 		ATF_COMPILE='no'
 
-	elif [[ $BOOT_USE_BLOBS == yes ]]; then
+	elif [[ $BOOT_SCENARIO == "only-blobs" ]]; then
 
 		UBOOT_TARGET_MAP="u-boot-dtb.bin;;idbloader.bin uboot.img trust.bin"
 		ATFSOURCE=''
 		ATF_COMPILE='no'
 
-	elif [[ $BOOT_RK3399_LEGACY_HYBRID == yes ]]; then # to be removed
-
-		UBOOT_TARGET_MAP="BL31=$RKBIN_DIR/$BL31_BLOB u-boot-dtb.bin spl/u-boot-spl.bin u-boot.itb;;spl/u-boot-spl.bin u-boot.itb"
-		ATFSOURCE=''
-		ATF_COMPILE='no'
-
-		legacy_uboot_locations
-
-	elif [[ $BOOT_RK3328_USE_AYUFAN_ATF == yes ]]; then # to be removed
-
-		UBOOT_TARGET_MAP=";;idbloader.bin uboot.img trust.bin"
-		ATFSOURCE='https://github.com/ayufan-rock64/arm-trusted-firmware'
-		ATF_COMPILER='aarch64-linux-gnu-'
-		ATFDIR='arm-trusted-firmware-rockchip64'
-		ATFBRANCH='branch:rockchip'
-		ATF_USE_GCC='> 6.3'
-		ATF_TARGET_MAP='PLAT=rk322xh DEBUG=1 bl31;;trust.bin'
-		ATF_TOOLCHAIN2="arm-linux-gnueabi-:> 5.0"
-
-		legacy_uboot_locations
-
 	fi
 
 	if [[ $BOOT_SUPPORT_SPI == yes ]]; then
@@ -206,31 +138,16 @@ prepare_boot_configuration()
 	fi
 }
 
-legacy_uboot_locations()
-{
-	BOOTSOURCE='https://github.com/ayufan-rock64/linux-u-boot'
-	BOOTDIR='u-boot-rockchip64'
-	BOOTBRANCH='branch:rockchip-master'
-	case $BRANCH in
-		legacy)
-			BOOTPATCHDIR="u-boot-rockchip64"
-			;;
-		*)
-			BOOTPATCHDIR="u-boot-rockchip64-dev"
-			;;
-	esac
-}
-
 uboot_custom_postprocess()
 {
 
-	if [[ $BOOT_USE_MAINLINE_ATF == yes || $BOOT_USE_TPL_SPL_BLOB == yes ]]; then
+	if [[ $BOOT_SCENARIO == "blobless" || $BOOT_SCENARIO == "tpl-spl-blob" ]]; then
 		:
-	elif [[ $BOOT_USE_SPL_BLOBS == yes ]]; then
+	elif [[ $BOOT_SCENARIO == "spl-blobs" ]]; then
 
 		tools/mkimage -n $BOOT_SOC -T rksd -d $RKBIN_DIR/$DDR_BLOB:spl/u-boot-spl.bin idbloader.img
 
-	elif [[ $BOOT_USE_BLOBS == yes ]]; then
+	elif [[ $BOOT_SCENARIO == "only-blobs" ]]; then
 
 		local tempfile=$(mktemp)
 		tools/mkimage -n $BOOT_SOC -T rksd -d $RKBIN_DIR/$DDR_BLOB idbloader.bin
@@ -238,27 +155,6 @@ uboot_custom_postprocess()
 		$PKG_PREFIX$RKBIN_DIR/tools/loaderimage --pack --uboot ./u-boot-dtb.bin uboot.img 0x200000
 		$PKG_PREFIX$RKBIN_DIR/tools/trust_merger --replace bl31.elf $RKBIN_DIR/$BL31_BLOB trust.ini
 
-	elif [[ $BOOT_RK3399_LEGACY_HYBRID == yes ]]; then
-
-		# 3399
-		tools/mkimage -n rk3399 -T rksd -d $SRC/cache/sources/rkbin-tools/rk33/rk3399_ddr_933MHz_v1.13.bin rksd_loader.img
-		cat spl/u-boot-spl.bin >> rksd_loader.img
-		dd if=u-boot.itb of=rksd_loader.img seek=448 conv=notrunc
-		cp rksd_loader.img $SRC/.tmp/$uboot_name/usr/lib/$uboot_name/$f_dst
-		tools/mkimage -n rk3399 -T rksd -d $SRC/cache/sources/rkbin-tools/rk33/rk3399_ddr_933MHz_v1.13.bin rkspi_loader.img
-		cat spl/u-boot-spl.bin >> rkspi_loader.img
-		for i in `seq 1 128`; do dd count=4 status=none; dd if=/dev/zero count=4 status=none; done < rkspi_loader.img > rkspi_loader.tmp
-		mv rkspi_loader.tmp rkspi_loader.img
-		dd if=u-boot.itb of=rkspi_loader.img seek=1024 conv=notrunc
-		cp rkspi_loader.img $SRC/.tmp/$uboot_name/usr/lib/$uboot_name/$f_dst
-
-	elif [[ $BOOT_RK3328_USE_AYUFAN_ATF == yes ]]; then
-
-		# 3328
-		tools/mkimage -n rk3328 -T rksd -d $SRC/cache/sources/rkbin-tools/rk33/rk3328_ddr_786MHz_v1.13.bin idbloader.bin
-		cat $SRC/cache/sources/rkbin-tools/rk33/rk3328_miniloader_v2.46.bin >> idbloader.bin
-		$PKG_PREFIX$RKBIN_DIR/tools/loaderimage --pack --uboot ./u-boot-dtb.bin uboot.img 0x200000
-
 	else
 		echo "Unsupported u-boot processing configuration!"
 		exit 1
@@ -278,12 +174,12 @@ write_uboot_platform()
 
 		dd if=$1/rksd_loader.img of=$2 seek=64 conv=notrunc status=none >/dev/null 2>&1
 
-	elif [[ -f $1/u-boot.itb ]]; then # $BOOT_USE_MAINLINE_ATF == yes || $BOOT_USE_TPL_SPL_BLOB == yes
+	elif [[ -f $1/u-boot.itb ]]; then # $BOOT_SCENARIO == "blobless" || $BOOT_SCENARIO == "tpl-spl-blob"
 
 		dd if=$1/idbloader.img of=$2 seek=64 conv=notrunc status=none >/dev/null 2>&1
 		dd if=$1/u-boot.itb of=$2 seek=16384 conv=notrunc status=none >/dev/null 2>&1
 
-	elif [[ -f $1/uboot.img ]]; then # $BOOT_USE_BLOBS == yes
+	elif [[ -f $1/uboot.img ]]; then # $BOOT_SCENARIO == "only-blobs"
 
 		dd if=$1/idbloader.bin of=$2 seek=64 conv=notrunc status=none >/dev/null 2>&1
 		dd if=$1/uboot.img of=$2 seek=16384 conv=notrunc status=none >/dev/null 2>&1
@@ -326,18 +222,6 @@ setup_write_uboot_platform()
 
 }
 
-
-atf_custom_postprocess()
-{
-
-	# remove bl31.bin which can be 4+GiB in size and thus may fill the tmpfs mount
-	rm -f build/rk322xh/debug/bl31.bin
-	# ATF
-	$PKG_PREFIX$RKBIN_DIR/tools/trust_merger trust.ini
-
-}
-
-
 family_tweaks()
 {
 

config/sources/families/rk3399.conf

@@ -1,8 +1,5 @@
 source "${BASH_SOURCE%/*}/include/rockchip64_common.inc"
 
-BOOTPATCHDIR="u-boot-rockchip64-mainline"
-BOOT_SOC="rk3399"
-
 case $BRANCH in
 
 	legacy)
@@ -16,38 +13,6 @@ case $BRANCH in
 
 esac
 
-if [[ $BOARD == roc-rk3399-pc ]]; then
-
-	BOOT_USE_MAINLINE_ATF=yes
-	BOOT_SUPPORT_SPI=yes
-
-elif [[ $BOARD == helios64 ]]; then
-
-	if [[ $BRANCH == legacy || $BRANCH == current ]]; then
-		BOOT_USE_BLOBS=yes
-		DDR_BLOB='rk33/rk3399_ddr_933MHz_v1.24.bin'
-		MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin'
-		BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
-	else
-		BOOT_USE_MAINLINE_ATF=yes
-	fi
-
-elif [[ $BOARD == nanopim4v2 || $BOARD == orangepi4 ]]; then
-
-	BOOT_USE_BLOBS=yes
-	DDR_BLOB='rk33/rk3399_ddr_933MHz_v1.24.bin'
-	MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin'
-	BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
-
-else
-
-	BOOT_USE_BLOBS=yes
-	DDR_BLOB='rk33/rk3399_ddr_800MHz_v1.24.bin'
-	MINILOADER_BLOB='rk33/rk3399_miniloader_v1.19.bin'
-	BL31_BLOB='rk33/rk3399_bl31_v1.30.elf'
-
-fi
-
 prepare_boot_configuration
 
 atf_custom_postprocess()

config/sources/families/rockchip64.conf

@@ -1,7 +1,5 @@
 source "${BASH_SOURCE%/*}/include/rockchip64_common.inc"
 
-BOOTPATCHDIR="u-boot-rockchip64-mainline"
-
 case $BRANCH in
 
 	legacy)

config/sources/families/rockpis.conf

@@ -1,6 +1,6 @@
 source "${BASH_SOURCE%/*}/include/rockchip64_common.inc"
 BOOTBRANCH='tag:v2020.10'
-BOOTPATCHDIR="u-boot-rockchip64-mainline"
+BOOTPATCHDIR="u-boot-rockchip64"
 BOOTENV_FILE='rockpis.txt'
 OVERLAY_PREFIX='rk3308'
 
@@ -10,7 +10,7 @@ case $BRANCH in
 		BOOTCONFIG="rockpi-s-rk3308_defconfig"
 		BOOTSOURCE='https://github.com/piter75/rockchip-u-boot.git'
 		BOOTBRANCH='branch:rockpis-next-dev'
-		BOOTPATCHDIR="u-boot-rockchip64"
+		BOOTPATCHDIR="u-boot-rockpis"
 		UBOOT_COMPILER="aarch64-linux-gnu-"
 		BOOTSCRIPT='boot-rockpis.cmd:boot.cmd'
 		UBOOT_USE_GCC='< 8.0'

lib/build-all-ng.sh

@@ -58,8 +58,8 @@ unset	LINUXFAMILY LINUXCONFIG KERNELDIR KERNELSOURCE KERNELBRANCH BOOTDIR BOOTSO
 		CRYPTROOT_SSH_UNLOCK_PORT CRYPTROOT_SSH_UNLOCK_KEY_NAME ROOT_MAPPER NETWORK HDMI USB WIRELESS ARMBIANMONITOR FORCE_BOOTSCRIPT_UPDATE \
 		UBOOT_TOOLCHAIN2 toolchain2 BUILD_REPOSITORY_URL BUILD_REPOSITORY_COMMIT BUILD_TARGET HOST BUILD_IMAGE DEB_STORAGE REPO_STORAGE REPO_CONFIG \
 		REPOSITORY_UPDATE PACKAGE_LIST_RELEASE LOCAL_MIRROR COMPILE_ATF PACKAGE_LIST_BOARD PACKAGE_LIST_FAMILY PACKAGE_LIST_DESKTOP_BOARD \
-		PACKAGE_LIST_DESKTOP_FAMILY ATF_COMPILE ATFPATCHDIR OFFSET BOOTSOURCEDIR BOOT_USE_BLOBS BOOT_SOC DDR_BLOB MINILOADER_BLOB BL31_BLOB \
-		BOOT_RK3328_USE_AYUFAN_ATF BOOT_USE_BLOBS BOOT_RK3399_LEGACY_HYBRID BOOT_USE_MAINLINE_ATF BOOT_USE_TPL_SPL_BLOB BOOT_USE_SPL_BLOBS BOOT_SUPPORT_SPI OFFLINE_WORK \
+		PACKAGE_LIST_DESKTOP_FAMILY ATF_COMPILE ATFPATCHDIR OFFSET BOOTSOURCEDIR \
+		BOOT_SOC DDR_BLOB MINILOADER_BLOB BL31_BLOB BOOT_SCENARIO BOOT_SUPPORT_SPI OFFLINE_WORK \
 		IMAGE_PARTITION_TABLE BOOT_LOGO UPSTREM_VER FORCED_MONTH_OFFSET PACKAGE_LIST_BOARD_REMOVE PACKAGE_LIST_FAMILY_REMOVE PACKAGE_LIST_DESKTOP \
 		PACKAGE_LIST_DESKTOP_BOARD_REMOVE PACKAGE_LIST_DESKTOP_FAMILY_REMOVE BOOTCONFIG_EDGE DESKTOP_ENVIRONMENT DESKTOP_ENVIRONMENT_CONFIG_NAME \
 		DESKTOP_APPGROUPS_SELECTED DESKTOP_APT_FLAGS_SELECTED DESKTOP_ENVIRONMENT_DIRPATH DESKTOP_ENVIRONMENT_PACKAGE_LIST_DIRPATH UBOOT_TARGET_MAP \

patch/atf/atf-rockchip64/add-trust-ini.patch

@@ -1,21 +0,0 @@
-diff --git a/trust.ini b/trust.ini
-new file mode 100644
-index 0000000..4af021a
---- /dev/null
-+++ b/trust.ini
-@@ -0,0 +1,15 @@
-+[VERSION]
-+MAJOR=1
-+MINOR=2
-+[BL30_OPTION]
-+SEC=0
-+[BL31_OPTION]
-+SEC=1
-+PATH=./build/rk322xh/debug/bl31/bl31.elf
-+ADDR=0x10000
-+[BL32_OPTION]
-+SEC=0
-+[BL33_OPTION]
-+SEC=0
-+[OUTPUT]
-+PATH=trust.bin

patch/atf/atf-rockchip64/board_rockpro64/add-trust-ini.patch

@@ -1,21 +0,0 @@
-diff --git a/trust.ini b/trust.ini
-new file mode 100644
-index 0000000..4af021a
---- /dev/null
-+++ b/trust.ini
-@@ -0,0 +1,15 @@
-+[VERSION]
-+MAJOR=1
-+MINOR=0
-+[BL30_OPTION]
-+SEC=0
-+[BL31_OPTION]
-+SEC=1
-+PATH=./build/rk3399/debug/bl31/bl31.elf
-+ADDR=0x10000
-+[BL32_OPTION]
-+SEC=0
-+[BL33_OPTION]
-+SEC=0
-+[OUTPUT]
-+PATH=trust.bin

patch/atf/atf-rockchip64/rk3328-efuse-init.patch

@@ -1,597 +0,0 @@
-diff --git a/plat/rockchip/rk3328/drivers/efuse/efuse.c b/plat/rockchip/rk3328/drivers/efuse/efuse.c
-new file mode 100644
-index 0000000..05bbcf4
---- /dev/null
-+++ b/plat/rockchip/rk3328/drivers/efuse/efuse.c
-@@ -0,0 +1,397 @@
-+/*
-+ * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd.
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *
-+ * Redistributions of source code must retain the above copyright notice, this
-+ * list of conditions and the following disclaimer.
-+ *
-+ * Redistributions in binary form must reproduce the above copyright notice,
-+ * this list of conditions and the following disclaimer in the documentation
-+ * and/or other materials provided with the distribution.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <common/debug.h>
-+#include <drivers/delay_timer.h>
-+#include <lib/mmio.h>
-+#include <platform_def.h>
-+#include <efuse.h>
-+#include <string.h>
-+
-+#define EFUSE_AUTO_MODE		1 // RK3328 wants auto mode on
-+
-+#define read32(reg)			mmio_read_32(reg)
-+#define write32(v, reg)			mmio_write_32(reg, v)
-+#define efuse8_read(offset)		mmio_read_32(EFUSE8_BASE + offset)
-+#define efuse8_write(v, offset)		mmio_write_32(EFUSE8_BASE + offset, v)
-+#define efuse32_read(offset)		mmio_read_32(EFUSE32_BASE + offset)
-+#define efuse32_write(v, offset)	mmio_write_32(EFUSE32_BASE + offset, v)
-+
-+/* global buf to store efuse data */
-+static uint32_t efuse32_buf[32] = {0};
-+
-+enum clk_type {
-+	CLK = 0,
-+	PCLK,
-+};
-+
-+int enable_efuse_clk()
-+{
-+
-+	uint32_t reg = 0;
-+
-+	reg = read32(CRU_BASE + CRU_CLKGATE_CON2);
-+	/* enable efuse work clk */
-+	if (reg & EFUSE_SRC_CLK_EN)
-+		write32(EFUSE_SRC_CLK_EN << CRU_WRITE_MASK,
-+			CRU_BASE + CRU_CLKGATE_CON2);
-+
-+	reg = read32(CRU_BASE + CRU_CLKGATE_CON15);
-+	/* enable efuse APB clk */
-+	if (reg & EFUSE_1024_PCLK_EN)
-+		write32(EFUSE_1024_PCLK_EN << CRU_WRITE_MASK,
-+			CRU_BASE + CRU_CLKGATE_CON15);
-+
-+	return reg;
-+
-+}
-+
-+/*
-+static uint32_t enable_efuse_clk(int clk)
-+{
-+	uint32_t reg = 0;
-+
-+	switch (clk) {
-+	case CLK:
-+		reg = read32(CRU_BASE + CRU_CLKGATE_CON2);
-+		// enable efuse work clk
-+		if (reg & EFUSE_SRC_CLK_EN)
-+			write32(EFUSE_SRC_CLK_EN << CRU_WRITE_MASK,
-+				CRU_BASE + CRU_CLKGATE_CON2);
-+		break;
-+	case PCLK:
-+		reg = read32(CRU_BASE + CRU_CLKGATE_CON15);
-+		// enable efuse APB clk 
-+		if (reg & EFUSE_1024_PCLK_EN)
-+			write32(EFUSE_1024_PCLK_EN << CRU_WRITE_MASK,
-+				CRU_BASE + CRU_CLKGATE_CON15);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return reg;
-+}
-+*/
-+
-+static void restore_efuse_clk(int clk, uint32_t reg)
-+{
-+	switch (clk) {
-+	case CLK:
-+		/* disable efuse work clk */
-+		if (reg & EFUSE_SRC_CLK_EN)
-+			write32(reg | (EFUSE_SRC_CLK_EN << CRU_WRITE_MASK),
-+				CRU_BASE + CRU_CLKGATE_CON2);
-+		break;
-+	case PCLK:
-+		/* disable efuse APB clk */
-+		if (reg & EFUSE_1024_PCLK_EN)
-+			write32(reg | (EFUSE_1024_PCLK_EN << CRU_WRITE_MASK),
-+				CRU_BASE + CRU_CLKGATE_CON15);
-+		break;
-+	default:
-+		return;
-+	}
-+}
-+
-+/* user mode and auto mode */
-+int rk_efuse32_readregs(uint32_t addr, uint32_t length, uint32_t *buf)
-+{
-+	uint32_t reg0 = 0;
-+	uint32_t reg1 = 0;
-+
-+	uint32_t efuse_base = 0;
-+
-+	if (addr > 31)
-+		return -1;
-+	if (length < 1 || length > 32)
-+		return -1;
-+	if (!buf)
-+		return -1;
-+
-+	if (addr < 24) {
-+		if (addr + length < 25)
-+			efuse_base = EFUSE32_BASE;
-+		else
-+			return -1;
-+	}
-+	if (addr > 23) {
-+		if (addr + length < 33)
-+			efuse_base = EFUSE8_BASE;
-+		else
-+			return -1;
-+	}
-+
-+	//reg0 = enable_efuse_clk(CLK);
-+	//reg1 = enable_efuse_clk(PCLK);
-+
-+#if EFUSE_AUTO_MODE
-+	do {
-+		write32(EFUSE_AUTO_RD | EFUSE_AUTO_ENABLE |
-+			((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT),
-+			efuse_base + REG_EFUSE_AUTO_CTRL);
-+		udelay(2);
-+		while (1) {
-+			if (read32(efuse_base + REG_EFUSE_INT_STATUS) & 0x01)
-+				break;
-+		}
-+		*buf = read32(efuse_base + REG_EFUSE_DOUT);
-+		write32(read32(efuse_base + REG_EFUSE_AUTO_CTRL) &
-+			(~EFUSE_AUTO_ENABLE), efuse_base + REG_EFUSE_AUTO_CTRL);
-+		write32(0x07, efuse_base + REG_EFUSE_INT_STATUS);
-+		buf++;
-+		addr++;
-+
-+	} while (--length);
-+#else
-+	/* enable read in user mode */
-+	write32((read32(efuse_base + REG_EFUSE_MOD) | EFUSE_RD_ENB_USER) &
-+		(~EFUSE_PG_ENB_USER), efuse_base + REG_EFUSE_MOD);
-+	write32(EFUSE_CSB, efuse_base + REG_EFUSE_CTRL);
-+	write32(EFUSE_LOAD | EFUSE_PGENB, efuse_base + REG_EFUSE_CTRL);
-+	udelay(2);
-+	do {
-+		write32(read32(efuse_base + REG_EFUSE_CTRL) &
-+			(~(EFUSE_A_MASK << EFUSE_A_SHIFT)),
-+			efuse_base + REG_EFUSE_CTRL);
-+		write32(read32(efuse_base + REG_EFUSE_CTRL) |
-+			((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT),
-+			efuse_base + REG_EFUSE_CTRL);
-+
-+		udelay(2);
-+		write32(read32(efuse_base + REG_EFUSE_CTRL) |
-+			EFUSE_STROBE, efuse_base + REG_EFUSE_CTRL);
-+		udelay(2);
-+		*buf = read32(efuse_base + REG_EFUSE_DOUT);
-+		write32(read32(efuse_base + REG_EFUSE_CTRL) &
-+			(~EFUSE_STROBE), efuse_base + REG_EFUSE_CTRL);
-+		udelay(2);
-+		buf++;
-+		addr++;
-+	} while (--length);
-+	udelay(2);
-+	write32(read32(efuse_base + REG_EFUSE_CTRL) | EFUSE_CSB,
-+		efuse_base + REG_EFUSE_CTRL);
-+	udelay(1);
-+#endif /* EFUSE_AUTO_MODE */
-+
-+	restore_efuse_clk(CLK, reg0);
-+	restore_efuse_clk(PCLK, reg1);
-+
-+	return 0;
-+}
-+
-+/*user mode and auto mode*/
-+int rk_efuse32_write(uint32_t addr, uint32_t val)
-+{
-+	uint32_t reg0 = 0, reg1 = 0, efuse_base = 0;
-+
-+	if (addr > 31)
-+		return -1;
-+
-+	if (addr < 24)
-+		efuse_base = EFUSE32_BASE;
-+	if (addr > 23 && addr < 32)
-+		efuse_base = EFUSE8_BASE;
-+
-+	//reg0 = enable_efuse_clk(CLK);
-+	//reg1 = enable_efuse_clk(PCLK);
-+
-+#if EFUSE_AUTO_MODE
-+	while (val) {
-+		if (val & 0x01) {
-+			write32((EFUSE_AUTO_ENABLE |
-+				((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT))
-+				& (~EFUSE_AUTO_RD),
-+				efuse_base + REG_EFUSE_AUTO_CTRL);
-+			udelay(2);
-+			while (1) {
-+				if (read32(efuse_base + REG_EFUSE_INT_STATUS) &
-+					   0x01)
-+					break;
-+			}
-+			write32(read32(efuse_base + REG_EFUSE_AUTO_CTRL) &
-+				(~EFUSE_AUTO_ENABLE),
-+				efuse_base + REG_EFUSE_AUTO_CTRL);
-+			write32(0x07, efuse_base + REG_EFUSE_INT_STATUS);
-+			udelay(2);
-+		}
-+		addr += 32;
-+		val = val >> 1;
-+		udelay(2);
-+	}
-+#else
-+	/* enable program in user mode */
-+	write32((read32(efuse_base + REG_EFUSE_MOD) | EFUSE_PG_ENB_USER) &
-+		(~EFUSE_RD_ENB_USER), efuse_base + REG_EFUSE_MOD);
-+	write32(EFUSE_CSB | EFUSE_LOAD | EFUSE_PGENB,
-+		efuse_base + REG_EFUSE_CTRL);
-+	write32(read32(efuse_base + REG_EFUSE_CTRL) & (~EFUSE_CSB),
-+		efuse_base + REG_EFUSE_CTRL);
-+	write32(read32(efuse_base + REG_EFUSE_CTRL) & (~EFUSE_PGENB) &
-+		(~EFUSE_LOAD), efuse_base + REG_EFUSE_CTRL);
-+	udelay(2);
-+
-+	while (val) {
-+		if (val & 0x01) {
-+			write32(read32(efuse_base + REG_EFUSE_CTRL) &
-+				(~(EFUSE_A_MASK << EFUSE_A_SHIFT)),
-+				efuse_base + REG_EFUSE_CTRL);
-+			write32(read32(efuse_base + REG_EFUSE_CTRL) |
-+				((addr & EFUSE_A_MASK) << EFUSE_A_SHIFT),
-+				efuse_base + REG_EFUSE_CTRL);
-+			udelay(2);
-+			write32(read32(efuse_base + REG_EFUSE_CTRL) |
-+				EFUSE_STROBE, efuse_base + REG_EFUSE_CTRL);
-+			udelay(10);
-+			write32(read32(efuse_base + REG_EFUSE_CTRL) &
-+				(~EFUSE_STROBE),
-+				efuse_base + REG_EFUSE_CTRL);
-+			udelay(2);
-+		}
-+		addr += 32;
-+		val = val >> 1;
-+	}
-+
-+	udelay(2);
-+	write32(read32(efuse_base + REG_EFUSE_CTRL) | EFUSE_LOAD |
-+		EFUSE_PGENB, efuse_base + REG_EFUSE_CTRL);
-+	write32(read32(efuse_base + REG_EFUSE_CTRL) | EFUSE_CSB,
-+		efuse_base + REG_EFUSE_CTRL);
-+	udelay(1);
-+#endif /* EFUSE_AUTO_MODE */
-+
-+	restore_efuse_clk(CLK, reg0);
-+	restore_efuse_clk(PCLK, reg1);
-+
-+	return 0;
-+}
-+
-+int rk_efuse32_read(uint32_t addr, uint32_t length, uint32_t *buf)
-+{
-+	if (!buf)
-+		return -1;
-+
-+	if (addr > 23) {
-+		if (length < 1 || length + addr > 32)
-+			return -1;
-+
-+		memcpy(buf, efuse32_buf + addr, length * sizeof(uint32_t));
-+	} else if (addr < 24) {
-+		if (length < 1 || length + addr > 24)
-+			return -1;
-+
-+		memcpy(buf, efuse32_buf + addr, length * sizeof(uint32_t));
-+	}
-+
-+	return 0;
-+}
-+
-+void mode_init(int sec)
-+{
-+	int reg;
-+	uint32_t efuse_base = 0;
-+
-+	if (sec == 1)
-+		efuse_base = EFUSE32_BASE;/*secure efuse addr*/
-+	if (sec == 0)
-+		efuse_base = EFUSE8_BASE;/*un_secure efsue addr*/
-+
-+#if EFUSE_AUTO_MODE
-+	/* enable auto mode */
-+	reg = read32(efuse_base + REG_EFUSE_MOD);
-+	write32(reg & (~EFUSE_USER_MODE), efuse_base + REG_EFUSE_MOD);
-+
-+	/* enable finish & auto_s_access_ns_err & auto_ns_access_s_err int */
-+	write32(0x07, efuse_base + REG_EFUSE_INT_CON);
-+	write32((T_CSB_P_S << 16) | T_CSB_P_L,
-+		efuse_base + REG_EFUSE_T_CSB_P);
-+	write32((T_PGENB_P_S << 16) | T_PGENB_P_L,
-+		efuse_base + REG_EFUSE_T_PGENB_P);
-+	write32((T_LOAD_P_S << 16) | T_LOAD_P_L,
-+		efuse_base + REG_EFUSE_T_LOAD_P);
-+	write32((T_ADDR_P_S << 16) | T_ADDR_P_L,
-+		efuse_base + REG_EFUSE_T_ADDR_P);
-+	write32((T_STROBE_P_S << 16) | T_STROBE_P_L,
-+		efuse_base + REG_EFUSE_T_STROBE_P);
-+	write32((T_CSB_R_S << 16) | T_CSB_R_L,
-+		efuse_base + REG_EFUSE_T_CSB_R);
-+	write32((T_PGENB_R_S << 16) | T_PGENB_R_L,
-+		efuse_base + REG_EFUSE_T_PGENB_R);
-+	write32((T_LOAD_R_S << 16) | T_LOAD_R_L,
-+		efuse_base + REG_EFUSE_T_LOAD_R);
-+	write32((T_ADDR_R_S << 16) | T_ADDR_R_L,
-+		efuse_base + REG_EFUSE_T_ADDR_R);
-+	write32((T_STROBE_R_S << 16) | T_STROBE_R_L,
-+		efuse_base + REG_EFUSE_T_STROBE_R);
-+#else
-+	reg = read32(efuse_base + REG_EFUSE_MOD);
-+	write32(reg | EFUSE_USER_MODE, efuse_base + REG_EFUSE_MOD);
-+#endif /* EFUSE_AUTO_MODE */
-+}
-+
-+void rk_efuse_prog_en(int n)
-+{
-+	if (n == 1) {
-+		write32(read32(GPIO2_BASE) & (~(0X1 << 3)), GPIO2_BASE);
-+		write32((efuse_pwren | efuse_pwren << 16) |
-+			((0) << 7 | efuse_pwren << 16 << 1),
-+			GRF_BASE + GRF_GPIO2A_IOMUX);
-+		/*efuse program enable*/
-+		write32((1 << 7) | (1 << 7 << 16), SGRF_BASE +
-+			EFUSE_SGRF_SOC_CON5);
-+	} else {
-+		write32((0 << 7) | (1 << 7 << 16),
-+			SGRF_BASE + EFUSE_SGRF_SOC_CON5);
-+		write32(0 << 6 | efuse_pwren << 16 |
-+			((0) << 7 | efuse_pwren << 16 << 1),
-+			GRF_BASE + GRF_GPIO2A_IOMUX);
-+		write32(read32(GPIO2_BASE) | (0X1 << 3), GPIO2_BASE);
-+	}
-+}
-+
-+int rk_efuse_init(void)
-+{
-+	mode_init(1);
-+	mode_init(0);
-+
-+	if (rk_efuse32_readregs(RK322XH_S_EFUSE_START,
-+				RK322XH_S_EFUSE_WORDS,
-+				efuse32_buf)) {
-+		ERROR("read S-efuse failed!!!!\n");
-+		return -1;
-+	}
-+
-+	if (rk_efuse32_readregs(RK322XH_NS_EFUSE_START,
-+				RK322XH_NS_EFUSE_WORDS,
-+				efuse32_buf + RK322XH_NS_EFUSE_START)) {
-+		ERROR("read NS-efuse failed!!!!\n");
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-diff --git a/plat/rockchip/rk3328/drivers/efuse/efuse.h b/plat/rockchip/rk3328/drivers/efuse/efuse.h
-new file mode 100644
-index 0000000..22275c2
---- /dev/null
-+++ b/plat/rockchip/rk3328/drivers/efuse/efuse.h
-@@ -0,0 +1,142 @@
-+/*
-+ * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd.
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *
-+ * Redistributions of source code must retain the above copyright notice, this
-+ * list of conditions and the following disclaimer.
-+ *
-+ * Redistributions in binary form must reproduce the above copyright notice,
-+ * this list of conditions and the following disclaimer in the documentation
-+ * and/or other materials provided with the distribution.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef EFUSE_H
-+#define EFUSE_H
-+
-+#include <platform_def.h>
-+
-+/* CRU controller register */
-+#define CRU_WRITE_MASK		(16)
-+
-+#define GRF_GPIO2A_IOMUX	(0x0020)
-+#define EFUSE_SGRF_SOC_CON5	(0X0014)
-+
-+#define CRU_CLKGATE_CON2	(0x0208)
-+#define CRU_CLKGATE_CON15	(0x023C)
-+#define EFUSE_SRC_CLK_EN	(1 << 13)
-+#define EFUSE_1024_PCLK_EN	(1 << 9)
-+
-+#define RK322XH_S_EFUSE_START	0
-+#define RK322XH_S_EFUSE_WORDS	24
-+#define RK322XH_NS_EFUSE_START	(RK322XH_S_EFUSE_START + RK322XH_S_EFUSE_WORDS)
-+#define RK322XH_NS_EFUSE_WORDS	8
-+
-+/* SGRF controller register */
-+#define SGRF_WRITE_MASK		(16)
-+
-+/* eFuse controller register */
-+#define CRU_CLKSEL_CON5		(0x0114)
-+#define REG_EFUSE_MOD		(0x0000)
-+#define efuse_pwren		(1 << 6)
-+#define EFUSE_RD_ENB_USER	(1 << 6)
-+#define EFUSE_PG_ENB_USER	(1 << 5)
-+#define EFUSE_STROBE_POL	(1 << 4)
-+#define EFUSE_LOAD_POL		(1 << 3)
-+#define EFUSE_PGENB_POL		(1 << 2)
-+#define EFUSE_CSB_POL		(1 << 1)
-+/* 0:auto mode; 1:user mode */
-+#define EFUSE_USER_MODE		(1 << 0)
-+
-+#define REG_EFUSE_RD_MASK_S	(0x0004)
-+#define REG_EFUSE_PG_MASK_S	(0x0008)
-+
-+#define REG_EFUSE_RD_MASK_NS	(0x000C)
-+#define REG_EFUSE_PG_MASK_NS	(0x0010)
-+
-+#define REG_EFUSE_INT_CON	(0x0014)
-+#define REG_EFUSE_INT_STATUS	(0x0018)
-+#define REG_EFUSE_USER_CTRL	(0x001C)
-+#define EFUSE_A_SHIFT		(16)
-+#define EFUSE_A_MASK		(0x3FF)
-+#define EFUSE_PGENB		(1 << 3) /* active low */
-+#define EFUSE_LOAD		(1 << 2)
-+#define EFUSE_STROBE		(1 << 1)
-+#define EFUSE_CSB		(1 << 0) /* active low */
-+#define REG_EFUSE_DOUT		(0x0020)
-+#define REG_EFUSE_AUTO_CTRL	(0x0024)
-+/* 0:programming mode; 1:read mode */
-+#define EFUSE_AUTO_RD		(1 << 1)
-+#define EFUSE_AUTO_ENABLE	(1 << 0)
-+
-+#define EFUSE_PG_ENB_MODE	(0 << 1)
-+
-+#define REG_EFUSE_T_CSB_P	(0x0028)
-+#define REG_EFUSE_T_PGENB_P	(0x002C)
-+#define REG_EFUSE_T_LOAD_P	(0x0030)
-+#define REG_EFUSE_T_ADDR_P	(0x0034)
-+#define REG_EFUSE_T_STROBE_P	(0x0038)
-+#define REG_EFUSE_T_CSB_R	(0x003C)
-+#define REG_EFUSE_T_PGENB_R	(0x0040)
-+#define REG_EFUSE_T_LOAD_R	(0x0044)
-+#define REG_EFUSE_T_ADDR_R	(0x0048)
-+#define REG_EFUSE_T_STROBE_R	(0x004C)
-+#define REG_EFUSE_REVISION	(0x0050)
-+#define REG_EFUSE_CTRL		REG_EFUSE_USER_CTRL
-+
-+#define T_CSB_P_S		1
-+#define T_PGENB_P_S		1
-+#define T_LOAD_P_S		1
-+#define T_ADDR_P_S		1
-+#define T_STROBE_P_S		2
-+#define T_CSB_P_L		241
-+#define T_PGENB_P_L		241
-+#define T_LOAD_P_L		241
-+#define T_ADDR_P_L		241
-+#define T_STROBE_P_L		240
-+#define T_CSB_R_S		1
-+#define T_PGENB_R_S		1
-+#define T_LOAD_R_S		1
-+#define T_ADDR_R_S		1
-+#define T_STROBE_R_S		2
-+#define T_CSB_R_L		4
-+#define T_PGENB_R_L		4
-+#define T_LOAD_R_L		4
-+#define T_ADDR_R_L		4
-+#define T_STROBE_R_L		3
-+
-+/*
-+ * readregs function is real-time read, from the efuse hardware.
-+ * read function is not real-time read, read the value stored in
-+ * memory when machine starting up.
-+ */
-+int rk_efuse8_readregs(uint32_t addr, uint32_t length, uint8_t *buf);
-+int rk_efuse8_write(uint32_t addr, uint8_t val);
-+
-+int rk_efuse32_readregs(uint32_t addr, uint32_t length, uint32_t *buf);
-+int rk_efuse32_write(uint32_t addr, uint32_t val);
-+int rk_efuse32_read(uint32_t addr, uint32_t length, uint32_t *buf);
-+
-+int enable_efuse_clk();
-+
-+void mode_init(int sec);
-+void rk_efuse_prog_en(int n);
-+
-+int rk_efuse_init(void);
-+
-+#endif /* RK_EFUSE_H */
-+
-diff --git a/plat/rockchip/rk3328/drivers/soc/soc.c b/plat/rockchip/rk3328/drivers/soc/soc.c
-index 306308f..48a001c 100644
---- a/plat/rockchip/rk3328/drivers/soc/soc.c
-+++ b/plat/rockchip/rk3328/drivers/soc/soc.c
-@@ -16,6 +16,7 @@
- #include <plat_private.h>
- #include <rk3328_def.h>
- #include <soc.h>
-+#include <efuse.h>
- 
- /* Table of regions to map using the MMU. */
- const mmap_region_t plat_rk_mmap[] = {
-@@ -153,6 +154,11 @@ void plat_rockchip_soc_init(void)
- 	secure_timer_init();
- 	sgrf_init();
- 
-+	mode_init(1);
-+	mode_init(0);
-+
-+	enable_efuse_clk();
-+
- 	NOTICE("BL31:Rockchip release version: v%d.%d\n",
- 	       MAJOR_VERSION, MINOR_VERSION);
- }
-diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
-index 0219422..8c570b2 100644
---- a/plat/rockchip/rk3328/platform.mk
-+++ b/plat/rockchip/rk3328/platform.mk
-@@ -20,6 +20,7 @@ PLAT_INCLUDES		:=	-Idrivers/arm/gic/common/			\
- 				-I${RK_PLAT_SOC}/				\
- 				-I${RK_PLAT_SOC}/drivers/pmu/			\
- 				-I${RK_PLAT_SOC}/drivers/soc/			\
-+				-I${RK_PLAT_SOC}/drivers/efuse/			\
- 				-I${RK_PLAT_SOC}/include/
- 
- RK_GIC_SOURCES		:=	drivers/arm/gic/common/gic_common.c		\
-@@ -50,7 +51,8 @@ BL31_SOURCES		+=	${RK_GIC_SOURCES}				\
- 				${RK_PLAT_COMMON}/plat_topology.c		\
- 				${RK_PLAT_COMMON}/aarch64/platform_common.c	\
- 				${RK_PLAT_SOC}/drivers/pmu/pmu.c		\
--				${RK_PLAT_SOC}/drivers/soc/soc.c
-+				${RK_PLAT_SOC}/drivers/soc/soc.c		\
-+				${RK_PLAT_SOC}/drivers/efuse/efuse.c
- 
- ifdef PLAT_RK_SECURE_DDR_MINILOADER
- BL31_SOURCES		+=	${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c

patch/u-boot/u-boot-rockchip64-edge/add-board-renegade.patch

@@ -1,552 +0,0 @@
-From 3f87b0c622e246f138d4d32c599fa087b880cade Mon Sep 17 00:00:00 2001
-From: zouxf <zxf@t-tchip.com.cn>
-Date: Tue, 6 Mar 2018 15:05:58 +0800
-Subject: [PATCH] firefly: add roc-rk3328-cc board support
-
-Change-Id: Idb11a95a01c828da1e4818e6b4814a448b754f6b
----
- arch/arm/dts/Makefile                        |   1 +
- arch/arm/dts/rk3328-roc-cc.dts               | 231 +++++++++++++++++++
- arch/arm/mach-rockchip/rk3328/Kconfig        |  11 +
- board/rockchip/roc_rk3328_cc/Kconfig         |  15 ++
- board/rockchip/roc_rk3328_cc/Makefile        |   7 +
- board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c |  85 +++++++
- configs/roc-rk3328-cc_defconfig              |  97 ++++++++
- include/configs/roc_rk3328_cc.h              |  18 ++
- 8 files changed, 465 insertions(+)
- create mode 100644 arch/arm/dts/rk3328-roc-cc.dts
- create mode 100644 board/rockchip/roc_rk3328_cc/Kconfig
- create mode 100644 board/rockchip/roc_rk3328_cc/Makefile
- create mode 100644 board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c
- create mode 100644 configs/roc-rk3328-cc_defconfig
- create mode 100644 include/configs/roc_rk3328_cc.h
-
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index 0032a21377..f548703a2a 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -46,6 +46,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
- 	rk3288-veyron-mickey.dtb \
- 	rk3288-veyron-minnie.dtb \
- 	rk3328-evb.dtb \
-+	rk3328-roc-cc.dtb \
-	rk3328-rock64.dtb \
- 	rk3368-lion.dtb \
- 	rk3368-sheep.dtb \
-diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts
-new file mode 100644
-index 0000000000..4f3c2cf935
---- /dev/null
-+++ b/arch/arm/dts/rk3328-roc-cc.dts
-@@ -0,0 +1,231 @@
-+/*
-+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
-+ *
-+ * SPDX-License-Identifier:     GPL-2.0+
-+ */
-+
-+/dts-v1/;
-+#include "rk3328.dtsi"
-+#include "rk3328-sdram-ddr3-666.dtsi"
-+
-+/ {
-+	model = "Firefly ROC-RK3328-CC";
-+	compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
-+
-+	chosen {
-+		stdout-path = &uart2;
-+	};
-+
-+	vcc3v3_sdmmc: sdmmc-pwren {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3";
-+		gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
-+		regulator-always-on;
-+		regulator-boot-on;
-+	};
-+
-+	vcc5v0_otg: vcc5v0-otg-drv {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		regulator-name = "vcc5v0_otg";
-+		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
-+		status = "disabled";	//usb host xhci and usb otg use the same gpio to enable power
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		regulator-name = "vcc5v0_host_xhci";
-+		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+};
-+
-+&saradc {
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	u-boot,dm-pre-reloc;
-+	status = "okay";
-+};
-+
-+&sdmmc {
-+	bus-width = <4>;
-+	cap-mmc-highspeed;
-+	cap-sd-highspeed;
-+	card-detect-delay = <200>;
-+	disable-wp;
-+	num-slots = <1>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+	status = "okay";
-+};
-+
-+&emmc {
-+	u-boot,dm-pre-reloc;
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	supports-emmc;
-+	disable-wp;
-+	non-removable;
-+	num-slots = <1>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-+	status = "okay";
-+};
-+
-+&u2phy {
-+        status = "okay";
-+};
-+
-+&u2phy_otg {
-+        status = "okay";
-+};
-+
-+&u2phy_host {
-+        status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb20_otg {
-+	vbus-supply = <&vcc5v0_otg>;
-+	status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+	vbus-supply = <&vcc5v0_host_xhci>;
-+	status = "okay";
-+};
-+
-+&i2c1 {
-+	clock-frequency = <400000>;
-+	i2c-scl-rising-time-ns = <168>;
-+	i2c-scl-falling-time-ns = <4>;
-+	status = "okay";
-+
-+	rk805: pmic@18 {
-+		compatible = "rockchip,rk805";
-+		status = "okay";
-+		reg = <0x18>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int_l>;
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		#clock-cells = <1>;
-+		clock-output-names = "xin32k", "rk805-clkout2";
-+
-+		pwrkey {
-+			status = "okay";
-+		};
-+
-+		regulators {
-+			vdd_logic: DCDC_REG1 {
-+				regulator-name = "vdd_logic";
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-ramp-delay = <6001>;
-+				regulator-boot-on;
-+				regulator-always-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+
-+			vdd_arm: DCDC_REG2 {
-+				regulator-name = "vdd_arm";
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-ramp-delay = <6001>;
-+				regulator-boot-on;
-+				regulator-always-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-boot-on;
-+				regulator-always-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vcc_io: DCDC_REG4 {
-+				regulator-name = "vcc_io";
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-boot-on;
-+				regulator-always-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vdd_18: LDO_REG1 {
-+				regulator-name = "vdd_18";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-boot-on;
-+				regulator-always-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc_18emmc: LDO_REG2 {
-+				regulator-name = "vcc_18emmc";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-boot-on;
-+				regulator-always-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vdd_10: LDO_REG3 {
-+				regulator-name = "vdd_10";
-+				regulator-min-microvolt = <1000000>;
-+				regulator-max-microvolt = <1000000>;
-+				regulator-boot-on;
-+				regulator-always-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&pinctrl {
-+	pmic {
-+		pmic_int_l: pmic-int-l {
-+		rockchip,pins =
-+			<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;	/* gpio1_d0 */
-+		};
-+	};
-+};
-+
-diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
-index 43afba2430..0faf50085f 100644
---- a/arch/arm/mach-rockchip/rk3328/Kconfig
-+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
-@@ -10,6 +10,16 @@ config TARGET_EVB_RK3328
- 	  with full function and phisical connectors support like
- 	  usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
- 
-+config TARGET_ROC_RK3328_CC
-+	bool "ROC-RK3328-CC board, "
-+	help
-+  	  ROC-RK3328-CC is a Raspberry Pi-2 sized 4K60P HDR Media Board Computer
-+  	  powered by Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor
-+  	  and support up to 4GB 2133MHz DDR4 memory.
-+  	  It provides eMMC module socket, MicroSD Card slot, Pi-2 Bus, Pi-P5+ Bus,
-+  	  USB 3.0 and many others peripheral devices interface for makers
-+  	  to integrate with sensors and devices
-+
- endchoice
- 
- config SYS_SOC
-@@ -19,5 +29,6 @@ config SYS_MALLOC_F_LEN
- 	default 0x0800
- 
- source "board/rockchip/evb_rk3328/Kconfig"
-+source "board/rockchip/roc_rk3328_cc/Kconfig"
- source "board/rockchip/rock64_rk3328/Kconfig"
- 
-diff --git a/board/rockchip/roc_rk3328_cc/Kconfig b/board/rockchip/roc_rk3328_cc/Kconfig
-new file mode 100644
-index 0000000000..074894a911
---- /dev/null
-+++ b/board/rockchip/roc_rk3328_cc/Kconfig
-@@ -0,0 +1,15 @@
-+if TARGET_ROC_RK3328_CC
-+
-+config SYS_BOARD
-+	default "roc_rk3328_cc"
-+
-+config SYS_VENDOR
-+	default "rockchip"
-+
-+config SYS_CONFIG_NAME
-+	default "roc_rk3328_cc"
-+
-+config BOARD_SPECIFIC_OPTIONS # dummy
-+	def_bool y
-+
-+endif
-diff --git a/board/rockchip/roc_rk3328_cc/Makefile b/board/rockchip/roc_rk3328_cc/Makefile
-new file mode 100644
-index 0000000000..79290147ee
---- /dev/null
-+++ b/board/rockchip/roc_rk3328_cc/Makefile
-@@ -0,0 +1,7 @@
-+#
-+# (C) Copyright 2018 FIREFLY
-+#
-+# SPDX-License-Identifier:     GPL-2.0+
-+#
-+
-+obj-y	+= roc-rk3328-cc.o
-diff --git a/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c b/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c
-new file mode 100644
-index 0000000000..3ff12301fe
---- /dev/null
-+++ b/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c
-@@ -0,0 +1,85 @@
-+/*
-+ * (C) Copyright 2018 FIREFLY
-+ *
-+ * SPDX-License-Identifier:     GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <asm/arch/hardware.h>
-+#include <asm/arch/grf_rk3328.h>
-+#include <asm/armv8/mmu.h>
-+#include <asm/io.h>
-+#include <dwc3-uboot.h>
-+#include <power/regulator.h>
-+#include <usb.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+int board_init(void)
-+{
-+	int ret;
-+#define GRF_BASE	0xff100000
-+	struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
-+
-+	/* uart2 select m1, sdcard select m1*/
-+	rk_clrsetreg(&grf->com_iomux,
-+		     IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
-+		     IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
-+		     IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
-+
-+	ret = regulators_enable_boot_on(false);
-+	if (ret)
-+		debug("%s: Cannot enable boot on regulator\n", __func__);
-+
-+#define GRF_SOC_CON10		0xff100428
-+	rk_setreg(GRF_SOC_CON10, (BIT(1) << 16) | (0 << 1));
-+
-+	return ret;
-+}
-+
-+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-+#include <usb.h>
-+#include <usb/dwc2_udc.h>
-+
-+static struct dwc2_plat_otg_data rk3328_otg_data = {
-+	.rx_fifo_sz	= 512,
-+	.np_tx_fifo_sz	= 16,
-+	.tx_fifo_sz	= 128,
-+};
-+
-+int board_usb_init(int index, enum usb_init_type init)
-+{
-+	int node;
-+	const char *mode;
-+	bool matched = false;
-+	const void *blob = gd->fdt_blob;
-+
-+	/* find the usb_otg node */
-+	node = fdt_node_offset_by_compatible(blob, -1,
-+					"rockchip,rk3328-usb");
-+
-+	while (node > 0) {
-+		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-+		if (mode && strcmp(mode, "otg") == 0) {
-+			matched = true;
-+			break;
-+		}
-+
-+		node = fdt_node_offset_by_compatible(blob, node,
-+					"rockchip,rk3328-usb");
-+	}
-+	if (!matched) {
-+		debug("Not found usb_otg device\n");
-+		return -ENODEV;
-+	}
-+
-+	rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-+
-+	return dwc2_udc_probe(&rk3328_otg_data);
-+}
-+
-+int board_usb_cleanup(int index, enum usb_init_type init)
-+{
-+	return 0;
-+}
-+#endif
-diff --git a/configs/roc-rk3328-cc_defconfig b/configs/roc-rk3328-cc_defconfig
-new file mode 100644
-index 0000000000..9a75395f38
---- /dev/null
-+++ b/configs/roc-rk3328-cc_defconfig
-@@ -0,0 +1,97 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SPL_LIBCOMMON_SUPPORT=y
-+CONFIG_SPL_LIBGENERIC_SUPPORT=y
-+CONFIG_SYS_MALLOC_F_LEN=0x2000
-+CONFIG_ROCKCHIP_RK3328=y
-+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
-+CONFIG_TPL_LIBCOMMON_SUPPORT=y
-+CONFIG_TPL_LIBGENERIC_SUPPORT=y
-+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-+CONFIG_TARGET_ROC_RK3328_CC=y
-+CONFIG_SPL_STACK_R_ADDR=0x600000
-+CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
-+CONFIG_SMBIOS_PRODUCT_NAME="roc_rk3328_roc"
-+CONFIG_DEBUG_UART=y
-+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-+# CONFIG_ANDROID_BOOT_IMAGE is not set
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_SPL_LOAD_FIT=y
-+CONFIG_SPL_FIT_GENERATOR="board/rockchip/evb_rk3328/mk_fit_atf.sh"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
-+CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_ATF_SUPPORT=y
-+CONFIG_TPL_BOOTROM_SUPPORT=y
-+CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
-+CONFIG_FASTBOOT_BUF_ADDR=0x800800
-+CONFIG_FASTBOOT_FLASH=y
-+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
-+CONFIG_CMD_BOOTZ=y
-+# CONFIG_CMD_IMLS is not set
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_USB=y
-+CONFIG_CMD_SETEXPR=y
-+CONFIG_CMD_TIME=y
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_TPL_OF_CONTROL=y
-+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_TPL_OF_PLATDATA=y
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_TPL_DM=y
-+CONFIG_REGMAP=y
-+CONFIG_SPL_REGMAP=y
-+CONFIG_TPL_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_SPL_SYSCON=y
-+CONFIG_TPL_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_SPL_CLK=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_DM_KEY=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_PHY=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PINCTRL=y
-+CONFIG_SPL_PINCTRL=y
-+CONFIG_PINCTRL_ROCKCHIP_RK3328=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_DM_REGULATOR_FIXED=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_RAM=y
-+CONFIG_SPL_RAM=y
-+CONFIG_TPL_RAM=y
-+CONFIG_DM_RESET=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_BASE=0xFF130000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_DEBUG_UART_ANNOUNCE=y
-+CONFIG_DEBUG_UART_SKIP_INIT=y
-+CONFIG_SYSRESET=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_DWC3=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_GENERIC=y
-+CONFIG_USB_DWC2=y
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DWC2_OTG=y
-+CONFIG_USB_GADGET_DOWNLOAD=y
-+CONFIG_G_DNL_MANUFACTURER="Rockchip"
-+CONFIG_G_DNL_VENDOR_NUM=0x2207
-+CONFIG_G_DNL_PRODUCT_NUM=0x330a
-+CONFIG_USE_TINY_PRINTF=y
-+CONFIG_SPL_TINY_MEMSET=y
-+CONFIG_ERRNO_STR=y
-+CONFIG_SMBIOS_MANUFACTURER="firefly"
-diff --git a/include/configs/roc_rk3328_cc.h b/include/configs/roc_rk3328_cc.h
-new file mode 100644
-index 0000000000..fc9c84e2e0
---- /dev/null
-+++ b/include/configs/roc_rk3328_cc.h
-@@ -0,0 +1,18 @@
-+/*
-+ * (C) Copyright 2018 FIREFLY
-+ *
-+ * SPDX-License-Identifier:     GPL-2.0+
-+ */
-+
-+#ifndef __ROC_RK3328_CC_H
-+#define __ROC_RK3328_CC_H
-+
-+#include <configs/rk3328_common.h>
-+
-+#define CONFIG_SYS_MMC_ENV_DEV 1
-+
-+#define SDRAM_BANK_SIZE			(2UL << 30)
-+
-+#define CONFIG_CONSOLE_SCROLL_LINES		10
-+
-+#endif

patch/u-boot/u-boot-rockchip64-edge/add-missing-SDMMC0_PWR_H-rockpro64.patch

@@ -1,46 +0,0 @@
-diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts
-index 12c7900..41dc902 100644
---- a/arch/arm/dts/rk3399-rockpro64.dts
-+++ b/arch/arm/dts/rk3399-rockpro64.dts
-@@ -374,6 +374,19 @@
- 				};
- 			};
- 
-+			vcc3v0_sd: vcc3v0-sd {
-+				compatible = "regulator-fixed";
-+				enable-active-high;
-+				gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&sdmmc0_pwr_h>;
-+				regulator-always-on;
-+				regulator-max-microvolt = <3000000>;
-+				regulator-min-microvolt = <3000000>;
-+				regulator-name = "vcc3v0_sd";
-+				vin-supply = <&vcc3v3_sys>;
-+			};
-+
- 			vcc3v3_s3: SWITCH_REG1 {
- 				regulator-name = "vcc3v3_s3";
- 				regulator-always-on;
-@@ -438,6 +451,13 @@
- 		};
- 	};
- 
-+	sd {
-+		sdmmc0_pwr_h: sdmmc0-pwr-h {
-+			rockchip,pins =
-+				<RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
- 	sdio-pwrseq {
- 		wifi_enable_h: wifi-enable-h {
- 			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-@@ -470,6 +490,7 @@
- };
- 
- &sdmmc {
-+	vmmc-supply = <&vcc3v0_sd>;
- 	u-boot,dm-spl;
- 	bus-width = <4>;
- 	status = "okay";

patch/u-boot/u-boot-rockchip64-edge/add-u-boot-delay-rockpro64.patch

@@ -1,13 +0,0 @@
-diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
-index 867f2e1..4a013c9 100644
---- a/configs/rockpro64-rk3399_defconfig
-+++ b/configs/rockpro64-rk3399_defconfig
-@@ -14,7 +14,7 @@ CONFIG_DEBUG_UART=y
- CONFIG_FIT=y
- CONFIG_SPL_LOAD_FIT=y
- CONFIG_SPL_FIT_GENERATOR="board/rockchip/rockpro64_rk3399/mk_fit_atf.sh"
--CONFIG_BOOTDELAY=0
-+CONFIG_BOOTDELAY=2
- # CONFIG_DISPLAY_CPUINFO is not set
- CONFIG_ANDROID_BOOTLOADER=y
- CONFIG_SPL_BOOTROM_SUPPORT=y

patch/u-boot/u-boot-rockchip64-edge/add-u-boot-setexpr-rockpro64.patch

@@ -1,13 +0,0 @@
-diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
-index 867f2e1..7ad985f 100644
---- a/configs/rockpro64-rk3399_defconfig
-+++ b/configs/rockpro64-rk3399_defconfig
-@@ -40,7 +40,7 @@ CONFIG_CMD_MMC=y
- CONFIG_CMD_SF=y
- CONFIG_CMD_USB=y
- CONFIG_CMD_USB_MASS_STORAGE=y
--# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_SETEXPR=y
- CONFIG_CMD_TIME=y
- CONFIG_CMD_REGULATOR=y
- CONFIG_CMD_MTDPARTS=y

patch/u-boot/u-boot-rockchip64-edge/board-renegade-add-recovery-button.patch

@@ -1,63 +0,0 @@
-From 6c8818cd725efe738184f87fe067d0066d116db0 Mon Sep 17 00:00:00 2001
-From: zouxf <zxf@t-tchip.com.cn>
-Date: Sat, 10 Mar 2018 14:12:29 +0800
-Subject: [PATCH] add recovery button
-
-Change-Id: If4a7bb9bfdadea8d09c47b6aded2ef6a75302f1b
----
- arch/arm/dts/rk3328-roc-cc.dts         | 5 +++++
- arch/arm/mach-rockchip/Kconfig         | 1 +
- arch/arm/mach-rockchip/boot_mode.c     | 2 +-
- arch/arm/mach-rockchip/rk3328/Kconfig  | 1 +
- arch/arm/mach-rockchip/rk3328/rk3328.c | 8 ++++++++
- 5 files changed, 16 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts
-index 4f3c2cf935..eab84c7769 100644
---- a/arch/arm/dts/rk3328-roc-cc.dts
-+++ b/arch/arm/dts/rk3328-roc-cc.dts
-@@ -42,6 +42,11 @@
- 		regulator-min-microvolt = <5000000>;
- 		regulator-max-microvolt = <5000000>;
- 	};
-+
-+	adc-keys {
-+		compatible = "adc-keys";
-+		io-channels = <&saradc 0>;
-+	};
- };
- 
- &saradc {
-diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c
-index d0dbff3bb8..7a997c0516 100644
---- a/arch/arm/mach-rockchip/boot_mode.c
-+++ b/arch/arm/mach-rockchip/boot_mode.c
-@@ -4,6 +4,7 @@
-  * SPDX-License-Identifier:     GPL-2.0+
-  */
- 
-+#define DEBUG
- #include <common.h>
- #include <adc.h>
- #include <asm/io.h>
-@@ -72,7 +73,6 @@ int setup_boot_mode(void)
- 	char env_preboot[256] = {0};
- 
- 	rockchip_dnl_mode_check();
--
- 	reg = (void *)CONFIG_ROCKCHIP_BOOT_MODE_REG;
- 
- 	boot_mode = readl(reg);
-diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
-index 0faf50085f..3dfe6c402e 100644
---- a/arch/arm/mach-rockchip/rk3328/Kconfig
-+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
-@@ -12,6 +12,7 @@ config TARGET_EVB_RK3328
- 
- config TARGET_ROC_RK3328_CC
- 	bool "ROC-RK3328-CC board, "
-+	select BOARD_LATE_INIT
- 	help
-   	  ROC-RK3328-CC is a Raspberry Pi-2 sized 4K60P HDR Media Board Computer
-   	  powered by Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor
-

patch/u-boot/u-boot-rockchip64-edge/board-renegade-leds.patch

@@ -1,51 +0,0 @@
-From 4f8960bd89243ace2282fbc890cf14cc8cca7a52 Mon Sep 17 00:00:00 2001
-From: zouxf <zxf@t-tchip.com.cn>
-Date: Wed, 14 Mar 2018 15:11:45 +0800
-Subject: [PATCH] firefly: dts: add led device to rk3328-roc-cc
-
-Change-Id: I60c39f4f71437d9cf9aac828deb9c19c3c9fe45a
----
- arch/arm/dts/rk3328-roc-cc.dts | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts
-index eab84c7769..b9b8fbc5ec 100644
---- a/arch/arm/dts/rk3328-roc-cc.dts
-+++ b/arch/arm/dts/rk3328-roc-cc.dts
-@@ -38,7 +38,7 @@
- 		compatible = "regulator-fixed";
- 		enable-active-high;
- 		regulator-name = "vcc5v0_host_xhci";
--		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
-+		gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
- 		regulator-min-microvolt = <5000000>;
- 		regulator-max-microvolt = <5000000>;
- 	};
-@@ -109,8 +109,10 @@
- };
- 
- &usb_host0_xhci {
--	vbus-supply = <&vcc5v0_host_xhci>;
-+	//vbus-supply = <&vcc5v0_host_xhci>;
-+	vbus-supply = <&vcc5v0_otg>;
- 	status = "okay";
-+	maximum-speed = "high-speed";
- };
- 
- &i2c1 {
-@@ -138,6 +140,14 @@
- 			status = "okay";
- 		};
- 
-+		led1 {
-+			label = "standby";
-+		};
-+
-+		led2 {
-+			label = "power";
-+		};
-+
- 		regulators {
- 			vdd_logic: DCDC_REG1 {
- 				regulator-name = "vdd_logic";
-

patch/u-boot/u-boot-rockchip64-edge/board-renegade-updates.patch

@@ -1,89 +0,0 @@
-diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
-index f1db5bf..3678f8c 100644
---- a/arch/arm/mach-rockchip/rk3328/rk3328.c
-+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
-@@ -90,7 +90,7 @@ int board_late_init(void)
- 	return rk_board_late_init();
- }
- 
--int board_init(void)
-+__weak int board_init(void)
- {
- 	int ret;
- #define GRF_BASE	0xff100000
-diff --git a/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c b/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c
-index 3ff1230..b4cc372 100644
---- a/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c
-+++ b/board/rockchip/roc_rk3328_cc/roc-rk3328-cc.c
-@@ -15,71 +15,3 @@
- 
- DECLARE_GLOBAL_DATA_PTR;
- 
--int board_init(void)
--{
--	int ret;
--#define GRF_BASE	0xff100000
--	struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
--
--	/* uart2 select m1, sdcard select m1*/
--	rk_clrsetreg(&grf->com_iomux,
--		     IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
--		     IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
--		     IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
--
--	ret = regulators_enable_boot_on(false);
--	if (ret)
--		debug("%s: Cannot enable boot on regulator\n", __func__);
--
--#define GRF_SOC_CON10		0xff100428
--	rk_setreg(GRF_SOC_CON10, (BIT(1) << 16) | (0 << 1));
--
--	return ret;
--}
--
--#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
--#include <usb.h>
--#include <usb/dwc2_udc.h>
--
--static struct dwc2_plat_otg_data rk3328_otg_data = {
--	.rx_fifo_sz	= 512,
--	.np_tx_fifo_sz	= 16,
--	.tx_fifo_sz	= 128,
--};
--
--int board_usb_init(int index, enum usb_init_type init)
--{
--	int node;
--	const char *mode;
--	bool matched = false;
--	const void *blob = gd->fdt_blob;
--
--	/* find the usb_otg node */
--	node = fdt_node_offset_by_compatible(blob, -1,
--					"rockchip,rk3328-usb");
--
--	while (node > 0) {
--		mode = fdt_getprop(blob, node, "dr_mode", NULL);
--		if (mode && strcmp(mode, "otg") == 0) {
--			matched = true;
--			break;
--		}
--
--		node = fdt_node_offset_by_compatible(blob, node,
--					"rockchip,rk3328-usb");
--	}
--	if (!matched) {
--		debug("Not found usb_otg device\n");
--		return -ENODEV;
--	}
--
--	rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
--
--	return dwc2_udc_probe(&rk3328_otg_data);
--}
--
--int board_usb_cleanup(int index, enum usb_init_type init)
--{
--	return 0;
--}
--#endif

patch/u-boot/u-boot-rockchip64-edge/enable-DT-overlays-support.patch

@@ -1,13 +0,0 @@
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index 0e8dc01..22170d2 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1125,6 +1125,8 @@ config ARCH_ROCKCHIP
-	imply TPL_SYSRESET
-	imply ADC
-	imply SARADC_ROCKCHIP
-+	select OF_LIBFDT
-+	select OF_LIBFDT_OVERLAY
- 
- config TARGET_THUNDERX_88XX
- 	bool "Support ThunderX 88xx"

patch/u-boot/u-boot-rockchip64-mainline/add-board-orangepi-r1plus.patch

@@ -1,187 +0,0 @@
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index 06ccc03e..a2657ebe 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
- dtb-$(CONFIG_ROCKCHIP_RK3328) += \
- 	rk3328-evb.dtb \
- 	rk3328-nanopi-r2-rev00.dtb \
-+	rk3328-orangepi-r1-plus.dtb \
- 	rk3328-roc-cc.dtb \
- 	rk3328-rock64.dtb \
- 	rk3328-rock-pi-e.dtb
-diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
-new file mode 100644
-index 00000000..cf3452ea
---- /dev/null
-+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
-@@ -0,0 +1,16 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
-+ */
-+
-+#include "rk3328-u-boot.dtsi"
-+#include "rk3328-sdram-ddr4-666.dtsi"
-+/ {
-+	chosen {
-+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
-+	};
-+};
-+
-+&usb_host0_xhci {
-+	status = "okay";
-+};
-diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
-new file mode 100644
-index 00000000..23023ad0
---- /dev/null
-+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
-@@ -0,0 +1,48 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2020 Shenzhen Xunlong Software CO.,Limited
-+ * Copyright (c) 2021 AmadeusGhost <amadeus@jmu.edu.cn>
-+ *
-+ * Based on Nanopi R2S
-+ */
-+
-+#include "rk3328-nanopi-r2-rev00.dts"
-+
-+/ {
-+	model = "Xunlong Orange Pi R1 Plus";
-+	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-+};
-+
-+&leds_gpio {
-+	rockchip,pins =
-+		<2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
-+		<2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
-+		<3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+};
-+
-+&leds {
-+	led@1 {
-+		gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-+	};
-+};
-+
-+&mach {
-+	compatible = "orangepi,board";
-+	hwrev = <2>;
-+	machine = "ORANGEPI-R1PLUS";
-+	model = "OrangePi R1PLUS";
-+};
-+
-+&spi0 {
-+	status = "okay";
-+
-+	spiflash@0 {
-+		compatible = "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <10000000>;
-+	};
-+};
-+
-+&uart1 {
-+	status = "okay";
-+};
-diff --git a/configs/orangepi_r1_plus_rk3328_defconfig b/configs/orangepi_r1_plus_rk3328_defconfig
-new file mode 100644
-index 00000000..ddbe9715
-@@ -0,0 +1,95 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SYS_TEXT_BASE=0x00200000
-+CONFIG_ROCKCHIP_RK3328=y
-+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-+CONFIG_TPL_LIBCOMMON_SUPPORT=y
-+CONFIG_TPL_LIBGENERIC_SUPPORT=y
-+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-+CONFIG_ENV_OFFSET=0x3F8000
-+CONFIG_SPL_STACK_R_ADDR=0x600000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEBUG_UART_BASE=0xFF130000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328"
-+CONFIG_DEBUG_UART=y
-+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-+# CONFIG_ANDROID_BOOT_IMAGE is not set
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_SPL_LOAD_FIT=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
-+CONFIG_MISC_INIT_R=y
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_DISPLAY_BOARDINFO_LATE=y
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
-+CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_ATF=y
-+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-+CONFIG_CMD_BOOTZ=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_USB=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_TIME=y
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_TPL_OF_CONTROL=y
-+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
-+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_TPL_OF_PLATDATA=y
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_TPL_DM=y
-+CONFIG_REGMAP=y
-+CONFIG_SPL_REGMAP=y
-+CONFIG_TPL_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_SPL_SYSCON=y
-+CONFIG_TPL_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_SPL_CLK=y
-+CONFIG_FASTBOOT_BUF_ADDR=0x800800
-+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_SPEED=20000000
-+CONFIG_DM_ETH=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_GMAC_ROCKCHIP=y
-+CONFIG_PHY=y
-+CONFIG_PINCTRL=y
-+CONFIG_SPL_PINCTRL=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_DM_REGULATOR_FIXED=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_RAM=y
-+CONFIG_SPL_RAM=y
-+CONFIG_TPL_RAM=y
-+CONFIG_DM_RESET=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYSRESET=y
-+# CONFIG_TPL_SYSRESET is not set
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_DWC3=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_GENERIC=y
-+CONFIG_USB_DWC2=y
-+CONFIG_USB_DWC3=y
-+# CONFIG_USB_DWC3_GADGET is not set
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DWC2_OTG=y
-+CONFIG_SPL_TINY_MEMSET=y
-+CONFIG_TPL_TINY_MEMSET=y
-+CONFIG_ERRNO_STR=y
-+CONFIG_SMBIOS_MANUFACTURER="pine64"

patch/u-boot/u-boot-rockchip64-mainline/add-trust-ini.patch

@@ -1,21 +0,0 @@
-diff --git a/trust.ini b/trust.ini
-new file mode 100644
-index 0000000..4af021a
---- /dev/null
-+++ b/trust.ini
-@@ -0,0 +1,15 @@
-+[VERSION]
-+MAJOR=1
-+MINOR=0
-+[BL30_OPTION]
-+SEC=0
-+[BL31_OPTION]
-+SEC=1
-+PATH=bl31.elf
-+ADDR=0x10000
-+[BL32_OPTION]
-+SEC=0
-+[BL33_OPTION]
-+SEC=0
-+[OUTPUT]
-+PATH=trust.bin

patch/u-boot/u-boot-rockchip64/0001-fixing-dtc-error.patch

@@ -1,37 +0,0 @@
-From 97bca7b4cec321501a710cb0ce8b598a9e746a19 Mon Sep 17 00:00:00 2001
-From: Igor Pecovnik <igor.pecovnik@gmail.com>
-Date: Mon, 8 Mar 2021 13:12:41 +0000
-Subject: [PATCH] ;spi;u-boot-spl.kwb:u-boot.flash
-
-Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
----
- scripts/dtc/dtc-lexer.l | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
-index fd825eb..f57c9a7 100644
---- a/scripts/dtc/dtc-lexer.l
-+++ b/scripts/dtc/dtc-lexer.l
-@@ -38,7 +38,7 @@ LINECOMMENT	"//".*\n
- #include "srcpos.h"
- #include "dtc-parser.tab.h"
- 
--YYLTYPE yylloc;
-+extern YYLTYPE yylloc;
- extern bool treesource_error;
- 
- /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
---- a/scripts/dtc/dtc-lexer.lex.c_shipped
-+++ b/scripts/dtc/dtc-lexer.lex.c_shipped
-@@ -637,7 +637,6 @@ char *yytext;
- #include "srcpos.h"
- #include "dtc-parser.tab.h"
- 
--YYLTYPE yylloc;
- extern bool treesource_error;
- 
- /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
-
--- 
-Created with Armbian build tools https://github.com/armbian/build
-

patch/u-boot/u-boot-rockchip64/board_z28pro/add_fdtfile_dt_overlays.patch

@@ -1,32 +0,0 @@
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index 84462f3..3291f9f
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1112,6 +1112,8 @@ config ARCH_ROCKCHIP
- 	select DM_USB if USB
- 	select DM_PWM
- 	select DM_REGULATOR
-+	select OF_LIBFDT
-+	select OF_LIBFDT_OVERLAY
- 	select CMD_ROCKUSB if USB_GADGET_DOWNLOAD
- 	select ENABLE_ARM_SOC_BOOT0_HOOK
- 	imply CMD_FASTBOOT
-diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
-index 513237e..a1bcebd
---- a/include/configs/rk3328_common.h
-+++ b/include/configs/rk3328_common.h
-@@ -73,12 +73,13 @@
- 	"fdt_addr_r=0x01f00000\0" \
- 	"kernel_addr_r=0x02000000\0" \
- 	"ramdisk_addr_r=0x04000000\0"
-+#define FDTFILE "rockchip/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
- 
- #include <config_distro_bootcmd.h>
- #define CONFIG_EXTRA_ENV_SETTINGS \
- 	ENV_MEM_LAYOUT_SETTINGS \
--	"fdtfile=" FDTFILE \
- 	"partitions=" PARTS_DEFAULT \
-+	"fdtfile=" FDTFILE "\0" \
- 	BOOTENV
- 
- #endif

patch/u-boot/u-boot-rockchip64/board_z28pro/switch_bootorder_mmc0_mmc1.patch

@@ -1,15 +0,0 @@
-diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
-index 1b00ef4..335b214 100644
---- a/include/configs/rockchip-common.h
-+++ b/include/configs/rockchip-common.h
-@@ -14,9 +14,9 @@
- /* First try to boot from SD (index 0), then eMMC (index 1 */
- #ifdef CONFIG_CMD_USB
- #define BOOT_TARGET_DEVICES(func) \
--	func(MMC, mmc, 0) \
- 	func(MMC, mmc, 1) \
- 	func(USB, usb, 0) \
-+        func(MMC, mmc, 0) \
- 	func(PXE, pxe, na) \
- 	func(DHCP, dchp, na)
- #else

patch/u-boot/u-boot-rockchip64/board_z28pro/use_sdmmc_ext.patch

@@ -1,192 +0,0 @@
-diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts
-index d19d609..5c72488 100644
---- a/arch/arm/dts/rk3328-rock64.dts
-+++ b/arch/arm/dts/rk3328-rock64.dts
-@@ -17,7 +17,7 @@
- 	};
-
- 	aliases {
--		spi0 = &spi0;
-+		mmc1 = &sdmmc_ext;
- 	};
-
- 	gmac_clkin: external-gmac-clock {
-@@ -37,7 +37,7 @@
- 	vcc3v3_sdmmc: sdmmc-pwren {
- 		compatible = "regulator-fixed";
- 		regulator-name = "vcc3v3";
--		gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
-+		gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
- 		regulator-always-on;
- 		regulator-boot-on;
- 	};
-@@ -75,16 +75,16 @@
- 	status = "okay";
- };
-
--&sdmmc {
-+&sdmmc_ext {
- 	u-boot,dm-spl;
- 	bus-width = <4>;
- 	cap-mmc-highspeed;
- 	cap-sd-highspeed;
--	card-detect-delay = <200>;
-+	cd-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
- 	disable-wp;
- 	num-slots = <1>;
- 	pinctrl-names = "default";
--	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+	pinctrl-0 = <&sdmmc0ext_clk>, <&sdmmc0ext_cmd>, <&sdmmc0ext_dectn>, <&sdmmc0ext_bus4>;
- 	status = "okay";
- };
-
-@@ -268,42 +268,6 @@
- 	status = "okay";
- };
-
--&spi0 {
--	u-boot,dm-spl;
--	status = "okay";
--
--	spiflash: spi-flash@0 {
--		u-boot,dm-spl;
--		#address-cells = <0x1>;
--		#size-cells = <1>;
--		compatible = "spi-flash";
--		reg = <0x0>;
--		spi-max-frequency = <25000000>;
--		status = "okay";
--
--		partitions {
--			compatible = "fixed-partitions";
--			#address-cells = <1>;
--			#size-cells = <1>;
--
--			loader@8000 {
--				label = "loader";
--				reg = <0x8000 0x3F0000>;
--			};
--
--			env@3f8000 {
--				label = "env";
--				reg = <0x3F8000 0x8000>;
--			};
--
--			vendor@7c0000 {
--				label = "vendor";
--				reg = <0x7C0000 0x40000>;
--			};
--		};
--	};
--};
--
- &pinctrl {
- 	pmic {
- 		pmic_int_l: pmic-int-l {
-diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
-index a396510..260117b 100644
---- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
-+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
-@@ -361,6 +361,17 @@ enum {
- 	GPIO2D4_SEL_MASK	= 0xff << GPIO2D4_SEL_SHIFT,
- 	GPIO2D4_EMMC_DATA1234	= 0xaa,
-
-+        /* GPIO3AL_IOMUX */
-+        GPIO3A0_SEL_SHIFT       = 0,
-+        GPIO3A0_SEL_MASK        = 0x71ff << GPIO3A0_SEL_SHIFT,
-+        GPIO3A0_CARD_DATA_CLK_CMD_DETN  = 0x36db,
-+
-+        /* GPIO3AH_IOMUX */
-+        GPIO3A5_SEL_SHIFT       = 0,
-+        GPIO3A5_SEL_MASK        = 0x1ff << GPIO3A5_SEL_SHIFT,
-+        GPIO3A5_CARD_DATA234	= 0xdb,
-+
-+
- 	/* GPIO3C_IOMUX */
- 	GPIO3C0_SEL_SHIFT	= 0,
- 	GPIO3C0_SEL_MASK	= 0x3fff << GPIO3C0_SEL_SHIFT,
-diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
-index f1db5bf..b627083 100644
---- a/arch/arm/mach-rockchip/rk3328/rk3328.c
-+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
-@@ -96,11 +96,10 @@ int board_init(void)
- #define GRF_BASE	0xff100000
- 	struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
-
--	/* uart2 select m1, sdcard select m1*/
-+	/* uart2 select m1, no sdcard select, because we use sdmmc_ext */
- 	rk_clrsetreg(&grf->com_iomux,
--		     IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
--		     IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
--		     IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
-+		     IOMUX_SEL_UART2_MASK,
-+		     IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
-
- 	ret = regulators_enable_boot_on(false);
- 	if (ret)
-diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
-index 8438047..9af8262 100644
---- a/drivers/clk/rockchip/clk_rk3328.c
-+++ b/drivers/clk/rockchip/clk_rk3328.c
-@@ -401,7 +401,7 @@ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
- 	switch (clk_id) {
- 	case HCLK_SDMMC:
- 	case SCLK_SDMMC:
--		con_id = 30;
-+		con_id = 43;
- 		break;
- 	case HCLK_EMMC:
- 	case SCLK_EMMC:
-@@ -429,7 +429,7 @@ static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
- 	switch (clk_id) {
- 	case HCLK_SDMMC:
- 	case SCLK_SDMMC:
--		con_id = 30;
-+		con_id = 43;
- 		break;
- 	case HCLK_EMMC:
- 	case SCLK_EMMC:
-diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
-index c928134..01ed39d 100644
---- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
-+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
-@@ -180,19 +180,17 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
- 			     << GPIO3C0_SEL_SHIFT);
- 		break;
- 	case PERIPH_ID_SDCARD:
--		/* SDMMC_PWREN use GPIO and init as regulator-fiexed  */
--		if (com_iomux & IOMUX_SEL_SDMMC_MASK)
--			rk_clrsetreg(&grf->gpio0d_iomux,
--				     GPIO0D6_SEL_MASK,
--				     GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
--		else
--			rk_clrsetreg(&grf->gpio2a_iomux,
--				     GPIO2A7_SEL_MASK,
--				     GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
--		rk_clrsetreg(&grf->gpio1a_iomux,
--			     GPIO1A0_SEL_MASK,
--			     GPIO1A0_CARD_DATA_CLK_CMD_DETN
--			     << GPIO1A0_SEL_SHIFT);
-+		/* SDMMC_PWREN use GPIO and init as regulator-fixed  */
-+		/* SDMMC0EXT hardcoded */
-+		rk_clrsetreg(&grf->gpio2a_iomux,
-+			     GPIO2A7_SEL_MASK,
-+			     GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
-+		rk_clrsetreg(&grf->gpio3al_iomux,
-+			     GPIO3A0_SEL_MASK,
-+				GPIO3A0_CARD_DATA_CLK_CMD_DETN << GPIO3A0_SEL_SHIFT);
-+                rk_clrsetreg(&grf->gpio3ah_iomux,
-+                             GPIO3A5_SEL_MASK,
-+				GPIO3A5_CARD_DATA234 << GPIO3A5_SEL_SHIFT);
- 		break;
- 	default:
- 		debug("mmc id = %d iomux error!\n", mmc_id);
-@@ -425,7 +423,7 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
- 		return PERIPH_ID_I2C2;
- 	case 39:
- 		return PERIPH_ID_I2C3;
--	case 12:
-+	case 4:
- 		return PERIPH_ID_SDCARD;
- 	case 14:
- 		return PERIPH_ID_EMMC;