mirror of
https://github.com/armbian/build
synced 2025-09-24 19:47:06 +07:00
rk3588: Integrate BOOTPATCHDIR with rk35xx
They both use the same U-Boot version now.
This commit is contained in:
ColorfulRhino
@@ -0,0 +1,5 @@
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config:
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overlay-directories:
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- { source: "defconfig", target: "configs" } # copies all files in defconfig dir to the configs/ dir in the u-boot source tree
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- { source: "dt", target: "arch/arm/dts" } # copies all files in dt dir to the arch/arm/dts dir in the u-boot source tree
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@@ -0,0 +1,41 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: amazingfate <liujianfeng1994@gmail.com>
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Date: Thu, 2 May 2024 01:45:23 +0800
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Subject: add u-boot pd negotiation support
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---
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drivers/power/power_delivery/tcpm.c | 4 ++--
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include/configs/rk3588_common.h | 2 +-
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2 files changed, 3 insertions(+), 3 deletions(-)
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diff --git a/drivers/power/power_delivery/tcpm.c b/drivers/power/power_delivery/tcpm.c
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index 22334c6230c4..1b94a401836a 100644
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--- a/drivers/power/power_delivery/tcpm.c
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+++ b/drivers/power/power_delivery/tcpm.c
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@@ -1390,8 +1390,8 @@ static void tcpm_pd_rx_handler(struct tcpm_port *port,
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*/
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if (!!(le16_to_cpu(msg->header) & PD_HEADER_DATA_ROLE) ==
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(port->data_role == TYPEC_HOST)) {
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- printf("Data role mismatch, initiating error recovery\n");
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- tcpm_set_state(port, ERROR_RECOVERY, 0);
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+ printf("Data role mismatch, hard resetting...\n");
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+ tcpm_set_state(port, HARD_RESET_SEND, 0);
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} else {
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if (cnt)
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tcpm_pd_data_request(port, msg);
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diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h
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index 549a2583c3ad..448ae2ec6ef0 100644
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--- a/include/configs/rk3588_common.h
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+++ b/include/configs/rk3588_common.h
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@@ -96,7 +96,7 @@
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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-#define CONFIG_PREBOOT
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+#define CONFIG_PREBOOT "charge_pd"
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#define CONFIG_LIB_HW_RAND
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#endif
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--
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Armbian
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@@ -0,0 +1,13 @@
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t a/configs/rock-5b-rk3588_defconfig b/configs/rock-5b-rk3588_defconfig
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index adcdb4d9..92951132 100644
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--- a/configs/rock-5b-rk3588_defconfig
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+++ b/configs/rock-5b-rk3588_defconfig
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@@ -21,7 +21,7 @@ CONFIG_TARGET_EVB_RK3588=y
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CONFIG_SPL_LIBDISK_SUPPORT=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI_SUPPORT=y
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-CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
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+CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb"
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_FIT_IMAGE_POST_PROCESS=y
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@@ -0,0 +1,182 @@
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diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
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index f7928a7f2..3c4d1e2f2 100644
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--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
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+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
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@@ -1067,6 +1067,7 @@ int arch_cpu_init(void)
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#endif
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#define BAD_CPU(mask, n) ((mask) & (1 << (n)))
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+#define BAD_GPU(mask, n) ((mask) & (1 << (n)))
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#define BAD_RKVENC(mask, n) ((mask) & (1 << (n)))
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#define BAD_RKVDEC(mask, n) ((mask) & (1 << (n)))
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@@ -1220,51 +1221,54 @@ static void fdt_rm_cpu(const void *blob, u8 cpu_mask)
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static void rk3582_fdt_rm_cpus(const void *blob, u8 cpu_mask)
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{
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- /*
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- * policy:
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- *
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- * 1. both of cores within the same cluster should be normal, otherwise
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- * remove both of them.
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- * 2. if core4~7 are all normal, remove core6 and core7 anyway.
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- */
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- if (BAD_CPU(cpu_mask, 4) || BAD_CPU(cpu_mask, 5))
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- cpu_mask |= BIT(4) | BIT(5);
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- if (BAD_CPU(cpu_mask, 6) || BAD_CPU(cpu_mask, 7))
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- cpu_mask |= BIT(6) | BIT(7);
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-
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- if (!BAD_CPU(cpu_mask, 4) & !BAD_CPU(cpu_mask, 5) &&
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- !BAD_CPU(cpu_mask, 6) & !BAD_CPU(cpu_mask, 7))
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- cpu_mask |= BIT(6) | BIT(7);
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+ if (BAD_CPU(cpu_mask, 4))
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+ cpu_mask |= BIT(4);
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+ if (BAD_CPU(cpu_mask, 5))
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+ cpu_mask |= BIT(5);
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+ if (BAD_CPU(cpu_mask, 6))
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+ cpu_mask |= BIT(6);
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+ if (BAD_CPU(cpu_mask, 7))
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+ cpu_mask |= BIT(7);
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fdt_rm_cooling_map(blob, cpu_mask);
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fdt_rm_cpu_affinity(blob, cpu_mask);
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fdt_rm_cpu(blob, cpu_mask);
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}
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-static void rk3582_fdt_rm_gpu(void *blob)
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+static void rk3582_fdt_rm_gpu(void *blob, u8 mask)
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{
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- /*
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- * policy:
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- *
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- * Remove GPU by default.
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- */
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- fdt_rm_path(blob, "/gpu@fb000000");
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- fdt_rm_path(blob, "/thermal-zones/soc-thermal/cooling-maps/map3");
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- debug("rm: gpu\n");
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+ /* If one core is bad, disable gpu */
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+ if ((BAD_GPU(mask, 0)) || (BAD_GPU(mask, 1)) || (BAD_GPU(mask, 2)) || (BAD_GPU(mask, 3)))
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+ {
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+ fdt_rm_path(blob, "/gpu@fb000000");
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+ fdt_rm_path(blob, "/thermal-zones/soc-thermal/cooling-maps/map3");
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+ debug("rm: gpu\n");
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+ }
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}
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-static void rk3582_fdt_rm_rkvdec01(void *blob)
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+static void rk3582_fdt_rm_rkvdec01(void *blob, u8 mask)
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{
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- /*
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- * policy:
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- *
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- * Remove rkvdec0 and rkvdec1 by default.
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- */
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- fdt_rm_path(blob, "/rkvdec-core@fdc38000");
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- fdt_rm_path(blob, "/iommu@fdc38700");
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- fdt_rm_path(blob, "/rkvdec-core@fdc48000");
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- fdt_rm_path(blob, "/iommu@fdc48700");
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- debug("rm: rkvdec0, rkvdec1\n");
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+ /* Only remove bad cores */
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+ if (BAD_RKVDEC(mask, 0)) {
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+ fdt_rm_path(blob, "/rkvdec-core@fdc38000");
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+ fdt_rm_path(blob, "/iommu@fdc38700");
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+ debug("rm: rkvdec0\n");
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+ }
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+ if (BAD_RKVDEC(mask, 1)) {
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+ fdt_rm_path(blob, "/rkvdec-core@fdc48000");
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+ fdt_rm_path(blob, "/iommu@fdc48700");
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+ debug("rm: rkvdec1\n");
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+ }
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+
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+ /* If there is bad core, fix multi core related nodes */
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+ if (BAD_RKVDEC(mask, 0) || BAD_RKVDEC(mask, 1)) {
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+ do_fixup_by_path((void *)blob, "/rkvdec-ccu",
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+ "status", "disabled", sizeof("disabled"), 0);
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+
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+ /* rename node name if the node exist, actually only one exist */
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+ fdt_rename_path(blob, "/rkvdec-core@fdc38000", "rkvdec@fdc38000");
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+ fdt_rename_path(blob, "/rkvdec-core@fdc48000", "rkvdec@fdc48000");
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+ }
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}
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static void rk3582_fdt_rm_rkvenc01(void *blob, u8 mask)
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@@ -1277,31 +1271,27 @@ static void rk3582_fdt_rm_rkvenc01(void *blob, u8 mask)
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* 3. disable '*-ccu' node
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* 4. rename '*-core@' node
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*/
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- if (!BAD_RKVENC(mask, 0) && !BAD_RKVENC(mask, 1)) {
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- /* rkvenc1 */
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+ if (BAD_RKVENC(mask, 0)) {
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+ fdt_rm_path(blob, "/rkvenc-core@fdbd0000");
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+ fdt_rm_path(blob, "/iommu@fdbdf000");
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+ debug("rm: rkvenv0\n");
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+
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+ }
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+ if (BAD_RKVENC(mask, 1)) {
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fdt_rm_path(blob, "/rkvenc-core@fdbe0000");
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fdt_rm_path(blob, "/iommu@fdbef000");
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debug("rm: rkvenv1\n");
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- } else {
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- if (BAD_RKVENC(mask, 0)) {
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- fdt_rm_path(blob, "/rkvenc-core@fdbd0000");
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- fdt_rm_path(blob, "/iommu@fdbdf000");
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- debug("rm: rkvenv0\n");
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-
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- }
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- if (BAD_RKVENC(mask, 1)) {
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- fdt_rm_path(blob, "/rkvenc-core@fdbe0000");
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- fdt_rm_path(blob, "/iommu@fdbef000");
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- debug("rm: rkvenv1\n");
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- }
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}
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- do_fixup_by_path((void *)blob, "/rkvenc-ccu",
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- "status", "disabled", sizeof("disabled"), 0);
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+ /* If there is bad core, fix multi core related nodes */
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+ if (BAD_RKVENC(mask, 0) || BAD_RKVENC(mask, 1)) {
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+ do_fixup_by_path((void *)blob, "/rkvenc-ccu",
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+ "status", "disabled", sizeof("disabled"), 0);
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- /* rename node name if the node exist, actually only one exist */
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- fdt_rename_path(blob, "/rkvenc-core@fdbd0000", "rkvenc@fdbd0000");
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- fdt_rename_path(blob, "/rkvenc-core@fdbe0000", "rkvenc@fdbe0000");
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+ /* rename node name if the node exist, actually only one exist */
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+ fdt_rename_path(blob, "/rkvenc-core@fdbd0000", "rkvenc@fdbd0000");
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+ fdt_rename_path(blob, "/rkvenc-core@fdbe0000", "rkvenc@fdbe0000");
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+ }
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}
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static void rk3583_fdt_rm_rkvdec01(void *blob, u8 mask)
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@@ -1352,6 +1342,7 @@ static int fdt_fixup_modules(void *blob)
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u8 rkvenc_mask;
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u8 rkvdec_mask;
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u8 cpu_mask;
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+ u8 gpu_mask;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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@@ -1386,12 +1377,10 @@ static int fdt_fixup_modules(void *blob)
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rkvenc_mask = (ip_state[2] & 0x1) | ((ip_state[2] & 0x4) >> 1);
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/* ip_state[1]: bit6,7 */
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rkvdec_mask = (ip_state[1] & 0xc0) >> 6;
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-#if 0
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/* ip_state[1]: bit1~4 */
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gpu_mask = (ip_state[1] & 0x1e) >> 1;
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-#endif
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debug("hw-mask: 0x%02x, 0x%02x, 0x%02x\n", ip_state[0], ip_state[1], ip_state[2]);
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- debug("sw-mask: 0x%02x, 0x%02x, 0x%02x\n", cpu_mask, rkvenc_mask, rkvdec_mask);
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+ debug("sw-mask: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n", cpu_mask, gpu_mask, rkvenc_mask, rkvdec_mask);
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/*
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* FIXUP WARNING!
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@@ -1408,8 +1397,8 @@ static int fdt_fixup_modules(void *blob)
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* So don't use pattern like "if (rkvenc_mask) then rk3582_fdt_rm_rkvenc01()",
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* just go through all of them as this chip is rk3582.
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*/
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- rk3582_fdt_rm_gpu(blob);
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- rk3582_fdt_rm_rkvdec01(blob);
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+ rk3582_fdt_rm_gpu(blob, gpu_mask);
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+ rk3582_fdt_rm_rkvdec01(blob, rkvdec_mask);
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rk3582_fdt_rm_rkvenc01(blob, rkvenc_mask);
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rk3582_fdt_rm_cpus(blob, cpu_mask);
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} else if (chip_id[0] == 0x35 && chip_id[1] == 0x83) {
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@@ -0,0 +1,13 @@
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t a/configs/rock-5a-rk3588s_defconfig b/configs/rock-5a-rk3588s_defconfig
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index adcdb4d9..92951132 100644
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--- a/configs/rock-5a-rk3588s_defconfig
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+++ b/configs/rock-5a-rk3588s_defconfig
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@@ -23,7 +23,7 @@
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CONFIG_SPL_LIBDISK_SUPPORT=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI_SUPPORT=y
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-CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
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+CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb"
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_FIT_IMAGE_POST_PROCESS=y
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@@ -0,0 +1,223 @@
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CONFIG_ARM=y
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CONFIG_ARM_CPU_SUSPEND=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SPL_GPIO_SUPPORT=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
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CONFIG_SYS_MALLOC_F_LEN=0x80000
|
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CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
|
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CONFIG_ROCKCHIP_RK3588=y
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CONFIG_ROCKCHIP_FIT_IMAGE=y
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CONFIG_ROCKCHIP_HWID_DTB=y
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CONFIG_ROCKCHIP_VENDOR_PARTITION=y
|
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CONFIG_USING_KERNEL_DTB_V2=y
|
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CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
|
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CONFIG_ROCKCHIP_NEW_IDB=y
|
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CONFIG_LOADER_INI="RK3588MINIALL.ini"
|
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CONFIG_TRUST_INI="RK3588TRUST.ini"
|
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CONFIG_SPL_SERIAL_SUPPORT=y
|
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CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
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CONFIG_TARGET_EVB_RK3588=y
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CONFIG_SPL_LIBDISK_SUPPORT=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
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CONFIG_SPL_SPI_SUPPORT=y
|
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CONFIG_DEFAULT_DEVICE_TREE="rk3588-armsom-sige7"
|
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CONFIG_DEBUG_UART=y
|
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CONFIG_FIT=y
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CONFIG_FIT_IMAGE_POST_PROCESS=y
|
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CONFIG_FIT_HW_CRYPTO=y
|
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CONFIG_SPL_LOAD_FIT=y
|
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CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_SPL_FIT_HW_CRYPTO=y
|
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# CONFIG_SPL_SYS_DCACHE_OFF is not set
|
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CONFIG_BOOTDELAY=0
|
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# CONFIG_DISPLAY_CPUINFO is not set
|
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CONFIG_ANDROID_BOOTLOADER=y
|
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CONFIG_ANDROID_AVB=y
|
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CONFIG_ANDROID_BOOT_IMAGE_HASH=y
|
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CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
|
||||
CONFIG_SPL_MMC_WRITE=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DTIMG=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_BOOT_ANDROID=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TFTP_BOOTM=y
|
||||
CONFIG_CMD_TFTP_FLASH=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_MTD_BLK=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_DTB_MINIMUM=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_OF_U_BOOT_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
# CONFIG_NET_TFTP_VARS is not set
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
# CONFIG_SARADC_ROCKCHIP is not set
|
||||
CONFIG_SARADC_ROCKCHIP_V2=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_SCMI=y
|
||||
CONFIG_SPL_CLK_SCMI=y
|
||||
CONFIG_DM_CRYPTO=y
|
||||
CONFIG_SPL_DM_CRYPTO=y
|
||||
CONFIG_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_ROCKCHIP=y
|
||||
CONFIG_SCMI_FIRMWARE=y
|
||||
CONFIG_SPL_SCMI_FIRMWARE=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_DM_KEY=y
|
||||
CONFIG_ADC_KEY=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SPL_MISC=y
|
||||
CONFIG_MISC_DECOMPRESS=y
|
||||
CONFIG_SPL_MISC_DECOMPRESS=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLK=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=80000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_NVME=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_SPI_RK8XX=y
|
||||
CONFIG_DM_POWER_DELIVERY=y
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
CONFIG_TYPEC_TCPCI=y
|
||||
CONFIG_TYPEC_HUSB311=y
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_RK860X=y
|
||||
CONFIG_REGULATOR_RK806=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_ROCKCHIP_SDRAM_COMMON=y
|
||||
CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_RESET_ROCKCHIP=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_ROCKCHIP_SPI=y
|
||||
CONFIG_ROCKCHIP_SFC=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_PCI=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_DRM_ROCKCHIP=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
|
||||
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
|
||||
CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_LIB_RAND=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_N_SIZE=0x200
|
||||
CONFIG_RSA_E_SIZE=0x10
|
||||
CONFIG_RSA_C_SIZE=0x20
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_AVB_LIBAVB=y
|
||||
CONFIG_AVB_LIBAVB_AB=y
|
||||
CONFIG_AVB_LIBAVB_ATX=y
|
||||
CONFIG_AVB_LIBAVB_USER=y
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
CONFIG_OPTEE_CLIENT=y
|
||||
CONFIG_OPTEE_V2=y
|
||||
CONFIG_CMD_CHARGE_DISPLAY=y
|
||||
CONFIG_DM_CHARGE_DISPLAY=y
|
||||
@@ -0,0 +1,216 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARM_CPU_SUSPEND=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x80000
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE=y
|
||||
CONFIG_ROCKCHIP_HWID_DTB=y
|
||||
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
|
||||
CONFIG_USING_KERNEL_DTB_V2=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
|
||||
CONFIG_ROCKCHIP_NEW_IDB=y
|
||||
CONFIG_LOADER_INI="RK3588MINIALL.ini"
|
||||
CONFIG_TRUST_INI="RK3588TRUST.ini"
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_TARGET_EVB_RK3588=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3588-armsom-w3"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_FIT_HW_CRYPTO=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_SPL_FIT_HW_CRYPTO=y
|
||||
# CONFIG_SPL_SYS_DCACHE_OFF is not set
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_DISABLE_CONSOLE=y
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_ANDROID_BOOTLOADER=y
|
||||
CONFIG_ANDROID_AVB=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
|
||||
CONFIG_SPL_MMC_WRITE=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DTIMG=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_BOOT_ANDROID=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TFTP_BOOTM=y
|
||||
CONFIG_CMD_TFTP_FLASH=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_MTD_BLK=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_DTB_MINIMUM=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
# CONFIG_NET_TFTP_VARS is not set
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
# CONFIG_SARADC_ROCKCHIP is not set
|
||||
CONFIG_SARADC_ROCKCHIP_V2=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_SCMI=y
|
||||
CONFIG_SPL_CLK_SCMI=y
|
||||
CONFIG_DM_CRYPTO=y
|
||||
CONFIG_SPL_DM_CRYPTO=y
|
||||
CONFIG_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_ROCKCHIP=y
|
||||
CONFIG_SCMI_FIRMWARE=y
|
||||
CONFIG_SPL_SCMI_FIRMWARE=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_DM_KEY=y
|
||||
CONFIG_ADC_KEY=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SPL_MISC=y
|
||||
CONFIG_MISC_DECOMPRESS=y
|
||||
CONFIG_SPL_MISC_DECOMPRESS=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLK=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=80000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_NVME=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_SPI_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_RK860X=y
|
||||
CONFIG_REGULATOR_RK806=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_ROCKCHIP_SDRAM_COMMON=y
|
||||
CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_RESET_ROCKCHIP=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_ROCKCHIP_SPI=y
|
||||
CONFIG_ROCKCHIP_SFC=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_PCI=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_DRM_ROCKCHIP=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
|
||||
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
|
||||
CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_LIB_RAND=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_N_SIZE=0x200
|
||||
CONFIG_RSA_E_SIZE=0x10
|
||||
CONFIG_RSA_C_SIZE=0x20
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_AVB_LIBAVB=y
|
||||
CONFIG_AVB_LIBAVB_AB=y
|
||||
CONFIG_AVB_LIBAVB_ATX=y
|
||||
CONFIG_AVB_LIBAVB_USER=y
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
CONFIG_OPTEE_CLIENT=y
|
||||
CONFIG_OPTEE_V2=y
|
||||
@@ -0,0 +1,216 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARM_CPU_SUSPEND=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x80000
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_ROCKCHIP_USB_BOOT=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE=y
|
||||
CONFIG_ROCKCHIP_HWID_DTB=y
|
||||
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
|
||||
CONFIG_USING_KERNEL_DTB_V2=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
|
||||
CONFIG_ROCKCHIP_NEW_IDB=y
|
||||
CONFIG_LOADER_INI="RK3588MINIALL.ini"
|
||||
CONFIG_TRUST_INI="RK3588TRUST.ini"
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_TARGET_EVB_RK3588=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-cm3588"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_LOCALVERSION="-armbian"
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_FIT_HW_CRYPTO=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_SPL_FIT_HW_CRYPTO=y
|
||||
# CONFIG_SPL_SYS_DCACHE_OFF is not set
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_ANDROID_BOOTLOADER=y
|
||||
CONFIG_ANDROID_AVB=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
|
||||
CONFIG_SPL_MMC_WRITE=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DTIMG=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_BOOT_ANDROID=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TFTP_BOOTM=y
|
||||
CONFIG_CMD_TFTP_FLASH=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_MTD_BLK=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_DTB_MINIMUM=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
# CONFIG_NET_TFTP_VARS is not set
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
# CONFIG_SARADC_ROCKCHIP is not set
|
||||
CONFIG_SARADC_ROCKCHIP_V2=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_SCMI=y
|
||||
CONFIG_SPL_CLK_SCMI=y
|
||||
CONFIG_DM_CRYPTO=y
|
||||
CONFIG_SPL_DM_CRYPTO=y
|
||||
CONFIG_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_ROCKCHIP=y
|
||||
CONFIG_SCMI_FIRMWARE=y
|
||||
CONFIG_SPL_SCMI_FIRMWARE=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_DM_KEY=y
|
||||
CONFIG_ADC_KEY=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SPL_MISC=y
|
||||
CONFIG_MISC_DECOMPRESS=y
|
||||
CONFIG_SPL_MISC_DECOMPRESS=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLK=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=80000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_NVME=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_SPI_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_RK860X=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_ROCKCHIP_SDRAM_COMMON=y
|
||||
CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_RESET_ROCKCHIP=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_ROCKCHIP_SPI=y
|
||||
CONFIG_ROCKCHIP_SFC=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_PCI=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_DRM_ROCKCHIP=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
|
||||
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
|
||||
CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_LIB_RAND=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_N_SIZE=0x200
|
||||
CONFIG_RSA_E_SIZE=0x10
|
||||
CONFIG_RSA_C_SIZE=0x20
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_AVB_LIBAVB=y
|
||||
CONFIG_AVB_LIBAVB_AB=y
|
||||
CONFIG_AVB_LIBAVB_ATX=y
|
||||
CONFIG_AVB_LIBAVB_USER=y
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
@@ -0,0 +1,216 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARM_CPU_SUSPEND=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x80000
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_ROCKCHIP_USB_BOOT=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE=y
|
||||
CONFIG_ROCKCHIP_HWID_DTB=y
|
||||
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
|
||||
CONFIG_USING_KERNEL_DTB_V2=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
|
||||
CONFIG_ROCKCHIP_NEW_IDB=y
|
||||
CONFIG_LOADER_INI="RK3588MINIALL.ini"
|
||||
CONFIG_TRUST_INI="RK3588TRUST.ini"
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_TARGET_EVB_RK3588=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_LOCALVERSION="-armbian"
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_FIT_HW_CRYPTO=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_SPL_FIT_HW_CRYPTO=y
|
||||
# CONFIG_SPL_SYS_DCACHE_OFF is not set
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_ANDROID_BOOTLOADER=y
|
||||
CONFIG_ANDROID_AVB=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
|
||||
CONFIG_SPL_MMC_WRITE=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DTIMG=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_BOOT_ANDROID=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TFTP_BOOTM=y
|
||||
CONFIG_CMD_TFTP_FLASH=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_MTD_BLK=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_DTB_MINIMUM=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
# CONFIG_NET_TFTP_VARS is not set
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
# CONFIG_SARADC_ROCKCHIP is not set
|
||||
CONFIG_SARADC_ROCKCHIP_V2=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_SCMI=y
|
||||
CONFIG_SPL_CLK_SCMI=y
|
||||
CONFIG_DM_CRYPTO=y
|
||||
CONFIG_SPL_DM_CRYPTO=y
|
||||
CONFIG_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_ROCKCHIP=y
|
||||
CONFIG_SCMI_FIRMWARE=y
|
||||
CONFIG_SPL_SCMI_FIRMWARE=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_DM_KEY=y
|
||||
CONFIG_ADC_KEY=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SPL_MISC=y
|
||||
CONFIG_MISC_DECOMPRESS=y
|
||||
CONFIG_SPL_MISC_DECOMPRESS=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLK=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=80000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_NVME=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_SPI_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_RK860X=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_ROCKCHIP_SDRAM_COMMON=y
|
||||
CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_RESET_ROCKCHIP=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_ROCKCHIP_SPI=y
|
||||
CONFIG_ROCKCHIP_SFC=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_PCI=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_DRM_ROCKCHIP=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
|
||||
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
|
||||
CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_LIB_RAND=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_N_SIZE=0x200
|
||||
CONFIG_RSA_E_SIZE=0x10
|
||||
CONFIG_RSA_C_SIZE=0x20
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_AVB_LIBAVB=y
|
||||
CONFIG_AVB_LIBAVB_AB=y
|
||||
CONFIG_AVB_LIBAVB_ATX=y
|
||||
CONFIG_AVB_LIBAVB_USER=y
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
@@ -0,0 +1,217 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARM_CPU_SUSPEND=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x80000
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_ROCKCHIP_USB_BOOT=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE=y
|
||||
CONFIG_ROCKCHIP_HWID_DTB=y
|
||||
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
|
||||
CONFIG_USING_KERNEL_DTB_V2=y
|
||||
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
|
||||
CONFIG_ROCKCHIP_NEW_IDB=y
|
||||
CONFIG_LOADER_INI="RK3588MINIALL.ini"
|
||||
CONFIG_TRUST_INI="RK3588TRUST.ini"
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_TARGET_EVB_RK3588=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-nanopi-r6s"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_FIT_HW_CRYPTO=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_SPL_FIT_HW_CRYPTO=y
|
||||
# CONFIG_SPL_SYS_DCACHE_OFF is not set
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_ANDROID_BOOTLOADER=y
|
||||
CONFIG_ANDROID_AVB=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
|
||||
CONFIG_SPL_MMC_WRITE=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DTIMG=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
CONFIG_CMD_GPT=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_BOOT_ANDROID=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TFTP_BOOTM=y
|
||||
CONFIG_CMD_TFTP_FLASH=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_MTD_BLK=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_SPL_DTB_MINIMUM=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
# CONFIG_NET_TFTP_VARS is not set
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
# CONFIG_SARADC_ROCKCHIP is not set
|
||||
CONFIG_SARADC_ROCKCHIP_V2=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_SCMI=y
|
||||
CONFIG_SPL_CLK_SCMI=y
|
||||
CONFIG_DM_CRYPTO=y
|
||||
CONFIG_SPL_DM_CRYPTO=y
|
||||
CONFIG_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_RNG_ROCKCHIP=y
|
||||
CONFIG_SCMI_FIRMWARE=y
|
||||
CONFIG_SPL_SCMI_FIRMWARE=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_DM_KEY=y
|
||||
CONFIG_ADC_KEY=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SPL_MISC=y
|
||||
CONFIG_MISC_DECOMPRESS=y
|
||||
CONFIG_SPL_MISC_DECOMPRESS=y
|
||||
CONFIG_ROCKCHIP_OTP=y
|
||||
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
|
||||
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLK=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=80000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_NVME=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_SPI_RK8XX=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_RK860X=y
|
||||
CONFIG_REGULATOR_RK806=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_TPL_RAM=y
|
||||
CONFIG_ROCKCHIP_SDRAM_COMMON=y
|
||||
CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_RESET_ROCKCHIP=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_ROCKCHIP_SPI=y
|
||||
CONFIG_ROCKCHIP_SFC=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_PCI=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_DRM_ROCKCHIP=y
|
||||
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
|
||||
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
|
||||
CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_LIB_RAND=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_N_SIZE=0x200
|
||||
CONFIG_RSA_E_SIZE=0x10
|
||||
CONFIG_RSA_C_SIZE=0x20
|
||||
CONFIG_LZ4=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_AVB_LIBAVB=y
|
||||
CONFIG_AVB_LIBAVB_AB=y
|
||||
CONFIG_AVB_LIBAVB_ATX=y
|
||||
CONFIG_AVB_LIBAVB_USER=y
|
||||
CONFIG_RK_AVB_LIBAVB_USER=y
|
||||
CONFIG_OPTEE_CLIENT=y
|
||||
CONFIG_OPTEE_V2=y
|
||||
CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
|
||||
@@ -0,0 +1,161 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3588.dtsi"
|
||||
#include "rk3588-u-boot.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
|
||||
/ {
|
||||
model = "ArmSoM SIGE7";
|
||||
compatible = "armsom,armsom-sige7", "rockchip,rk3588";
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
led_sys: led-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "led_sys";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; // Turn on user led
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 1>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
|
||||
volumeup-key {
|
||||
u-boot,dm-pre-reloc;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
label = "volume up";
|
||||
press-threshold-microvolt = <1750>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pcie30: vcc3v3-pcie30 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie30";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
u-boot,dm-pre-reloc;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3m0_xfer>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
usbc0: fusb302@22 {
|
||||
compatible = "fcs,fusb302";
|
||||
u-boot,dm-pre-reloc;
|
||||
reg = <0x22>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
|
||||
int-n-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usbc0_int>;
|
||||
// vbus-supply = <&vcc12v_dcin>;
|
||||
status = "okay";
|
||||
|
||||
usb_con: connector {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
data-role = "dual";
|
||||
power-role = "sink";
|
||||
try-power-role = "sink";
|
||||
op-sink-microwatt = <1000000>;
|
||||
sink-pdos =
|
||||
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
|
||||
PDO_VAR(5000, 12000, 5000)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
|
||||
usbc {
|
||||
u-boot,dm-pre-reloc;
|
||||
usbc0_int: usbc0-int {
|
||||
u-boot,dm-pre-reloc;
|
||||
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3m0_xfer {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&php_grf {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&ioc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&cru {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pcfg_pull_none_smt {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,88 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3588.dtsi"
|
||||
#include "rk3588-u-boot.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "ArmSoM W3 (LGA Module ArmSoM-LM5 LP4x) V1.1";
|
||||
compatible = "rockchip,rk3588-armsom-w3", "rockchip,rk3588";
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
led_sys: led-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "led_sys";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; // Turn on user led
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 1>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
|
||||
volumeup-key {
|
||||
u-boot,dm-pre-reloc;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
label = "volume up";
|
||||
press-threshold-microvolt = <1750>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pcie30: vcc3v3-pcie30 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie30";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,235 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3588.dtsi"
|
||||
#include "rk3588-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec CM3588";
|
||||
compatible = "friendlyelec,cm3588", "rockchip,rk3588";
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc_5v0: vcc-5v0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_5v0_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie30: vcc3v3-pcie30 {
|
||||
u-boot,dm-pre-reloc;
|
||||
startup-delay-us = <50000>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie30";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
led_sys: led-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "led_sys";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; // Turn on user led
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1l0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
/* 2. CON14: pcie30phy port0 lane1 */
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <1>;
|
||||
phys = <&pcie30phy>;
|
||||
reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
nvme1: pcie@20,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1l1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
/* 4. CON16: pcie30phy port1 lane1 */
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <1>;
|
||||
phys = <&pcie30phy>;
|
||||
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00300000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
nvme3: pcie@30,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
/* 1. CON13: pcie30phy port0 lane0 */
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
nvme0: pcie@0,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
u-boot,dm-pre-reloc;
|
||||
/* 3. CON15: pcie30phy port1 lane0 */
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
nvme2: pcie@10,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
u-boot,dm-pre-reloc;
|
||||
rockchip,pcie30-phymode = <PHY_MODE_PCIE_NABIBI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2_psu {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_grf {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&usb2phy2_grf {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
usb {
|
||||
u-boot,dm-pre-reloc;
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
u-boot,dm-pre-reloc;
|
||||
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
power {
|
||||
u-boot,dm-spl;
|
||||
vcc_5v0_en: vcc-5v0-en {
|
||||
u-boot,dm-spl;
|
||||
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
161
patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588-nanopc-t6.dts
Normal file
161
patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588-nanopc-t6.dts
Normal file
@@ -0,0 +1,161 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3588.dtsi"
|
||||
#include "rk3588-u-boot.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "NanoPC-T6";
|
||||
compatible = "nanopc,nanopc-t6", "rockchip,rk3588";
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc_5v0: vcc-5v0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_5v0_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie30: vcc3v3-pcie30 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie30";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
startup-delay-us = <50000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
led_sys: led-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "led_sys";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; // Turn on user led
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x4 {
|
||||
u-boot,dm-pre-reloc;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2_psu {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_grf {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&usb2phy2_grf {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
usb {
|
||||
u-boot,dm-pre-reloc;
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
u-boot,dm-pre-reloc;
|
||||
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
power {
|
||||
u-boot,dm-spl;
|
||||
vcc_5v0_en: vcc-5v0-en {
|
||||
u-boot,dm-spl;
|
||||
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,126 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3588.dtsi"
|
||||
#include "rk3588-u-boot.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "NanoPi R6S";
|
||||
compatible = "nanopi,nanopi-r6s", "rockchip,rk3588";
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc_5v0: vcc-5v0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_5v0_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
led_sys: led-sys {
|
||||
u-boot,dm-pre-reloc;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "led_sys";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; // Turn on user led
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb2phy0_grf {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&usb2phy2_grf {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
usb {
|
||||
u-boot,dm-pre-reloc;
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
u-boot,dm-pre-reloc;
|
||||
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
power {
|
||||
u-boot,dm-spl;
|
||||
vcc_5v0_en: vcc-5v0-en {
|
||||
u-boot,dm-spl;
|
||||
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user