From 73691a9e24440e0a8104b2c25d168ba8947a10ad Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 4 Aug 2022 21:50:40 +0200 Subject: [PATCH] meson64: edge: rework to kernel 5.19 (#3941) * meson64-edge/5.19: use `tag:v5.19-rc2`, meson64 kernel config and kernel patches, by @adeepv * meson64-edge/5.19: we don't need `CONFIG_ARCH_ROCKCHIP=y` for meson64, right? * meson64-edge/5.19: remove `meson_drv_shutdown` revert patch, instead `CONFIG_DRM_MESON=y` and its dependencies in .config - this allows other meson64's to shutdown properly, while allowing the N2(+) to reboot without kernel-side hangs * meson64-edge/5.19: odroidn2(+): remove SD UHS modes patch for ODROID N2(+) - it works when cold-booted - but changes voltage to enable - when rebooted, voltage persists and uboot can't read the SD anymore - adding the "odroid,reboot" driver+dt that is supposed to fix this, doesn't - so for now remove it * meson64-edge/5.19: odroidn2(+): add dumb gpio fan at 30 celsius - backport from rework in 5.10 * meson64-edge/5.19: odroidhc4: bring back `fan1_input` by adding fan details to DT - yeah, I know; the cooling map is right there too, so empty, poor thing. for later. * meson64-edge/5.19: bump to 5.19-rc3 * meson64-edge/5.19: radxa-zero: add patch to remove UHS mode so `wifi` works - sent by @pyavitz: https://raw.githubusercontent.com/pyavitz/debian-image-builder/feature/patches/amlogic/radxazero/wifi/001-arm64-dts-amlogic-radxa-zero-sdio-card-speed.patch - tested by @lanefu * meson64-edge/5.19: bump to 5.19-rc4 * meson64-edge/5.19: bump to 5.19-rc5 * meson64-edge/5.19: bump to 5.19-rc7 * meson64-edge/5.19: bump to 5.19.y branch, which is 5.19.0 right now * Add kernel config - tested on Odroid N2+ Co-authored-by: Vyacheslav Bocharov Co-authored-by: Igor Pecovnik --- config/kernel/linux-meson64-edge.config | 1274 +++++++------ .../families/include/meson64_common.inc | 12 +- .../meson64-5.19/add-board-radxa-zero2.patch | 576 ++++++ ...use-gpio-fan-matrix-instead-of-array.patch | 39 + ...ard-khadas-vim3-fix-missing-i2c3-nod.patch | 38 + ...ard-khadas-vims-add-rtc-vrtc-aliases.patch | 60 + .../board-nanopi-k2-add-uartC-alias.patch | 12 + .../board-nanopi-k2-enable-emmc.patch | 22 + .../board-odroidc2-add-uartA-uartC.patch | 32 + .../board-odroidc2-enable-SPI.patch | 37 + .../board-odroidc2-enable-scpi-dvfs.patch | 14 + .../board-odroidhc4-enable-fan1_input.patch | 29 + .../board-odroidn2-add-dumb-gpio-fan.patch | 40 + ...oidn2-add-gpio-fan-as-cooling-device.patch | 73 + ...d-odroidn2-add-spi-flash-enabled-dts.patch | 84 + ...ard-odroidn2plus-Add-missing-CPU-opp.patch | 46 + ...add-support-for-the-usb-c-controller.patch | 94 + ...-dts-slow-down-sdio-for-working-wifi.patch | 12 + .../drv-spi-spidev-remove-warnings.patch | 31 + ...eral-add-Amlogic-Meson-GX-PM-Suspend.patch | 135 ++ ...eral-add-overlay-compilation-support.patch | 91 + ...hdmi-call-hdmi_set_cts_n-after-clock.patch | 29 + ...eral-drm-panfrost-fix-reference-leak.patch | 39 + ...ral-fix-Kodi-sysinfo-CPU-information.patch | 31 + ...add-new-display-resolution-2560x1440.patch | 76 + ...odec-reorder-channel-allocation-list.patch | 202 +++ ...mon-pwm-fan-fix-to-add-pwm1_enable-t.patch | 141 ++ .../general-increase-cma-pool-896MB.patch | 56 + ...put-touchscreen-Add-D-WAV-Multitouch.patch | 637 +++++++ .../general-kernel-odroidn2-current.patch | 16 + ...cec-silence-CEC-timeout-message-HACK.patch | 40 + .../general-memory-marked-nomap.patch | 38 + ...aiu-Fix-HDMI-codec-control-selection.patch | 233 +++ ...al-meson-gx-mmc-fix-deferred-probing.patch | 35 + ...c-set-core-clock-phase-to-270-degres.patch | 59 + ...ral-meson-vdec-add-HEVC-decode-codec.patch | 1609 +++++++++++++++++ ...n-vdec-add-handling-to-HEVC-decoder-.patch | 157 ++ ...ec-check-if-parser-has-really-parser.patch | 51 + ...n-vdec-improve-mmu-and-fbc-handling-.patch | 586 ++++++ ...n-vdec-remove-redundant-if-statement.patch | 29 + .../general-meson64-overlays.patch | 262 +++ ...m-gpio-Add-a-generic-gpio-based-PWM-.patch | 368 ++++ ...ernate-pulse-and-space-timing-events.patch | 14 + .../general-si2168-fix-cmd-timeout.patch | 28 + ...soc-remove-mono-channel-as-it-curren.patch | 37 + ...al-spi-nor-add-support-for-XT25F128B.patch | 90 + ...prove-handling-of-hubs-with-no-ports.patch | 54 + ...gpio-irq-patch-from-https-lkml.org-l.patch | 100 + ...02-arm64-meson-add-JetHub-D1p-device.patch | 47 + .../meson64-5.19/jethome-0003-overlay.patch | 65 + ...x-dts-add-support-for-GX-PM-and-VRTC.patch | 41 + .../meson-gxbb-dts-i2cX-missing-pins.patch | 22 + ...n-gxbb-vdec-add-HEVC-support-to-GXBB.patch | 39 + ...eson-gxm-vdec-add-VP9-support-to-GXM.patch | 44 + .../meson-sm1-dts-add-higher-clocks.patch | 34 + patch/kernel/meson64-edge | 2 +- 56 files changed, 7513 insertions(+), 549 deletions(-) create mode 100644 patch/kernel/archive/meson64-5.19/add-board-radxa-zero2.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-khadas-vim2-use-gpio-fan-matrix-instead-of-array.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-khadas-vim3-fix-missing-i2c3-nod.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-khadas-vims-add-rtc-vrtc-aliases.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-nanopi-k2-add-uartC-alias.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-nanopi-k2-enable-emmc.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-odroidc2-add-uartA-uartC.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-odroidc2-enable-SPI.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-odroidc2-enable-scpi-dvfs.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-odroidhc4-enable-fan1_input.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-odroidn2-add-dumb-gpio-fan.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-odroidn2-add-gpio-fan-as-cooling-device.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-odroidn2-add-spi-flash-enabled-dts.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-odroidn2plus-Add-missing-CPU-opp.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch create mode 100644 patch/kernel/archive/meson64-5.19/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch create mode 100644 patch/kernel/archive/meson64-5.19/drv-spi-spidev-remove-warnings.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-add-Amlogic-Meson-GX-PM-Suspend.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-add-overlay-compilation-support.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-drm-panfrost-fix-reference-leak.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-fix-Kodi-sysinfo-CPU-information.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-gpu-drm-add-new-display-resolution-2560x1440.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-hdmi-codec-reorder-channel-allocation-list.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-hwmon-pwm-fan-fix-to-add-pwm1_enable-t.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-increase-cma-pool-896MB.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-input-touchscreen-Add-D-WAV-Multitouch.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-kernel-odroidn2-current.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-media-cec-silence-CEC-timeout-message-HACK.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-memory-marked-nomap.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-meson-aiu-Fix-HDMI-codec-control-selection.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-fix-deferred-probing.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-meson-vdec-add-HEVC-decode-codec.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-meson-vdec-add-handling-to-HEVC-decoder-.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-meson-vdec-check-if-parser-has-really-parser.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-meson-vdec-improve-mmu-and-fbc-handling-.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-meson-vdec-remove-redundant-if-statement.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-meson64-overlays.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-pwm-gpio-Add-a-generic-gpio-based-PWM-.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-rc-drivers-should-produce-alternate-pulse-and-space-timing-events.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-si2168-fix-cmd-timeout.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-sound-soc-remove-mono-channel-as-it-curren.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-spi-nor-add-support-for-XT25F128B.patch create mode 100644 patch/kernel/archive/meson64-5.19/general-usb-core-improve-handling-of-hubs-with-no-ports.patch create mode 100644 patch/kernel/archive/meson64-5.19/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch create mode 100644 patch/kernel/archive/meson64-5.19/jethome-0002-arm64-meson-add-JetHub-D1p-device.patch create mode 100644 patch/kernel/archive/meson64-5.19/jethome-0003-overlay.patch create mode 100644 patch/kernel/archive/meson64-5.19/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch create mode 100644 patch/kernel/archive/meson64-5.19/meson-gxbb-dts-i2cX-missing-pins.patch create mode 100644 patch/kernel/archive/meson64-5.19/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch create mode 100644 patch/kernel/archive/meson64-5.19/meson-gxm-vdec-add-VP9-support-to-GXM.patch create mode 100644 patch/kernel/archive/meson64-5.19/meson-sm1-dts-add-higher-clocks.patch diff --git a/config/kernel/linux-meson64-edge.config b/config/kernel/linux-meson64-edge.config index 950fd1d6d..333e1f9ff 100644 --- a/config/kernel/linux-meson64-edge.config +++ b/config/kernel/linux-meson64-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.17.1 Kernel Configuration +# Linux/arm64 5.19.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y @@ -16,6 +16,7 @@ CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=122 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y @@ -31,9 +32,9 @@ CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYSVIPC_COMPAT=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_WATCH_QUEUE is not set @@ -52,7 +53,6 @@ CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y @@ -106,6 +106,7 @@ CONFIG_PREEMPT_BUILD=y CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y CONFIG_PREEMPTION=y +# CONFIG_PREEMPT_DYNAMIC is not set # # CPU/Task time and stats accounting @@ -136,7 +137,6 @@ CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU=y -CONFIG_TASKS_RUDE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y @@ -161,6 +161,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_CC_HAS_INT128=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y @@ -209,6 +210,7 @@ CONFIG_RD_LZO=y CONFIG_RD_LZ4=y CONFIG_RD_ZSTD=y # CONFIG_BOOT_CONFIG is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y @@ -240,7 +242,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y @@ -257,22 +258,12 @@ CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y -# CONFIG_COMPAT_BRK is not set -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -CONFIG_SLAB_MERGE_DEFAULT=y -# CONFIG_SLAB_FREELIST_RANDOM is not set -# CONFIG_SLAB_FREELIST_HARDENED is not set -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -CONFIG_SLUB_CPU_PARTIAL=y CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y # end of General setup CONFIG_ARM64=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_64BIT=y CONFIG_MMU=y CONFIG_ARM64_PAGE_SHIFT=12 @@ -325,7 +316,7 @@ CONFIG_ARCH_MESON=y # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set -CONFIG_ARCH_ROCKCHIP=y +# CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S32 is not set # CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_INTEL_SOCFPGA is not set @@ -490,10 +481,12 @@ CONFIG_ARM64_EPAN=y # end of ARMv8.7 architectural features CONFIG_ARM64_SVE=y +CONFIG_ARM64_SME=y CONFIG_ARM64_MODULE_PLTS=y # CONFIG_ARM64_PSEUDO_NMI is not set CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set +CONFIG_ARCH_NR_GPIO=0 # end of Kernel Features # @@ -506,8 +499,6 @@ CONFIG_EFI=y CONFIG_DMI=y # end of Boot options -CONFIG_SYSVIPC_COMPAT=y - # # Power management options # @@ -549,6 +540,7 @@ CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set CONFIG_DT_IDLE_STATES=y +CONFIG_DT_IDLE_GENPD=y # # ARM CPU Idle Drivers @@ -665,6 +657,8 @@ CONFIG_CRYPTO_SHA2_ARM64_CE=y CONFIG_CRYPTO_SHA3_ARM64=m CONFIG_CRYPTO_SM3_ARM64_CE=m CONFIG_CRYPTO_SM4_ARM64_CE=m +CONFIG_CRYPTO_SM4_ARM64_CE_BLK=m +CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=m CONFIG_CRYPTO_GHASH_ARM64_CE=y # CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set CONFIG_CRYPTO_AES_ARM64=y @@ -686,6 +680,7 @@ CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_KRETPROBES=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y @@ -756,6 +751,7 @@ CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y # CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y @@ -766,8 +762,11 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y # # GCOV-based kernel profiling @@ -779,7 +778,6 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set -# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y @@ -789,6 +787,7 @@ CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_MODULE_SIG=y @@ -810,6 +809,7 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y @@ -841,6 +841,7 @@ CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_PM=y CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y # # IO Schedulers @@ -874,6 +875,7 @@ CONFIG_FREEZER=y CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y CONFIG_ARCH_HAVE_ELF_PROT=y CONFIG_ARCH_USE_GNU_PROPERTY=y CONFIG_ELFCORE=y @@ -886,6 +888,41 @@ CONFIG_COREDUMP=y # # Memory Management options # +CONFIG_ZPOOL=y +CONFIG_SWAP=y +CONFIG_ZSWAP=y +CONFIG_ZSWAP_DEFAULT_ON=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd" +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="z3fold" +CONFIG_ZBUD=y +CONFIG_Z3FOLD=y +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +# CONFIG_COMPAT_BRK is not set CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y @@ -895,8 +932,8 @@ CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -# CONFIG_MEMORY_HOTPLUG is not set CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_MEMORY_HOTPLUG is not set CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_MEMORY_BALLOON=y @@ -917,6 +954,7 @@ CONFIG_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_USE_PERCPU_NUMA_NODE_ID=y @@ -927,40 +965,25 @@ CONFIG_CMA=y # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 -CONFIG_ZSWAP=y -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set -CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y -CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd" -# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y -# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT="z3fold" -CONFIG_ZSWAP_DEFAULT_ON=y -CONFIG_ZPOOL=y -CONFIG_ZBUD=y -CONFIG_Z3FOLD=y -CONFIG_ZSMALLOC=y -# CONFIG_ZSMALLOC_STAT is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y CONFIG_VMAP_PFN=y +CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set -# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_MAPPING_DIRTY_HELPERS=y CONFIG_SECRETMEM=y # CONFIG_ANON_VMA_NAME is not set +# CONFIG_USERFAULTFD is not set # # Data Access Monitoring @@ -1689,6 +1712,7 @@ CONFIG_OPENVSWITCH_GENEVE=m CONFIG_VSOCKETS=m CONFIG_VSOCKETS_DIAG=m CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VMWARE_VMCI_VSOCKETS=m CONFIG_VIRTIO_VSOCKETS=m CONFIG_VIRTIO_VSOCKETS_COMMON=m CONFIG_HYPERV_VSOCKETS=m @@ -1772,6 +1796,9 @@ CONFIG_CAN_C_CAN_PCI=m CONFIG_CAN_CC770=m CONFIG_CAN_CC770_ISA=m CONFIG_CAN_CC770_PLATFORM=m +CONFIG_CAN_CTUCANFD=m +CONFIG_CAN_CTUCANFD_PCI=m +CONFIG_CAN_CTUCANFD_PLATFORM=m # CONFIG_CAN_IFI_CANFD is not set CONFIG_CAN_M_CAN=m CONFIG_CAN_M_CAN_PCI=m @@ -1881,6 +1908,7 @@ CONFIG_AF_RXRPC=m # CONFIG_AF_KCM is not set CONFIG_STREAM_PARSER=y CONFIG_MCTP=y +CONFIG_MCTP_FLOWS=y CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y @@ -1984,6 +2012,7 @@ CONFIG_NET_SELFTESTS=y CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y +# CONFIG_PAGE_POOL_STATS is not set CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y CONFIG_NETDEV_ADDR_LIST_TEST=m @@ -2023,6 +2052,8 @@ CONFIG_PCIE_BUS_DEFAULT=y # CONFIG_PCIE_BUS_SAFE is not set # CONFIG_PCIE_BUS_PERFORMANCE is not set # CONFIG_PCIE_BUS_PEER2PEER is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_ACPI=y # CONFIG_HOTPLUG_PCI_ACPI_IBM is not set @@ -2041,8 +2072,6 @@ CONFIG_PCI_XGENE_MSI=y # CONFIG_PCIE_ALTERA is not set CONFIG_PCI_HOST_THUNDER_PEM=y CONFIG_PCI_HOST_THUNDER_ECAM=y -CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCI_HYPERV_INTERFACE=m # CONFIG_PCIE_MICROCHIP_HOST is not set # CONFIG_PCIE_HISI_ERR is not set @@ -2054,7 +2083,6 @@ CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y # CONFIG_PCIE_DW_PLAT_HOST is not set CONFIG_PCI_HISI=y -# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set CONFIG_PCIE_KIRIN=y CONFIG_PCI_MESON=y # CONFIG_PCIE_AL is not set @@ -2086,15 +2114,19 @@ CONFIG_PCI_MESON=y # end of PCI switch controller drivers CONFIG_CXL_BUS=m -CONFIG_CXL_MEM=m +CONFIG_CXL_PCI=m # CONFIG_CXL_MEM_RAW_COMMANDS is not set CONFIG_CXL_ACPI=m +CONFIG_CXL_MEM=m +CONFIG_CXL_PORT=m +CONFIG_CXL_SUSPEND=y # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set # # Generic Driver Options # +CONFIG_AUXILIARY_BUS=y CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y @@ -2108,11 +2140,13 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set # CONFIG_FW_LOADER_COMPRESS is not set CONFIG_FW_CACHE=y +# CONFIG_FW_UPLOAD is not set # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -2150,6 +2184,7 @@ CONFIG_VEXPRESS_CONFIG=y CONFIG_MHI_BUS=m # CONFIG_MHI_BUS_DEBUG is not set CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_BUS_EP=m # end of Bus devices CONFIG_CONNECTOR=m @@ -2164,8 +2199,11 @@ CONFIG_CONNECTOR=m CONFIG_ARM_SCMI_PROTOCOL=y CONFIG_ARM_SCMI_HAVE_TRANSPORT=y CONFIG_ARM_SCMI_HAVE_SHMEM=y +CONFIG_ARM_SCMI_HAVE_MSG=y CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y +CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y CONFIG_ARM_SCMI_TRANSPORT_SMC=y +# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set CONFIG_ARM_SCMI_POWER_DOMAIN=y # end of ARM System Control and Management Interface Protocol @@ -2178,7 +2216,6 @@ CONFIG_DMIID=y # CONFIG_DMI_SYSFS is not set # CONFIG_ISCSI_IBFT is not set # CONFIG_FW_CFG_SYSFS is not set -CONFIG_SYSFB=y # CONFIG_SYSFB_SIMPLEFB is not set CONFIG_ARM_FFA_TRANSPORT=m CONFIG_ARM_FFA_SMCCC=y @@ -2201,12 +2238,14 @@ CONFIG_EFI_CAPSULE_LOADER=y # CONFIG_EFI_TEST is not set # CONFIG_RESET_ATTACK_MITIGATION is not set # CONFIG_EFI_DISABLE_PCI_DMA is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EFI_COCO_SECRET is not set # end of EFI (Extensible Firmware Interface) Support CONFIG_UEFI_CPER=y CONFIG_UEFI_CPER_ARM=y -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y CONFIG_MESON_SM=y CONFIG_MESON_GX_PM=y CONFIG_ARM_PSCI_FW=y @@ -2335,7 +2374,6 @@ CONFIG_MTD_NAND_PLATFORM=m CONFIG_MTD_NAND_CADENCE=m # CONFIG_MTD_NAND_ARASAN is not set CONFIG_MTD_NAND_INTEL_LGM=m -CONFIG_MTD_NAND_ROCKCHIP=m # # Misc @@ -2356,6 +2394,7 @@ CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y # CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set # CONFIG_MTD_NAND_ECC_SW_BCH is not set +CONFIG_MTD_NAND_ECC_MXIC=y # end of ECC engine support # end of NAND @@ -2372,7 +2411,6 @@ CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y # CONFIG_MTD_SPI_NOR_SWP_KEEP is not set # CONFIG_MTD_UBI is not set CONFIG_MTD_HYPERBUS=m -CONFIG_HBMC_AM654=m CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set @@ -2430,6 +2468,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_NVME_CORE=m CONFIG_BLK_DEV_NVME=m # CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_VERBOSE_ERRORS is not set # CONFIG_NVME_HWMON is not set CONFIG_NVME_FABRICS=m # CONFIG_NVME_FC is not set @@ -2464,6 +2503,7 @@ CONFIG_PCI_ENDPOINT_TEST=m # CONFIG_XILINX_SDFEC is not set CONFIG_MISC_RTSX=m CONFIG_HISI_HIKEY_USB=m +CONFIG_OPEN_DICE=m # CONFIG_C2PORT is not set # @@ -2491,6 +2531,7 @@ CONFIG_CB710_DEBUG_ASSUMPTIONS=y # CONFIG_SENSORS_LIS3_I2C is not set CONFIG_ALTERA_STAPL=m +CONFIG_VMWARE_VMCI=m CONFIG_GENWQE=m CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 # CONFIG_ECHO is not set @@ -2570,14 +2611,6 @@ CONFIG_SCSI_HISI_SAS_PCI=m # CONFIG_SCSI_MPT2SAS is not set CONFIG_SCSI_MPI3MR=m # CONFIG_SCSI_SMARTPQI is not set -CONFIG_SCSI_UFSHCD=m -# CONFIG_SCSI_UFSHCD_PCI is not set -CONFIG_SCSI_UFSHCD_PLATFORM=m -# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set -# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set -# CONFIG_SCSI_UFS_BSG is not set -# CONFIG_SCSI_UFS_HPB is not set -# CONFIG_SCSI_UFS_HWMON is not set # CONFIG_SCSI_HPTIOP is not set # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set @@ -2869,7 +2902,11 @@ CONFIG_NET_DSA_XRS700X=m CONFIG_NET_DSA_XRS700X_I2C=m CONFIG_NET_DSA_XRS700X_MDIO=m CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_REALTEK_MDIO=m CONFIG_NET_DSA_REALTEK_SMI=m +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m CONFIG_NET_DSA_SMSC_LAN9303=m CONFIG_NET_DSA_SMSC_LAN9303_I2C=m CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m @@ -2902,8 +2939,6 @@ CONFIG_AMD_XGBE=y CONFIG_NET_VENDOR_AQUANTIA=y CONFIG_AQTION=m CONFIG_NET_VENDOR_ARC=y -CONFIG_ARC_EMAC_CORE=m -CONFIG_EMAC_ROCKCHIP=m CONFIG_NET_VENDOR_ASIX=y CONFIG_SPI_AX88796C=m # CONFIG_SPI_AX88796C_COMPRESSION is not set @@ -2931,8 +2966,6 @@ CONFIG_BNXT_SRIOV=y CONFIG_BNXT_FLOWER_OFFLOAD=y # CONFIG_BNXT_DCB is not set CONFIG_BNXT_HWMON=y -CONFIG_NET_VENDOR_BROCADE=y -CONFIG_BNA=m CONFIG_NET_VENDOR_CADENCE=y CONFIG_MACB=y CONFIG_MACB_USE_HWSTAMP=y @@ -2954,6 +2987,8 @@ CONFIG_NET_VENDOR_CISCO=y # CONFIG_ENIC is not set CONFIG_NET_VENDOR_CORTINA=y # CONFIG_GEMINI_ETHERNET is not set +CONFIG_NET_VENDOR_DAVICOM=y +CONFIG_DM9051=m # CONFIG_DNET is not set CONFIG_NET_VENDOR_DEC=y # CONFIG_NET_TULIP is not set @@ -2966,6 +3001,9 @@ CONFIG_NET_VENDOR_ENGLEDER=y # CONFIG_TSNEP is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_FUN_CORE=m +CONFIG_FUN_ETH=m CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_GVE is not set CONFIG_NET_VENDOR_HISILICON=y @@ -2995,7 +3033,6 @@ CONFIG_IGBVF=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set -CONFIG_NET_VENDOR_MICROSOFT=y # CONFIG_JME is not set CONFIG_NET_VENDOR_LITEX=y # CONFIG_LITEX_LITEETH is not set @@ -3008,6 +3045,7 @@ CONFIG_OCTEONTX2_MBOX=m # CONFIG_OCTEONTX2_AF is not set CONFIG_OCTEONTX2_PF=m CONFIG_OCTEONTX2_VF=m +CONFIG_OCTEON_EP=m CONFIG_PRESTERA=m CONFIG_PRESTERA_PCI=m CONFIG_NET_VENDOR_MELLANOX=y @@ -3029,9 +3067,12 @@ CONFIG_NET_VENDOR_MICROCHIP=y CONFIG_NET_VENDOR_MICROSEMI=y CONFIG_MSCC_OCELOT_SWITCH_LIB=m CONFIG_MSCC_OCELOT_SWITCH=m +CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y # CONFIG_MYRI10GE is not set # CONFIG_FEALNX is not set +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set CONFIG_NET_VENDOR_NATSEMI=y # CONFIG_NATSEMI is not set # CONFIG_NS83820 is not set @@ -3040,8 +3081,6 @@ CONFIG_NET_VENDOR_NETERION=y # CONFIG_VXGE is not set CONFIG_NET_VENDOR_NETRONOME=y # CONFIG_NFP is not set -CONFIG_NET_VENDOR_NI=y -# CONFIG_NI_XGE_MANAGEMENT_ENET is not set CONFIG_NET_VENDOR_8390=y # CONFIG_NE2K_PCI is not set CONFIG_NET_VENDOR_NVIDIA=y @@ -3058,6 +3097,8 @@ CONFIG_NET_VENDOR_QLOGIC=y # CONFIG_QLCNIC is not set # CONFIG_NETXEN_NIC is not set # CONFIG_QED is not set +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_BNA=m CONFIG_NET_VENDOR_QUALCOMM=y CONFIG_QCA7000=m # CONFIG_QCA7000_SPI is not set @@ -3076,14 +3117,19 @@ CONFIG_ROCKER=m CONFIG_NET_VENDOR_SAMSUNG=y # CONFIG_SXGBE_ETH is not set CONFIG_NET_VENDOR_SEEQ=y -CONFIG_NET_VENDOR_SOLARFLARE=y -# CONFIG_SFC is not set -# CONFIG_SFC_FALCON is not set CONFIG_NET_VENDOR_SILAN=y # CONFIG_SC92031 is not set CONFIG_NET_VENDOR_SIS=y # CONFIG_SIS900 is not set # CONFIG_SIS190 is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +# CONFIG_SFC is not set +# CONFIG_SFC_FALCON is not set +CONFIG_SFC_SIENA=m +CONFIG_SFC_SIENA_MTD=y +CONFIG_SFC_SIENA_MCDI_MON=y +# CONFIG_SFC_SIENA_SRIOV is not set +CONFIG_SFC_SIENA_MCDI_LOGGING=y CONFIG_NET_VENDOR_SMSC=y CONFIG_SMC91X=y # CONFIG_EPIC100 is not set @@ -3097,7 +3143,6 @@ CONFIG_STMMAC_PLATFORM=y # CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=m CONFIG_DWMAC_MESON=m -CONFIG_DWMAC_ROCKCHIP=m CONFIG_DWMAC_INTEL_PLAT=m CONFIG_DWMAC_LOONGSON=m # CONFIG_STMMAC_PCI is not set @@ -3141,6 +3186,7 @@ CONFIG_SFP=m CONFIG_AMD_PHY=m CONFIG_MESON_GXL_PHY=m CONFIG_ADIN_PHY=m +CONFIG_ADIN1100_PHY=m CONFIG_AQUANTIA_PHY=m CONFIG_AX88796B_PHY=m CONFIG_BROADCOM_PHY=m @@ -3182,6 +3228,7 @@ CONFIG_DP83TC811_PHY=m CONFIG_DP83848_PHY=m # CONFIG_DP83867_PHY is not set CONFIG_DP83869_PHY=m +CONFIG_DP83TD510_PHY=m CONFIG_VITESSE_PHY=m # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set @@ -3190,6 +3237,7 @@ CONFIG_VITESSE_PHY=m # MCTP Device Drivers # CONFIG_MCTP_SERIAL=m +CONFIG_MCTP_TRANSPORT_I2C=m # end of MCTP Device Drivers CONFIG_MDIO_DEVICE=y @@ -3435,9 +3483,12 @@ CONFIG_MT7663S=m CONFIG_MT7921_COMMON=m CONFIG_MT7921E=m CONFIG_MT7921S=m +CONFIG_MT7921U=m CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_PURELIFI=y +CONFIG_PLFXLC=m CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=m CONFIG_RT2400PCI=m @@ -3507,6 +3558,8 @@ CONFIG_RSI_91X=m CONFIG_RSI_SDIO=m CONFIG_RSI_USB=m CONFIG_RSI_COEX=y +CONFIG_WLAN_VENDOR_SILABS=y +# CONFIG_WFX is not set CONFIG_WLAN_VENDOR_ST=y CONFIG_CW1200=m CONFIG_CW1200_WLAN_SDIO=m @@ -3521,7 +3574,6 @@ CONFIG_WLCORE=m CONFIG_WLCORE_SPI=m CONFIG_WLCORE_SDIO=m CONFIG_WILINK_PLATFORM_DATA=y -CONFIG_RTL8822BS=m CONFIG_RTL8723DU=m CONFIG_RTL8723DS=m CONFIG_RTL8822CS=m @@ -3545,7 +3597,6 @@ CONFIG_VIRT_WIFI=m CONFIG_IEEE802154_DRIVERS=m CONFIG_IEEE802154_FAKELB=m CONFIG_IEEE802154_AT86RF230=m -# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set CONFIG_IEEE802154_MRF24J40=m CONFIG_IEEE802154_CC2520=m CONFIG_IEEE802154_ATUSB=m @@ -3564,6 +3615,7 @@ CONFIG_WWAN_HWSIM=m CONFIG_MHI_WWAN_CTRL=m CONFIG_MHI_WWAN_MBIM=m CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_MTK_T7XX=m # end of Wireless WAN # CONFIG_XEN_NETDEV_FRONTEND is not set @@ -3584,6 +3636,7 @@ CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=y +CONFIG_INPUT_VIVALDIFMAP=y # # Userland interfaces @@ -3690,6 +3743,7 @@ CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PXRC is not set CONFIG_JOYSTICK_QWIIC=m # CONFIG_JOYSTICK_FSIA6B is not set +CONFIG_JOYSTICK_SENSEHAT=m # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_88PM860X=m @@ -3738,6 +3792,7 @@ CONFIG_TOUCHSCREEN_ILITEK=m # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set CONFIG_TOUCHSCREEN_MSG2638=m # CONFIG_TOUCHSCREEN_MTOUCH is not set +CONFIG_TOUCHSCREEN_IMAGIS=m # CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set @@ -3845,6 +3900,7 @@ CONFIG_INPUT_PCAP=m # CONFIG_INPUT_IMS_PCU is not set CONFIG_INPUT_IQS269A=m CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_IQS7222=m # CONFIG_INPUT_CMA3000 is not set CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y # CONFIG_INPUT_SOC_BUTTON_ARRAY is not set @@ -3949,7 +4005,6 @@ CONFIG_SERIAL_SC16IS7XX_CORE=m CONFIG_SERIAL_SC16IS7XX=m CONFIG_SERIAL_SC16IS7XX_I2C=y CONFIG_SERIAL_SC16IS7XX_SPI=y -CONFIG_SERIAL_BCM63XX=m CONFIG_SERIAL_ALTERA_JTAGUART=m CONFIG_SERIAL_ALTERA_UART=m CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 @@ -4004,7 +4059,6 @@ CONFIG_HW_RANDOM_TIMERIOMEM=m CONFIG_HW_RANDOM_BA431=m CONFIG_HW_RANDOM_VIRTIO=m CONFIG_HW_RANDOM_MESON=m -CONFIG_HW_RANDOM_CAVIUM=m CONFIG_HW_RANDOM_OPTEE=m CONFIG_HW_RANDOM_CCTRNG=m CONFIG_HW_RANDOM_XIPHERA=m @@ -4078,6 +4132,7 @@ CONFIG_I2C_ALGOPCA=m # # PC SMBus host controller drivers # +CONFIG_I2C_CCGX_UCSI=m CONFIG_I2C_ALI1535=m CONFIG_I2C_ALI1563=m CONFIG_I2C_ALI15X3=m @@ -4187,7 +4242,6 @@ CONFIG_SPI_PL022=y CONFIG_SPI_PXA2XX=m CONFIG_SPI_PXA2XX_PCI=m # CONFIG_SPI_ROCKCHIP is not set -CONFIG_SPI_ROCKCHIP_SFC=m CONFIG_SPI_SC18IS602=m CONFIG_SPI_SIFIVE=m CONFIG_SPI_MXIC=m @@ -4271,7 +4325,6 @@ CONFIG_PINCTRL_MCP23S08=m # CONFIG_PINCTRL_OCELOT is not set CONFIG_PINCTRL_PALMAS=m # CONFIG_PINCTRL_RK805 is not set -CONFIG_PINCTRL_ROCKCHIP=y CONFIG_PINCTRL_SINGLE=y # CONFIG_PINCTRL_STMFX is not set CONFIG_PINCTRL_SX150X=y @@ -4289,6 +4342,7 @@ CONFIG_PINCTRL_MESON_AXG=y CONFIG_PINCTRL_MESON_AXG_PMX=y CONFIG_PINCTRL_MESON_G12A=y CONFIG_PINCTRL_MESON_A1=y +CONFIG_PINCTRL_MESON_S4=m # # Renesas pinctrl drivers @@ -4324,7 +4378,6 @@ CONFIG_GPIO_HLWD=m CONFIG_GPIO_LOGICVC=m CONFIG_GPIO_MB86S7X=m CONFIG_GPIO_PL061=y -CONFIG_GPIO_ROCKCHIP=m CONFIG_GPIO_SAMA5D2_PIOBU=m # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y @@ -4478,6 +4531,7 @@ CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PDA_POWER=m CONFIG_GENERIC_ADC_BATTERY=m +CONFIG_IP5XXX_POWER=m CONFIG_MAX8925_POWER=m CONFIG_WM831X_BACKUP=m CONFIG_WM831X_POWER=m @@ -4491,6 +4545,7 @@ CONFIG_BATTERY_DS2760=m CONFIG_BATTERY_DS2780=m CONFIG_BATTERY_DS2781=m CONFIG_BATTERY_DS2782=m +# CONFIG_BATTERY_SAMSUNG_SDI is not set CONFIG_BATTERY_SBS=m CONFIG_CHARGER_SBS=m CONFIG_MANAGER_SBS=m @@ -4548,6 +4603,7 @@ CONFIG_CHARGER_CROS_PCHG=y CONFIG_CHARGER_UCS1002=m CONFIG_CHARGER_BD99954=m CONFIG_RN5T618_POWER=m +CONFIG_BATTERY_UG3105=m CONFIG_HWMON=y CONFIG_HWMON_VID=m # CONFIG_HWMON_DEBUG_CHIP is not set @@ -4661,7 +4717,9 @@ CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=m CONFIG_SENSORS_NTC_THERMISTOR=m CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775_CORE=m CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT6775_I2C=m CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m @@ -4670,6 +4728,9 @@ CONFIG_SENSORS_NZXT_SMART2=m CONFIG_SENSORS_OCC_P8_I2C=m CONFIG_SENSORS_OCC=m CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PECI_CPUTEMP=m +CONFIG_SENSORS_PECI_DIMMTEMP=m +CONFIG_SENSORS_PECI=m CONFIG_PMBUS=m CONFIG_SENSORS_PMBUS=m CONFIG_SENSORS_ADM1266=m @@ -4688,6 +4749,7 @@ CONFIG_SENSORS_IR38064=m CONFIG_SENSORS_IRPS5401=m CONFIG_SENSORS_ISL68137=m CONFIG_SENSORS_LM25066=m +# CONFIG_SENSORS_LM25066_REGULATOR is not set CONFIG_SENSORS_LTC2978=m CONFIG_SENSORS_LTC2978_REGULATOR=y CONFIG_SENSORS_LTC3815=m @@ -4703,6 +4765,8 @@ CONFIG_SENSORS_MP2888=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP5023=m CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +# CONFIG_SENSORS_PLI1209BC_REGULATOR is not set CONFIG_SENSORS_PM6764TR=m CONFIG_SENSORS_PXE1610=m CONFIG_SENSORS_Q54SJ108A2=m @@ -4711,7 +4775,9 @@ CONFIG_SENSORS_TPS40422=m CONFIG_SENSORS_TPS53679=m CONFIG_SENSORS_UCD9000=m CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_XDPE152=m CONFIG_SENSORS_XDPE122=m +# CONFIG_SENSORS_XDPE122_REGULATOR is not set CONFIG_SENSORS_ZL6100=m CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_SBTSI=m @@ -4722,6 +4788,7 @@ CONFIG_SENSORS_SHT3x=m CONFIG_SENSORS_SHT4x=m CONFIG_SENSORS_SHTC1=m CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SY7636A=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_EMC1403=m CONFIG_SENSORS_EMC2103=m @@ -4749,6 +4816,7 @@ CONFIG_SENSORS_TMP103=m CONFIG_SENSORS_TMP108=m CONFIG_SENSORS_TMP401=m CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m CONFIG_SENSORS_TMP513=m CONFIG_SENSORS_VEXPRESS=m CONFIG_SENSORS_VIA686A=m @@ -4794,7 +4862,6 @@ CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_THERMAL_MMIO=m CONFIG_MAX77620_THERMAL=m -CONFIG_ROCKCHIP_THERMAL=m CONFIG_DA9062_THERMAL=m CONFIG_AMLOGIC_THERMAL=y CONFIG_GENERIC_ADC_THERMAL=m @@ -4942,6 +5009,7 @@ CONFIG_MFD_MAX77620=y CONFIG_MFD_MAX77650=m CONFIG_MFD_MAX77686=m CONFIG_MFD_MAX77693=y +CONFIG_MFD_MAX77714=m CONFIG_MFD_MAX77843=y CONFIG_MFD_MAX8907=m CONFIG_MFD_MAX8925=y @@ -4967,6 +5035,7 @@ CONFIG_MFD_RK808=y CONFIG_MFD_RN5T618=m CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SI476X_CORE=m +CONFIG_MFD_SIMPLE_MFD_I2C=m CONFIG_MFD_SM501=m CONFIG_MFD_SM501_GPIO=y CONFIG_MFD_SKY81452=m @@ -5134,6 +5203,8 @@ CONFIG_REGULATOR_ROHM=m CONFIG_REGULATOR_RT4801=m CONFIG_REGULATOR_RT4831=m # CONFIG_REGULATOR_RT5033 is not set +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5759=m CONFIG_REGULATOR_RT6160=m CONFIG_REGULATOR_RT6245=m CONFIG_REGULATOR_RTQ2134=m @@ -5144,12 +5215,14 @@ CONFIG_REGULATOR_S2MPS11=y # CONFIG_REGULATOR_S5M8767 is not set # CONFIG_REGULATOR_SKY81452 is not set # CONFIG_REGULATOR_SLG51000 is not set +CONFIG_REGULATOR_SY7636A=m # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set CONFIG_REGULATOR_SY8827N=m # CONFIG_REGULATOR_TPS51632 is not set CONFIG_REGULATOR_TPS6105X=m CONFIG_REGULATOR_TPS62360=m +CONFIG_REGULATOR_TPS6286X=m CONFIG_REGULATOR_TPS65023=m CONFIG_REGULATOR_TPS6507X=m CONFIG_REGULATOR_TPS65086=m @@ -5170,54 +5243,53 @@ CONFIG_REGULATOR_WM8400=m CONFIG_REGULATOR_WM8994=m CONFIG_REGULATOR_QCOM_LABIBB=m CONFIG_RC_CORE=m -CONFIG_RC_MAP=m CONFIG_LIRC=y +CONFIG_RC_MAP=m CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m CONFIG_IR_NEC_DECODER=m CONFIG_IR_RC5_DECODER=m CONFIG_IR_RC6_DECODER=m -CONFIG_IR_JVC_DECODER=m -CONFIG_IR_SONY_DECODER=m +CONFIG_IR_RCMM_DECODER=m CONFIG_IR_SANYO_DECODER=m CONFIG_IR_SHARP_DECODER=m -CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_SONY_DECODER=m CONFIG_IR_XMP_DECODER=m -CONFIG_IR_IMON_DECODER=m -CONFIG_IR_RCMM_DECODER=m CONFIG_RC_DEVICES=y -CONFIG_RC_ATI_REMOTE=m CONFIG_IR_ENE=m +CONFIG_IR_FINTEK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m CONFIG_IR_IMON=m CONFIG_IR_IMON_RAW=m -CONFIG_IR_MCEUSB=m CONFIG_IR_ITE_CIR=m -CONFIG_IR_FINTEK=m +CONFIG_IR_MCEUSB=m CONFIG_IR_MESON=m CONFIG_IR_MESON_TX=m CONFIG_IR_NUVOTON=m -CONFIG_IR_REDRAT3=m -CONFIG_IR_SPI=m -CONFIG_IR_STREAMZAP=m -CONFIG_IR_IGORPLUGUSB=m -CONFIG_IR_IGUANA=m -CONFIG_IR_TTUSBIR=m -CONFIG_RC_LOOPBACK=m -CONFIG_IR_GPIO_CIR=m -CONFIG_IR_GPIO_TX=m CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m CONFIG_IR_SERIAL=m CONFIG_IR_SERIAL_TRANSMITTER=y -CONFIG_RC_XBOX_DVD=m +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m CONFIG_IR_TOY=m -CONFIG_CEC_CORE=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_XBOX_DVD=m +CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y CONFIG_CEC_PIN=y # # CEC support # -# CONFIG_MEDIA_CEC_RC is not set CONFIG_CEC_PIN_ERROR_INJ=y CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_CEC_CH7322=m @@ -5256,7 +5328,6 @@ CONFIG_DVB_CORE=m # # Video4Linux options # -CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_I2C=y CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set @@ -5288,6 +5359,10 @@ CONFIG_DVB_DYNAMIC_MINORS=y # CONFIG_DVB_ULE_DEBUG is not set # end of Digital TV options +# +# Media drivers +# + # # Media drivers # @@ -5296,12 +5371,8 @@ CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_VIDEO_CPIA2=m CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m CONFIG_USB_GSPCA_BENQ=m CONFIG_USB_GSPCA_CONEX=m CONFIG_USB_GSPCA_CPIA1=m @@ -5326,13 +5397,13 @@ CONFIG_USB_GSPCA_SN9C2028=m CONFIG_USB_GSPCA_SN9C20X=m CONFIG_USB_GSPCA_SONIXB=m CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m CONFIG_USB_GSPCA_SPCA500=m CONFIG_USB_GSPCA_SPCA501=m CONFIG_USB_GSPCA_SPCA505=m CONFIG_USB_GSPCA_SPCA506=m CONFIG_USB_GSPCA_SPCA508=m CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SPCA1528=m CONFIG_USB_GSPCA_SQ905=m CONFIG_USB_GSPCA_SQ905C=m CONFIG_USB_GSPCA_SQ930X=m @@ -5348,29 +5419,33 @@ CONFIG_USB_GSPCA_VC032X=m CONFIG_USB_GSPCA_VICAM=m CONFIG_USB_GSPCA_XIRLINK_CIT=m CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m CONFIG_USB_PWC=m # CONFIG_USB_PWC_DEBUG is not set CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_VIDEO_CPIA2=m -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m CONFIG_USB_S2255=m +CONFIG_USB_STKWEBCAM=m CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_ZR364XX=m # # Analog TV USB devices # -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_STK1160_COMMON=m -CONFIG_VIDEO_STK1160=m CONFIG_VIDEO_GO7007=m CONFIG_VIDEO_GO7007_USB=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m # # Analog/digital TV USB devices @@ -5389,34 +5464,9 @@ CONFIG_VIDEO_TM6000_DVB=m # # Digital TV USB devices # -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_DIB3000MC=m -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -# CONFIG_DVB_USB_CXUSB_ANALOG is not set -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AZ6027=m -CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set CONFIG_DVB_USB_V2=m CONFIG_DVB_USB_AF9015=m CONFIG_DVB_USB_AF9035=m @@ -5424,19 +5474,44 @@ CONFIG_DVB_USB_ANYSEE=m CONFIG_DVB_USB_AU6610=m CONFIG_DVB_USB_AZ6007=m CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m CONFIG_DVB_USB_EC168=m CONFIG_DVB_USB_GL861=m CONFIG_DVB_USB_LME2510=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_DVBSKY=m CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +# CONFIG_DVB_USB_CXUSB_ANALOG is not set +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m CONFIG_DVB_TTUSB_BUDGET=m CONFIG_DVB_TTUSB_DEC=m -CONFIG_SMS_USB_DRV=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set -CONFIG_DVB_AS102=m # # Webcam, TV (analog/digital) USB devices @@ -5466,17 +5541,20 @@ CONFIG_VIDEO_TW68=m # # Media capture/analog TV support # +CONFIG_VIDEO_DT3155=m CONFIG_VIDEO_IVTV=m CONFIG_VIDEO_IVTV_ALSA=m CONFIG_VIDEO_FB_IVTV=m CONFIG_VIDEO_HEXIUM_GEMINI=m CONFIG_VIDEO_HEXIUM_ORION=m CONFIG_VIDEO_MXB=m -CONFIG_VIDEO_DT3155=m # # Media capture/analog/hybrid TV support # +CONFIG_VIDEO_BT848=m +CONFIG_DVB_BT8XX=m +# CONFIG_VIDEO_COBALT is not set CONFIG_VIDEO_CX18=m CONFIG_VIDEO_CX18_ALSA=m CONFIG_VIDEO_CX23885=m @@ -5490,75 +5568,178 @@ CONFIG_VIDEO_CX88_DVB=m CONFIG_VIDEO_CX88_ENABLE_VP3054=y CONFIG_VIDEO_CX88_VP3054=m CONFIG_VIDEO_CX88_MPEG=m -CONFIG_VIDEO_BT848=m -CONFIG_DVB_BT8XX=m CONFIG_VIDEO_SAA7134=m CONFIG_VIDEO_SAA7134_ALSA=m CONFIG_VIDEO_SAA7134_RC=y CONFIG_VIDEO_SAA7134_DVB=m CONFIG_VIDEO_SAA7134_GO7007=m CONFIG_VIDEO_SAA7164=m -# CONFIG_VIDEO_COBALT is not set # # Media digital TV PCI Adapters # +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +CONFIG_DVB_DM1105=m +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +# CONFIG_DVB_NETUP_UNIDVB is not set +CONFIG_DVB_NGENE=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_SMIPCIE=m CONFIG_DVB_BUDGET_CORE=m CONFIG_DVB_BUDGET=m CONFIG_DVB_BUDGET_CI=m CONFIG_DVB_BUDGET_AV=m -CONFIG_DVB_B2C2_FLEXCOP_PCI=m -# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set -CONFIG_DVB_PLUTO2=m -CONFIG_DVB_DM1105=m -CONFIG_DVB_PT1=m -CONFIG_DVB_PT3=m -CONFIG_MANTIS_CORE=m -CONFIG_DVB_MANTIS=m -CONFIG_DVB_HOPPER=m -CONFIG_DVB_NGENE=m -CONFIG_DVB_DDBRIDGE=m -# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set -CONFIG_DVB_SMIPCIE=m -# CONFIG_DVB_NETUP_UNIDVB is not set -CONFIG_RADIO_ADAPTERS=y +CONFIG_RADIO_ADAPTERS=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +# CONFIG_RADIO_SI476X is not set CONFIG_RADIO_TEA575X=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_USB_RAREMONO=m CONFIG_RADIO_SI470X=m CONFIG_USB_SI470X=m CONFIG_I2C_SI470X=m -CONFIG_RADIO_SI4713=m CONFIG_USB_SI4713=m CONFIG_PLATFORM_SI4713=m CONFIG_I2C_SI4713=m -# CONFIG_RADIO_SI476X is not set -CONFIG_USB_MR800=m -CONFIG_USB_DSBR=m -CONFIG_RADIO_MAXIRADIO=m -CONFIG_RADIO_SHARK=m -CONFIG_RADIO_SHARK2=m -CONFIG_USB_KEENE=m -CONFIG_USB_RAREMONO=m -CONFIG_USB_MA901=m -CONFIG_RADIO_TEA5764=m -CONFIG_RADIO_SAA7706H=m -CONFIG_RADIO_TEF6862=m -CONFIG_RADIO_WL1273=m +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MUX=m + +# +# Allegro DVT media platform drivers +# + +# +# Amlogic media platform drivers +# +CONFIG_VIDEO_MESON_GE2D=m + +# +# Amphion drivers +# + +# +# Aspeed media platform drivers +# +CONFIG_VIDEO_ASPEED=m + +# +# Atmel media platform drivers +# + +# +# Cadence media platform drivers +# +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m + +# +# Chips&Media media platform drivers +# + +# +# Intel media platform drivers +# + +# +# Marvell media platform drivers +# +CONFIG_VIDEO_CAFE_CCIC=m + +# +# Mediatek media platform drivers +# + +# +# NVidia media platform drivers +# + +# +# NXP media platform drivers +# + +# +# Qualcomm media platform drivers +# + +# +# Renesas media platform drivers +# + +# +# Rockchip media platform drivers +# + +# +# Samsung media platform drivers +# + +# +# STMicroelectronics media platform drivers +# + +# +# Sunxi media platform drivers +# + +# +# Texas Instruments drivers +# + +# +# VIA media platform drivers +# + +# +# Xilinx media platform drivers +# +CONFIG_VIDEO_XILINX=m +CONFIG_VIDEO_XILINX_CSI2RXSS=m +CONFIG_VIDEO_XILINX_TPG=m +CONFIG_VIDEO_XILINX_VTC=m + +# +# MMC/SDIO DVB adapters +# +CONFIG_SMS_SDIO_DRV=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +# CONFIG_DVB_TEST_DRIVERS is not set CONFIG_MEDIA_COMMON_OPTIONS=y # # common driver options # +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_TTPCI_EEPROM=m CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m -CONFIG_TTPCI_EEPROM=m -CONFIG_CYPRESS_FIRMWARE=m -CONFIG_VIDEOBUF2_CORE=m -CONFIG_VIDEOBUF2_V4L2=m -CONFIG_VIDEOBUF2_MEMOPS=m -CONFIG_VIDEOBUF2_DMA_CONTIG=m -CONFIG_VIDEOBUF2_VMALLOC=m -CONFIG_VIDEOBUF2_DMA_SG=m -CONFIG_VIDEOBUF2_DVB=m CONFIG_DVB_B2C2_FLEXCOP=m CONFIG_VIDEO_SAA7146=m CONFIG_VIDEO_SAA7146_VV=m @@ -5566,37 +5747,13 @@ CONFIG_SMS_SIANO_MDTV=m CONFIG_SMS_SIANO_RC=y # CONFIG_SMS_SIANO_DEBUGFS is not set CONFIG_VIDEO_V4L2_TPG=m -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_CAFE_CCIC=m -CONFIG_VIDEO_CADENCE=y -CONFIG_VIDEO_CADENCE_CSI2RX=m -CONFIG_VIDEO_CADENCE_CSI2TX=m -CONFIG_VIDEO_ASPEED=m -CONFIG_VIDEO_MUX=m -CONFIG_VIDEO_ROCKCHIP_ISP1=m -CONFIG_VIDEO_XILINX=m -CONFIG_VIDEO_XILINX_CSI2RXSS=m -CONFIG_VIDEO_XILINX_TPG=m -CONFIG_VIDEO_XILINX_VTC=m -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m -CONFIG_VIDEO_MESON_GE2D=m -CONFIG_VIDEO_ROCKCHIP_RGA=m -CONFIG_DVB_PLATFORM_DRIVERS=y -CONFIG_SDR_PLATFORM_DRIVERS=y - -# -# MMC/SDIO DVB adapters -# -CONFIG_SMS_SDIO_DRV=m -CONFIG_V4L_TEST_DRIVERS=y -CONFIG_VIDEO_VIMC=m -CONFIG_VIDEO_VIVID=m -CONFIG_VIDEO_VIVID_CEC=y -CONFIG_VIDEO_VIVID_MAX_DEVS=64 -CONFIG_VIDEO_VIM2M=m -CONFIG_VIDEO_VICODEC=m -# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_DVB=m # end of Media drivers # @@ -5609,25 +5766,118 @@ CONFIG_MEDIA_ATTACH=y # CONFIG_VIDEO_IR_I2C=m +# +# Camera sensor devices +# +CONFIG_VIDEO_APTINA_PLL=m +CONFIG_VIDEO_CCS_PLL=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_MAX9271_LIB=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9M032=m +CONFIG_VIDEO_MT9M111=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T001=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_NOON010PC30=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV2740=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV6650=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_OV9734=m +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RDACM21=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K4ECGX=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_S5K6AA=m +CONFIG_VIDEO_SR030PC30=m +CONFIG_VIDEO_VS6624=m +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_M5MOLS=m +# end of Camera sensor devices + +# +# Lens drivers +# +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +# end of Lens drivers + +# +# Flash devices +# +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +# end of Flash devices + # # Audio decoders, processors and mixers # -CONFIG_VIDEO_TVAUDIO=m -CONFIG_VIDEO_TDA7432=m -CONFIG_VIDEO_TDA9840=m -CONFIG_VIDEO_TDA1997X=m -CONFIG_VIDEO_TEA6415C=m -CONFIG_VIDEO_TEA6420=m -CONFIG_VIDEO_MSP3400=m CONFIG_VIDEO_CS3308=m CONFIG_VIDEO_CS5345=m CONFIG_VIDEO_CS53L32A=m -CONFIG_VIDEO_TLV320AIC23B=m -CONFIG_VIDEO_UDA1342=m -CONFIG_VIDEO_WM8775=m -CONFIG_VIDEO_WM8739=m -CONFIG_VIDEO_VP27SMPX=m +CONFIG_VIDEO_MSP3400=m CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_VP27SMPX=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_WM8775=m # end of Audio decoders, processors and mixers # @@ -5649,7 +5899,9 @@ CONFIG_VIDEO_ADV7842_CEC=y CONFIG_VIDEO_BT819=m CONFIG_VIDEO_BT856=m CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_ISL7998X=m CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_MAX9286=m CONFIG_VIDEO_ML86V7667=m CONFIG_VIDEO_SAA7110=m CONFIG_VIDEO_SAA711X=m @@ -5663,7 +5915,6 @@ CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m CONFIG_VIDEO_TW9910=m CONFIG_VIDEO_VPX3220=m -CONFIG_VIDEO_MAX9286=m # # Video and audio decoders @@ -5675,16 +5926,16 @@ CONFIG_VIDEO_CX25840=m # # Video encoders # -CONFIG_VIDEO_SAA7127=m -CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_AD9389B=m CONFIG_VIDEO_ADV7170=m CONFIG_VIDEO_ADV7175=m CONFIG_VIDEO_ADV7343=m CONFIG_VIDEO_ADV7393=m CONFIG_VIDEO_ADV7511=m CONFIG_VIDEO_ADV7511_CEC=y -CONFIG_VIDEO_AD9389B=m CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7185=m CONFIG_VIDEO_THS8200=m # end of Video encoders @@ -5710,112 +5961,17 @@ CONFIG_SDR_MAX2175=m # # Miscellaneous helper chips # -CONFIG_VIDEO_THS7303=m -CONFIG_VIDEO_M52790=m CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_M52790=m CONFIG_VIDEO_ST_MIPID02=m +CONFIG_VIDEO_THS7303=m # end of Miscellaneous helper chips -# -# Camera sensor devices -# -CONFIG_VIDEO_APTINA_PLL=m -CONFIG_VIDEO_CCS_PLL=m -CONFIG_VIDEO_HI556=m -CONFIG_VIDEO_HI846=m -CONFIG_VIDEO_IMX208=m -CONFIG_VIDEO_IMX214=m -CONFIG_VIDEO_IMX219=m -CONFIG_VIDEO_IMX258=m -CONFIG_VIDEO_IMX274=m -CONFIG_VIDEO_IMX290=m -CONFIG_VIDEO_IMX319=m -CONFIG_VIDEO_IMX334=m -CONFIG_VIDEO_IMX335=m -CONFIG_VIDEO_IMX355=m -CONFIG_VIDEO_IMX412=m -CONFIG_VIDEO_OV02A10=m -CONFIG_VIDEO_OV2640=m -CONFIG_VIDEO_OV2659=m -CONFIG_VIDEO_OV2680=m -CONFIG_VIDEO_OV2685=m -CONFIG_VIDEO_OV2740=m -CONFIG_VIDEO_OV5640=m -CONFIG_VIDEO_OV5645=m -CONFIG_VIDEO_OV5647=m -CONFIG_VIDEO_OV5648=m -CONFIG_VIDEO_OV6650=m -CONFIG_VIDEO_OV5670=m -CONFIG_VIDEO_OV5675=m -CONFIG_VIDEO_OV5693=m -CONFIG_VIDEO_OV5695=m -CONFIG_VIDEO_OV7251=m -CONFIG_VIDEO_OV772X=m -CONFIG_VIDEO_OV7640=m -CONFIG_VIDEO_OV7670=m -CONFIG_VIDEO_OV7740=m -CONFIG_VIDEO_OV8856=m -CONFIG_VIDEO_OV8865=m -CONFIG_VIDEO_OV9282=m -CONFIG_VIDEO_OV9640=m -CONFIG_VIDEO_OV9650=m -CONFIG_VIDEO_OV9734=m -CONFIG_VIDEO_OV13858=m -CONFIG_VIDEO_OV13B10=m -CONFIG_VIDEO_VS6624=m -CONFIG_VIDEO_MT9M001=m -CONFIG_VIDEO_MT9M032=m -CONFIG_VIDEO_MT9M111=m -CONFIG_VIDEO_MT9P031=m -CONFIG_VIDEO_MT9T001=m -CONFIG_VIDEO_MT9T112=m -CONFIG_VIDEO_MT9V011=m -CONFIG_VIDEO_MT9V032=m -CONFIG_VIDEO_MT9V111=m -CONFIG_VIDEO_SR030PC30=m -CONFIG_VIDEO_NOON010PC30=m -CONFIG_VIDEO_M5MOLS=m -CONFIG_VIDEO_MAX9271_LIB=m -CONFIG_VIDEO_RDACM20=m -CONFIG_VIDEO_RDACM21=m -CONFIG_VIDEO_RJ54N1=m -CONFIG_VIDEO_S5K6AA=m -CONFIG_VIDEO_S5K6A3=m -CONFIG_VIDEO_S5K4ECGX=m -CONFIG_VIDEO_S5K5BAF=m -CONFIG_VIDEO_CCS=m -CONFIG_VIDEO_ET8EK8=m -CONFIG_VIDEO_S5C73M3=m -# end of Camera sensor devices - -# -# Lens drivers -# -CONFIG_VIDEO_AD5820=m -CONFIG_VIDEO_AK7375=m -CONFIG_VIDEO_DW9714=m -CONFIG_VIDEO_DW9768=m -CONFIG_VIDEO_DW9807_VCM=m -# end of Lens drivers - -# -# Flash devices -# -CONFIG_VIDEO_ADP1653=m -CONFIG_VIDEO_LM3560=m -CONFIG_VIDEO_LM3646=m -# end of Flash devices - -# -# SPI helper chips -# -CONFIG_VIDEO_GS1662=m -# end of SPI helper chips - # # Media SPI Adapters # CONFIG_CXD2880_SPI_DRV=m +CONFIG_VIDEO_GS1662=m # end of Media SPI Adapters CONFIG_MEDIA_TUNER=m @@ -5823,43 +5979,43 @@ CONFIG_MEDIA_TUNER=m # # Customize TV tuners # -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA18250=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MSI001=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2063=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_MT2131=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_XC4000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_MAX2165=m -CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC0011=m CONFIG_MEDIA_TUNER_FC0012=m CONFIG_MEDIA_TUNER_FC0013=m -CONFIG_MEDIA_TUNER_TDA18212=m -CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC2580=m -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_TUA9001=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_TUNER_IT913X=m -CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m CONFIG_MEDIA_TUNER_MXL301RF=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m # end of Customize TV tuners # @@ -5869,126 +6025,126 @@ CONFIG_MEDIA_TUNER_QM1D1B0004=m # # Multistandard (satellite) frontends # +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_MXL5XX=m CONFIG_DVB_STB0899=m CONFIG_DVB_STB6100=m CONFIG_DVB_STV090x=m CONFIG_DVB_STV0910=m CONFIG_DVB_STV6110x=m CONFIG_DVB_STV6111=m -CONFIG_DVB_MXL5XX=m -CONFIG_DVB_M88DS3103=m # # Multistandard (cable + terrestrial) frontends # CONFIG_DVB_DRXK=m -CONFIG_DVB_TDA18271C2DD=m -CONFIG_DVB_SI2165=m CONFIG_DVB_MN88472=m CONFIG_DVB_MN88473=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_TDA18271C2DD=m # # DVB-S (satellite) frontends # CONFIG_DVB_CX24110=m -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -CONFIG_DVB_ZL10036=m -CONFIG_DVB_ZL10039=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_STV6110=m -CONFIG_DVB_STV0900=m -CONFIG_DVB_TDA8083=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TDA8261=m -CONFIG_DVB_VES1X93=m -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_TUA6100=m CONFIG_DVB_CX24116=m CONFIG_DVB_CX24117=m CONFIG_DVB_CX24120=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_TS2020=m +CONFIG_DVB_CX24123=m CONFIG_DVB_DS3000=m CONFIG_DVB_MB86A16=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV6110=m CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m # # DVB-T (terrestrial) frontends # -CONFIG_DVB_SP887X=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_AS102_FE=m CONFIG_DVB_CX22700=m CONFIG_DVB_CX22702=m -CONFIG_DVB_S5H1432=m -CONFIG_DVB_DRXD=m -CONFIG_DVB_L64781=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m CONFIG_DVB_DIB3000MB=m CONFIG_DVB_DIB3000MC=m CONFIG_DVB_DIB7000M=m CONFIG_DVB_DIB7000P=m CONFIG_DVB_DIB9000=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m +CONFIG_DVB_DRXD=m CONFIG_DVB_EC100=m -CONFIG_DVB_STV0367=m -CONFIG_DVB_CXD2820R=m -CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_L64781=m +CONFIG_DVB_MT352=m +CONFIG_DVB_NXT6000=m CONFIG_DVB_RTL2830=m CONFIG_DVB_RTL2832=m CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1432=m CONFIG_DVB_SI2168=m -CONFIG_DVB_AS102_FE=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m CONFIG_DVB_ZD1301_DEMOD=m -CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_ZL10353=m CONFIG_DVB_CXD2880=m # # DVB-C (cable) frontends # -CONFIG_DVB_VES1820=m +CONFIG_DVB_STV0297=m CONFIG_DVB_TDA10021=m CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m +CONFIG_DVB_VES1820=m # # ATSC (North American/Korean Terrestrial/Cable DTV) frontends # -CONFIG_DVB_NXT200X=m -CONFIG_DVB_OR51211=m -CONFIG_DVB_OR51132=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_LGDT3306A=m -CONFIG_DVB_LG2160=m -CONFIG_DVB_S5H1409=m CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m -CONFIG_DVB_S5H1411=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m CONFIG_DVB_MXL692=m +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m # # ISDB-T (terrestrial) frontends # -CONFIG_DVB_S921=m CONFIG_DVB_DIB8000=m CONFIG_DVB_MB86A20S=m +CONFIG_DVB_S921=m # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # -CONFIG_DVB_TC90522=m CONFIG_DVB_MN88443X=m +CONFIG_DVB_TC90522=m # # Digital terrestrial only tuners/PLL @@ -6000,25 +6156,25 @@ CONFIG_DVB_TUNER_DIB0090=m # # SEC control devices for DVB-S # -CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m CONFIG_DVB_LNBH25=m CONFIG_DVB_LNBH29=m CONFIG_DVB_LNBP21=m CONFIG_DVB_LNBP22=m -CONFIG_DVB_ISL6405=m -CONFIG_DVB_ISL6421=m -CONFIG_DVB_ISL6423=m -CONFIG_DVB_A8293=m -CONFIG_DVB_LGS8GL5=m -CONFIG_DVB_LGS8GXX=m -CONFIG_DVB_ATBM8830=m -CONFIG_DVB_TDA665x=m -CONFIG_DVB_IX2505V=m CONFIG_DVB_M88RS2000=m -CONFIG_DVB_AF9033=m -CONFIG_DVB_HORUS3A=m -CONFIG_DVB_ASCOT2E=m -CONFIG_DVB_HELENE=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_DRX39XYJ=m # # Common Interface (EN50221) controller drivers @@ -6036,26 +6192,29 @@ CONFIG_DVB_DUMMY_FE=m # # Graphics support # -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -CONFIG_DRM=m +CONFIG_DRM=y CONFIG_DRM_MIPI_DBI=m CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_DP_AUX_BUS=m -# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_KMS_HELPER=m +CONFIG_DRM_KMS_HELPER=y # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +CONFIG_DRM_DP_AUX_BUS=m +CONFIG_DRM_DISPLAY_HELPER=y +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set CONFIG_DRM_DP_CEC=y CONFIG_DRM_TTM=m CONFIG_DRM_VRAM_HELPER=m CONFIG_DRM_TTM_HELPER=m -CONFIG_DRM_GEM_CMA_HELPER=m +CONFIG_DRM_GEM_CMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=m CONFIG_DRM_SCHED=m @@ -6125,7 +6284,9 @@ CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m CONFIG_DRM_PANEL_LG_LB035Q02=m # CONFIG_DRM_PANEL_LG_LG4573 is not set CONFIG_DRM_PANEL_NEC_NL8048HL11=m +CONFIG_DRM_PANEL_NEWVISION_NV3052C=m CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT35560=m # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set CONFIG_DRM_PANEL_NOVATEK_NT36672A=m CONFIG_DRM_PANEL_NOVATEK_NT39016=m @@ -6156,7 +6317,6 @@ CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m CONFIG_DRM_PANEL_SITRONIX_ST7701=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -CONFIG_DRM_PANEL_SONY_ACX424AKP=m CONFIG_DRM_PANEL_SONY_ACX565AKM=m # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set CONFIG_DRM_PANEL_TDO_TL070WSH30=m @@ -6179,8 +6339,11 @@ CONFIG_DRM_CDNS_DSI=m CONFIG_DRM_CHIPONE_ICN6211=m # CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_CROS_EC_ANX7688=m -CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_DISPLAY_CONNECTOR=y +CONFIG_DRM_FSL_LDB=m +CONFIG_DRM_ITE_IT6505=m CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9211=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_ITE_IT66121=m @@ -6210,9 +6373,10 @@ CONFIG_DRM_ANALOGIX_DP=m CONFIG_DRM_ANALOGIX_ANX7625=m # CONFIG_DRM_I2C_ADV7511 is not set CONFIG_DRM_CDNS_MHDP8546=m -CONFIG_DRM_DW_HDMI=m +CONFIG_DRM_DW_HDMI=y # CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +CONFIG_DRM_DW_HDMI_GP_AUDIO=m # CONFIG_DRM_DW_HDMI_CEC is not set # end of Display Interface Bridges @@ -6220,12 +6384,13 @@ CONFIG_DRM_DW_HDMI_I2S_AUDIO=m # CONFIG_DRM_HISI_HIBMC is not set CONFIG_DRM_HISI_KIRIN=m # CONFIG_DRM_MXSFB is not set -CONFIG_DRM_MESON=m -CONFIG_DRM_MESON_DW_HDMI=m +CONFIG_DRM_MESON=y +CONFIG_DRM_MESON_DW_HDMI=y # CONFIG_DRM_ARCPGU is not set CONFIG_DRM_BOCHS=m # CONFIG_DRM_CIRRUS_QEMU is not set CONFIG_DRM_GM12U320=m +CONFIG_DRM_PANEL_MIPI_DBI=m CONFIG_DRM_SIMPLEDRM=m CONFIG_TINYDRM_HX8357D=m CONFIG_TINYDRM_ILI9163=m @@ -6243,6 +6408,9 @@ CONFIG_DRM_LIMA=m CONFIG_DRM_PANFROST=m CONFIG_DRM_TIDSS=m CONFIG_DRM_GUD=m +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m CONFIG_DRM_HYPERV=m CONFIG_DRM_LEGACY=y # CONFIG_DRM_TDFX is not set @@ -6250,8 +6418,9 @@ CONFIG_DRM_LEGACY=y # CONFIG_DRM_MGA is not set # CONFIG_DRM_VIA is not set # CONFIG_DRM_SAVAGE is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y CONFIG_DRM_NOMODESET=y +CONFIG_DRM_PRIVACY_SCREEN=y # # Frame buffer Devices @@ -6377,10 +6546,10 @@ CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y # CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set -CONFIG_BOOTSPLASH=y # end of Console display driver support # CONFIG_LOGO is not set @@ -6425,6 +6594,7 @@ CONFIG_SND_ALOOP=m CONFIG_SND_VIRMIDI=m CONFIG_SND_MTPAV=m CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SERIAL_GENERIC=m CONFIG_SND_MPU401=m # CONFIG_SND_AC97_POWER_SAVE is not set CONFIG_SND_PCI=y @@ -6522,6 +6692,7 @@ CONFIG_SND_SOC=m CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_COMPRESS=y +CONFIG_SND_SOC_UTILS_KUNIT_TEST=m CONFIG_SND_SOC_ADI=m CONFIG_SND_SOC_ADI_AXI_I2S=m CONFIG_SND_SOC_ADI_AXI_SPDIF=m @@ -6578,15 +6749,6 @@ CONFIG_SND_MESON_G12A_TOHDMITX=m CONFIG_SND_SOC_MESON_T9015=m # end of ASoC support for Amlogic platforms -CONFIG_SND_SOC_ROCKCHIP=m -CONFIG_SND_SOC_ROCKCHIP_I2S=m -CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m -CONFIG_SND_SOC_ROCKCHIP_PDM=m -CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -CONFIG_SND_SOC_ROCKCHIP_MAX98090=m -CONFIG_SND_SOC_ROCKCHIP_RT5645=m -CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m -CONFIG_SND_SOC_RK3399_GRU_SOUND=m # CONFIG_SND_SOC_SOF_TOPLEVEL is not set # @@ -6628,6 +6790,7 @@ CONFIG_SND_SOC_AK4642=m CONFIG_SND_SOC_AK5386=m CONFIG_SND_SOC_AK5558=m CONFIG_SND_SOC_ALC5623=m +CONFIG_SND_SOC_AW8738=m CONFIG_SND_SOC_BD28623=m CONFIG_SND_SOC_BT_SCO=m CONFIG_SND_SOC_CPCAP=m @@ -6641,6 +6804,10 @@ CONFIG_SND_SOC_CS35L41_LIB=m CONFIG_SND_SOC_CS35L41=m CONFIG_SND_SOC_CS35L41_SPI=m CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L45_TABLES=m +CONFIG_SND_SOC_CS35L45=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L45_I2C=m CONFIG_SND_SOC_CS42L42=m CONFIG_SND_SOC_CS42L51=m CONFIG_SND_SOC_CS42L51_I2C=m @@ -6661,7 +6828,6 @@ CONFIG_SND_SOC_CS4349=m CONFIG_SND_SOC_CS53L30=m CONFIG_SND_SOC_CX2072X=m CONFIG_SND_SOC_DA7213=m -CONFIG_SND_SOC_DA7219=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_HDMI_CODEC=m CONFIG_SND_SOC_ES7134=m @@ -6674,7 +6840,6 @@ CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_ICS43432=m CONFIG_SND_SOC_INNO_RK3036=m CONFIG_SND_SOC_MAX98088=m -CONFIG_SND_SOC_MAX98090=m CONFIG_SND_SOC_MAX98357A=m CONFIG_SND_SOC_MAX98504=m CONFIG_SND_SOC_MAX9867=m @@ -6683,6 +6848,7 @@ CONFIG_SND_SOC_MAX98520=m CONFIG_SND_SOC_MAX98373=m CONFIG_SND_SOC_MAX98373_I2C=m CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m CONFIG_SND_SOC_MAX9860=m CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m @@ -6708,12 +6874,9 @@ CONFIG_SND_SOC_PCM512x_SPI=m CONFIG_SND_SOC_RK3328=m CONFIG_SND_SOC_RK817=m CONFIG_SND_SOC_RL6231=m -CONFIG_SND_SOC_RT5514=m -CONFIG_SND_SOC_RT5514_SPI=m CONFIG_SND_SOC_RT5616=m CONFIG_SND_SOC_RT5631=m CONFIG_SND_SOC_RT5640=m -CONFIG_SND_SOC_RT5645=m CONFIG_SND_SOC_RT5659=m CONFIG_SND_SOC_RT9120=m CONFIG_SND_SOC_SGTL5000=m @@ -6739,6 +6902,7 @@ CONFIG_SND_SOC_TAS2770=m CONFIG_SND_SOC_TAS5086=m CONFIG_SND_SOC_TAS571X=m CONFIG_SND_SOC_TAS5720=m +CONFIG_SND_SOC_TAS5805M=m CONFIG_SND_SOC_TAS6424=m CONFIG_SND_SOC_TDA7419=m CONFIG_SND_SOC_TFA9879=m @@ -6766,6 +6930,8 @@ CONFIG_SND_SOC_WM8580=m CONFIG_SND_SOC_WM8711=m CONFIG_SND_SOC_WM8728=m CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m CONFIG_SND_SOC_WM8737=m CONFIG_SND_SOC_WM8741=m CONFIG_SND_SOC_WM8750=m @@ -6778,6 +6944,7 @@ CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SOC_WM8804_SPI=m CONFIG_SND_SOC_WM8903=m CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8940=m CONFIG_SND_SOC_WM8960=m CONFIG_SND_SOC_WM8962=m CONFIG_SND_SOC_WM8974=m @@ -6795,6 +6962,7 @@ CONFIG_SND_SOC_NAU8821=m CONFIG_SND_SOC_NAU8822=m CONFIG_SND_SOC_NAU8824=m CONFIG_SND_SOC_TPA6130A2=m +CONFIG_SND_SOC_LPASS_MACRO_COMMON=m CONFIG_SND_SOC_LPASS_WSA_MACRO=m CONFIG_SND_SOC_LPASS_VA_MACRO=m CONFIG_SND_SOC_LPASS_RX_MACRO=m @@ -6858,6 +7026,7 @@ CONFIG_HID_GFRM=m CONFIG_HID_GLORIOUS=m CONFIG_HID_HOLTEK=m CONFIG_HOLTEK_FF=y +CONFIG_HID_VIVALDI_COMMON=m CONFIG_HID_GOOGLE_HAMMER=m CONFIG_HID_VIVALDI=m CONFIG_HID_GT683R=m @@ -6887,6 +7056,7 @@ CONFIG_LOGIWHEELS_FF=y CONFIG_HID_MAGICMOUSE=m CONFIG_HID_MALTRON=m # CONFIG_HID_MAYFLASH is not set +CONFIG_HID_MEGAWORLD_FF=m CONFIG_HID_REDRAGON=m CONFIG_HID_MICROSOFT=m CONFIG_HID_MONTEREY=m @@ -6909,12 +7079,14 @@ CONFIG_HID_PICOLCD_CIR=y CONFIG_HID_PLANTRONICS=m CONFIG_HID_PLAYSTATION=m # CONFIG_PLAYSTATION_FF is not set +CONFIG_HID_RAZER=m CONFIG_HID_PRIMAX=m CONFIG_HID_RETRODE=m CONFIG_HID_ROCCAT=m CONFIG_HID_SAITEK=m CONFIG_HID_SAMSUNG=m CONFIG_HID_SEMITEK=m +CONFIG_HID_SIGMAMICRO=m CONFIG_HID_SONY=m CONFIG_SONY_FF=y CONFIG_HID_SPEEDLINK=m @@ -7354,12 +7526,15 @@ CONFIG_TYPEC_UCSI=m CONFIG_UCSI_CCG=m CONFIG_UCSI_ACPI=m CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_RT1719=m CONFIG_TYPEC_HD3SS3220=m CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_WUSB3801=m # # USB Type-C Multiplexer/DeMultiplexer Switch support # +CONFIG_TYPEC_MUX_FSA4480=m CONFIG_TYPEC_MUX_PI3USB30532=m # end of USB Type-C Multiplexer/DeMultiplexer Switch support @@ -7412,7 +7587,6 @@ CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_HI3798CV200=y CONFIG_MMC_DW_K3=y # CONFIG_MMC_DW_PCI is not set -CONFIG_MMC_DW_ROCKCHIP=m # CONFIG_MMC_VUB300 is not set # CONFIG_MMC_USHC is not set # CONFIG_MMC_USDHI6ROL0 is not set @@ -7425,6 +7599,15 @@ CONFIG_MMC_HSQ=m CONFIG_MMC_SDHCI_XENON=y # CONFIG_MMC_SDHCI_OMAP is not set CONFIG_MMC_SDHCI_AM654=m +CONFIG_MMC_LITEX=m +CONFIG_SCSI_UFSHCD=m +# CONFIG_SCSI_UFS_BSG is not set +# CONFIG_SCSI_UFS_HPB is not set +# CONFIG_SCSI_UFS_HWMON is not set +# CONFIG_SCSI_UFSHCD_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -7498,6 +7681,12 @@ CONFIG_LEDS_TPS6105X=m # Flash and Torch LED drivers # +# +# RGB LED drivers +# +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_QCOM_LPG=m + # # LED Triggers # @@ -7664,6 +7853,7 @@ CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_WM831X=m CONFIG_RTC_DRV_WM8350=m CONFIG_RTC_DRV_PCF50633=m +CONFIG_RTC_DRV_OPTEE=m # CONFIG_RTC_DRV_ZYNQMP is not set # CONFIG_RTC_DRV_CROS_EC is not set CONFIG_RTC_DRV_NTXEC=m @@ -7763,11 +7953,13 @@ CONFIG_VFIO_PCI=y # CONFIG_VFIO_PLATFORM is not set # CONFIG_VFIO_MDEV is not set CONFIG_VIRT_DRIVERS=y +CONFIG_VMGENID=m CONFIG_NITRO_ENCLAVES=m CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI_LIB=y CONFIG_VIRTIO_PCI_LIB_LEGACY=y CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_PCI_LEGACY=y CONFIG_VIRTIO_VDPA=m @@ -7825,6 +8017,7 @@ CONFIG_XEN_PRIVCMD=m CONFIG_XEN_EFI=y CONFIG_XEN_AUTO_XLATE=y CONFIG_XEN_FRONT_PGDIR_SHBUF=m +# CONFIG_XEN_VIRTIO is not set # end of Xen driver support # CONFIG_GREYBUS is not set @@ -7859,7 +8052,6 @@ CONFIG_VT6656=m # Analog to digital converters # # CONFIG_AD7816 is not set -# CONFIG_AD7280 is not set # end of Analog to digital converters # @@ -7902,33 +8094,23 @@ CONFIG_AD9834=m CONFIG_FB_SM750=m CONFIG_STAGING_MEDIA=y -# CONFIG_VIDEO_HANTRO is not set # CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_MESON_VDEC=m -# CONFIG_VIDEO_ROCKCHIP_VDEC is not set CONFIG_VIDEO_ZORAN=m -CONFIG_VIDEO_ZORAN_DC30=m -CONFIG_VIDEO_ZORAN_ZR36060=m -CONFIG_VIDEO_ZORAN_BUZ=m -CONFIG_VIDEO_ZORAN_DC10=m -CONFIG_VIDEO_ZORAN_LML33=m -CONFIG_VIDEO_ZORAN_LML33R10=m -CONFIG_VIDEO_ZORAN_AVS6EYES=m +CONFIG_VIDEO_ZORAN_DC30=y +CONFIG_VIDEO_ZORAN_ZR36060=y +CONFIG_VIDEO_ZORAN_BUZ=y +CONFIG_VIDEO_ZORAN_DC10=y +CONFIG_VIDEO_ZORAN_LML33=y +CONFIG_VIDEO_ZORAN_LML33R10=y +CONFIG_VIDEO_ZORAN_AVS6EYES=y CONFIG_DVB_AV7110_IR=y CONFIG_DVB_AV7110=m CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_PATCH=m CONFIG_DVB_SP8870=m - -# -# Android -# -# end of Android - # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set -# CONFIG_GS_FPGABOOT is not set -# CONFIG_UNISYSSPAR is not set CONFIG_COMMON_CLK_XLNX_CLKWZRD=m CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m @@ -7972,9 +8154,13 @@ CONFIG_MOST_COMPONENTS=m CONFIG_XIL_AXIS_FIFO=m # CONFIG_FIELDBUS_DEV is not set # CONFIG_QLGE is not set -# CONFIG_WFX is not set + +# +# VME Device Drivers +# # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y +CONFIG_CHROMEOS_ACPI=m # CONFIG_CHROMEOS_TBMC is not set CONFIG_CROS_EC=y # CONFIG_CROS_EC_I2C is not set @@ -7991,9 +8177,9 @@ CONFIG_CROS_EC_SYSFS=m CONFIG_CROS_EC_TYPEC=m CONFIG_CROS_USBPD_LOGGER=m CONFIG_CROS_USBPD_NOTIFY=m +CONFIG_CHROMEOS_PRIVACY_SCREEN=m # CONFIG_MELLANOX_PLATFORM is not set CONFIG_SURFACE_PLATFORMS=y -CONFIG_SURFACE_3_BUTTON=m # CONFIG_SURFACE_3_POWER_OPREGION is not set CONFIG_SURFACE_GPE=m CONFIG_SURFACE_HOTPLUG=m @@ -8026,13 +8212,13 @@ CONFIG_COMMON_CLK_SI544=m # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=y -# CONFIG_COMMON_CLK_LAN966X is not set CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_TWL6040=m CONFIG_COMMON_CLK_AXI_CLKGEN=m CONFIG_COMMON_CLK_XGENE=y CONFIG_COMMON_CLK_PALMAS=m CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_RS9_PCIE=m # CONFIG_COMMON_CLK_VC5 is not set CONFIG_COMMON_CLK_BD718XX=m # CONFIG_COMMON_CLK_FIXED_MMIO is not set @@ -8056,14 +8242,9 @@ CONFIG_COMMON_CLK_AXG_AUDIO=m CONFIG_COMMON_CLK_G12A=y # end of Clock support for Amlogic platforms -CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y -CONFIG_CLK_RK3568=y # CONFIG_XILINX_VCU is not set +CONFIG_CLK_KUNIT_TEST=m +CONFIG_CLK_GATE_KUNIT_TEST=m CONFIG_HWSPINLOCK=y # @@ -8072,8 +8253,6 @@ CONFIG_HWSPINLOCK=y CONFIG_TIMER_OF=y CONFIG_TIMER_ACPI=y CONFIG_TIMER_PROBE=y -CONFIG_CLKSRC_MMIO=y -CONFIG_ROCKCHIP_TIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y @@ -8088,7 +8267,6 @@ CONFIG_ARM_MHU=y CONFIG_ARM_MHU_V2=m CONFIG_PLATFORM_MHU=y # CONFIG_PL320_MBOX is not set -# CONFIG_ROCKCHIP_MBOX is not set CONFIG_PCC=y # CONFIG_ALTERA_MBOX is not set # CONFIG_MAILBOX_TEST is not set @@ -8111,7 +8289,6 @@ CONFIG_IOMMU_DEFAULT_DMA_STRICT=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y -# CONFIG_ROCKCHIP_IOMMU is not set CONFIG_ARM_SMMU=y # CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y @@ -8130,6 +8307,7 @@ CONFIG_ARM_SMMU_V3=y # CONFIG_RPMSG=y # CONFIG_RPMSG_CHAR is not set +CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_NS=m CONFIG_RPMSG_QCOM_GLINK=y CONFIG_RPMSG_QCOM_GLINK_RPM=y @@ -8145,7 +8323,7 @@ CONFIG_RPMSG_QCOM_GLINK_RPM=y # # Amlogic SoC drivers # -CONFIG_MESON_CANVAS=m +CONFIG_MESON_CANVAS=y CONFIG_MESON_CLK_MEASURE=y CONFIG_MESON_GX_SOCINFO=y CONFIG_MESON_GX_PM_DOMAINS=y @@ -8184,9 +8362,6 @@ CONFIG_LITEX_SOC_CONTROLLER=m CONFIG_QCOM_QMI_HELPERS=m # end of Qualcomm SoC drivers -CONFIG_ROCKCHIP_GRF=y -CONFIG_ROCKCHIP_IODOMAIN=m -# CONFIG_ROCKCHIP_PM_DOMAINS is not set CONFIG_SOC_TI=y # @@ -8209,7 +8384,6 @@ CONFIG_DEVFREQ_GOV_PASSIVE=m # # DEVFREQ Drivers # -# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set # CONFIG_PM_DEVFREQ_EVENT is not set CONFIG_EXTCON=y @@ -8262,6 +8436,9 @@ CONFIG_ADXL345_SPI=m CONFIG_ADXL355=m CONFIG_ADXL355_I2C=m CONFIG_ADXL355_SPI=m +CONFIG_ADXL367=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m CONFIG_ADXL372=m CONFIG_ADXL372_SPI=m CONFIG_ADXL372_I2C=m @@ -8316,6 +8493,7 @@ CONFIG_AD7091R5=m CONFIG_AD7124=m # CONFIG_AD7192 is not set CONFIG_AD7266=m +# CONFIG_AD7280 is not set CONFIG_AD7291=m CONFIG_AD7292=m CONFIG_AD7298=m @@ -8368,7 +8546,6 @@ CONFIG_QCOM_VADC_COMMON=m # CONFIG_QCOM_SPMI_VADC is not set CONFIG_QCOM_SPMI_ADC5=m CONFIG_RN5T618_ADC=m -CONFIG_ROCKCHIP_SARADC=m # CONFIG_SD_ADC_MODULATOR is not set CONFIG_TI_ADC081C=m CONFIG_TI_ADC0832=m @@ -8409,6 +8586,7 @@ CONFIG_AD74413R=m # Amplifiers # # CONFIG_AD8366 is not set +CONFIG_ADA4250=m CONFIG_HMC425=m # end of Amplifiers @@ -8483,6 +8661,7 @@ CONFIG_AD3552R=m # CONFIG_AD5593R is not set # CONFIG_AD5504 is not set # CONFIG_AD5624R_SPI is not set +CONFIG_LTC2688=m CONFIG_AD5686=m CONFIG_AD5686_SPI=m CONFIG_AD5696_I2C=m @@ -8542,6 +8721,8 @@ CONFIG_ADMV8818=m # CONFIG_ADF4350 is not set CONFIG_ADF4371=m CONFIG_ADMV1013=m +CONFIG_ADMV1014=m +CONFIG_ADMV4420=m CONFIG_ADRF6780=m # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -8799,7 +8980,10 @@ CONFIG_MB1232=m # CONFIG_PING is not set # CONFIG_RFD77402 is not set # CONFIG_SRF04 is not set +CONFIG_SX_COMMON=m CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m # CONFIG_SX9500 is not set # CONFIG_SRF08 is not set CONFIG_VCNL3020=m @@ -8846,9 +9030,9 @@ CONFIG_PWM_LP3943=m CONFIG_PWM_MESON=y CONFIG_PWM_NTXEC=m # CONFIG_PWM_PCA9685 is not set -CONFIG_PWM_ROCKCHIP=m CONFIG_PWM_TWL=m CONFIG_PWM_TWL_LED=m +CONFIG_PWM_XILINX=m # # IRQ chip support @@ -8862,12 +9046,12 @@ CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ITS_PCI=y # CONFIG_AL_FIC is not set CONFIG_MADERA_IRQ=m +# CONFIG_XILINX_INTC is not set CONFIG_PARTITION_PERCPU=y CONFIG_MESON_IRQ_GPIO=y # end of IRQ chip support # CONFIG_IPACK_BUS is not set -CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_MESON=y CONFIG_RESET_MESON_AUDIO_ARB=m @@ -8897,11 +9081,9 @@ CONFIG_PHY_MESON_AXG_MIPI_DPHY=m CONFIG_PHY_CADENCE_TORRENT=m # CONFIG_PHY_CADENCE_DPHY is not set +CONFIG_PHY_CADENCE_DPHY_RX=m CONFIG_PHY_CADENCE_SIERRA=m CONFIG_PHY_CADENCE_SALVO=m -CONFIG_PHY_FSL_IMX8MQ_USB=m -# CONFIG_PHY_MIXEL_MIPI_DPHY is not set -# CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_LAN966X_SERDES is not set @@ -8910,16 +9092,6 @@ CONFIG_PHY_FSL_IMX8MQ_USB=m # CONFIG_PHY_OCELOT_SERDES is not set CONFIG_PHY_QCOM_USB_HS=y # CONFIG_PHY_QCOM_USB_HSIC is not set -CONFIG_PHY_ROCKCHIP_DP=m -CONFIG_PHY_ROCKCHIP_DPHY_RX0=m -CONFIG_PHY_ROCKCHIP_EMMC=m -CONFIG_PHY_ROCKCHIP_INNO_HDMI=m -CONFIG_PHY_ROCKCHIP_INNO_USB2=m -CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m -CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m -CONFIG_PHY_ROCKCHIP_PCIE=m -CONFIG_PHY_ROCKCHIP_TYPEC=m -CONFIG_PHY_ROCKCHIP_USB=m CONFIG_PHY_SAMSUNG_USB2=y # CONFIG_PHY_TUSB1210 is not set # end of PHY Subsystem @@ -8939,7 +9111,6 @@ CONFIG_ARM_PMU_ACPI=y # CONFIG_ARM_DSU_PMU is not set # CONFIG_ARM_SPE_PMU is not set CONFIG_ARM_DMC620_PMU=m -# CONFIG_MARVELL_CN10K_TAD_PMU is not set CONFIG_HISI_PMU=y # CONFIG_HISI_PCIE_PMU is not set # end of Performance monitor support @@ -8961,8 +9132,6 @@ CONFIG_DEV_DAX=m CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_SPMI_SDAM=m -CONFIG_ROCKCHIP_EFUSE=m -CONFIG_ROCKCHIP_OTP=m CONFIG_MESON_EFUSE=y CONFIG_MESON_MX_EFUSE=y CONFIG_RAVE_SP_EEPROM=m @@ -8978,14 +9147,7 @@ CONFIG_NVMEM_RMEM=m # CONFIG_FPGA is not set # CONFIG_FSI is not set CONFIG_TEE=y - -# -# TEE drivers -# CONFIG_OPTEE=y -CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 -# end of TEE drivers - CONFIG_MULTIPLEXER=m # @@ -9010,6 +9172,9 @@ CONFIG_MOST=m CONFIG_MOST_USB_HDM=m # CONFIG_MOST_CDEV is not set CONFIG_MOST_SND=m +CONFIG_PECI=m +CONFIG_PECI_CPU=m +# CONFIG_HTE is not set # end of Device Drivers # @@ -9076,9 +9241,14 @@ CONFIG_F2FS_FS_SECURITY=y CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FAULT_INJECTION is not set CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_IOSTAT=y +# CONFIG_F2FS_UNFAIR_RWSEM is not set # CONFIG_ZONEFS_FS is not set -CONFIG_FS_DAX=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_EXPORTFS_BLOCK_OPS=y @@ -9106,7 +9276,6 @@ CONFIG_AUTOFS_FS=m CONFIG_FUSE_FS=y CONFIG_CUSE=m CONFIG_VIRTIO_FS=m -CONFIG_FUSE_DAX=y CONFIG_OVERLAY_FS=y # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -9125,6 +9294,7 @@ CONFIG_FSCACHE_STATS=y CONFIG_CACHEFILES=m # CONFIG_CACHEFILES_DEBUG is not set # CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set # end of Caches # @@ -9174,6 +9344,9 @@ CONFIG_TMPFS_XATTR=y CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y +CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y @@ -9293,7 +9466,6 @@ CONFIG_NFS_DISABLE_UDP_SUPPORT=y # CONFIG_NFS_V4_2_READ_PLUS is not set CONFIG_NFSD=m CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_PNFS=y @@ -9409,7 +9581,10 @@ CONFIG_KEYS=y CONFIG_KEYS_REQUEST_CACHE=y CONFIG_PERSISTENT_KEYRINGS=y CONFIG_TRUSTED_KEYS=y +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_TRUSTED_KEYS_TEE=y CONFIG_ENCRYPTED_KEYS=y +# CONFIG_USER_DECRYPTED_DATA is not set CONFIG_KEY_DH_OPERATIONS=y # CONFIG_SECURITY_DMESG_RESTRICT is not set CONFIG_SECURITY=y @@ -9420,7 +9595,6 @@ CONFIG_SECURITY_PATH=y CONFIG_LSM_MMAP_MIN_ADDR=0 CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y CONFIG_HARDENED_USERCOPY=y -# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set CONFIG_FORTIFY_SOURCE=y # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_SECURITY_SELINUX=y @@ -9460,6 +9634,7 @@ CONFIG_INTEGRITY_SIGNATURE=y CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y CONFIG_INTEGRITY_TRUSTED_KEYRING=y CONFIG_INTEGRITY_PLATFORM_KEYRING=y +# CONFIG_INTEGRITY_MACHINE_KEYRING is not set CONFIG_LOAD_UEFI_KEYS=y CONFIG_INTEGRITY_AUDIT=y # CONFIG_IMA is not set @@ -9488,6 +9663,10 @@ CONFIG_INIT_STACK_NONE=y CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RANDSTRUCT_FULL is not set +# CONFIG_RANDSTRUCT_PERFORMANCE is not set # end of Kernel hardening options # end of Security options @@ -9538,6 +9717,7 @@ CONFIG_CRYPTO_ENGINE=y # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y +# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=m @@ -9590,6 +9770,7 @@ CONFIG_CRYPTO_XXHASH=y CONFIG_CRYPTO_BLAKE2B=y CONFIG_CRYPTO_BLAKE2S=m CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_POLY1305=y CONFIG_CRYPTO_MD4=m @@ -9601,6 +9782,7 @@ CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_SM3_GENERIC=m CONFIG_CRYPTO_STREEBOG=m CONFIG_CRYPTO_WP512=y @@ -9624,6 +9806,7 @@ CONFIG_CRYPTO_CHACHA20=y CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=y CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_TWOFISH_COMMON=y @@ -9666,7 +9849,6 @@ CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m CONFIG_CRYPTO_DEV_NITROX=m CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m # CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set -CONFIG_CRYPTO_DEV_ROCKCHIP=m CONFIG_CRYPTO_DEV_VIRTIO=m CONFIG_CRYPTO_DEV_SAFEXCEL=m CONFIG_CRYPTO_DEV_CCREE=m @@ -9680,13 +9862,12 @@ CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y # CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y -CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS8_PRIVATE_KEY_PARSER=m -CONFIG_TPM_KEY_PARSER=m CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=m CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set # # Certificates for signature checking @@ -9702,6 +9883,7 @@ CONFIG_SECONDARY_TRUSTED_KEYRING=y CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" # CONFIG_SYSTEM_REVOCATION_LIST is not set +# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y @@ -9745,12 +9927,13 @@ CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_SM4=m # end of Crypto library routines +CONFIG_LIB_MEMNEQ=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y +CONFIG_CRC64_ROCKSOFT=y CONFIG_CRC_ITU_T=y CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set @@ -9774,8 +9957,8 @@ CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_COMPRESS=m -CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4HC_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y @@ -9826,7 +10009,6 @@ CONFIG_SWIOTLB=y # CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y -CONFIG_DMA_REMAP=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_CMA=y CONFIG_DMA_PERNUMA_CMA=y @@ -9907,10 +10089,16 @@ CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + # # Compile-time checks and compiler options # -# CONFIG_DEBUG_INFO is not set +CONFIG_DEBUG_INFO_NONE=y +# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -9942,14 +10130,12 @@ CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y CONFIG_HAVE_ARCH_KCSAN=y # end of Generic Kernel Debugging Instruments -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MISC=y - # # Networking Debugging # # CONFIG_NET_DEV_REFCNT_TRACKER is not set # CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set # end of Networking Debugging # @@ -9957,7 +10143,10 @@ CONFIG_DEBUG_MISC=y # # CONFIG_PAGE_EXTENSION is not set # CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set # CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_TABLE_CHECK is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_RODATA_TEST is not set CONFIG_ARCH_HAS_DEBUG_WX=y @@ -9965,8 +10154,6 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -10058,6 +10245,7 @@ CONFIG_RCU_SCALE_TEST=m CONFIG_RCU_TORTURE_TEST=m CONFIG_RCU_REF_SCALE_TEST=m CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 CONFIG_RCU_TRACE=y # CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging @@ -10096,6 +10284,7 @@ CONFIG_KUNIT_TEST=m CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT_ALL_TESTS=m # CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y @@ -10105,6 +10294,7 @@ CONFIG_RUNTIME_TESTING_MENU=y CONFIG_TEST_MIN_HEAP=m # CONFIG_TEST_SORT is not set CONFIG_TEST_DIV64=m +CONFIG_KPROBES_SANITY_TEST=m CONFIG_BACKTRACE_SELF_TEST=m CONFIG_TEST_REF_TRACKER=m CONFIG_RBTREE_TEST=m @@ -10123,7 +10313,6 @@ CONFIG_TEST_SCANF=m # CONFIG_TEST_BITMAP is not set # CONFIG_TEST_UUID is not set CONFIG_TEST_XARRAY=m -# CONFIG_TEST_OVERFLOW is not set # CONFIG_TEST_RHASHTABLE is not set # CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set @@ -10147,11 +10336,12 @@ CONFIG_BITS_TEST=m CONFIG_SLUB_KUNIT_TEST=m CONFIG_RATIONAL_KUNIT_TEST=m CONFIG_MEMCPY_KUNIT_TEST=m +CONFIG_OVERFLOW_KUNIT_TEST=m +CONFIG_STACKINIT_KUNIT_TEST=m # CONFIG_TEST_UDELAY is not set # CONFIG_TEST_STATIC_KEYS is not set # CONFIG_TEST_KMOD is not set CONFIG_TEST_MEMCAT_P=m -CONFIG_TEST_STACKINIT=m # CONFIG_TEST_MEMINIT is not set CONFIG_TEST_FREE_PAGES=m CONFIG_ARCH_USE_MEMTEST=y diff --git a/config/sources/families/include/meson64_common.inc b/config/sources/families/include/meson64_common.inc index 333d87cff..6ed90f3de 100644 --- a/config/sources/families/include/meson64_common.inc +++ b/config/sources/families/include/meson64_common.inc @@ -21,7 +21,7 @@ CPUMAX=${CPUMAX:-1536000} GOVERNOR=${GOVERNOR:-ondemand} case $BRANCH in - + legacy) KERNELSOURCE='https://github.com/hardkernel/linux' #KERNELBRANCH='branch:odroidg12-4.9.y' @@ -35,7 +35,7 @@ case $BRANCH in ;; edge) - KERNELBRANCH='branch:linux-5.17.y' + KERNELBRANCH='branch:linux-5.19.y' KERNELPATCHDIR='meson64-edge' ;; @@ -289,7 +289,7 @@ family_tweaks_bsp() cat <<-EOF > "$destination"/etc/X11/xorg.conf Section "Device" Identifier "DRM Graphics Acclerated" - + ## Use modesetting and glamor Driver "modesetting" Option "AccelMethod" "glamor" ### "glamor" to enable 3D acceleration, "none" to disable. @@ -297,9 +297,9 @@ family_tweaks_bsp() Option "Dri2Vsync" "true" Option "TripleBuffer" "True" ## End glamor configuration - + EndSection - + Section "Screen" Identifier "Default Screen" SubSection "Display" @@ -312,7 +312,7 @@ family_tweaks_bsp() } # This is an extension method, put directly in meson64_common. A "built-in" extension if you will. -# If used in more than one place, it could be moved to an extension: enable_extension "amlogic-fip-tools" +# If used in more than one place, it could be moved to an extension: enable_extension "amlogic-fip-tools" function fetch_sources_tools__amlogic_fip() { fetch_from_repo "https://github.com/armbian/odroidc2-blobs" "odroidc2-blobs" "branch:master" fetch_from_repo "https://github.com/LibreELEC/amlogic-boot-fip" "amlogic-boot-fip" "branch:master" diff --git a/patch/kernel/archive/meson64-5.19/add-board-radxa-zero2.patch b/patch/kernel/archive/meson64-5.19/add-board-radxa-zero2.patch new file mode 100644 index 000000000..042aa7d78 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/add-board-radxa-zero2.patch @@ -0,0 +1,576 @@ +From 9c2db9e795f4d73e78a02f6c8cb313e6bcf34f7e Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Wed, 16 Feb 2022 07:27:07 +0000 +Subject: [PATCH 69/90] WIP: dt-bindings: arm: amlogic: add support for Radxa + Zero2 + +The Radxa Zero2 is a small form-factor SBC using the Amlogic +A311D chip. + +Signed-off-by: Christian Hewitt +--- + Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml +index 05365bb50b29..d069aecabeb3 100644 +--- a/Documentation/devicetree/bindings/arm/amlogic.yaml ++++ b/Documentation/devicetree/bindings/arm/amlogic.yaml +@@ -152,6 +152,7 @@ properties: + items: + - enum: + - khadas,vim3 ++ - radxa,zero2 + - const: amlogic,a311d + - const: amlogic,g12b + +-- +2.35.1 + +From aadb6d12609309106f6ab7a56face84c19859796 Mon Sep 17 00:00:00 2001 +From: Yuntian Zhang +Date: Fri, 14 Jan 2022 15:50:02 +0000 +Subject: [PATCH 70/90] WIP: arm64: dts: meson: add support for Radxa Zero2 + +Radxa Zero2 is a small form factor SBC based on the Amlogic A311D +chipset that ships in a number of eMMC configurations: + +- Amlogic A311D (Quad A73 + Dual A53) CPU +- 4GB LPDDR4 RAM +- 32/64/128GB eMMC +- Mali G52-MP4 GPU +- HDMI 2.1 output (micro) +- BCM4345 WiFi (2.4/5GHz a/b/g/n/ac) and BT 5.0 +- 1x USB 2.0 port - Type C (OTG) +- 1x USB 3.0 port - Type C (Host) +- 1x micro SD Card slot +- 40 Pin GPIO header + +Signed-off-by: Yuntian Zhang +Signed-off-by: Christian Hewitt +--- + arch/arm64/boot/dts/amlogic/Makefile | 1 + + .../dts/amlogic/meson-g12b-radxa-zero2.dts | 499 ++++++++++++++++++ + 2 files changed, 500 insertions(+) + create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts + +diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile +index 8773211df50e..f231280cd808 100644 +--- a/arch/arm64/boot/dts/amlogic/Makefile ++++ b/arch/arm64/boot/dts/amlogic/Makefile +@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb ++dtb-$(CONFIG_ARCH_MESON) += meson-g12b-radxa-zero2.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +new file mode 100644 +index 000000000000..fefa6f2b7abf +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +@@ -0,0 +1,499 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre, SAS ++ * Author: Neil Armstrong ++ * Copyright (c) 2019 Christian Hewitt ++ * Copyright (c) 2022 Radxa Limited ++ * Author: Yuntian Zhang ++ */ ++ ++/dts-v1/; ++ ++#include "meson-g12b-a311d.dtsi" ++#include ++#include ++#include ++#include ++ ++/ { ++ compatible = "radxa,zero2", "amlogic,a311d", "amlogic,g12b"; ++ model = "Radxa Zero2"; ++ ++ aliases { ++ serial0 = &uart_AO; ++ serial2 = &uart_A; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x80000000>; ++ }; ++ ++ gpio-keys-polled { ++ compatible = "gpio-keys-polled"; ++ poll-interval = <100>; ++ power-button { ++ label = "power"; ++ linux,code = ; ++ gpios = <&gpio_ao GPIOAO_3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-green { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio GPIOA_12 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ cvbs-connector { ++ status = "disabled"; ++ compatible = "composite-video-connector"; ++ ++ port { ++ cvbs_connector_in: endpoint { ++ remote-endpoint = <&cvbs_vdac_out>; ++ }; ++ }; ++ }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_connector_in: endpoint { ++ remote-endpoint = <&hdmi_tx_tmds_out>; ++ }; ++ }; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; ++ clocks = <&wifi32k>; ++ clock-names = "ext_clock"; ++ }; ++ ++ ao_5v: regulator-ao_5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "AO_5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vcc_1v8: regulator-vcc_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_3v3>; ++ regulator-always-on; ++ }; ++ ++ vcc_3v3: regulator-vcc_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ /* FIXME: actually controlled by VDDCPU_B_EN */ ++ }; ++ ++ vddao_1v8: regulator-vddao_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vddao_3v3: regulator-vddao_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&ao_5v>; ++ regulator-always-on; ++ }; ++ ++ vddcpu_a: regulator-vddcpu-a { ++ /* ++ * MP8756GD Regulator. ++ */ ++ compatible = "pwm-regulator"; ++ ++ regulator-name = "VDDCPU_A"; ++ regulator-min-microvolt = <730000>; ++ regulator-max-microvolt = <1022000>; ++ ++ pwm-supply = <&ao_5v>; ++ ++ pwms = <&pwm_ab 0 1250 0>; ++ pwm-dutycycle-range = <100 0>; ++ ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vddcpu_b: regulator-vddcpu-b { ++ /* ++ * Silergy SY8120B1ABC Regulator. ++ */ ++ compatible = "pwm-regulator"; ++ ++ regulator-name = "VDDCPU_B"; ++ regulator-min-microvolt = <730000>; ++ regulator-max-microvolt = <1022000>; ++ ++ pwm-supply = <&ao_5v>; ++ ++ pwms = <&pwm_AO_cd 1 1250 0>; ++ pwm-dutycycle-range = <100 0>; ++ ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sound { ++ compatible = "amlogic,axg-sound-card"; ++ model = "RADXA-ZERO2"; ++ audio-aux-devs = <&tdmout_b>; ++ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", ++ "TDMOUT_B IN 1", "FRDDR_B OUT 1", ++ "TDMOUT_B IN 2", "FRDDR_C OUT 1", ++ "TDM_B Playback", "TDMOUT_B OUT"; ++ ++ assigned-clocks = <&clkc CLKID_MPLL2>, ++ <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&frddr_a>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&frddr_b>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&frddr_c>; ++ }; ++ ++ /* 8ch hdmi interface */ ++ dai-link-3 { ++ sound-dai = <&tdmif_b>; ++ dai-format = "i2s"; ++ dai-tdm-slot-tx-mask-0 = <1 1>; ++ dai-tdm-slot-tx-mask-1 = <1 1>; ++ dai-tdm-slot-tx-mask-2 = <1 1>; ++ dai-tdm-slot-tx-mask-3 = <1 1>; ++ mclk-fs = <256>; ++ ++ codec { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; ++ }; ++ }; ++ ++ /* hdmi glue */ ++ dai-link-4 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; ++ ++ codec { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++ ++ wifi32k: wifi32k { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ ++ }; ++}; ++ ++&arb { ++ status = "okay"; ++}; ++ ++&cec_AO { ++ pinctrl-0 = <&cec_ao_a_h_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ ++&cecb_AO { ++ pinctrl-0 = <&cec_ao_b_h_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ ++&clkc_audio { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vddcpu_b>; ++ operating-points-v2 = <&cpu_opp_table_0>; ++ clocks = <&clkc CLKID_CPU_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vddcpu_b>; ++ operating-points-v2 = <&cpu_opp_table_0>; ++ clocks = <&clkc CLKID_CPU_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu100 { ++ cpu-supply = <&vddcpu_a>; ++ operating-points-v2 = <&cpub_opp_table_1>; ++ clocks = <&clkc CLKID_CPUB_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu101 { ++ cpu-supply = <&vddcpu_a>; ++ operating-points-v2 = <&cpub_opp_table_1>; ++ clocks = <&clkc CLKID_CPUB_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu102 { ++ cpu-supply = <&vddcpu_a>; ++ operating-points-v2 = <&cpub_opp_table_1>; ++ clocks = <&clkc CLKID_CPUB_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu103 { ++ cpu-supply = <&vddcpu_a>; ++ operating-points-v2 = <&cpub_opp_table_1>; ++ clocks = <&clkc CLKID_CPUB_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cvbs_vdac_port { ++ cvbs_vdac_out: endpoint { ++ remote-endpoint = <&cvbs_connector_in>; ++ }; ++}; ++ ++&frddr_a { ++ status = "okay"; ++}; ++ ++&frddr_b { ++ status = "okay"; ++}; ++ ++&frddr_c { ++ status = "okay"; ++}; ++ ++&gpio { ++ gpio-line-names = ++ /* GPIOZ */ ++ "PIN_27", "PIN_28", "PIN_7", "PIN_11", "PIN_13", "PIN_15", "PIN_18", "PIN_40", ++ "", "", "", "", "", "", "", "", ++ /* GPIOH */ ++ "", "", "", "", "PIN_19", "PIN_21", "PIN_24", "PIN_23", ++ "", ++ /* BOOT */ ++ "", "", "", "", "", "", "", "", ++ "", "", "", "", "EMMC_PWRSEQ", "", "", "", ++ /* GPIOC */ ++ "", "", "", "", "", "", "SD_CD", "PIN_36", ++ /* GPIOA */ ++ "PIN_32", "PIN_12", "PIN_35", "", "", "PIN_38", "", "", ++ "", "", "", "", "LED_GREEN", "PIN_31", "PIN_3", "PIN_5", ++ /* GPIOX */ ++ "", "", "", "", "", "", "SDIO_PWRSEQ", "", ++ "", "", "", "", "", "", "", "", ++ "", "BT_SHUTDOWN", "", ""; ++}; ++ ++&gpio_ao { ++ gpio-line-names = ++ /* GPIOAO */ ++ "PIN_8", "PIN_10", "", "BTN_POWER", "", "", "", "PIN_29", ++ "PIN_33", "PIN_37", "FAN", "", ++ /* GPIOE */ ++ "", "", ""; ++}; ++ ++&hdmi_tx { ++ status = "okay"; ++ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; ++ pinctrl-names = "default"; ++ hdmi-supply = <&ao_5v>; ++}; ++ ++&hdmi_tx_tmds_port { ++ hdmi_tx_tmds_out: endpoint { ++ remote-endpoint = <&hdmi_connector_in>; ++ }; ++}; ++ ++&ir { ++ status = "disabled"; ++ pinctrl-0 = <&remote_input_ao_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&pwm_ab { ++ pinctrl-0 = <&pwm_a_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin0"; ++ status = "okay"; ++}; ++ ++&pwm_ef { ++ pinctrl-0 = <&pwm_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin2"; ++ status = "okay"; ++}; ++ ++&pwm_AO_cd { ++ pinctrl-0 = <&pwm_ao_d_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin4"; ++ status = "okay"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vddao_1v8>; ++}; ++ ++/* SDIO */ ++&sd_emmc_a { ++ status = "okay"; ++ pinctrl-0 = <&sdio_pins>; ++ pinctrl-1 = <&sdio_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ max-frequency = <100000000>; ++ ++ non-removable; ++ disable-wp; ++ ++ /* WiFi firmware requires power to be kept while in suspend */ ++ keep-power-in-suspend; ++ ++ mmc-pwrseq = <&sdio_pwrseq>; ++ ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddao_1v8>; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ }; ++}; ++ ++/* SD card */ ++&sd_emmc_b { ++ status = "okay"; ++ pinctrl-0 = <&sdcard_c_pins>; ++ pinctrl-1 = <&sdcard_clk_gate_c_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ max-frequency = <50000000>; ++ disable-wp; ++ ++ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddao_3v3>; ++}; ++ ++/* eMMC */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ max-frequency = <200000000>; ++ disable-wp; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++}; ++ ++&tdmif_b { ++ status = "okay"; ++}; ++ ++&tdmout_b { ++ status = "okay"; ++}; ++ ++&tohdmitx { ++ status = "okay"; ++}; ++ ++&uart_A { ++ status = "okay"; ++ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; ++ max-speed = <2000000>; ++ clocks = <&wifi32k>; ++ clock-names = "lpo"; ++ }; ++}; ++ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb { ++ status = "okay"; ++}; +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/board-khadas-vim2-use-gpio-fan-matrix-instead-of-array.patch b/patch/kernel/archive/meson64-5.19/board-khadas-vim2-use-gpio-fan-matrix-instead-of-array.patch new file mode 100644 index 000000000..49791e5c2 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-khadas-vim2-use-gpio-fan-matrix-instead-of-array.patch @@ -0,0 +1,39 @@ +From 4f925789d0713c48deb5067187c7e5acba397054 Mon Sep 17 00:00:00 2001 +From: David Heidelberg +Date: Sat, 27 Nov 2021 07:23:35 +0000 +Subject: [PATCH 28/90] FROMLIST(v1): arm64: dts: meson: make dts use gpio-fan + matrix instead of array + +No functional changes. + +Adjust to comply with dt-schema requirements +and make possible to validate values. + +Signed-off-by: David Heidelberg +--- + arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +index 9c26d7489d2a..c5e3b5587135 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +@@ -54,10 +54,11 @@ gpio_fan: gpio-fan { + gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH + &gpio GPIODV_15 GPIO_ACTIVE_HIGH>; + /* Dummy RPM values since fan is optional */ +- gpio-fan,speed-map = <0 0 +- 1 1 +- 2 2 +- 3 3>; ++ gpio-fan,speed-map = ++ <0 0>, ++ <1 1>, ++ <2 2>, ++ <3 3>; + #cooling-cells = <2>; + }; + +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/board-khadas-vim3-fix-missing-i2c3-nod.patch b/patch/kernel/archive/meson64-5.19/board-khadas-vim3-fix-missing-i2c3-nod.patch new file mode 100644 index 000000000..dfbb76890 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-khadas-vim3-fix-missing-i2c3-nod.patch @@ -0,0 +1,38 @@ +From 04ba78002ded0f9089b7fae6550a56ccd0669e65 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Fri, 21 Feb 2020 04:43:22 +0000 +Subject: [PATCH 086/101] WIP: arm64: dts: meson: khadas-vim3: fix missing i2c3 + node + +Fixes: c6d29c66e582 ("arm64: dts: meson-g12b-khadas-vim3: add initial device-tree") + +The i2c3 node was missed in the original device-tree and is required for the +optional Khadas 3705 fan to work. + +Suggested-by: Art Nikpal +Signed-off-by: Christian Hewittt +--- + arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +index 0ef60c7151cb..6022805d2032 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +@@ -217,6 +217,13 @@ + }; + }; + ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ + &i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; +-- +2.17.1 + diff --git a/patch/kernel/archive/meson64-5.19/board-khadas-vims-add-rtc-vrtc-aliases.patch b/patch/kernel/archive/meson64-5.19/board-khadas-vims-add-rtc-vrtc-aliases.patch new file mode 100644 index 000000000..c4422fed5 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-khadas-vims-add-rtc-vrtc-aliases.patch @@ -0,0 +1,60 @@ +From 5ff8dfecb282089107d1bd3da6b612c5294fe0cb Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Thu, 21 Jan 2021 01:35:36 +0000 +Subject: [PATCH 07/90] HACK: arm64: dts: meson: add rtc/vrtc aliases to Khadas + VIM + +Add aliases to ensure the vrtc time (which normally proves first) is /dev/rtc1 +while the onboard rtc chip claims /dev/rtc0. + +Signed-off-by: Christian Hewitt +--- + arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +index 6ab1cc125b96..24af15e18026 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +@@ -29,6 +29,8 @@ button-function { + aliases { + serial2 = &uart_AO_B; + ethernet0 = ðmac; ++ rtc0 = &rtc; ++ rtc1 = &vrtc; + }; + + gpio-keys-polled { +-- +2.35.1 + +From 293a4281d04100f1a0ab8ced46a45fc557f6e130 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Sat, 6 Nov 2021 13:01:08 +0000 +Subject: [PATCH 08/90] HACK: arm64: dts: meson: add rtc/vrtc aliases to Khadas + VIM2 + +Add aliases to ensure the vrtc time (which normally proves first) is /dev/rtc1 +while the onboard rtc chip claims /dev/rtc0. + +Signed-off-by: Christian Hewitt +--- + arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +index 86bdc0baf032..9c26d7489d2a 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +@@ -18,6 +18,8 @@ / { + aliases { + serial0 = &uart_AO; + serial2 = &uart_AO_B; ++ rtc0 = &rtc; ++ rtc1 = &vrtc; + }; + + chosen { +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/board-nanopi-k2-add-uartC-alias.patch b/patch/kernel/archive/meson64-5.19/board-nanopi-k2-add-uartC-alias.patch new file mode 100644 index 000000000..1f634cdb3 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-nanopi-k2-add-uartC-alias.patch @@ -0,0 +1,12 @@ +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +index cbe99bd..80c87e0 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +@@ -13,6 +13,7 @@ + + aliases { + serial0 = &uart_AO; ++ serial2 = &uart_C; + ethernet0 = ðmac; + }; + diff --git a/patch/kernel/archive/meson64-5.19/board-nanopi-k2-enable-emmc.patch b/patch/kernel/archive/meson64-5.19/board-nanopi-k2-enable-emmc.patch new file mode 100644 index 000000000..f27399f82 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-nanopi-k2-enable-emmc.patch @@ -0,0 +1,22 @@ +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +index 80c87e0bb..340559727 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +@@ -382,7 +382,7 @@ + + /* eMMC */ + &sd_emmc_c { +- status = "disabled"; ++ status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; +@@ -392,8 +392,6 @@ + non-removable; + disable-wp; + cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc3v3>; diff --git a/patch/kernel/archive/meson64-5.19/board-odroidc2-add-uartA-uartC.patch b/patch/kernel/archive/meson64-5.19/board-odroidc2-add-uartA-uartC.patch new file mode 100644 index 000000000..b3c9eb7f3 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-odroidc2-add-uartA-uartC.patch @@ -0,0 +1,32 @@ +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +index 201596247fd9..b2cb12fb46fd 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +@@ -17,6 +17,8 @@ / { + + aliases { + serial0 = &uart_AO; ++ serial1 = &uart_A; ++ serial2 = &uart_C; + ethernet0 = ðmac; + }; + +@@ -399,6 +401,18 @@ &uart_AO { + pinctrl-names = "default"; + }; + ++&uart_A { ++ status = "disabled"; ++ pinctrl-0 = <&uart_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&uart_C { ++ status = "disabled"; ++ pinctrl-0 = <&uart_c_pins>; ++ pinctrl-names = "default"; ++}; ++ + &usb0_phy { + status = "disabled"; + phy-supply = <&usb_otg_pwr>; diff --git a/patch/kernel/archive/meson64-5.19/board-odroidc2-enable-SPI.patch b/patch/kernel/archive/meson64-5.19/board-odroidc2-enable-SPI.patch new file mode 100644 index 000000000..44b9769f1 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-odroidc2-enable-SPI.patch @@ -0,0 +1,37 @@ +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +index b2cb12fb46fd..c252de8e4b17 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +@@ -176,6 +176,32 @@ hdmi_connector_in: endpoint { + }; + }; + ++ spi-gpio { ++ compatible = "spi-gpio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ ranges; ++ status = "disabled"; ++ sck-gpios = <&gpio GPIOX_2 0>; ++ miso-gpios = <&gpio GPIOX_4 0>; ++ mosi-gpios = <&gpio GPIOX_7 0>; ++ cs-gpios = <&gpio GPIOX_3 0 ++ &gpio GPIOX_1 0>; ++ num-chipselects = <2>; ++ ++ /* clients */ ++ spidev0@0 { ++ compatible = "spidev"; ++ reg = <0>; ++ spi-max-frequency = <500000>; ++ }; ++ spidev0@1 { ++ compatible = "spidev"; ++ reg = <1>; ++ spi-max-frequency = <500000>; ++ }; ++ }; ++ + sound { + compatible = "amlogic,gx-sound-card"; + model = "ODROID-C2"; diff --git a/patch/kernel/archive/meson64-5.19/board-odroidc2-enable-scpi-dvfs.patch b/patch/kernel/archive/meson64-5.19/board-odroidc2-enable-scpi-dvfs.patch new file mode 100644 index 000000000..dbe1e637f --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-odroidc2-enable-scpi-dvfs.patch @@ -0,0 +1,14 @@ +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +index d147c853a..dbde670ba 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +@@ -246,7 +246,8 @@ + }; + + &scpi_clocks { +- status = "disabled"; ++ /* Works only with new blobs that have limited DVFS table */ ++ status = "okay"; + }; + + /* SD */ diff --git a/patch/kernel/archive/meson64-5.19/board-odroidhc4-enable-fan1_input.patch b/patch/kernel/archive/meson64-5.19/board-odroidhc4-enable-fan1_input.patch new file mode 100644 index 000000000..51e4820e5 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-odroidhc4-enable-fan1_input.patch @@ -0,0 +1,29 @@ +From 9058e8940ae84b1bc97693d9aca7b27f55bb1964 Mon Sep 17 00:00:00 2001 +From: Ricardo Pardini +Date: Sun, 26 Jun 2022 03:47:06 +0200 +Subject: [PATCH] ODROID-HC4: add DT attributes to enable fan1_input + +- from vendor kernel modified DT +- this allows userspace fancontrol/pwmconfig to work +--- + arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +index 0764f1bb5..2b0752144 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +@@ -23,6 +23,10 @@ fan0: pwm-fan { + cooling-max-state = <3>; + cooling-levels = <0 120 170 220>; + pwms = <&pwm_cd 1 40000 0>; ++ fan-supply = <&vcc_5v>; ++ interrupt-parent = <&gpio_intc>; ++ interrupts = <84 IRQ_TYPE_EDGE_FALLING>; ++ pulses-per-revolutions = <2>; + }; + + leds { +-- +2.36.1 + diff --git a/patch/kernel/archive/meson64-5.19/board-odroidn2-add-dumb-gpio-fan.patch b/patch/kernel/archive/meson64-5.19/board-odroidn2-add-dumb-gpio-fan.patch new file mode 100644 index 000000000..e227d9e82 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-odroidn2-add-dumb-gpio-fan.patch @@ -0,0 +1,40 @@ +From 86d9151effff69d2a8fc2027a31dd60bd8c6eb05 Mon Sep 17 00:00:00 2001 +Message-Id: <86d9151effff69d2a8fc2027a31dd60bd8c6eb05.1627311993.git.stefan@agner.ch> +In-Reply-To: +References: +From: Stefan Agner +Date: Mon, 11 Jan 2021 11:38:54 +0100 +Subject: [PATCH 5/9] arm64: dts: meson: g12b: add GPIO fan support + +Add simple GPIO fan node to support a fan on GPIO J8. Unfortunately the +pad used to control the fan does not support real PWM, hence the RPM +cannot be modulated. + +Signed-off-by: Stefan Agner +Tested-by: Ricardo Pardini +--- + arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi (revision e209be874602b0a650b442801cbffe529aa7dfff) ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi (date 1655943404649) +@@ -44,6 +44,15 @@ + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + ++ /* 5V 80x80x10.8mm cooling fan from Hardkernel shop... */ ++ fan0: gpio-fan { ++ #cooling-cells = <2>; ++ compatible = "gpio-fan"; ++ gpio-fan,speed-map = <0 0 1600 1>; ++ gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ + leds { + compatible = "gpio-leds"; + +-- +2.32.0 + diff --git a/patch/kernel/archive/meson64-5.19/board-odroidn2-add-gpio-fan-as-cooling-device.patch b/patch/kernel/archive/meson64-5.19/board-odroidn2-add-gpio-fan-as-cooling-device.patch new file mode 100644 index 000000000..1b07af63e --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-odroidn2-add-gpio-fan-as-cooling-device.patch @@ -0,0 +1,73 @@ +From f1120f132dbdf2e7f7acf328de55bbdce877d882 Mon Sep 17 00:00:00 2001 +Message-Id: +In-Reply-To: +References: +From: Stefan Agner +Date: Mon, 11 Jan 2021 15:53:55 +0100 +Subject: [PATCH 6/9] arm64: dts: meson: g12b: odroid-n2: add fan as cooling + device +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add the GPIO fan as a cooling device for the CPU thermal zone. Since we +have only full fan speed available with this, set the tripping point to +30°C. + +Signed-off-by: Stefan Agner +--- + .../dts/amlogic/meson-g12b-odroid-n2.dtsi | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +index e8a3ede698b5..dd345c6aa4b5 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +@@ -388,6 +388,44 @@ &clkc_audio { + status = "okay"; + }; + ++&cpu_thermal { ++ trips { ++ cpu_warm: cpu_warm { ++ hysteresis = <5000>; ++ temperature = <30000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ cooling-device = ++ <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ trip = <&cpu_warm>; ++ }; ++ map1 { ++ trip = <&cpu_passive>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ map2 { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &cpu0 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; +-- +2.32.0 + diff --git a/patch/kernel/archive/meson64-5.19/board-odroidn2-add-spi-flash-enabled-dts.patch b/patch/kernel/archive/meson64-5.19/board-odroidn2-add-spi-flash-enabled-dts.patch new file mode 100644 index 000000000..a329eca65 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-odroidn2-add-spi-flash-enabled-dts.patch @@ -0,0 +1,84 @@ +Index: arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-spi.dts +IDEA additional info: +Subsystem: com.intellij.openapi.diff.impl.patch.CharsetEP +<+>UTF-8 +=================================================================== +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-spi.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-spi.dts +new file mode 100644 +--- /dev/null (date 1630421486471) ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-spi.dts (date 1630421486471) +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "meson-g12b-odroid-n2.dts" ++ ++/ { ++ model = "Hardkernel ODROID-N2 with SPI"; ++}; ++ ++#include "meson-g12b-odroid-n2-enable-spi.dtsi" +Index: arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus-spi.dts +IDEA additional info: +Subsystem: com.intellij.openapi.diff.impl.patch.CharsetEP +<+>UTF-8 +=================================================================== +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus-spi.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus-spi.dts +new file mode 100644 +--- /dev/null (date 1630421477913) ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus-spi.dts (date 1630421477913) +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "meson-g12b-odroid-n2-plus.dts" ++ ++/ { ++ model = "Hardkernel ODROID-N2Plus with SPI"; ++}; ++ ++#include "meson-g12b-odroid-n2-enable-spi.dtsi" +Index: arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-enable-spi.dtsi +IDEA additional info: +Subsystem: com.intellij.openapi.diff.impl.patch.CharsetEP +<+>UTF-8 +=================================================================== +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-enable-spi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-enable-spi.dtsi +new file mode 100644 +--- /dev/null (date 1630421525557) ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-enable-spi.dtsi (date 1630421525557) +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/* ++ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, and change bus-width to 4 then spifc can be enabled. ++ */ ++&sd_emmc_c { ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>; ++ bus-width = <4>; ++}; ++ ++&spifc { ++ status = "okay"; ++}; +Index: arch/arm64/boot/dts/amlogic/Makefile +IDEA additional info: +Subsystem: com.intellij.openapi.diff.impl.patch.CharsetEP +<+>UTF-8 +=================================================================== +diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile +index f231280cd808..da3225d31e38 100644 +--- a/arch/arm64/boot/dts/amlogic/Makefile ++++ b/arch/arm64/boot/dts/amlogic/Makefile +@@ -10,7 +10,9 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb ++dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-spi.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb ++dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus-spi.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-radxa-zero2.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb diff --git a/patch/kernel/archive/meson64-5.19/board-odroidn2plus-Add-missing-CPU-opp.patch b/patch/kernel/archive/meson64-5.19/board-odroidn2plus-Add-missing-CPU-opp.patch new file mode 100644 index 000000000..d9f307131 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-odroidn2plus-Add-missing-CPU-opp.patch @@ -0,0 +1,46 @@ +From 712b399ed54f49e0ac7ae92c57ed775604eaaed9 Mon Sep 17 00:00:00 2001 +From: Igor Pecovnik +Date: Wed, 10 Feb 2021 18:07:08 +0100 +Subject: [PATCH] Add missing CPU opp values for clocking g12b / N2+ higher + +Signed-off-by: Igor Pecovnik +--- + .../arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +index d61f43052..75030d197 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +@@ -65,6 +65,14 @@ opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1001000>; + }; ++ opp-1908000000 { ++ opp-hz = /bits/ 64 <1908000000>; ++ opp-microvolt = <1030000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <1040000>; ++ }; + }; + + cpub_opp_table_1: opp-table-1 { +@@ -145,5 +153,13 @@ opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1011000>; + }; ++ opp-2304000000 { ++ opp-hz = /bits/ 64 <2304000000>; ++ opp-microvolt = <1030000>; ++ }; ++ opp-2400000000 { ++ opp-hz = /bits/ 64 <2400000000>; ++ opp-microvolt = <1040000>; ++ }; + }; + }; +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/archive/meson64-5.19/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch b/patch/kernel/archive/meson64-5.19/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch new file mode 100644 index 000000000..cb9eb7413 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch @@ -0,0 +1,94 @@ +From 795fad491189f7fd6034d6d639602119a4e60755 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Tue, 17 Aug 2021 16:16:43 +0000 +Subject: [PATCH 68/90] WIP: arm64: dts: meson: radxa-zero: add support for the + usb type-c controller + +Radxa Zero uses an FUSB302 type-c controller, so lets enable it. + +NB: Polarity swapping via GPIO is not implemented in the current driver +(see drivers/usb/typec/tcpm/fusb302.c) so it is not possible to handle +GPIOAO_6 for USB3 polarity control. + +Suggested-by: Neil Armstrong +Signed-off-by: Christian Hewitt +--- + .../dts/amlogic/meson-g12a-radxa-zero.dts | 44 +++++++++++++++++++ + 1 file changed, 44 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +index e3bb6df42ff3..5e3dc013409f 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +@@ -60,6 +60,14 @@ sdio_pwrseq: sdio-pwrseq { + clock-names = "ext_clock"; + }; + ++ typec2_vbus: regulator-typec2_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "TYPEC2_VBUS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&ao_5v>; ++ }; ++ + ao_5v: regulator-ao_5v { + compatible = "regulator-fixed"; + regulator-name = "AO_5V"; +@@ -191,6 +199,18 @@ wifi32k: wifi32k { + }; + }; + ++&ao_pinctrl { ++ /* Ensure the TYPE C controller irq pin is not driven by the SoC */ ++ fusb302_irq_pins: fusb302_irq { ++ mux { ++ groups = "GPIOAO_5"; ++ function = "gpio_aobus"; ++ bias-pull-up; ++ output-disable; ++ }; ++ }; ++}; ++ + &arb { + status = "okay"; + }; +@@ -278,6 +298,22 @@ &ir { + pinctrl-names = "default"; + }; + ++&i2c_AO { ++ fusb302@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ ++ pinctrl-0 = <&fusb302_irq_pins>; ++ pinctrl-names = "default"; ++ interrupt-parent = <&gpio_intc>; ++ interrupts = <59 IRQ_TYPE_LEVEL_LOW>; ++ ++ vbus-supply = <&typec2_vbus>; ++ ++ status = "okay"; ++ }; ++}; ++ + &pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; +@@ -403,3 +439,11 @@ &usb { + status = "okay"; + dr_mode = "host"; + }; ++ ++&usb2_phy0 { ++ phy-supply = <&typec2_vbus>; ++}; ++ ++&usb3_pcie_phy { ++ phy-supply = <&typec2_vbus>; ++}; +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch b/patch/kernel/archive/meson64-5.19/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch new file mode 100644 index 000000000..eb246e1fa --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch @@ -0,0 +1,12 @@ +diff -Naur a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +--- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts 2022-03-20 16:14:17.000000000 -0400 ++++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts 2022-03-27 07:44:01.636737819 -0400 +@@ -310,7 +310,7 @@ + + bus-width = <4>; + cap-sd-highspeed; +- sd-uhs-sdr50; ++ cap-mmc-highspeed; + max-frequency = <100000000>; + + non-removable; diff --git a/patch/kernel/archive/meson64-5.19/drv-spi-spidev-remove-warnings.patch b/patch/kernel/archive/meson64-5.19/drv-spi-spidev-remove-warnings.patch new file mode 100644 index 000000000..b060c0d74 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/drv-spi-spidev-remove-warnings.patch @@ -0,0 +1,31 @@ +From 2653defc5e22ba86bd1d455eb01fc7edd2958473 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 11:56:51 +0300 +Subject: [PATCH 08/50] drv:spi:spidev remove warnings + +--- + drivers/spi/spidev.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c +index b2775d82d2d7..3c65d3d74559 100644 +--- a/drivers/spi/spidev.c ++++ b/drivers/spi/spidev.c +@@ -683,6 +683,7 @@ static const struct file_operations spidev_fops = { + static struct class *spidev_class; + + static const struct spi_device_id spidev_spi_ids[] = { ++ { .name = "spi-dev" }, + { .name = "dh2228fv" }, + { .name = "ltc2488" }, + { .name = "sx1301" }, +@@ -709,6 +710,7 @@ static int spidev_of_check(struct device *dev) + } + + static const struct of_device_id spidev_dt_ids[] = { ++ { .compatible = "armbian,spi-dev", .data = &spidev_of_check }, + { .compatible = "rohm,dh2228fv", .data = &spidev_of_check }, + { .compatible = "lineartechnology,ltc2488", .data = &spidev_of_check }, + { .compatible = "semtech,sx1301", .data = &spidev_of_check }, +-- +2.35.3 diff --git a/patch/kernel/archive/meson64-5.19/general-add-Amlogic-Meson-GX-PM-Suspend.patch b/patch/kernel/archive/meson64-5.19/general-add-Amlogic-Meson-GX-PM-Suspend.patch new file mode 100644 index 000000000..11c7cbfb7 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-add-Amlogic-Meson-GX-PM-Suspend.patch @@ -0,0 +1,135 @@ +From e0252efa9190de31a2fc98eed28b273428a3fe36 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Thu, 3 Nov 2016 15:29:23 +0100 +Subject: [PATCH 05/90] HACK: arm64: meson: add Amlogic Meson GX PM Suspend + +The Amlogic Meson GX SoCs uses a non-standard argument to the +PSCI CPU_SUSPEND call to enter system suspend. + +Implement such call within platform_suspend_ops. + +Signed-off-by: Neil Armstrong +--- + drivers/firmware/meson/Kconfig | 6 ++ + drivers/firmware/meson/Makefile | 1 + + drivers/firmware/meson/meson_gx_pm.c | 86 ++++++++++++++++++++++++++++ + 3 files changed, 93 insertions(+) + create mode 100644 drivers/firmware/meson/meson_gx_pm.c + +diff --git a/drivers/firmware/meson/Kconfig b/drivers/firmware/meson/Kconfig +index f2fdd3756648..d3ead92ac61b 100644 +--- a/drivers/firmware/meson/Kconfig ++++ b/drivers/firmware/meson/Kconfig +@@ -9,3 +9,9 @@ config MESON_SM + depends on ARM64_4K_PAGES + help + Say y here to enable the Amlogic secure monitor driver ++ ++config MESON_GX_PM ++ bool ++ default ARCH_MESON if ARM64 ++ help ++ Say y here to enable the Amlogic GX SoC Power Management +diff --git a/drivers/firmware/meson/Makefile b/drivers/firmware/meson/Makefile +index c6c09483b622..0193cdfee32f 100644 +--- a/drivers/firmware/meson/Makefile ++++ b/drivers/firmware/meson/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_MESON_SM) += meson_sm.o ++obj-$(CONFIG_MESON_GX_PM) += meson_gx_pm.o +diff --git a/drivers/firmware/meson/meson_gx_pm.c b/drivers/firmware/meson/meson_gx_pm.c +new file mode 100644 +index 000000000000..c104c2e4c77f +--- /dev/null ++++ b/drivers/firmware/meson/meson_gx_pm.c +@@ -0,0 +1,86 @@ ++/* ++ * Amlogic Meson GX Power Management ++ * ++ * Copyright (c) 2016 Baylibre, SAS. ++ * Author: Neil Armstrong ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++/* ++ * The Amlogic GX SoCs uses a special argument value to the ++ * PSCI CPU_SUSPEND method to enter SUSPEND_MEM. ++ */ ++ ++#define MESON_SUSPEND_PARAM 0x0010000 ++#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name ++ ++static int meson_gx_suspend_finish(unsigned long arg) ++{ ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(PSCI_FN_NATIVE(0_2, CPU_SUSPEND), arg, ++ virt_to_phys(cpu_resume), 0, 0, 0, 0, 0, &res); ++ ++ return res.a0; ++} ++ ++static int meson_gx_suspend_enter(suspend_state_t state) ++{ ++ switch (state) { ++ case PM_SUSPEND_MEM: ++ return cpu_suspend(MESON_SUSPEND_PARAM, ++ meson_gx_suspend_finish); ++ } ++ ++ return -EINVAL; ++} ++ ++static const struct platform_suspend_ops meson_gx_pm_ops = { ++ .enter = meson_gx_suspend_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++static const struct of_device_id meson_gx_pm_match[] = { ++ { .compatible = "amlogic,meson-gx-pm", }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, meson_gx_pm_match); ++ ++static int meson_gx_pm_probe(struct platform_device *pdev) ++{ ++ suspend_set_ops(&meson_gx_pm_ops); ++ ++ return 0; ++} ++ ++static struct platform_driver meson_gx_pm_driver = { ++ .probe = meson_gx_pm_probe, ++ .driver = { ++ .name = "meson-gx-pm", ++ .of_match_table = meson_gx_pm_match, ++ }, ++}; ++ ++module_platform_driver(meson_gx_pm_driver); ++ ++MODULE_AUTHOR("Neil Armstrong "); ++MODULE_DESCRIPTION("Amlogic Meson GX PM driver"); ++MODULE_LICENSE("GPL v2"); +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-add-overlay-compilation-support.patch b/patch/kernel/archive/meson64-5.19/general-add-overlay-compilation-support.patch new file mode 100644 index 000000000..84d43d1fa --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-add-overlay-compilation-support.patch @@ -0,0 +1,91 @@ +diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore +index 8c759326baf4..e6ce8f6ad4b1 100644 +--- a/arch/arm/boot/.gitignore ++++ b/arch/arm/boot/.gitignore +@@ -4,3 +4,5 @@ zImage + xipImage + bootpImage + uImage ++*.dtb* ++*.scr +diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst +index 190d781e84f4..6540de71182b 100644 +--- a/scripts/Makefile.dtbinst ++++ b/scripts/Makefile.dtbinst +@@ -18,9 +18,12 @@ include $(srctree)/scripts/Kbuild.include + include $(src)/Makefile + + dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-))) ++dtbos := $(addprefix $(dst)/, $(dtbo-y)) ++scrs := $(addprefix $(dst)/, $(scr-y)) ++readmes := $(addprefix $(dst)/, $(dtbotxt-y)) + subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m)) + +-__dtbs_install: $(dtbs) $(subdirs) ++__dtbs_install: $(dtbs) $(dtbos) $(scrs) $(readmes) $(subdirs) + @: + + quiet_cmd_dtb_install = INSTALL $@ +@@ -32,6 +35,15 @@ $(dst)/%.dtb: $(obj)/%.dtb + $(dst)/%.dtbo: $(obj)/%.dtbo + $(call cmd,dtb_install) + ++$(dst)/%.dtbo: $(obj)/%.dtbo ++ $(call cmd,dtb_install) ++ ++$(dst)/%.scr: $(obj)/%.scr ++ $(call cmd,dtb_install) ++ ++$(dst)/README.meson-overlays: $(src)/README.meson-overlays ++ $(call cmd,dtb_install) ++ + PHONY += $(subdirs) + $(subdirs): + $(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@) +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index d1425778664b..a28448cebd7c 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -311,6 +311,9 @@ quiet_cmd_gzip = GZIP $@ + DTC ?= $(objtree)/scripts/dtc/dtc + DTC_FLAGS += -Wno-interrupt_provider + ++# Overlay support ++DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg ++ + # Disable noisy checks by default + ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) + DTC_FLAGS += -Wno-unit_address_vs_reg \ +@@ -371,7 +374,7 @@ DT_BINDING_DIR := Documentation/devicetree/bindings + DT_TMP_SCHEMA := $(objtree)/$(DT_BINDING_DIR)/processed-schema.json + + quiet_cmd_dtb_check = CHECK $@ +- cmd_dtb_check = $(DT_CHECKER) $(DT_CHECKER_FLAGS) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) $@ || true ++ cmd_dtb_check = $(DT_CHECKER) $(DT_CHECKER_FLAGS) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) $@ || true + endif + + define rule_dtc +@@ -385,6 +388,23 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE + $(call if_changed_dep,dtc) + ++quiet_cmd_dtco = DTCO $@ ++cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \ ++ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ ++ $(DTC) -O dtb -o $@ -b 0 \ ++ -i $(dir $<) $(DTC_FLAGS) \ ++ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ ++ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ++ ++$(obj)/%.dtbo: $(src)/%.dts FORCE ++ $(call if_changed_dep,dtco) ++ ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) ++ + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + + # Bzip2 diff --git a/patch/kernel/archive/meson64-5.19/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch b/patch/kernel/archive/meson64-5.19/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch new file mode 100644 index 000000000..50127dd15 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch @@ -0,0 +1,29 @@ +From 192ff185a6f85f2519cc4b97aa015a836f5a8fbb Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 9 Jul 2018 21:25:15 +0200 +Subject: [PATCH 10/84] TEMP: drm: dw-hdmi: call hdmi_set_cts_n after clock is + enabled + +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 3e1be9894ed1..733c3dec04de 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -781,6 +781,11 @@ static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) + else + hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; + hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); ++ ++ if (enable) { ++ hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); ++ hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); ++ } + } + + static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi) +-- +2.7.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-drm-panfrost-fix-reference-leak.patch b/patch/kernel/archive/meson64-5.19/general-drm-panfrost-fix-reference-leak.patch new file mode 100644 index 000000000..56295b584 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-drm-panfrost-fix-reference-leak.patch @@ -0,0 +1,39 @@ +From 0eb45601fe5d6b3aa9eb7038bb51df6b5fb9f860 Mon Sep 17 00:00:00 2001 +From: Qinglang Miao +Date: Sat, 28 Nov 2020 16:10:04 +0000 +Subject: [PATCH 08/58] FROMLIST(v1): drm/panfrost: fix reference leak in + panfrost_job_hw_submit + +pm_runtime_get_sync will increment pm usage counter even it +failed. Forgetting to putting operation will result in a +reference leak here. + +A new function pm_runtime_resume_and_get is introduced in +[0] to keep usage counter balanced. So We fix the reference +leak by replacing it with new funtion. + +[0] dd8088d5a896 ("PM: runtime: Add pm_runtime_resume_and_get to deal with usage counter") + +Fixes: f3ba91228e8e ("drm/panfrost: Add initial panfrost driver") +Reported-by: Hulk Robot +Signed-off-by: Qinglang Miao +--- + drivers/gpu/drm/panfrost/panfrost_job.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c +index 04e6f6f9b742..d6d5c15184f9 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_job.c ++++ b/drivers/gpu/drm/panfrost/panfrost_job.c +@@ -157,7 +157,7 @@ static void panfrost_job_hw_submit(struct panfrost_job *job, int js) + + panfrost_devfreq_record_busy(&pfdev->pfdevfreq); + +- ret = pm_runtime_get_sync(pfdev->dev); ++ ret = pm_runtime_resume_and_get(pfdev->dev); + if (ret < 0) + return; + +-- +2.25.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-fix-Kodi-sysinfo-CPU-information.patch b/patch/kernel/archive/meson64-5.19/general-fix-Kodi-sysinfo-CPU-information.patch new file mode 100644 index 000000000..bdb118825 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-fix-Kodi-sysinfo-CPU-information.patch @@ -0,0 +1,31 @@ +From 5c9793b46115c2fd774678de7ff5efd7d6ae8d72 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Sat, 13 Apr 2019 05:45:18 +0000 +Subject: [PATCH 03/90] HACK: arm64: fix Kodi sysinfo CPU information + +This allows the CPU information to show in the Kodi sysinfo screen, e.g. + +"ARMv8 Processor rev 4 (v81)" on Amlogic devices + +Signed-off-by: Christian Hewitt +--- + arch/arm64/kernel/cpuinfo.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c +index 591c18a889a5..fdd91a00a285 100644 +--- a/arch/arm64/kernel/cpuinfo.c ++++ b/arch/arm64/kernel/cpuinfo.c +@@ -151,8 +151,7 @@ static int c_show(struct seq_file *m, void *v) + * "processor". Give glibc what it expects. + */ + seq_printf(m, "processor\t: %d\n", i); +- if (compat) +- seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", ++ seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", + MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); + + seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-gpu-drm-add-new-display-resolution-2560x1440.patch b/patch/kernel/archive/meson64-5.19/general-gpu-drm-add-new-display-resolution-2560x1440.patch new file mode 100644 index 000000000..4dadf47dc --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-gpu-drm-add-new-display-resolution-2560x1440.patch @@ -0,0 +1,76 @@ +From 9175674ca107a9090936d7373927567f41d1ae7e Mon Sep 17 00:00:00 2001 +From: Dongjin Kim +Date: Thu, 10 Sep 2020 11:01:33 +0900 +Subject: [PATCH] ODROID-COMMON: gpu/drm: add new display resolution 2560x1440 + +Signed-off-by: Joy Cho +Signed-off-by: Dongjin Kim +--- + drivers/gpu/drm/meson/meson_vclk.c | 18 ++++++++++++++++++ + drivers/gpu/drm/meson/meson_venc.c | 5 +++-- + 2 files changed, 21 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c +index 2a82119eb58e..eb4c251d79b7 100644 +--- a/drivers/gpu/drm/meson/meson_vclk.c ++++ b/drivers/gpu/drm/meson/meson_vclk.c +@@ -357,6 +357,8 @@ enum { + MESON_VCLK_HDMI_594000, + /* 2970 /1 /1 /1 /5 /1 => /1 /2 */ + MESON_VCLK_HDMI_594000_YUV420, ++/* 4830 /2 /1 /2 /5 /1 => /1 /1 */ ++ MESON_VCLK_HDMI_241500, + }; + + struct meson_vclk_params { +@@ -467,6 +469,18 @@ struct meson_vclk_params { + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 1, + }, ++ [MESON_VCLK_HDMI_241500] = { ++ .pll_freq = 4830000, ++ .phy_freq = 2415000, ++ .venc_freq = 241500, ++ .vclk_freq = 241500, ++ .pixel_freq = 241500, ++ .pll_od1 = 2, ++ .pll_od2 = 1, ++ .pll_od3 = 2, ++ .vid_pll_div = VID_PLL_DIV_5, ++ .vclk_div = 1, ++ }, + { /* sentinel */ }, + }; + +@@ -873,6 +887,10 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, + m = 0xf7; + frac = vic_alternate_clock ? 0x8148 : 0x10000; + break; ++ case 4830000: ++ m = 0xc9; ++ frac = 0xd560; ++ break; + } + + meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3); +diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c +index 3c55ed003359..559ab3b5e212 100644 +--- a/drivers/gpu/drm/meson/meson_venc.c ++++ b/drivers/gpu/drm/meson/meson_venc.c +@@ -866,10 +866,11 @@ meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode) + DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)) + return MODE_BAD; + +- if (mode->hdisplay < 640 || mode->hdisplay > 1920) ++ /* support higher resolution than 1920x1080 */ ++ if (mode->hdisplay < 640 || mode->hdisplay > 2560) + return MODE_BAD_HVALUE; + +- if (mode->vdisplay < 480 || mode->vdisplay > 1200) ++ if (mode->vdisplay < 480 || mode->vdisplay > 1600) + return MODE_BAD_VVALUE; + + return MODE_OK; +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-hdmi-codec-reorder-channel-allocation-list.patch b/patch/kernel/archive/meson64-5.19/general-hdmi-codec-reorder-channel-allocation-list.patch new file mode 100644 index 000000000..a48b290d4 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-hdmi-codec-reorder-channel-allocation-list.patch @@ -0,0 +1,202 @@ +From dd29d3d05631c4afdab56fb696424565a4afefba Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 23 Dec 2018 02:24:38 +0100 +Subject: [PATCH 53/90] WIP: ASoC: hdmi-codec: reorder channel allocation list + +Wrong channel allocation is selected by hdmi_codec_get_ch_alloc_table_idx(). + +E.g when ELD reports FL|FR|LFE|FC|RL|RR or FL|FR|LFE|FC|RL|RR|RC|RLC|RRC + +ca_id 0x01 with speaker mask FL|FR|LFE gets selected instead of +ca_id 0x03 with speaker mask FL|FR|LFE|FC for 4 channels + +and + +ca_id 0x04 with speaker mask FL|FR|RC gets selected instead of +ca_id 0x0b with speaker mask FL|FR|LFE|FC|RL|RR for 6 channels + +Fix this by reorder the channel allocation list with +most specific speaker mask at the top. + +Signed-off-by: Jonas Karlman +--- + sound/soc/codecs/hdmi-codec.c | 140 +++++++++++++++++++--------------- + 1 file changed, 77 insertions(+), 63 deletions(-) + +diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c +index b07607a9ecea..a12015471ea2 100644 +--- a/sound/soc/codecs/hdmi-codec.c ++++ b/sound/soc/codecs/hdmi-codec.c +@@ -188,84 +188,97 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { + /* + * hdmi_codec_channel_alloc: speaker configuration available for CEA + * +- * This is an ordered list that must match with hdmi_codec_8ch_chmaps struct ++ * This is an ordered list where ca_id must exist in hdmi_codec_8ch_chmaps + * The preceding ones have better chances to be selected by + * hdmi_codec_get_ch_alloc_table_idx(). + */ + static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { + { .ca_id = 0x00, .n_ch = 2, +- .mask = FL | FR}, +- /* 2.1 */ +- { .ca_id = 0x01, .n_ch = 4, +- .mask = FL | FR | LFE}, +- /* Dolby Surround */ ++ .mask = FL | FR }, ++ { .ca_id = 0x03, .n_ch = 4, ++ .mask = FL | FR | LFE | FC }, + { .ca_id = 0x02, .n_ch = 4, + .mask = FL | FR | FC }, +- /* surround51 */ ++ { .ca_id = 0x01, .n_ch = 4, ++ .mask = FL | FR | LFE }, + { .ca_id = 0x0b, .n_ch = 6, +- .mask = FL | FR | LFE | FC | RL | RR}, +- /* surround40 */ +- { .ca_id = 0x08, .n_ch = 6, +- .mask = FL | FR | RL | RR }, +- /* surround41 */ +- { .ca_id = 0x09, .n_ch = 6, +- .mask = FL | FR | LFE | RL | RR }, +- /* surround50 */ ++ .mask = FL | FR | LFE | FC | RL | RR }, + { .ca_id = 0x0a, .n_ch = 6, + .mask = FL | FR | FC | RL | RR }, +- /* 6.1 */ +- { .ca_id = 0x0f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | RC }, +- /* surround71 */ ++ { .ca_id = 0x09, .n_ch = 6, ++ .mask = FL | FR | LFE | RL | RR }, ++ { .ca_id = 0x08, .n_ch = 6, ++ .mask = FL | FR | RL | RR }, ++ { .ca_id = 0x07, .n_ch = 6, ++ .mask = FL | FR | LFE | FC | RC }, ++ { .ca_id = 0x06, .n_ch = 6, ++ .mask = FL | FR | FC | RC }, ++ { .ca_id = 0x05, .n_ch = 6, ++ .mask = FL | FR | LFE | RC }, ++ { .ca_id = 0x04, .n_ch = 6, ++ .mask = FL | FR | RC }, + { .ca_id = 0x13, .n_ch = 8, + .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, +- /* others */ +- { .ca_id = 0x03, .n_ch = 8, +- .mask = FL | FR | LFE | FC }, +- { .ca_id = 0x04, .n_ch = 8, +- .mask = FL | FR | RC}, +- { .ca_id = 0x05, .n_ch = 8, +- .mask = FL | FR | LFE | RC }, +- { .ca_id = 0x06, .n_ch = 8, +- .mask = FL | FR | FC | RC }, +- { .ca_id = 0x07, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RC }, +- { .ca_id = 0x0c, .n_ch = 8, +- .mask = FL | FR | RC | RL | RR }, +- { .ca_id = 0x0d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RC }, +- { .ca_id = 0x0e, .n_ch = 8, +- .mask = FL | FR | FC | RL | RR | RC }, +- { .ca_id = 0x10, .n_ch = 8, +- .mask = FL | FR | RL | RR | RLC | RRC }, +- { .ca_id = 0x11, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, + { .ca_id = 0x12, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | RLC | RRC }, +- { .ca_id = 0x14, .n_ch = 8, +- .mask = FL | FR | FLC | FRC }, +- { .ca_id = 0x15, .n_ch = 8, +- .mask = FL | FR | LFE | FLC | FRC }, +- { .ca_id = 0x16, .n_ch = 8, +- .mask = FL | FR | FC | FLC | FRC }, +- { .ca_id = 0x17, .n_ch = 8, +- .mask = FL | FR | LFE | FC | FLC | FRC }, +- { .ca_id = 0x18, .n_ch = 8, +- .mask = FL | FR | RC | FLC | FRC }, +- { .ca_id = 0x19, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FLC | FRC }, +- { .ca_id = 0x1a, .n_ch = 8, +- .mask = FL | FR | RC | FC | FLC | FRC }, +- { .ca_id = 0x1b, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FC | FLC | FRC }, +- { .ca_id = 0x1c, .n_ch = 8, +- .mask = FL | FR | RL | RR | FLC | FRC }, +- { .ca_id = 0x1d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | FLC | FRC }, + { .ca_id = 0x1e, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | FLC | FRC }, +- { .ca_id = 0x1f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, ++ { .ca_id = 0x11, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | FLC | FRC }, ++ { .ca_id = 0x10, .n_ch = 8, ++ .mask = FL | FR | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1c, .n_ch = 8, ++ .mask = FL | FR | RL | RR | FLC | FRC }, ++ { .ca_id = 0x0f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | RC }, ++ { .ca_id = 0x1b, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0e, .n_ch = 8, ++ .mask = FL | FR | FC | RL | RR | RC }, ++ { .ca_id = 0x1a, .n_ch = 8, ++ .mask = FL | FR | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RC }, ++ { .ca_id = 0x19, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FLC | FRC }, ++ { .ca_id = 0x0c, .n_ch = 8, ++ .mask = FL | FR | RC | RL | RR }, ++ { .ca_id = 0x18, .n_ch = 8, ++ .mask = FL | FR | RC | FLC | FRC }, ++ { .ca_id = 0x17, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | FLC | FRC }, ++ { .ca_id = 0x16, .n_ch = 8, ++ .mask = FL | FR | FC | FLC | FRC }, ++ { .ca_id = 0x15, .n_ch = 8, ++ .mask = FL | FR | LFE | FLC | FRC }, ++ { .ca_id = 0x14, .n_ch = 8, ++ .mask = FL | FR | FLC | FRC }, ++ { .ca_id = 0x0b, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR }, ++ { .ca_id = 0x0a, .n_ch = 8, ++ .mask = FL | FR | FC | RL | RR }, ++ { .ca_id = 0x09, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR }, ++ { .ca_id = 0x08, .n_ch = 8, ++ .mask = FL | FR | RL | RR }, ++ { .ca_id = 0x07, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RC }, ++ { .ca_id = 0x06, .n_ch = 8, ++ .mask = FL | FR | FC | RC }, ++ { .ca_id = 0x05, .n_ch = 8, ++ .mask = FL | FR | LFE | RC }, ++ { .ca_id = 0x04, .n_ch = 8, ++ .mask = FL | FR | RC }, ++ { .ca_id = 0x03, .n_ch = 8, ++ .mask = FL | FR | LFE | FC }, ++ { .ca_id = 0x02, .n_ch = 8, ++ .mask = FL | FR | FC }, ++ { .ca_id = 0x01, .n_ch = 8, ++ .mask = FL | FR | LFE }, + }; + + struct hdmi_codec_priv { +@@ -374,7 +387,8 @@ static int hdmi_codec_chmap_ctl_get(struct snd_kcontrol *kcontrol, + struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); + struct hdmi_codec_priv *hcp = info->private_data; + +- map = info->chmap[hcp->chmap_idx].map; ++ if (hcp->chmap_idx != HDMI_CODEC_CHMAP_IDX_UNKNOWN) ++ map = info->chmap[hcp->chmap_idx].map; + + for (i = 0; i < info->max_channels; i++) { + if (hcp->chmap_idx == HDMI_CODEC_CHMAP_IDX_UNKNOWN) +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-hwmon-pwm-fan-fix-to-add-pwm1_enable-t.patch b/patch/kernel/archive/meson64-5.19/general-hwmon-pwm-fan-fix-to-add-pwm1_enable-t.patch new file mode 100644 index 000000000..d7ee98eab --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-hwmon-pwm-fan-fix-to-add-pwm1_enable-t.patch @@ -0,0 +1,141 @@ +From 9f34f631a394fb13fbe5c4fca5e9ab3792d4c7d6 Mon Sep 17 00:00:00 2001 +From: Dongjin Kim +Date: Wed, 30 Jun 2021 11:38:33 +0900 +Subject: [PATCH] ODROID-COMMON: hwmon: (pwm-fan): fix to add 'pwm1_enable' to + set PWM fan mode + +Change-Id: If0562f497703b8660206dad80d7933902bbf53e4 +--- + drivers/hwmon/pwm-fan.c | 67 +++++++++++++++++++++++++++++++++++++---- + 1 file changed, 61 insertions(+), 6 deletions(-) + +diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c +index f12b9a28a232..383a24316985 100644 +--- a/drivers/hwmon/pwm-fan.c ++++ b/drivers/hwmon/pwm-fan.c +@@ -8,6 +8,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -44,6 +45,7 @@ struct pwm_fan_ctx { + unsigned int pwm_fan_max_state; + unsigned int *pwm_fan_cooling_levels; + struct thermal_cooling_device *cdev; ++ int enable; + + struct hwmon_chip_info info; + struct hwmon_channel_info fan_channel; +@@ -99,6 +101,10 @@ static int __set_pwm(struct pwm_fan_ctx *ctx, unsigned long pwm) + struct pwm_state *state = &ctx->pwm_state; + + mutex_lock(&ctx->lock); ++ ++ if (!ctx->enable) ++ pwm = MAX_PWM; ++ + if (ctx->pwm_value == pwm) + goto exit_set_pwm_err; + +@@ -183,6 +189,51 @@ static const struct hwmon_ops pwm_fan_hwmon_ops = { + .write = pwm_fan_write, + }; + ++static ssize_t enable_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct pwm_fan_ctx *ctx = dev_get_drvdata(dev); ++ int err; ++ unsigned long val; ++ ++ err = kstrtoul(buf, 10, &val); ++ if (err) ++ return err; ++ ++ mutex_lock(&ctx->lock); ++ ctx->enable = val; ++ mutex_unlock(&ctx->lock); ++ ++ err = __set_pwm(ctx, ctx->pwm_fan_cooling_levels[ctx->pwm_fan_state]); ++ ++ return err ? err : count; ++} ++ ++static ssize_t enable_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct pwm_fan_ctx *ctx = dev_get_drvdata(dev); ++ ++ return sprintf(buf, "%u\n", ctx->enable); ++} ++ ++static SENSOR_DEVICE_ATTR_RW(pwm1_enable, enable, 0); ++ ++static struct attribute *pwm_fan_attrs[] = { ++ &sensor_dev_attr_pwm1_enable.dev_attr.attr, ++ NULL, ++}; ++ ++static const struct attribute_group pwm_fan_group = { ++ .attrs = pwm_fan_attrs, ++}; ++ ++static const struct attribute_group *pwm_fan_groups[] = { ++ &pwm_fan_group, ++ NULL, ++}; ++ + /* thermal cooling device callbacks */ + static int pwm_fan_get_max_state(struct thermal_cooling_device *cdev, + unsigned long *state) +@@ -214,7 +265,7 @@ static int + pwm_fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state) + { + struct pwm_fan_ctx *ctx = cdev->devdata; +- int ret; ++ int ret = 0; + + if (!ctx || (state > ctx->pwm_fan_max_state)) + return -EINVAL; +@@ -222,10 +273,12 @@ pwm_fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state) + if (state == ctx->pwm_fan_state) + return 0; + +- ret = __set_pwm(ctx, ctx->pwm_fan_cooling_levels[state]); +- if (ret) { +- dev_err(&cdev->device, "Cannot set pwm!\n"); +- return ret; ++ if (ctx->enable >= 2) { ++ ret = __set_pwm(ctx, ctx->pwm_fan_cooling_levels[state]); ++ if (ret) { ++ dev_err(&cdev->device, "Cannot set pwm!\n"); ++ return ret; ++ } + } + + ctx->pwm_fan_state = state; +@@ -316,6 +369,8 @@ static int pwm_fan_probe(struct platform_device *pdev) + if (IS_ERR(ctx->pwm)) + return dev_err_probe(dev, PTR_ERR(ctx->pwm), "Could not get PWM\n"); + ++ ctx->enable = 2; ++ + platform_set_drvdata(pdev, ctx); + + ctx->reg_en = devm_regulator_get_optional(dev, "fan"); +@@ -434,7 +489,7 @@ static int pwm_fan_probe(struct platform_device *pdev) + ctx->info.info = channels; + + hwmon = devm_hwmon_device_register_with_info(dev, "pwmfan", +- ctx, &ctx->info, NULL); ++ ctx, &ctx->info, pwm_fan_groups); + if (IS_ERR(hwmon)) { + dev_err(dev, "Failed to register hwmon device\n"); + return PTR_ERR(hwmon); +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-increase-cma-pool-896MB.patch b/patch/kernel/archive/meson64-5.19/general-increase-cma-pool-896MB.patch new file mode 100644 index 000000000..fd0911c4f --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-increase-cma-pool-896MB.patch @@ -0,0 +1,56 @@ +From 4b6096bb3fd5bdc139a45e022e4a2380ea919dea Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Sat, 13 Apr 2019 05:41:51 +0000 +Subject: [PATCH 01/90] HACK: set meson-gx cma pool to 896MB + +This change sets the CMA pool to a larger 896MB! value for vdec use + +Signed-off-by: Christian Hewitt +--- + arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +index aa14ea017a61..99b8916e0c5d 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +@@ -58,7 +58,7 @@ secmon_reserved_bl32: secmon@5300000 { + linux,cma { + compatible = "shared-dma-pool"; + reusable; +- size = <0x0 0x10000000>; ++ size = <0x0 0x38000000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; +-- +2.35.1 + +From 18586e3d94827f63903c4cd596a0a06134261c00 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Wed, 14 Aug 2019 19:58:14 +0000 +Subject: [PATCH 02/90] HACK: set meson-g12 cma pool to 896MB + +This change sets the CMA pool to a larger 896MB! value for vdec use + +Signed-off-by: Christian Hewitt +--- + arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +index f84d4b489e0b..04da23119ff1 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +@@ -116,7 +116,7 @@ secmon_reserved_bl32: secmon@5300000 { + linux,cma { + compatible = "shared-dma-pool"; + reusable; +- size = <0x0 0x10000000>; ++ size = <0x0 0x38000000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-input-touchscreen-Add-D-WAV-Multitouch.patch b/patch/kernel/archive/meson64-5.19/general-input-touchscreen-Add-D-WAV-Multitouch.patch new file mode 100644 index 000000000..aab3dbd27 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-input-touchscreen-Add-D-WAV-Multitouch.patch @@ -0,0 +1,637 @@ +From b615e1a2ac4cc58734db101cd209aed0a11d2343 Mon Sep 17 00:00:00 2001 +From: Hyeonki Hong +Date: Thu, 5 Mar 2020 19:01:43 +0900 +Subject: [PATCH] ODROID-COMMON: input/touchscreen: Add D-WAV Multitouch + driver. + +Change-Id: Ia1c8c29d3f69c6ba5d630279c4cc98119b68ab71 +--- + drivers/hid/hid-ids.h | 6 + + drivers/hid/hid-quirks.c | 3 + + drivers/input/touchscreen/Kconfig | 10 + + drivers/input/touchscreen/Makefile | 1 + + drivers/input/touchscreen/dwav-usb-mt.c | 554 ++++++++++++++++++++++++ + 5 files changed, 574 insertions(+) + create mode 100644 drivers/input/touchscreen/dwav-usb-mt.c + +diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h +index a5a5a64c7abc..39c719033cd0 100644 +--- a/drivers/hid/hid-ids.h ++++ b/drivers/hid/hid-ids.h +@@ -1372,4 +1372,10 @@ + #define USB_VENDOR_ID_SIGNOTEC 0x2133 + #define USB_DEVICE_ID_SIGNOTEC_VIEWSONIC_PD1011 0x0018 + ++#define USB_DEVICE_ID_DWAV_MULTITOUCH 0x0005 ++ ++#define USB_VENDOR_ID_ODROID 0x16b4 ++#define USB_DEVICE_ID_VU5 0x0704 ++#define USB_DEVICE_ID_VU7PLUS 0x0705 ++ + #endif +diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c +index ee7e504e7279..4d876faea391 100644 +--- a/drivers/hid/hid-quirks.c ++++ b/drivers/hid/hid-quirks.c +@@ -863,6 +863,9 @@ static const struct hid_device_id hid_ignore_list[] = { + { HID_USB_DEVICE(USB_VENDOR_ID_SYNAPTICS, USB_DEVICE_ID_SYNAPTICS_DPAD) }, + #endif + { HID_USB_DEVICE(USB_VENDOR_ID_YEALINK, USB_DEVICE_ID_YEALINK_P1K_P4K_B2K) }, ++ ++ { HID_USB_DEVICE(USB_VENDOR_ID_ODROID, USB_DEVICE_ID_VU5) }, ++ { HID_USB_DEVICE(USB_VENDOR_ID_ODROID, USB_DEVICE_ID_VU7PLUS) }, + { } + }; + +diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig +index 2f6adfb7b938..cec65479dc79 100644 +--- a/drivers/input/touchscreen/Kconfig ++++ b/drivers/input/touchscreen/Kconfig +@@ -1367,4 +1367,14 @@ config TOUCHSCREEN_ZINITIX + To compile this driver as a module, choose M here: the + module will be called zinitix. + ++config TOUCHSCREEN_DWAV_USB_MT ++ tristate "D-WAV Scientific USB MultiTouch" ++ depends on USB_ARCH_HAS_HCD ++ select USB ++ help ++ Say Y here if you have a D-WAV Scientific USB(HID) based MultiTouch ++ controller. ++ ++ module will be called dwav-usb-mt. ++ + endif +diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile +index 39a8127cf6a5..f8bede5caafd 100644 +--- a/drivers/input/touchscreen/Makefile ++++ b/drivers/input/touchscreen/Makefile +@@ -115,3 +115,4 @@ obj-$(CONFIG_TOUCHSCREEN_ROHM_BU21023) += rohm_bu21023.o + obj-$(CONFIG_TOUCHSCREEN_RASPBERRYPI_FW) += raspberrypi-ts.o + obj-$(CONFIG_TOUCHSCREEN_IQS5XX) += iqs5xx.o + obj-$(CONFIG_TOUCHSCREEN_ZINITIX) += zinitix.o ++obj-$(CONFIG_TOUCHSCREEN_DWAV_USB_MT) += dwav-usb-mt.o +diff --git a/drivers/input/touchscreen/dwav-usb-mt.c b/drivers/input/touchscreen/dwav-usb-mt.c +new file mode 100644 +index 000000000000..7ec8b6dd15fd +--- /dev/null ++++ b/drivers/input/touchscreen/dwav-usb-mt.c +@@ -0,0 +1,554 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * D-WAV Scientific USB(HID) MultiTouch Screen Driver(Based on usbtouchscreen.c) ++ * ++ * Copyright (C) Hardkernel, 2015 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define USB_VENDOR_ID_DWAV 0x0eef /* 800 x 480, 7" DWAV touch */ ++#define USB_DEVICE_ID_VU7 0x0005 ++ ++#define USB_VENDOR_ID_ODROID 0x16b4 ++#define USB_DEVICE_ID_VU5 0x0704 ++#define USB_DEVICE_ID_VU7PLUS 0x0705 ++ ++enum { ++ ODROID_VU7 = 0, /* 800 x 480, 7" Touch */ ++ ODROID_VU5, /* 800 x 480, 5" Touch */ ++ ODROID_VU7PLUS, /* 1024 x 600, 7" Touch */ ++}; ++ ++struct usbtouch_device_info { ++ char name[64]; ++ int max_x; ++ int max_y; ++ int max_press; ++ int max_finger; ++}; ++ ++const struct usbtouch_device_info DEV_INFO[] = { ++ [ODROID_VU7] = { ++ .name = "ODROID VU7 MultiTouch(800x480)", ++ .max_x = 800, ++ .max_y = 480, ++ .max_press = 255, ++ .max_finger = 5, ++ }, ++ [ODROID_VU5] = { ++ .name = "ODROID VU5 MultiTouch(800x480)", ++ .max_x = 800, ++ .max_y = 480, ++ .max_press = 255, ++ .max_finger = 5, ++ }, ++ [ODROID_VU7PLUS] = { ++ .name = "ODROID VU7 Plus MultiTouch(1024x600)", ++ .max_x = 1024, ++ .max_y = 600, ++ .max_press = 255, ++ .max_finger = 5, ++ }, ++}; ++ ++static const struct usb_device_id dwav_usb_mt_devices[] = { ++ {USB_DEVICE(USB_VENDOR_ID_DWAV, USB_DEVICE_ID_VU7), ++ .driver_info = ODROID_VU7}, ++ {USB_DEVICE(USB_VENDOR_ID_ODROID, USB_DEVICE_ID_VU5), ++ .driver_info = ODROID_VU5}, ++ {USB_DEVICE(USB_VENDOR_ID_ODROID, USB_DEVICE_ID_VU7PLUS), ++ .driver_info = ODROID_VU7PLUS}, ++ {} ++}; ++ ++struct dwav_raw { /* Total 25 bytes */ ++ unsigned char header; /* frame header 0xAA*/ ++ unsigned char press; ++ /* Touch flag (1:valid touch data, 0:touch finished) */ ++ unsigned short x1; /* 1st x */ ++ unsigned short y1; /* 1st y */ ++ unsigned char end; ++ /* 1st touch finish flags 0xBB, RPI only uses the first 7 bytes */ ++ unsigned char ids; /* touch ID(bit field) */ ++ unsigned short y2; ++ unsigned short x2; ++ unsigned short y3; ++ unsigned short x3; ++ unsigned short y4; ++ unsigned short x4; ++ unsigned short y5; ++ unsigned short x5; ++ unsigned char tail; /* frame end 0xCC */ ++}; ++ ++#define TS_EVENT_UNKNOWN 0x00 ++#define TS_EVENT_PRESS 0x01 ++#define TS_EVENT_RELEASE 0x02 ++ ++struct finger_t { ++ unsigned int status; /* ts event type */ ++ unsigned int x; /* ts data x */ ++ unsigned int y; /* ts data y */ ++} __packed; ++ ++struct dwav_usb_mt { ++ char name[128], phys[64]; ++ ++ int dev_id; ++ /* for URB Data DMA */ ++ dma_addr_t data_dma; ++ unsigned char *data; ++ int data_size; ++ ++ struct urb *irq; ++ struct usb_interface *interface; ++ struct input_dev *input; ++ ++ struct finger_t *finger; ++}; ++ ++static void dwav_usb_mt_report(struct dwav_usb_mt *dwav_usb_mt) ++{ ++ int id, max_x, max_y, max_press, max_finger; ++ ++ max_x = DEV_INFO[dwav_usb_mt->dev_id].max_x; ++ max_y = DEV_INFO[dwav_usb_mt->dev_id].max_y; ++ max_press = DEV_INFO[dwav_usb_mt->dev_id].max_press; ++ max_finger = DEV_INFO[dwav_usb_mt->dev_id].max_finger; ++ ++ for (id = 0; id < max_finger; id++) { ++ ++ if (dwav_usb_mt->finger[id].status == TS_EVENT_UNKNOWN) ++ continue; ++ ++ if (dwav_usb_mt->finger[id].x >= max_x || ++ dwav_usb_mt->finger[id].y >= max_y) ++ continue; ++ ++ input_mt_slot(dwav_usb_mt->input, id); ++ ++ if (dwav_usb_mt->finger[id].status != TS_EVENT_RELEASE) { ++ input_mt_report_slot_state(dwav_usb_mt->input, ++ MT_TOOL_FINGER, true); ++ input_report_abs(dwav_usb_mt->input, ++ ABS_MT_POSITION_X, ++ dwav_usb_mt->finger[id].x); ++ input_report_abs(dwav_usb_mt->input, ++ ABS_MT_POSITION_Y, ++ dwav_usb_mt->finger[id].y); ++ input_report_abs(dwav_usb_mt->input, ++ ABS_MT_PRESSURE, ++ max_press); ++ } else { ++ input_mt_report_slot_state(dwav_usb_mt->input, ++ MT_TOOL_FINGER, false); ++ dwav_usb_mt->finger[id].status = TS_EVENT_UNKNOWN; ++ } ++ input_mt_report_pointer_emulation(dwav_usb_mt->input, true); ++ input_sync(dwav_usb_mt->input); ++ } ++} ++ ++static void dwav_usb_mt_process(struct dwav_usb_mt *dwav_usb_mt, ++ unsigned char *pkt, int len) ++{ ++ struct dwav_raw *dwav_raw = (struct dwav_raw *)pkt; ++ unsigned char bit_mask, cnt; ++ ++ for (cnt = 0, bit_mask = 0x01; ++ cnt < DEV_INFO[dwav_usb_mt->dev_id].max_finger; ++ cnt++, bit_mask <<= 1) { ++ if ((dwav_raw->ids & bit_mask) && dwav_raw->press) { ++ dwav_usb_mt->finger[cnt].status = TS_EVENT_PRESS; ++ switch (cnt) { ++ case 0: ++ dwav_usb_mt->finger[cnt].x ++ = cpu_to_be16(dwav_raw->x1); ++ dwav_usb_mt->finger[cnt].y ++ = cpu_to_be16(dwav_raw->y1); ++ break; ++ case 1: ++ dwav_usb_mt->finger[cnt].x ++ = cpu_to_be16(dwav_raw->x2); ++ dwav_usb_mt->finger[cnt].y ++ = cpu_to_be16(dwav_raw->y2); ++ break; ++ case 2: ++ dwav_usb_mt->finger[cnt].x ++ = cpu_to_be16(dwav_raw->x3); ++ dwav_usb_mt->finger[cnt].y ++ = cpu_to_be16(dwav_raw->y3); ++ break; ++ case 3: ++ dwav_usb_mt->finger[cnt].x ++ = cpu_to_be16(dwav_raw->x4); ++ dwav_usb_mt->finger[cnt].y ++ = cpu_to_be16(dwav_raw->y4); ++ break; ++ case 4: ++ dwav_usb_mt->finger[cnt].x ++ = cpu_to_be16(dwav_raw->x5); ++ dwav_usb_mt->finger[cnt].y ++ = cpu_to_be16(dwav_raw->y5); ++ break; ++ default: ++ break; ++ } ++ } else { ++ if (dwav_usb_mt->finger[cnt].status == TS_EVENT_PRESS) ++ dwav_usb_mt->finger[cnt].status ++ = TS_EVENT_RELEASE; ++ else ++ dwav_usb_mt->finger[cnt].status ++ = TS_EVENT_UNKNOWN; ++ } ++ } ++ dwav_usb_mt_report(dwav_usb_mt); ++} ++ ++static void dwav_usb_mt_irq(struct urb *urb) ++{ ++ struct dwav_usb_mt *dwav_usb_mt = urb->context; ++ struct device *dev = &dwav_usb_mt->interface->dev; ++ int retval; ++ ++ switch (urb->status) { ++ case 0: ++ /* success */ ++ break; ++ case -ETIME: ++ /* this urb is timing out */ ++ dev_dbg(dev, "%s - urb timed out - was the device unplugged?\n", ++ __func__); ++ return; ++ case -ECONNRESET: ++ case -ENOENT: ++ case -ESHUTDOWN: ++ case -EPIPE: ++ /* this urb is terminated, clean up */ ++ dev_dbg(dev, "%s - urb shutting down with status: %d\n", ++ __func__, urb->status); ++ return; ++ default: ++ dev_dbg(dev, "%s - nonzero urb status received: %d\n", ++ __func__, urb->status); ++ goto exit; ++ } ++ ++ dwav_usb_mt_process(dwav_usb_mt, dwav_usb_mt->data, urb->actual_length); ++ ++exit: ++ usb_mark_last_busy(interface_to_usbdev(dwav_usb_mt->interface)); ++ retval = usb_submit_urb(urb, GFP_ATOMIC); ++ if (retval) { ++ dev_err(dev, "%s - usb_submit_urb failed with result: %d\n", ++ __func__, retval); ++ } ++} ++ ++static int dwav_usb_mt_open(struct input_dev *input) ++{ ++ struct dwav_usb_mt *dwav_usb_mt = input_get_drvdata(input); ++ int r; ++ ++ dwav_usb_mt->irq->dev = interface_to_usbdev(dwav_usb_mt->interface); ++ ++ r = usb_autopm_get_interface(dwav_usb_mt->interface) ? -EIO : 0; ++ if (r < 0) ++ goto out; ++ ++ if (usb_submit_urb(dwav_usb_mt->irq, GFP_KERNEL)) { ++ r = -EIO; ++ goto out_put; ++ } ++ ++ dwav_usb_mt->interface->needs_remote_wakeup = 1; ++out_put: ++ usb_autopm_put_interface(dwav_usb_mt->interface); ++out: ++ return r; ++} ++ ++static void dwav_usb_mt_close(struct input_dev *input) ++{ ++ struct dwav_usb_mt *dwav_usb_mt = input_get_drvdata(input); ++ int r; ++ ++ usb_kill_urb(dwav_usb_mt->irq); ++ ++ r = usb_autopm_get_interface(dwav_usb_mt->interface); ++ ++ dwav_usb_mt->interface->needs_remote_wakeup = 0; ++ if (!r) ++ usb_autopm_put_interface(dwav_usb_mt->interface); ++} ++ ++static int dwav_usb_mt_suspend(struct usb_interface *intf, pm_message_t message) ++{ ++ struct dwav_usb_mt *dwav_usb_mt = usb_get_intfdata(intf); ++ ++ usb_kill_urb(dwav_usb_mt->irq); ++ ++ return 0; ++} ++ ++static int dwav_usb_mt_resume(struct usb_interface *intf) ++{ ++ struct dwav_usb_mt *dwav_usb_mt = usb_get_intfdata(intf); ++ struct input_dev *input = dwav_usb_mt->input; ++ int result = 0; ++ ++ mutex_lock(&input->mutex); ++ if (input->users) ++ result = usb_submit_urb(dwav_usb_mt->irq, GFP_NOIO); ++ mutex_unlock(&input->mutex); ++ ++ return result; ++} ++ ++static int dwav_usb_mt_reset_resume(struct usb_interface *intf) ++{ ++ struct dwav_usb_mt *dwav_usb_mt = usb_get_intfdata(intf); ++ struct input_dev *input = dwav_usb_mt->input; ++ int err = 0; ++ ++ /* restart IO if needed */ ++ mutex_lock(&input->mutex); ++ if (input->users) ++ err = usb_submit_urb(dwav_usb_mt->irq, GFP_NOIO); ++ mutex_unlock(&input->mutex); ++ ++ return err; ++} ++ ++static void dwav_usb_mt_free_buffers(struct usb_device *udev, ++ struct dwav_usb_mt *dwav_usb_mt) ++{ ++ usb_free_coherent(udev, dwav_usb_mt->data_size, ++ dwav_usb_mt->data, dwav_usb_mt->data_dma); ++} ++ ++static struct usb_endpoint_descriptor *dwav_usb_mt_get_input_endpoint( ++ struct usb_host_interface *interface) ++{ ++ int i; ++ ++ for (i = 0; i < interface->desc.bNumEndpoints; i++) { ++ if (usb_endpoint_dir_in(&interface->endpoint[i].desc)) ++ return &interface->endpoint[i].desc; ++ } ++ ++ return NULL; ++} ++ ++static int dwav_usb_mt_init(struct dwav_usb_mt *dwav_usb_mt, void *dev) ++{ ++ int err; ++ struct input_dev *input_dev = (struct input_dev *)dev; ++ ++ input_dev->name = dwav_usb_mt->name; ++ input_dev->phys = dwav_usb_mt->phys; ++ ++ input_set_drvdata(input_dev, dwav_usb_mt); ++ ++ input_dev->open = dwav_usb_mt_open; ++ input_dev->close = dwav_usb_mt_close; ++ ++ input_dev->id.bustype = BUS_USB; ++ ++ /* single touch */ ++ input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); ++ input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); ++ ++ input_set_abs_params(input_dev, ABS_X, 0, ++ DEV_INFO[dwav_usb_mt->dev_id].max_x, 0, 0); ++ input_set_abs_params(input_dev, ABS_Y, 0, ++ DEV_INFO[dwav_usb_mt->dev_id].max_y, 0, 0); ++ ++ /* multi touch */ ++ input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0, ++ DEV_INFO[dwav_usb_mt->dev_id].max_x, 0, 0); ++ input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0, ++ DEV_INFO[dwav_usb_mt->dev_id].max_y, 0, 0); ++ input_mt_init_slots(input_dev, ++ DEV_INFO[dwav_usb_mt->dev_id].max_finger, 0); ++ ++ err = input_register_device(input_dev); ++ if (err) { ++ pr_err("%s - input_register_device failed, err: %d\n", ++ __func__, err); ++ return err; ++ } ++ ++ dwav_usb_mt->input = input_dev; ++ ++ return 0; ++} ++ ++static int dwav_usb_mt_probe(struct usb_interface *intf, ++ const struct usb_device_id *id) ++{ ++ struct dwav_usb_mt *dwav_usb_mt = NULL; ++ struct input_dev *input_dev = NULL; ++ struct usb_endpoint_descriptor *endpoint; ++ struct usb_device *udev = interface_to_usbdev(intf); ++ ++ int err = 0; ++ ++ endpoint = dwav_usb_mt_get_input_endpoint(intf->cur_altsetting); ++ if (!endpoint) ++ return -ENXIO; ++ ++ dwav_usb_mt = kzalloc(sizeof(struct dwav_usb_mt), GFP_KERNEL); ++ if (!dwav_usb_mt) ++ return -ENOMEM; ++ ++ dwav_usb_mt->dev_id = id->driver_info; ++ ++ dwav_usb_mt->finger = kzalloc(sizeof(struct finger_t) * ++ DEV_INFO[dwav_usb_mt->dev_id].max_finger, ++ GFP_KERNEL); ++ ++ if (!dwav_usb_mt->finger) ++ goto err_free_mem; ++ ++ input_dev = input_allocate_device(); ++ if (!input_dev) ++ goto err_free_mem; ++ ++ dwav_usb_mt->data_size = sizeof(struct dwav_raw); ++ dwav_usb_mt->data = usb_alloc_coherent(udev, dwav_usb_mt->data_size, ++ GFP_KERNEL, &dwav_usb_mt->data_dma); ++ if (!dwav_usb_mt->data) ++ goto err_free_mem; ++ ++ dwav_usb_mt->irq = usb_alloc_urb(0, GFP_KERNEL); ++ if (!dwav_usb_mt->irq) { ++ dev_dbg(&intf->dev, ++ "%s - usb_alloc_urb failed: usbtouch->irq\n", ++ __func__); ++ goto err_free_buffers; ++ } ++ ++ if (usb_endpoint_type(endpoint) == USB_ENDPOINT_XFER_INT) { ++ usb_fill_int_urb(dwav_usb_mt->irq, udev, ++ usb_rcvintpipe(udev, endpoint->bEndpointAddress), ++ dwav_usb_mt->data, dwav_usb_mt->data_size, ++ dwav_usb_mt_irq, dwav_usb_mt, endpoint->bInterval); ++ } else { ++ usb_fill_bulk_urb(dwav_usb_mt->irq, udev, ++ usb_rcvbulkpipe(udev, endpoint->bEndpointAddress), ++ dwav_usb_mt->data, dwav_usb_mt->data_size, ++ dwav_usb_mt_irq, dwav_usb_mt); ++ } ++ ++ dwav_usb_mt->irq->dev = udev; ++ dwav_usb_mt->irq->transfer_dma = dwav_usb_mt->data_dma; ++ dwav_usb_mt->irq->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; ++ ++ dwav_usb_mt->interface = intf; ++ ++ if (udev->manufacturer) ++ strlcpy(dwav_usb_mt->name, ++ udev->manufacturer, sizeof(dwav_usb_mt->name)); ++ ++ if (udev->product) { ++ if (udev->manufacturer) ++ strlcat(dwav_usb_mt->name, ++ " ", sizeof(dwav_usb_mt->name)); ++ ++ strlcat(dwav_usb_mt->name, ++ udev->product, sizeof(dwav_usb_mt->name)); ++ } ++ ++ if (!strlen(dwav_usb_mt->name)) { ++ snprintf(dwav_usb_mt->name, sizeof(dwav_usb_mt->name), ++ "D-WAV Scientific MultiTouch %04x:%04x", ++ le16_to_cpu(udev->descriptor.idVendor), ++ le16_to_cpu(udev->descriptor.idProduct)); ++ } ++ ++ usb_make_path(udev, dwav_usb_mt->phys, sizeof(dwav_usb_mt->phys)); ++ strlcat(dwav_usb_mt->phys, "/input0", sizeof(dwav_usb_mt->phys)); ++ ++ usb_to_input_id(udev, &input_dev->id); ++ ++ input_dev->dev.parent = &intf->dev; ++ ++ err = dwav_usb_mt_init(dwav_usb_mt, (void *)input_dev); ++ if (err) ++ goto err_free_urb; ++ ++ usb_set_intfdata(intf, dwav_usb_mt); ++ ++ dev_info(&intf->dev, "%s\n", DEV_INFO[dwav_usb_mt->dev_id].name); ++ ++ return 0; ++ ++err_free_urb: ++ usb_free_urb(dwav_usb_mt->irq); ++ ++err_free_buffers: ++ dwav_usb_mt_free_buffers(udev, dwav_usb_mt); ++ ++err_free_mem: ++ if (input_dev) ++ input_free_device(input_dev); ++ kfree(dwav_usb_mt); ++ ++ return err; ++} ++ ++static void dwav_usb_mt_disconnect(struct usb_interface *intf) ++{ ++ struct dwav_usb_mt *dwav_usb_mt = usb_get_intfdata(intf); ++ ++ if (!dwav_usb_mt) ++ return; ++ ++ dev_dbg(&intf->dev, ++ "%s - dwav_usb_mt is initialized, cleaning up\n", ++ __func__); ++ ++ usb_set_intfdata(intf, NULL); ++ ++ /* this will stop IO via close */ ++ input_unregister_device(dwav_usb_mt->input); ++ ++ usb_free_urb(dwav_usb_mt->irq); ++ ++ dwav_usb_mt_free_buffers(interface_to_usbdev(intf), dwav_usb_mt); ++ ++ kfree(dwav_usb_mt); ++} ++ ++MODULE_DEVICE_TABLE(usb, dwav_usb_mt_devices); ++ ++static struct usb_driver dwav_usb_mt_driver = { ++ .name = "dwav_usb_mt", ++ .probe = dwav_usb_mt_probe, ++ .disconnect = dwav_usb_mt_disconnect, ++ .suspend = dwav_usb_mt_suspend, ++ .resume = dwav_usb_mt_resume, ++ .reset_resume = dwav_usb_mt_reset_resume, ++ .id_table = dwav_usb_mt_devices, ++ .supports_autosuspend = 1, ++}; ++ ++module_usb_driver(dwav_usb_mt_driver); ++ ++MODULE_AUTHOR("Hardkernel Co.,Ltd"); ++MODULE_DESCRIPTION("D-WAV USB(HID) MultiTouch Driver"); ++MODULE_LICENSE("GPL"); ++ ++MODULE_ALIAS("dwav_usb_mt"); +\ No newline at end of file +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-kernel-odroidn2-current.patch b/patch/kernel/archive/meson64-5.19/general-kernel-odroidn2-current.patch new file mode 100644 index 000000000..955079287 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-kernel-odroidn2-current.patch @@ -0,0 +1,16 @@ +diff --git a/scripts/package/builddeb b/scripts/package/builddeb +index 67cd420dcf89..e445d84b6cbc 100755 +--- a/scripts/package/builddeb ++++ b/scripts/package/builddeb +@@ -218,6 +218,11 @@ if [ "$ARCH" != "um" ]; then + create_package linux-libc-dev debian/linux-libc-dev + fi + ++sed -e "s/exit 0//g" -i $tmpdir/DEBIAN/postinst ++cat >> $tmpdir/DEBIAN/postinst < /dev/null 2>&1 ++exit 0 ++EOT + create_package "$packagename" "$tmpdir" + + if [ -n "$BUILD_DEBUG" ] ; then diff --git a/patch/kernel/archive/meson64-5.19/general-media-cec-silence-CEC-timeout-message-HACK.patch b/patch/kernel/archive/meson64-5.19/general-media-cec-silence-CEC-timeout-message-HACK.patch new file mode 100644 index 000000000..437bd0615 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-media-cec-silence-CEC-timeout-message-HACK.patch @@ -0,0 +1,40 @@ +From 03bfb3f6a703d7671508b698c5a552d0a0e0197b Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Tue, 7 Jan 2020 07:12:47 +0000 +Subject: [PATCH 055/101] HACK: media: cec: silence CEC timeout message + +If testing with an AVR that does not pass-through CEC state the system +log fills with timeout messages. Silence this to stop the log rotation +and ensure other issues are visible. + +[ 42.718009] cec-meson_ao_cec: message ff 84 50 00 01 timed out +[ 45.021994] cec-meson_ao_cec: message ff 87 00 15 82 timed out +[ 47.325965] cec-meson_ao_cec: message 10 timed out +[ 49.630023] cec-meson_ao_cec: message 10 timed out +[ 51.933960] cec-meson_ao_cec: message 10 timed out + +Signed-off-by: Christian Hewitt +--- + drivers/media/cec/core/cec-adap.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c +index 8bf91b5a7d0e..74a33366cc26 100644 +--- a/drivers/media/cec/core/cec-adap.c ++++ b/drivers/media/cec/core/cec-adap.c +@@ -501,9 +501,9 @@ int cec_thread_func(void *_adap) + * default). + */ + if (adap->transmitting) { +- pr_warn("cec-%s: message %*ph timed out\n", adap->name, +- adap->transmitting->msg.len, +- adap->transmitting->msg.msg); ++ //pr_warn("cec-%s: message %*ph timed out\n", adap->name, ++ // adap->transmitting->msg.len, ++ // adap->transmitting->msg.msg); + /* Just give up on this. */ + cec_data_cancel(adap->transmitting, + CEC_TX_STATUS_TIMEOUT, 0); +-- +2.17.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-memory-marked-nomap.patch b/patch/kernel/archive/meson64-5.19/general-memory-marked-nomap.patch new file mode 100644 index 000000000..6f01098af --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-memory-marked-nomap.patch @@ -0,0 +1,38 @@ +From 4d11a956070513a173dd9fd0d6e981918a6331e4 Mon Sep 17 00:00:00 2001 +From: Stefan Agner +Date: Wed, 15 Sep 2021 05:00:45 +0000 +Subject: [PATCH 11/90] HACK: of: partial revert of fdt.c changes + +This resolves reports similar to the below which are present in dmesg +since Linux 5.10; which are also causing crashes in some distros: + +[ 0.000000] OF: fdt: Reserved memory: failed to reserve memory for node 'secmon@5000000': base 0x0000000005000000, size 3 MiB + +Signed-off-by: Christian Hewitt +--- + drivers/of/fdt.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c +index ec315b060cd5..15e9c0c2a2c6 100644 +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -481,15 +481,6 @@ static int __init early_init_dt_reserve_memory_arch(phys_addr_t base, + phys_addr_t size, bool nomap) + { + if (nomap) { +- /* +- * If the memory is already reserved (by another region), we +- * should not allow it to be marked nomap, but don't worry +- * if the region isn't memory as it won't be mapped. +- */ +- if (memblock_overlaps_region(&memblock.memory, base, size) && +- memblock_is_region_reserved(base, size)) +- return -EBUSY; +- + return memblock_mark_nomap(base, size); + } + return memblock_reserve(base, size); +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-meson-aiu-Fix-HDMI-codec-control-selection.patch b/patch/kernel/archive/meson64-5.19/general-meson-aiu-Fix-HDMI-codec-control-selection.patch new file mode 100644 index 000000000..88e979908 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-meson-aiu-Fix-HDMI-codec-control-selection.patch @@ -0,0 +1,233 @@ +From 712edc341073c350a11658186609eafd292dbe8a Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 3 Oct 2021 05:35:48 +0000 +Subject: [PATCH 27/90] FROMLIST(v1): ASoC: meson: aiu: Fix HDMI codec control + selection + +The HDMI controllers on Amlogic Meson SoCs which use the AIU +audio-controller have two different audio format inputs: +- I2S which is also the only configuration supported on GXBB, GXL and + GXM SoCs since there's no SPDIF support in the DesignWare HDMI + controller driver (at the time of writing this) +- SPDIF can be used optionally, including pass-through formats + +Switching between these requires us to set different registers: +AIU_HDMI_CLK_DATA_CTRL[1:0] "HDMI_DATA_CLK_SEL": +- 0x0 disables the HDMI output clock +- 0x1 selects the PCM clock +- 0x2 selects the AIU clock +- 0x3 is reserved + +AIU_HDMI_CLK_DATA_CTRL[5:4] "HDMI_DATA_SEL": +- 0x0 outputs constant zero, disables HDMI data +- 0x1 selects PCM data +- 0x2 selects AIU I2S data +- 0x3 is reserved + +AIU_CLK_CTRL_MORE[6] "HDMITX_SEL_AOCLKX2": +- 0x0 selects cts_i958 as AIU clk to hdmi_tx_audio_master_clk +- 0x1 selects cts_aoclkx2_int as AIU clk to hdmi_tx_audio_master_clk + +The Meson8/8b/8m2 vendor driver uses the following settings: +SPDIF output to the HDMI controller: +- 0x2 (AIU clock) in AIU_HDMI_CLK_DATA_CTRL[1:0] +- 0x0 (no HDMI data) in AIU_HDMI_CLK_DATA_CTRL[5:4] +- 0x0 (using cts_i958 as AIU clk) in AIU_CLK_CTRL_MORE[6] +I2S output to the HDMI controller: +- 0x2 (AIU clock) in AIU_HDMI_CLK_DATA_CTRL[1:0] +- 0x2 (I2S data) in AIU_HDMI_CLK_DATA_CTRL[5:4] +- 0x0 (using cts_aoclkx2_int as AIU clk) in AIU_CLK_CTRL_MORE[6] + +The GXBB/GXL/GXM vendor driver uses the following settings: +SPDIF output to the HDMI controller: +- not setting AIU_HDMI_CLK_DATA_CTRL at all +- 0x0 (using cts_i958 as AIU clk) in AIU_CLK_CTRL_MORE[6] +I2S output to the HDMI controller: +- 0x2 (AIU clock) in AIU_HDMI_CLK_DATA_CTRL[1:0] +- 0x2 (I2S data) in AIU_HDMI_CLK_DATA_CTRL[5:4] +- 0x0 (using cts_aoclkx2_int as AIU clk) in AIU_CLK_CTRL_MORE[6] + +Set the three registers at the same time following what the vendor +driver does on Meson8/8b/8m2 SoCs. This makes the SPDIF output to the +HDMI controller work. The entries and order of the entries in the enum +is not changed on purpose to not break old configurations. + +Fixes: b82b734c0e9a7 ("ASoC: meson: aiu: add hdmi codec control support") +Signed-off-by: Martin Blumenstingl +--- + sound/soc/meson/aiu-codec-ctrl.c | 108 ++++++++++++++++++++++-------- + sound/soc/meson/aiu-encoder-i2s.c | 6 -- + 2 files changed, 80 insertions(+), 34 deletions(-) + +diff --git a/sound/soc/meson/aiu-codec-ctrl.c b/sound/soc/meson/aiu-codec-ctrl.c +index c3ea733fce91..2b8575491aeb 100644 +--- a/sound/soc/meson/aiu-codec-ctrl.c ++++ b/sound/soc/meson/aiu-codec-ctrl.c +@@ -12,14 +12,60 @@ + #include "aiu.h" + #include "meson-codec-glue.h" + +-#define CTRL_CLK_SEL GENMASK(1, 0) +-#define CTRL_DATA_SEL_SHIFT 4 +-#define CTRL_DATA_SEL (0x3 << CTRL_DATA_SEL_SHIFT) +- +-static const char * const aiu_codec_ctrl_mux_texts[] = { +- "DISABLED", "PCM", "I2S", ++#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL GENMASK(1, 0) ++#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_DISABLE 0x0 ++#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_PCM 0x1 ++#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_AIU 0x2 ++#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL GENMASK(5, 4) ++#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_OUTPUT_ZERO 0x0 ++#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_PCM_DATA 0x1 ++#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_I2S_DATA 0x2 ++ ++#define AIU_CLK_CTRL_MORE_AMCLK BIT(6) ++ ++#define AIU_HDMI_CTRL_MUX_DISABLED 0 ++#define AIU_HDMI_CTRL_MUX_PCM 1 ++#define AIU_HDMI_CTRL_MUX_I2S 2 ++ ++static const char * const aiu_codec_hdmi_ctrl_mux_texts[] = { ++ [AIU_HDMI_CTRL_MUX_DISABLED] = "DISABLED", ++ [AIU_HDMI_CTRL_MUX_PCM] = "PCM", ++ [AIU_HDMI_CTRL_MUX_I2S] = "I2S", + }; + ++static int aiu_codec_ctrl_mux_get_enum(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_component *component = ++ snd_soc_dapm_kcontrol_component(kcontrol); ++ unsigned int ctrl, more, mux = AIU_HDMI_CTRL_MUX_DISABLED; ++ ++ ctrl = snd_soc_component_read(component, AIU_HDMI_CLK_DATA_CTRL); ++ if (FIELD_GET(AIU_HDMI_CLK_DATA_CTRL_CLK_SEL, ctrl) != ++ AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_AIU) { ++ goto out; ++ } ++ ++ more = snd_soc_component_read(component, AIU_CLK_CTRL_MORE); ++ if (FIELD_GET(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL, ctrl) == ++ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_I2S_DATA && ++ !!(more & AIU_CLK_CTRL_MORE_AMCLK)) { ++ mux = AIU_HDMI_CTRL_MUX_I2S; ++ goto out; ++ } ++ ++ if (FIELD_GET(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL, ctrl) == ++ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_OUTPUT_ZERO && ++ !(more & AIU_CLK_CTRL_MORE_AMCLK)) { ++ mux = AIU_HDMI_CTRL_MUX_PCM; ++ goto out; ++ } ++ ++out: ++ ucontrol->value.enumerated.item[0] = mux; ++ return 0; ++} ++ + static int aiu_codec_ctrl_mux_put_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +@@ -28,45 +74,51 @@ static int aiu_codec_ctrl_mux_put_enum(struct snd_kcontrol *kcontrol, + struct snd_soc_dapm_context *dapm = + snd_soc_dapm_kcontrol_dapm(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; +- unsigned int mux, changed; ++ unsigned int mux, ctrl, more; + + mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]); +- changed = snd_soc_component_test_bits(component, e->reg, +- CTRL_DATA_SEL, +- FIELD_PREP(CTRL_DATA_SEL, mux)); + +- if (!changed) +- return 0; ++ if (mux == AIU_HDMI_CTRL_MUX_I2S) { ++ ctrl = FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL, ++ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_I2S_DATA); ++ more = AIU_CLK_CTRL_MORE_AMCLK; ++ } else { ++ ctrl = FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_DATA_SEL, ++ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_OUTPUT_ZERO); ++ more = 0; ++ } ++ ++ if (mux == AIU_HDMI_CTRL_MUX_DISABLED) { ++ ctrl |= FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_CLK_SEL, ++ AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_DISABLE); ++ } else { ++ ctrl |= FIELD_PREP(AIU_HDMI_CLK_DATA_CTRL_CLK_SEL, ++ AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_AIU); ++ } + + /* Force disconnect of the mux while updating */ + snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL); + +- /* Reset the source first */ +- snd_soc_component_update_bits(component, e->reg, +- CTRL_CLK_SEL | +- CTRL_DATA_SEL, +- FIELD_PREP(CTRL_CLK_SEL, 0) | +- FIELD_PREP(CTRL_DATA_SEL, 0)); ++ snd_soc_component_update_bits(component, AIU_HDMI_CLK_DATA_CTRL, ++ AIU_HDMI_CLK_DATA_CTRL_CLK_SEL | ++ AIU_HDMI_CLK_DATA_CTRL_DATA_SEL, ++ ctrl); + +- /* Set the appropriate source */ +- snd_soc_component_update_bits(component, e->reg, +- CTRL_CLK_SEL | +- CTRL_DATA_SEL, +- FIELD_PREP(CTRL_CLK_SEL, mux) | +- FIELD_PREP(CTRL_DATA_SEL, mux)); ++ snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE, ++ AIU_CLK_CTRL_MORE_AMCLK, ++ more); + + snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL); + + return 1; + } + +-static SOC_ENUM_SINGLE_DECL(aiu_hdmi_ctrl_mux_enum, AIU_HDMI_CLK_DATA_CTRL, +- CTRL_DATA_SEL_SHIFT, +- aiu_codec_ctrl_mux_texts); ++static SOC_ENUM_SINGLE_VIRT_DECL(aiu_hdmi_ctrl_mux_enum, ++ aiu_codec_hdmi_ctrl_mux_texts); + + static const struct snd_kcontrol_new aiu_hdmi_ctrl_mux = + SOC_DAPM_ENUM_EXT("HDMI Source", aiu_hdmi_ctrl_mux_enum, +- snd_soc_dapm_get_enum_double, ++ aiu_codec_ctrl_mux_get_enum, + aiu_codec_ctrl_mux_put_enum); + + static const struct snd_soc_dapm_widget aiu_hdmi_ctrl_widgets[] = { +diff --git a/sound/soc/meson/aiu-encoder-i2s.c b/sound/soc/meson/aiu-encoder-i2s.c +index 67729de41a73..88637deb2d7a 100644 +--- a/sound/soc/meson/aiu-encoder-i2s.c ++++ b/sound/soc/meson/aiu-encoder-i2s.c +@@ -23,7 +23,6 @@ + #define AIU_CLK_CTRL_AOCLK_INVERT BIT(6) + #define AIU_CLK_CTRL_LRCLK_INVERT BIT(7) + #define AIU_CLK_CTRL_LRCLK_SKEW GENMASK(9, 8) +-#define AIU_CLK_CTRL_MORE_HDMI_AMCLK BIT(6) + #define AIU_CLK_CTRL_MORE_I2S_DIV GENMASK(5, 0) + #define AIU_CODEC_DAC_LRCLK_CTRL_DIV GENMASK(11, 0) + +@@ -176,11 +175,6 @@ static int aiu_encoder_i2s_set_clocks(struct snd_soc_component *component, + if (ret) + return ret; + +- /* Make sure amclk is used for HDMI i2s as well */ +- snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE, +- AIU_CLK_CTRL_MORE_HDMI_AMCLK, +- AIU_CLK_CTRL_MORE_HDMI_AMCLK); +- + return 0; + } + +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-fix-deferred-probing.patch b/patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-fix-deferred-probing.patch new file mode 100644 index 000000000..77e98a325 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-fix-deferred-probing.patch @@ -0,0 +1,35 @@ +From b83c8168c58ccb96f92a4b6ecf1b8b7483fcced3 Mon Sep 17 00:00:00 2001 +From: Sergey Shtylyov +Date: Fri, 24 Dec 2021 06:09:57 +0000 +Subject: [PATCH 38/90] FROMLIST(v1): mmc: meson-gx: fix deferred probing + +The driver overrides the error codes and IRQ0 returned by platform_get_irq() +to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe +permanently instead of the deferred probing. Switch to propagating the error +codes upstream. IRQ0 is no longer returned by platform_get_irq(), so we now +can safely ignore it... + +Fixes: cbcaac6d7dd2 ("mmc: meson-gx-mmc: Fix platform_get_irq's error checking") +Signed-off-by: Sergey Shtylyov +--- + drivers/mmc/host/meson-gx-mmc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c +index 58ab9d90bc8b..1a11a4bf4d4f 100644 +--- a/drivers/mmc/host/meson-gx-mmc.c ++++ b/drivers/mmc/host/meson-gx-mmc.c +@@ -1183,8 +1183,8 @@ static int meson_mmc_probe(struct platform_device *pdev) + } + + host->irq = platform_get_irq(pdev, 0); +- if (host->irq <= 0) { +- ret = -EINVAL; ++ if (host->irq < 0) { ++ ret = host->irq; + goto free_host; + } + +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch b/patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch new file mode 100644 index 000000000..704e97c2d --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch @@ -0,0 +1,59 @@ +From 5c5664545a97520bbce591add5a7dbbea143b999 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Thu, 14 Jan 2021 17:43:02 +0100 +Subject: [PATCH 54/90] WIP: mmc: meson-gx-mmc: set core clock phase to 270 + degrees for AXG compatible controllers + +Signed-off-by: Neil Armstrong +--- + drivers/mmc/host/meson-gx-mmc.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c +index 1a11a4bf4d4f..df60312a1765 100644 +--- a/drivers/mmc/host/meson-gx-mmc.c ++++ b/drivers/mmc/host/meson-gx-mmc.c +@@ -38,6 +38,7 @@ + #define CLK_RX_PHASE_MASK GENMASK(13, 12) + #define CLK_PHASE_0 0 + #define CLK_PHASE_180 2 ++#define CLK_PHASE_270 3 + #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) + #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) + #define CLK_V2_ALWAYS_ON BIT(24) +@@ -136,6 +137,7 @@ struct meson_mmc_data { + unsigned int rx_delay_mask; + unsigned int always_on; + unsigned int adjust; ++ unsigned int clk_core_phase; + }; + + struct sd_emmc_desc { +@@ -428,7 +430,7 @@ static int meson_mmc_clk_init(struct meson_host *host) + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ + clk_reg = CLK_ALWAYS_ON(host); + clk_reg |= CLK_DIV_MASK; +- clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); ++ clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->data->clk_core_phase); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); + writel(clk_reg, host->regs + SD_EMMC_CLOCK); +@@ -1337,6 +1339,7 @@ static const struct meson_mmc_data meson_gx_data = { + .rx_delay_mask = CLK_V2_RX_DELAY_MASK, + .always_on = CLK_V2_ALWAYS_ON, + .adjust = SD_EMMC_ADJUST, ++ .clk_core_phase = CLK_PHASE_180, + }; + + static const struct meson_mmc_data meson_axg_data = { +@@ -1344,6 +1347,7 @@ static const struct meson_mmc_data meson_axg_data = { + .rx_delay_mask = CLK_V3_RX_DELAY_MASK, + .always_on = CLK_V3_ALWAYS_ON, + .adjust = SD_EMMC_V3_ADJUST, ++ .clk_core_phase = CLK_PHASE_270, + }; + + static const struct of_device_id meson_mmc_of_match[] = { +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-meson-vdec-add-HEVC-decode-codec.patch b/patch/kernel/archive/meson64-5.19/general-meson-vdec-add-HEVC-decode-codec.patch new file mode 100644 index 000000000..cb8319fca --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-meson-vdec-add-HEVC-decode-codec.patch @@ -0,0 +1,1609 @@ +From 478ef90d4bb38e6c5ae11c4abd6142fc7336c746 Mon Sep 17 00:00:00 2001 +From: benjamin545 +Date: Thu, 15 Jul 2021 17:08:42 -0400 +Subject: [PATCH 64/90] WIP: drivers: meson: vdec: add HEVC decode codec + +--- + drivers/staging/media/meson/vdec/Makefile | 2 +- + drivers/staging/media/meson/vdec/codec_hevc.c | 1440 +++++++++++++++++ + drivers/staging/media/meson/vdec/codec_hevc.h | 13 + + drivers/staging/media/meson/vdec/esparser.c | 2 +- + drivers/staging/media/meson/vdec/hevc_regs.h | 1 + + .../staging/media/meson/vdec/vdec_platform.c | 49 + + 6 files changed, 1505 insertions(+), 2 deletions(-) + create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.c + create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.h + +diff --git a/drivers/staging/media/meson/vdec/Makefile b/drivers/staging/media/meson/vdec/Makefile +index 6e726af84ac9..16f848e456b9 100644 +--- a/drivers/staging/media/meson/vdec/Makefile ++++ b/drivers/staging/media/meson/vdec/Makefile +@@ -3,6 +3,6 @@ + + meson-vdec-objs = esparser.o vdec.o vdec_helpers.o vdec_platform.o + meson-vdec-objs += vdec_1.o vdec_hevc.o +-meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o ++meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o codec_hevc.o + + obj-$(CONFIG_VIDEO_MESON_VDEC) += meson-vdec.o +diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c +new file mode 100644 +index 000000000000..3a6fd04a2d33 +--- /dev/null ++++ b/drivers/staging/media/meson/vdec/codec_hevc.c +@@ -0,0 +1,1440 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2018 Maxime Jourdan ++ * Copyright (C) 2015 Amlogic, Inc. All rights reserved. ++ */ ++ ++#include ++#include ++ ++#include "codec_hevc.h" ++#include "dos_regs.h" ++#include "hevc_regs.h" ++#include "vdec_helpers.h" ++#include "codec_hevc_common.h" ++ ++/* HEVC reg mapping */ ++#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0 ++ #define HEVC_ACTION_DONE 0xff ++#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1 ++#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2 ++#define HEVC_VPS_BUFFER HEVC_ASSIST_SCRATCH_3 ++#define HEVC_SPS_BUFFER HEVC_ASSIST_SCRATCH_4 ++#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5 ++#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6 ++#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7 ++#define H265_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_7 ++#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8 ++#define HEVC_sao_mem_unit HEVC_ASSIST_SCRATCH_9 ++#define HEVC_SAO_ABV HEVC_ASSIST_SCRATCH_A ++#define HEVC_sao_vb_size HEVC_ASSIST_SCRATCH_B ++#define HEVC_SAO_VB HEVC_ASSIST_SCRATCH_C ++#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D ++#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E ++#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F ++#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F ++#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G ++#define HEVC_DECODE_MODE2 HEVC_ASSIST_SCRATCH_H ++#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I ++#define HEVC_DECODE_MODE HEVC_ASSIST_SCRATCH_J ++ #define DECODE_MODE_SINGLE 0 ++#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K ++#define HEVC_AUX_ADR HEVC_ASSIST_SCRATCH_L ++#define HEVC_AUX_DATA_SIZE HEVC_ASSIST_SCRATCH_M ++#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N ++ ++#define AMRISC_MAIN_REQ 0x04 ++ ++/* HEVC Constants */ ++#define MAX_REF_PIC_NUM 24 ++#define MAX_REF_ACTIVE 16 ++#define MAX_TILE_COL_NUM 10 ++#define MAX_TILE_ROW_NUM 20 ++#define MAX_SLICE_NUM 800 ++#define INVALID_POC 0x80000000 ++ ++/* HEVC Workspace layout */ ++#define MPRED_MV_BUF_SIZE 0x120000 ++ ++#define IPP_SIZE 0x4000 ++#define SAO_ABV_SIZE 0x30000 ++#define SAO_VB_SIZE 0x30000 ++#define SH_TM_RPS_SIZE 0x800 ++#define VPS_SIZE 0x800 ++#define SPS_SIZE 0x800 ++#define PPS_SIZE 0x2000 ++#define SAO_UP_SIZE 0x2800 ++#define SWAP_BUF_SIZE 0x800 ++#define SWAP_BUF2_SIZE 0x800 ++#define SCALELUT_SIZE 0x8000 ++#define DBLK_PARA_SIZE 0x20000 ++#define DBLK_DATA_SIZE 0x80000 ++#define DBLK_DATA2_SIZE 0x80000 ++#define MMU_VBH_SIZE 0x5000 ++#define MPRED_ABV_SIZE 0x8000 ++#define MPRED_MV_SIZE (MPRED_MV_BUF_SIZE * MAX_REF_PIC_NUM) ++#define RPM_BUF_SIZE 0x100 ++#define LMEM_SIZE 0xA00 ++ ++#define IPP_OFFSET 0x00 ++#define SAO_ABV_OFFSET (IPP_OFFSET + IPP_SIZE) ++#define SAO_VB_OFFSET (SAO_ABV_OFFSET + SAO_ABV_SIZE) ++#define SH_TM_RPS_OFFSET (SAO_VB_OFFSET + SAO_VB_SIZE) ++#define VPS_OFFSET (SH_TM_RPS_OFFSET + SH_TM_RPS_SIZE) ++#define SPS_OFFSET (VPS_OFFSET + VPS_SIZE) ++#define PPS_OFFSET (SPS_OFFSET + SPS_SIZE) ++#define SAO_UP_OFFSET (PPS_OFFSET + PPS_SIZE) ++#define SWAP_BUF_OFFSET (SAO_UP_OFFSET + SAO_UP_SIZE) ++#define SWAP_BUF2_OFFSET (SWAP_BUF_OFFSET + SWAP_BUF_SIZE) ++#define SCALELUT_OFFSET (SWAP_BUF2_OFFSET + SWAP_BUF2_SIZE) ++#define DBLK_PARA_OFFSET (SCALELUT_OFFSET + SCALELUT_SIZE) ++#define DBLK_DATA_OFFSET (DBLK_PARA_OFFSET + DBLK_PARA_SIZE) ++#define DBLK_DATA2_OFFSET (DBLK_DATA_OFFSET + DBLK_DATA_SIZE) ++#define MMU_VBH_OFFSET (DBLK_DATA2_OFFSET + DBLK_DATA2_SIZE) ++#define MPRED_ABV_OFFSET (MMU_VBH_OFFSET + MMU_VBH_SIZE) ++#define MPRED_MV_OFFSET (MPRED_ABV_OFFSET + MPRED_ABV_SIZE) ++#define RPM_OFFSET (MPRED_MV_OFFSET + MPRED_MV_SIZE) ++#define LMEM_OFFSET (RPM_OFFSET + RPM_BUF_SIZE) ++ ++/* ISR decode status */ ++#define HEVC_DEC_IDLE 0x0 ++#define HEVC_NAL_UNIT_VPS 0x1 ++#define HEVC_NAL_UNIT_SPS 0x2 ++#define HEVC_NAL_UNIT_PPS 0x3 ++#define HEVC_NAL_UNIT_CODED_SLICE_SEGMENT 0x4 ++#define HEVC_CODED_SLICE_SEGMENT_DAT 0x5 ++#define HEVC_SLICE_DECODING 0x6 ++#define HEVC_NAL_UNIT_SEI 0x7 ++#define HEVC_SLICE_SEGMENT_DONE 0x8 ++#define HEVC_NAL_SEARCH_DONE 0x9 ++#define HEVC_DECPIC_DATA_DONE 0xa ++#define HEVC_DECPIC_DATA_ERROR 0xb ++#define HEVC_SEI_DAT 0xc ++#define HEVC_SEI_DAT_DONE 0xd ++ ++/* RPM misc_flag0 */ ++#define PCM_LOOP_FILTER_DISABLED_FLAG_BIT 0 ++#define PCM_ENABLE_FLAG_BIT 1 ++#define LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT 2 ++#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 3 ++#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT 4 ++#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT 5 ++#define DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT 6 ++#define SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT 7 ++#define SLICE_SAO_LUMA_FLAG_BIT 8 ++#define SLICE_SAO_CHROMA_FLAG_BIT 9 ++#define SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 10 ++ ++/* Constants for HEVC_MPRED_CTRL1 */ ++#define AMVP_MAX_NUM_CANDS_MEM 3 ++#define AMVP_MAX_NUM_CANDS 2 ++#define NUM_CHROMA_MODE 5 ++#define DM_CHROMA_IDX 36 ++ ++/* Buffer sizes */ ++#define SIZE_WORKSPACE ALIGN(LMEM_OFFSET + LMEM_SIZE, 64 * SZ_1K) ++#define SIZE_AUX (SZ_1K * 16) ++#define SIZE_FRAME_MMU (0x1200 * 4) ++#define RPM_SIZE 0x80 ++#define RPS_USED_BIT 14 ++ ++/* Data received from the HW in this form, do not rearrange */ ++union rpm_param { ++ struct { ++ u16 data[RPM_SIZE]; ++ } l; ++ struct { ++ u16 CUR_RPS[MAX_REF_ACTIVE]; ++ u16 num_ref_idx_l0_active; ++ u16 num_ref_idx_l1_active; ++ u16 slice_type; ++ u16 slice_temporal_mvp_enable_flag; ++ u16 dependent_slice_segment_flag; ++ u16 slice_segment_address; ++ u16 num_title_rows_minus1; ++ u16 pic_width_in_luma_samples; ++ u16 pic_height_in_luma_samples; ++ u16 log2_min_coding_block_size_minus3; ++ u16 log2_diff_max_min_coding_block_size; ++ u16 log2_max_pic_order_cnt_lsb_minus4; ++ u16 POClsb; ++ u16 collocated_from_l0_flag; ++ u16 collocated_ref_idx; ++ u16 log2_parallel_merge_level; ++ u16 five_minus_max_num_merge_cand; ++ u16 sps_num_reorder_pics_0; ++ u16 modification_flag; ++ u16 tiles_flags; ++ u16 num_tile_columns_minus1; ++ u16 num_tile_rows_minus1; ++ u16 tile_width[8]; ++ u16 tile_height[8]; ++ u16 misc_flag0; ++ u16 pps_beta_offset_div2; ++ u16 pps_tc_offset_div2; ++ u16 slice_beta_offset_div2; ++ u16 slice_tc_offset_div2; ++ u16 pps_cb_qp_offset; ++ u16 pps_cr_qp_offset; ++ u16 first_slice_segment_in_pic_flag; ++ u16 m_temporalId; ++ u16 m_nalUnitType; ++ u16 vui_num_units_in_tick_hi; ++ u16 vui_num_units_in_tick_lo; ++ u16 vui_time_scale_hi; ++ u16 vui_time_scale_lo; ++ u16 bit_depth; ++ u16 profile_etc; ++ u16 sei_frame_field_info; ++ u16 video_signal_type; ++ u16 modification_list[0x20]; ++ u16 conformance_window_flag; ++ u16 conf_win_left_offset; ++ u16 conf_win_right_offset; ++ u16 conf_win_top_offset; ++ u16 conf_win_bottom_offset; ++ u16 chroma_format_idc; ++ u16 color_description; ++ u16 aspect_ratio_idc; ++ u16 sar_width; ++ u16 sar_height; ++ } p; ++}; ++ ++enum nal_unit_type { ++ NAL_UNIT_CODED_SLICE_BLA = 16, ++ NAL_UNIT_CODED_SLICE_BLANT = 17, ++ NAL_UNIT_CODED_SLICE_BLA_N_LP = 18, ++ NAL_UNIT_CODED_SLICE_IDR = 19, ++ NAL_UNIT_CODED_SLICE_IDR_N_LP = 20, ++}; ++ ++enum slice_type { ++ B_SLICE = 0, ++ P_SLICE = 1, ++ I_SLICE = 2, ++}; ++ ++/* A frame being decoded */ ++struct hevc_frame { ++ struct list_head list; ++ struct vb2_v4l2_buffer *vbuf; ++ u32 offset; ++ u32 poc; ++ ++ int referenced; ++ u32 num_reorder_pic; ++ ++ u32 cur_slice_idx; ++ u32 cur_slice_type; ++ ++ /* 2 lists (L0/L1) ; 800 slices ; 16 refs */ ++ u32 ref_poc_list[2][MAX_SLICE_NUM][MAX_REF_ACTIVE]; ++ u32 ref_num[2]; ++}; ++ ++struct codec_hevc { ++ struct mutex lock; ++ ++ /* Common part of the HEVC decoder */ ++ struct codec_hevc_common common; ++ ++ /* Buffer for the HEVC Workspace */ ++ void *workspace_vaddr; ++ dma_addr_t workspace_paddr; ++ ++ /* AUX buffer */ ++ void *aux_vaddr; ++ dma_addr_t aux_paddr; ++ ++ /* Contains many information parsed from the bitstream */ ++ union rpm_param rpm_param; ++ ++ /* Information computed from the RPM */ ++ u32 lcu_size; // Largest Coding Unit ++ u32 lcu_x_num; ++ u32 lcu_y_num; ++ u32 lcu_total; ++ ++ /* Current Frame being handled */ ++ struct hevc_frame *cur_frame; ++ u32 curr_poc; ++ /* Collocated Reference Picture */ ++ struct hevc_frame *col_frame; ++ u32 col_poc; ++ ++ /* All ref frames used by the HW at a given time */ ++ struct list_head ref_frames_list; ++ u32 frames_num; ++ ++ /* Coded resolution reported by the hardware */ ++ u32 width, height; ++ /* Resolution minus the conformance window offsets */ ++ u32 dst_width, dst_height; ++ ++ u32 prev_tid0_poc; ++ u32 slice_segment_addr; ++ u32 slice_addr; ++ u32 ldc_flag; ++ ++ /* Whether we detected the bitstream as 10-bit */ ++ int is_10bit; ++}; ++ ++static u32 codec_hevc_num_pending_bufs(struct amvdec_session *sess) ++{ ++ struct codec_hevc *hevc; ++ u32 ret; ++ ++ hevc = sess->priv; ++ if (!hevc) ++ return 0; ++ ++ mutex_lock(&hevc->lock); ++ ret = hevc->frames_num; ++ mutex_unlock(&hevc->lock); ++ ++ return ret; ++} ++ ++/* Update the L0 and L1 reference lists for a given frame */ ++static void codec_hevc_update_frame_refs(struct amvdec_session *sess, ++ struct hevc_frame *frame) ++{ ++ struct codec_hevc *hevc = sess->priv; ++ union rpm_param *params = &hevc->rpm_param; ++ int num_ref_idx_l0_active = ++ (params->p.num_ref_idx_l0_active > MAX_REF_ACTIVE) ? ++ MAX_REF_ACTIVE : params->p.num_ref_idx_l0_active; ++ int num_ref_idx_l1_active = ++ (params->p.num_ref_idx_l1_active > MAX_REF_ACTIVE) ? ++ MAX_REF_ACTIVE : params->p.num_ref_idx_l1_active; ++ int ref_picset0[MAX_REF_ACTIVE] = { 0 }; ++ int ref_picset1[MAX_REF_ACTIVE] = { 0 }; ++ u16 *mod_list = params->p.modification_list; ++ int num_neg = 0; ++ int num_pos = 0; ++ int total_num; ++ int i; ++ ++ for (i = 0; i < MAX_REF_ACTIVE; i++) { ++ frame->ref_poc_list[0][frame->cur_slice_idx][i] = 0; ++ frame->ref_poc_list[1][frame->cur_slice_idx][i] = 0; ++ } ++ ++ for (i = 0; i < MAX_REF_ACTIVE; i++) { ++ u16 cur_rps = params->p.CUR_RPS[i]; ++ int delt = cur_rps & ((1 << (RPS_USED_BIT - 1)) - 1); ++ ++ if (cur_rps & 0x8000) ++ break; ++ ++ if (!((cur_rps >> RPS_USED_BIT) & 1)) ++ continue; ++ ++ if ((cur_rps >> (RPS_USED_BIT - 1)) & 1) { ++ ref_picset0[num_neg] = ++ frame->poc - ((1 << (RPS_USED_BIT - 1)) - delt); ++ num_neg++; ++ } else { ++ ref_picset1[num_pos] = frame->poc + delt; ++ num_pos++; ++ } ++ } ++ ++ total_num = num_neg + num_pos; ++ ++ if (total_num <= 0) ++ goto end; ++ ++ for (i = 0; i < num_ref_idx_l0_active; i++) { ++ int cidx; ++ if (params->p.modification_flag & 0x1) ++ cidx = mod_list[i]; ++ else ++ cidx = i % total_num; ++ ++ frame->ref_poc_list[0][frame->cur_slice_idx][i] = ++ cidx >= num_neg ? ref_picset1[cidx - num_neg] : ++ ref_picset0[cidx]; ++ } ++ ++ if (params->p.slice_type != B_SLICE) ++ goto end; ++ ++ if (params->p.modification_flag & 0x2) { ++ for (i = 0; i < num_ref_idx_l1_active; i++) { ++ int cidx; ++ if (params->p.modification_flag & 0x1) ++ cidx = mod_list[num_ref_idx_l0_active + i]; ++ else ++ cidx = mod_list[i]; ++ ++ frame->ref_poc_list[1][frame->cur_slice_idx][i] = ++ (cidx >= num_pos) ? ref_picset0[cidx - num_pos] ++ : ref_picset1[cidx]; ++ } ++ } else { ++ for (i = 0; i < num_ref_idx_l1_active; i++) { ++ int cidx = i % total_num; ++ frame->ref_poc_list[1][frame->cur_slice_idx][i] = ++ cidx >= num_pos ? ref_picset0[cidx - num_pos] : ++ ref_picset1[cidx]; ++ } ++ } ++ ++end: ++ frame->ref_num[0] = num_ref_idx_l0_active; ++ frame->ref_num[1] = num_ref_idx_l1_active; ++ ++ dev_dbg(sess->core->dev, ++ "Frame %u; slice %u; slice_type %u; num_l0 %u; num_l1 %u\n", ++ frame->poc, frame->cur_slice_idx, params->p.slice_type, ++ frame->ref_num[0], frame->ref_num[1]); ++} ++ ++static void codec_hevc_update_ldc_flag(struct codec_hevc *hevc) ++{ ++ struct hevc_frame *frame = hevc->cur_frame; ++ u32 slice_type = frame->cur_slice_type; ++ u32 slice_idx = frame->cur_slice_idx; ++ int i; ++ ++ hevc->ldc_flag = 0; ++ ++ if (slice_type == I_SLICE) ++ return; ++ ++ hevc->ldc_flag = 1; ++ for (i = 0; (i < frame->ref_num[0]) && hevc->ldc_flag; i++) { ++ if (frame->ref_poc_list[0][slice_idx][i] > frame->poc) { ++ hevc->ldc_flag = 0; ++ break; ++ } ++ } ++ ++ if (slice_type == P_SLICE) ++ return; ++ ++ for (i = 0; (i < frame->ref_num[1]) && hevc->ldc_flag; i++) { ++ if (frame->ref_poc_list[1][slice_idx][i] > frame->poc) { ++ hevc->ldc_flag = 0; ++ break; ++ } ++ } ++} ++ ++/* Tag "old" frames that are no longer referenced */ ++static void codec_hevc_update_referenced(struct codec_hevc *hevc) ++{ ++ union rpm_param *param = &hevc->rpm_param; ++ struct hevc_frame *frame; ++ int i; ++ u32 curr_poc = hevc->curr_poc; ++ ++ list_for_each_entry(frame, &hevc->ref_frames_list, list) { ++ int is_referenced = 0; ++ u32 poc_tmp; ++ ++ if (!frame->referenced) ++ continue; ++ ++ for (i = 0; i < MAX_REF_ACTIVE; i++) { ++ int delt; ++ if (param->p.CUR_RPS[i] & 0x8000) ++ break; ++ ++ delt = param->p.CUR_RPS[i] & ++ ((1 << (RPS_USED_BIT - 1)) - 1); ++ if (param->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) { ++ poc_tmp = curr_poc - ++ ((1 << (RPS_USED_BIT - 1)) - delt); ++ } else ++ poc_tmp = curr_poc + delt; ++ if (poc_tmp == frame->poc) { ++ is_referenced = 1; ++ break; ++ } ++ } ++ ++ frame->referenced = is_referenced; ++ } ++} ++ ++static struct hevc_frame * ++codec_hevc_get_lowest_poc_frame(struct codec_hevc *hevc) ++{ ++ struct hevc_frame *tmp, *ret = NULL; ++ u32 poc = INT_MAX; ++ ++ list_for_each_entry(tmp, &hevc->ref_frames_list, list) { ++ if (tmp->poc < poc) { ++ ret = tmp; ++ poc = tmp->poc; ++ } ++ } ++ ++ return ret; ++} ++ ++/* Try to output as many frames as possible */ ++static void codec_hevc_output_frames(struct amvdec_session *sess) ++{ ++ struct hevc_frame *tmp; ++ struct codec_hevc *hevc = sess->priv; ++ ++ while ((tmp = codec_hevc_get_lowest_poc_frame(hevc))) { ++ if (hevc->curr_poc && ++ (tmp->referenced || ++ tmp->num_reorder_pic >= hevc->frames_num)) ++ break; ++ ++ dev_dbg(sess->core->dev, "DONE frame poc %u; vbuf %u\n", ++ tmp->poc, tmp->vbuf->vb2_buf.index); ++ amvdec_dst_buf_done_offset(sess, tmp->vbuf, tmp->offset, ++ V4L2_FIELD_NONE, false); ++ list_del(&tmp->list); ++ kfree(tmp); ++ hevc->frames_num--; ++ } ++} ++ ++ ++static int ++codec_hevc_setup_workspace(struct amvdec_session *sess, ++ struct codec_hevc *hevc) ++{ ++ struct amvdec_core *core = sess->core; ++ u32 revision = core->platform->revision; ++ dma_addr_t wkaddr; ++ ++ /* Allocate some memory for the HEVC decoder's state */ ++ hevc->workspace_vaddr = dma_alloc_coherent(core->dev, SIZE_WORKSPACE, ++ &wkaddr, GFP_KERNEL); ++ if (!hevc->workspace_vaddr) ++ return -ENOMEM; ++ ++ hevc->workspace_paddr = wkaddr; ++ ++ amvdec_write_dos(core, HEVCD_IPP_LINEBUFF_BASE, wkaddr + IPP_OFFSET); ++ amvdec_write_dos(core, HEVC_RPM_BUFFER, wkaddr + RPM_OFFSET); ++ amvdec_write_dos(core, HEVC_SHORT_TERM_RPS, wkaddr + SH_TM_RPS_OFFSET); ++ amvdec_write_dos(core, HEVC_VPS_BUFFER, wkaddr + VPS_OFFSET); ++ amvdec_write_dos(core, HEVC_SPS_BUFFER, wkaddr + SPS_OFFSET); ++ amvdec_write_dos(core, HEVC_PPS_BUFFER, wkaddr + PPS_OFFSET); ++ amvdec_write_dos(core, HEVC_SAO_UP, wkaddr + SAO_UP_OFFSET); ++ ++ if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, hevc->is_10bit)) { ++ amvdec_write_dos(core, HEVC_SAO_MMU_VH0_ADDR, ++ wkaddr + MMU_VBH_OFFSET); ++ amvdec_write_dos(core, HEVC_SAO_MMU_VH1_ADDR, ++ wkaddr + MMU_VBH_OFFSET + (MMU_VBH_SIZE / 2)); ++ ++ if (revision >= VDEC_REVISION_G12A) ++ amvdec_write_dos(core, HEVC_ASSIST_MMU_MAP_ADDR, ++ hevc->common.mmu_map_paddr); ++ else ++ amvdec_write_dos(core, H265_MMU_MAP_BUFFER, ++ hevc->common.mmu_map_paddr); ++ } else if (revision < VDEC_REVISION_G12A) { ++ amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER, ++ wkaddr + SWAP_BUF_OFFSET); ++ amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER2, ++ wkaddr + SWAP_BUF2_OFFSET); ++ } ++ ++ amvdec_write_dos(core, HEVC_SCALELUT, wkaddr + SCALELUT_OFFSET); ++ amvdec_write_dos(core, HEVC_DBLK_CFG4, wkaddr + DBLK_PARA_OFFSET); ++ amvdec_write_dos(core, HEVC_DBLK_CFG5, wkaddr + DBLK_DATA_OFFSET); ++ if (revision >= VDEC_REVISION_G12A) ++ amvdec_write_dos(core, HEVC_DBLK_CFGE, ++ wkaddr + DBLK_DATA2_OFFSET); ++ ++ amvdec_write_dos(core, LMEM_DUMP_ADR, wkaddr + LMEM_OFFSET); ++ ++ return 0; ++} ++ ++static int codec_hevc_start(struct amvdec_session *sess) ++{ ++ struct amvdec_core *core = sess->core; ++ struct codec_hevc *hevc; ++ u32 val; ++ int i; ++ int ret; ++ ++ hevc = kzalloc(sizeof(*hevc), GFP_KERNEL); ++ if (!hevc) ++ return -ENOMEM; ++ ++ INIT_LIST_HEAD(&hevc->ref_frames_list); ++ hevc->curr_poc = INVALID_POC; ++ ++ ret = codec_hevc_setup_workspace(sess, hevc); ++ if (ret) ++ goto free_hevc; ++ ++ val = BIT(0); /* stream_fetch_enable */ ++ if (core->platform->revision >= VDEC_REVISION_G12A) ++ val |= (0xf << 25); /* arwlen_axi_max */ ++ amvdec_write_dos_bits(core, HEVC_STREAM_CONTROL, val); ++ ++ val = amvdec_read_dos(core, HEVC_PARSER_INT_CONTROL) & 0x03ffffff; ++ val |= (3 << 29) | BIT(27) | BIT(24) | BIT(22) | BIT(7) | BIT(4) | ++ BIT(0); ++ amvdec_write_dos(core, HEVC_PARSER_INT_CONTROL, val); ++ amvdec_write_dos_bits(core, HEVC_SHIFT_STATUS, BIT(1) | BIT(0)); ++ amvdec_write_dos(core, HEVC_SHIFT_CONTROL, ++ (3 << 6) | BIT(5) | BIT(2) | BIT(0)); ++ amvdec_write_dos(core, HEVC_CABAC_CONTROL, 1); ++ amvdec_write_dos(core, HEVC_PARSER_CORE_CONTROL, 1); ++ amvdec_write_dos(core, HEVC_DEC_STATUS_REG, 0); ++ ++ amvdec_write_dos(core, HEVC_IQIT_SCALELUT_WR_ADDR, 0); ++ for (i = 0; i < 1024; ++i) ++ amvdec_write_dos(core, HEVC_IQIT_SCALELUT_DATA, 0); ++ ++ amvdec_write_dos(core, HEVC_DECODE_SIZE, 0); ++ ++ amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE, BIT(16)); ++ for (i = 0; i < ARRAY_SIZE(vdec_hevc_parser_cmd); ++i) ++ amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE, ++ vdec_hevc_parser_cmd[i]); ++ ++ amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0); ++ amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1); ++ amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2); ++ amvdec_write_dos(core, HEVC_PARSER_IF_CONTROL, ++ BIT(5) | BIT(2) | BIT(0)); ++ ++ amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(0)); ++ amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(1)); ++ ++ amvdec_write_dos(core, HEVC_WAIT_FLAG, 1); ++ ++ /* clear mailbox interrupt */ ++ amvdec_write_dos(core, HEVC_ASSIST_MBOX1_CLR_REG, 1); ++ /* enable mailbox interrupt */ ++ amvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 1); ++ /* disable PSCALE for hardware sharing */ ++ amvdec_write_dos(core, HEVC_PSCALE_CTRL, 0); ++ /* Let the uCode do all the parsing */ ++ amvdec_write_dos(core, NAL_SEARCH_CTL, 0xc); ++ ++ amvdec_write_dos(core, DECODE_STOP_POS, 0); ++ amvdec_write_dos(core, HEVC_DECODE_MODE, DECODE_MODE_SINGLE); ++ amvdec_write_dos(core, HEVC_DECODE_MODE2, 0); ++ ++ /* AUX buffers */ ++ hevc->aux_vaddr = dma_alloc_coherent(core->dev, SIZE_AUX, ++ &hevc->aux_paddr, GFP_KERNEL); ++ if (!hevc->aux_vaddr) { ++ dev_err(core->dev, "Failed to request HEVC AUX\n"); ++ ret = -ENOMEM; ++ goto free_hevc; ++ } ++ ++ amvdec_write_dos(core, HEVC_AUX_ADR, hevc->aux_paddr); ++ amvdec_write_dos(core, HEVC_AUX_DATA_SIZE, ++ (((SIZE_AUX) >> 4) << 16) | 0); ++ mutex_init(&hevc->lock); ++ sess->priv = hevc; ++ ++ return 0; ++ ++free_hevc: ++ kfree(hevc); ++ return ret; ++} ++ ++static void codec_hevc_flush_output(struct amvdec_session *sess) ++{ ++ struct codec_hevc *hevc = sess->priv; ++ struct hevc_frame *tmp; ++ ++ while (!list_empty(&hevc->ref_frames_list)) { ++ tmp = codec_hevc_get_lowest_poc_frame(hevc); ++ amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE); ++ list_del(&tmp->list); ++ kfree(tmp); ++ hevc->frames_num--; ++ } ++} ++ ++static int codec_hevc_stop(struct amvdec_session *sess) ++{ ++ struct codec_hevc *hevc = sess->priv; ++ struct amvdec_core *core = sess->core; ++ ++ mutex_lock(&hevc->lock); ++ codec_hevc_flush_output(sess); ++ ++ if (hevc->workspace_vaddr) ++ dma_free_coherent(core->dev, SIZE_WORKSPACE, ++ hevc->workspace_vaddr, ++ hevc->workspace_paddr); ++ ++ if (hevc->aux_vaddr) ++ dma_free_coherent(core->dev, SIZE_AUX, ++ hevc->aux_vaddr, hevc->aux_paddr); ++ ++ codec_hevc_free_fbc_buffers(sess, &hevc->common); ++ mutex_unlock(&hevc->lock); ++ mutex_destroy(&hevc->lock); ++ ++ return 0; ++} ++ ++static struct hevc_frame * ++codec_hevc_get_frame_by_poc(struct codec_hevc *hevc, u32 poc) ++{ ++ struct hevc_frame *tmp; ++ ++ list_for_each_entry(tmp, &hevc->ref_frames_list, list) { ++ if (tmp->poc == poc) ++ return tmp; ++ } ++ ++ return NULL; ++} ++ ++static struct hevc_frame * ++codec_hevc_prepare_new_frame(struct amvdec_session *sess) ++{ ++ struct amvdec_core *core = sess->core; ++ struct hevc_frame *new_frame = NULL; ++ struct codec_hevc *hevc = sess->priv; ++ struct vb2_v4l2_buffer *vbuf; ++ union rpm_param *params = &hevc->rpm_param; ++ ++ new_frame = kzalloc(sizeof(*new_frame), GFP_KERNEL); ++ if (!new_frame) ++ return NULL; ++ ++ vbuf = v4l2_m2m_dst_buf_remove(sess->m2m_ctx); ++ if (!vbuf) { ++ dev_err(sess->core->dev, "No dst buffer available\n"); ++ return NULL; ++ } ++ ++ new_frame->vbuf = vbuf; ++ new_frame->referenced = 1; ++ new_frame->poc = hevc->curr_poc; ++ new_frame->cur_slice_type = params->p.slice_type; ++ new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0; ++ new_frame->offset = amvdec_read_dos(core, HEVC_SHIFT_BYTE_COUNT); ++ ++ list_add_tail(&new_frame->list, &hevc->ref_frames_list); ++ hevc->frames_num++; ++ ++ return new_frame; ++} ++ ++static void ++codec_hevc_set_sao(struct amvdec_session *sess, struct hevc_frame *frame) ++{ ++ struct amvdec_core *core = sess->core; ++ struct codec_hevc *hevc = sess->priv; ++ struct vb2_buffer *vb = &frame->vbuf->vb2_buf; ++ union rpm_param *param = &hevc->rpm_param; ++ u32 pic_height_cu = ++ (hevc->height + hevc->lcu_size - 1) / hevc->lcu_size; ++ u32 sao_mem_unit = (hevc->lcu_size == 16 ? 9 : ++ hevc->lcu_size == 32 ? 14 : 24) << 4; ++ u32 sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu; ++ u32 misc_flag0 = param->p.misc_flag0; ++ dma_addr_t buf_y_paddr; ++ dma_addr_t buf_u_v_paddr; ++ u32 slice_deblocking_filter_disabled_flag; ++ u32 val, val_2; ++ ++ val = (amvdec_read_dos(core, HEVC_SAO_CTRL0) & ~0xf) | ++ ilog2(hevc->lcu_size); ++ amvdec_write_dos(core, HEVC_SAO_CTRL0, val); ++ ++ amvdec_write_dos(core, HEVC_SAO_PIC_SIZE, ++ hevc->width | (hevc->height << 16)); ++ amvdec_write_dos(core, HEVC_SAO_PIC_SIZE_LCU, ++ (hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16); ++ ++ if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit) || ++ codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap, ++ hevc->is_10bit)) ++ buf_y_paddr = ++ hevc->common.fbc_buffer_paddr[vb->index]; ++ else ++ buf_y_paddr = ++ vb2_dma_contig_plane_dma_addr(vb, 0); ++ ++ if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) { ++ val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000; ++ amvdec_write_dos(core, HEVC_SAO_CTRL5, val); ++ amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr); ++ } ++ ++ if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) { ++ buf_y_paddr = ++ vb2_dma_contig_plane_dma_addr(vb, 0); ++ buf_u_v_paddr = ++ vb2_dma_contig_plane_dma_addr(vb, 1); ++ amvdec_write_dos(core, HEVC_SAO_Y_START_ADDR, buf_y_paddr); ++ amvdec_write_dos(core, HEVC_SAO_C_START_ADDR, buf_u_v_paddr); ++ amvdec_write_dos(core, HEVC_SAO_Y_WPTR, buf_y_paddr); ++ amvdec_write_dos(core, HEVC_SAO_C_WPTR, buf_u_v_paddr); ++ } ++ ++ if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap, ++ hevc->is_10bit)) { ++ dma_addr_t header_adr = vb2_dma_contig_plane_dma_addr(vb, 0); ++ if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit)) ++ header_adr = hevc->common.mmu_header_paddr[vb->index]; ++ amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr); ++ /* use HEVC_CM_HEADER_START_ADDR */ ++ amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10)); ++ amvdec_write_dos_bits(core, HEVC_SAO_CTRL9, BIT(0)); ++ } ++ ++ amvdec_write_dos(core, HEVC_SAO_Y_LENGTH, ++ amvdec_get_output_size(sess)); ++ amvdec_write_dos(core, HEVC_SAO_C_LENGTH, ++ (amvdec_get_output_size(sess) / 2)); ++ ++ if (frame->cur_slice_idx == 0) { ++ if (core->platform->revision >= VDEC_REVISION_G12A) { ++ if (core->platform->revision >= VDEC_REVISION_SM1) ++ val = 0xfc << 8; ++ else ++ val = 0x54 << 8; ++ ++ /* enable first, compressed write */ ++ if (codec_hevc_use_fbc(sess->pixfmt_cap, ++ hevc->is_10bit)) ++ val |= BIT(8); ++ ++ /* enable second, uncompressed write */ ++ if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) ++ val |= BIT(9); ++ ++ /* dblk pipeline mode=1 for performance */ ++ if (hevc->width >= 1280) ++ val |= BIT(4); ++ ++ amvdec_write_dos(core, HEVC_DBLK_CFGB, val); ++ amvdec_write_dos(core, HEVC_DBLK_STS1 + 16, BIT(28)); ++ } ++ ++ amvdec_write_dos(core, HEVC_DBLK_CFG2, ++ hevc->width | (hevc->height << 16)); ++ ++ val = 0; ++ if ((misc_flag0 >> PCM_ENABLE_FLAG_BIT) & 0x1) ++ val |= ((misc_flag0 >> ++ PCM_LOOP_FILTER_DISABLED_FLAG_BIT) & 0x1) << 3; ++ ++ val |= (param->p.pps_cb_qp_offset & 0x1f) << 4; ++ val |= (param->p.pps_cr_qp_offset & 0x1f) << 9; ++ val |= (hevc->lcu_size == 64) ? 0 : ++ ((hevc->lcu_size == 32) ? 1 : 2); ++ amvdec_write_dos(core, HEVC_DBLK_CFG1, val); ++ } ++ ++ val = amvdec_read_dos(core, HEVC_SAO_CTRL1) & ~0x3ff3; ++ val |= 0xff0; /* Set endianness for 2-bytes swaps (nv12) */ ++ if (core->platform->revision < VDEC_REVISION_G12A) { ++ if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) ++ val |= BIT(0); /* disable cm compression */ ++ /* TOFIX: Handle Amlogic Framebuffer compression */ ++ } ++ ++ amvdec_write_dos(core, HEVC_SAO_CTRL1, val); ++ ++ if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) { ++ /* no downscale for NV12 */ ++ val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000; ++ amvdec_write_dos(core, HEVC_SAO_CTRL5, val); ++ } ++ ++ val = amvdec_read_dos(core, HEVCD_IPP_AXIIF_CONFIG) & ~0x30; ++ val |= 0xf; ++ amvdec_write_dos(core, HEVCD_IPP_AXIIF_CONFIG, val); ++ ++ val = 0; ++ val_2 = amvdec_read_dos(core, HEVC_SAO_CTRL0); ++ val_2 &= (~0x300); ++ ++ slice_deblocking_filter_disabled_flag = (misc_flag0 >> ++ SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1; ++ if ((misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT)) ++ && (misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT))) { ++ val |= slice_deblocking_filter_disabled_flag << 2; ++ ++ if (!slice_deblocking_filter_disabled_flag) { ++ val |= (param->p.slice_beta_offset_div2 & 0xf) << 3; ++ val |= (param->p.slice_tc_offset_div2 & 0xf) << 7; ++ } ++ } else { ++ val |= ++ ((misc_flag0 >> ++ PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1) << 2; ++ ++ if (((misc_flag0 >> PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & ++ 0x1) == 0) { ++ val |= (param->p.pps_beta_offset_div2 & 0xf) << 3; ++ val |= (param->p.pps_tc_offset_div2 & 0xf) << 7; ++ } ++ } ++ if ((misc_flag0 & (1 << PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)) ++ && ((misc_flag0 & (1 << SLICE_SAO_LUMA_FLAG_BIT)) ++ || (misc_flag0 & (1 << SLICE_SAO_CHROMA_FLAG_BIT)) ++ || (!slice_deblocking_filter_disabled_flag))) { ++ val |= ++ ((misc_flag0 >> ++ SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT) ++ & 0x1) << 1; ++ val_2 |= ++ ((misc_flag0 >> ++ SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT) ++ & 0x1) << 9; ++ } else { ++ val |= ++ ((misc_flag0 >> ++ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT) ++ & 0x1) << 1; ++ val_2 |= ++ ((misc_flag0 >> ++ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT) ++ & 0x1) << 9; ++ } ++ ++ amvdec_write_dos(core, HEVC_DBLK_CFG9, val); ++ amvdec_write_dos(core, HEVC_SAO_CTRL0, val_2); ++ ++ amvdec_write_dos(core, HEVC_sao_mem_unit, sao_mem_unit); ++ amvdec_write_dos(core, HEVC_SAO_ABV, ++ hevc->workspace_paddr + SAO_ABV_OFFSET); ++ amvdec_write_dos(core, HEVC_sao_vb_size, sao_vb_size); ++ amvdec_write_dos(core, HEVC_SAO_VB, ++ hevc->workspace_paddr + SAO_VB_OFFSET); ++} ++ ++static dma_addr_t codec_hevc_get_frame_mv_paddr(struct codec_hevc *hevc, ++ struct hevc_frame *frame) ++{ ++ return hevc->workspace_paddr + MPRED_MV_OFFSET + ++ (frame->vbuf->vb2_buf.index * MPRED_MV_BUF_SIZE); ++} ++ ++static void ++codec_hevc_set_mpred_ctrl(struct amvdec_core *core, struct codec_hevc *hevc) ++{ ++ union rpm_param *param = &hevc->rpm_param; ++ u32 slice_type = param->p.slice_type; ++ u32 lcu_size_log2 = ilog2(hevc->lcu_size); ++ u32 val; ++ ++ val = slice_type | ++ MPRED_CTRL0_ABOVE_EN | ++ MPRED_CTRL0_MV_WR_EN | ++ MPRED_CTRL0_BUF_LINEAR | ++ (lcu_size_log2 << 16) | ++ (3 << 20) | /* cu_size_log2 */ ++ (param->p.log2_parallel_merge_level << 24); ++ ++ if (slice_type != I_SLICE) ++ val |= MPRED_CTRL0_MV_RD_EN; ++ ++ if (param->p.collocated_from_l0_flag) ++ val |= MPRED_CTRL0_COL_FROM_L0; ++ ++ if (param->p.slice_temporal_mvp_enable_flag) ++ val |= MPRED_CTRL0_TMVP; ++ ++ if (hevc->ldc_flag) ++ val |= MPRED_CTRL0_LDC; ++ ++ if (param->p.dependent_slice_segment_flag) ++ val |= MPRED_CTRL0_NEW_SLI_SEG; ++ ++ if (param->p.slice_segment_address == 0) ++ val |= MPRED_CTRL0_NEW_PIC | ++ MPRED_CTRL0_NEW_TILE; ++ ++ amvdec_write_dos(core, HEVC_MPRED_CTRL0, val); ++ ++ val = (5 - param->p.five_minus_max_num_merge_cand) | ++ (AMVP_MAX_NUM_CANDS << 4) | ++ (AMVP_MAX_NUM_CANDS_MEM << 8) | ++ (NUM_CHROMA_MODE << 12) | ++ (DM_CHROMA_IDX << 16); ++ amvdec_write_dos(core, HEVC_MPRED_CTRL1, val); ++} ++ ++static void codec_hevc_set_mpred_mv(struct amvdec_core *core, ++ struct codec_hevc *hevc, ++ struct hevc_frame *frame, ++ struct hevc_frame *col_frame) ++{ ++ union rpm_param *param = &hevc->rpm_param; ++ u32 lcu_size_log2 = ilog2(hevc->lcu_size); ++ u32 mv_mem_unit = lcu_size_log2 == 6 ? 0x200 : ++ lcu_size_log2 == 5 ? 0x80 : 0x20; ++ dma_addr_t col_mv_rd_start_addr, col_mv_rd_ptr, col_mv_rd_end_addr; ++ dma_addr_t mpred_mv_wr_ptr; ++ u32 val; ++ ++ val = amvdec_read_dos(core, HEVC_MPRED_CURR_LCU); ++ ++ col_mv_rd_start_addr = codec_hevc_get_frame_mv_paddr(hevc, col_frame); ++ mpred_mv_wr_ptr = codec_hevc_get_frame_mv_paddr(hevc, frame) + ++ (hevc->slice_addr * mv_mem_unit); ++ col_mv_rd_ptr = col_mv_rd_start_addr + ++ (hevc->slice_addr * mv_mem_unit); ++ col_mv_rd_end_addr = col_mv_rd_start_addr + ++ (hevc->lcu_total * mv_mem_unit); ++ ++ amvdec_write_dos(core, HEVC_MPRED_MV_WR_START_ADDR, ++ codec_hevc_get_frame_mv_paddr(hevc, frame)); ++ amvdec_write_dos(core, HEVC_MPRED_MV_RD_START_ADDR, ++ col_mv_rd_start_addr); ++ ++ if (param->p.slice_segment_address == 0) { ++ amvdec_write_dos(core, HEVC_MPRED_ABV_START_ADDR, ++ hevc->workspace_paddr + MPRED_ABV_OFFSET); ++ amvdec_write_dos(core, HEVC_MPRED_MV_WPTR, mpred_mv_wr_ptr); ++ amvdec_write_dos(core, HEVC_MPRED_MV_RPTR, ++ col_mv_rd_start_addr); ++ } else { ++ amvdec_write_dos(core, HEVC_MPRED_MV_RPTR, col_mv_rd_ptr); ++ } ++ ++ amvdec_write_dos(core, HEVC_MPRED_MV_RD_END_ADDR, col_mv_rd_end_addr); ++} ++ ++/* Update motion prediction with the current slice */ ++static void codec_hevc_set_mpred(struct amvdec_session *sess, ++ struct hevc_frame *frame, ++ struct hevc_frame *col_frame) ++{ ++ struct amvdec_core *core = sess->core; ++ struct codec_hevc *hevc = sess->priv; ++ u32 *ref_num = frame->ref_num; ++ u32 *ref_poc_l0 = frame->ref_poc_list[0][frame->cur_slice_idx]; ++ u32 *ref_poc_l1 = frame->ref_poc_list[1][frame->cur_slice_idx]; ++ u32 val; ++ int i; ++ ++ codec_hevc_set_mpred_ctrl(core, hevc); ++ codec_hevc_set_mpred_mv(core, hevc, frame, col_frame); ++ ++ amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE, ++ hevc->width | (hevc->height << 16)); ++ ++ val = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16); ++ amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE_LCU, val); ++ ++ amvdec_write_dos(core, HEVC_MPRED_REF_NUM, ++ (ref_num[1] << 8) | ref_num[0]); ++ amvdec_write_dos(core, HEVC_MPRED_REF_EN_L0, (1 << ref_num[0]) - 1); ++ amvdec_write_dos(core, HEVC_MPRED_REF_EN_L1, (1 << ref_num[1]) - 1); ++ ++ amvdec_write_dos(core, HEVC_MPRED_CUR_POC, hevc->curr_poc); ++ amvdec_write_dos(core, HEVC_MPRED_COL_POC, hevc->col_poc); ++ ++ for (i = 0; i < MAX_REF_ACTIVE; ++i) { ++ amvdec_write_dos(core, HEVC_MPRED_L0_REF00_POC + i * 4, ++ ref_poc_l0[i]); ++ amvdec_write_dos(core, HEVC_MPRED_L1_REF00_POC + i * 4, ++ ref_poc_l1[i]); ++ } ++} ++ ++/* motion compensation reference cache controller */ ++static void codec_hevc_set_mcrcc(struct amvdec_session *sess) ++{ ++ struct amvdec_core *core = sess->core; ++ struct codec_hevc *hevc = sess->priv; ++ u32 val, val_2; ++ int l0_cnt = 0; ++ int l1_cnt = 0x7fff; ++ ++ if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) { ++ l0_cnt = hevc->cur_frame->ref_num[0]; ++ l1_cnt = hevc->cur_frame->ref_num[1]; ++ } ++ ++ if (hevc->cur_frame->cur_slice_type == I_SLICE) { ++ amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0); ++ return; ++ } ++ ++ if (hevc->cur_frame->cur_slice_type == P_SLICE) { ++ amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, ++ BIT(1)); ++ val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR); ++ val &= 0xffff; ++ val |= (val << 16); ++ amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val); ++ ++ if (l0_cnt == 1) { ++ amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val); ++ } else { ++ val = amvdec_read_dos(core, ++ HEVCD_MPP_ANC_CANVAS_DATA_ADDR); ++ val &= 0xffff; ++ val |= (val << 16); ++ amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val); ++ } ++ } else { /* B_SLICE */ ++ amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 0); ++ val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR); ++ val &= 0xffff; ++ val |= (val << 16); ++ amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val); ++ ++ amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, ++ BIT(12) | BIT(1)); ++ val_2 = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR); ++ val_2 &= 0xffff; ++ val_2 |= (val_2 << 16); ++ if (val == val_2 && l1_cnt > 1) { ++ val_2 = amvdec_read_dos(core, ++ HEVCD_MPP_ANC_CANVAS_DATA_ADDR); ++ val_2 &= 0xffff; ++ val_2 |= (val_2 << 16); ++ } ++ amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val); ++ } ++ ++ /* enable mcrcc progressive-mode */ ++ amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0xff0); ++} ++ ++static void codec_hevc_set_ref_list(struct amvdec_session *sess, ++ u32 ref_num, u32 *ref_poc_list) ++{ ++ struct codec_hevc *hevc = sess->priv; ++ struct hevc_frame *ref_frame; ++ struct amvdec_core *core = sess->core; ++ int i; ++ u32 buf_id_y; ++ u32 buf_id_uv; ++ ++ for (i = 0; i < ref_num; i++) { ++ ref_frame = codec_hevc_get_frame_by_poc(hevc, ref_poc_list[i]); ++ ++ if (!ref_frame) { ++ dev_warn(core->dev, "Couldn't find ref. frame %u\n", ++ ref_poc_list[i]); ++ continue; ++ } ++ ++ if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) { ++ buf_id_y = buf_id_uv = ref_frame->vbuf->vb2_buf.index; ++ } else { ++ buf_id_y = ref_frame->vbuf->vb2_buf.index * 2; ++ buf_id_uv = buf_id_y + 1; ++ } ++ ++ amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ++ (buf_id_uv << 16) | ++ (buf_id_uv << 8) | ++ buf_id_y); ++ } ++} ++ ++static void codec_hevc_set_mc(struct amvdec_session *sess, ++ struct hevc_frame *frame) ++{ ++ struct amvdec_core *core = sess->core; ++ ++ if (frame->cur_slice_type == I_SLICE) ++ return; ++ ++ amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1); ++ codec_hevc_set_ref_list(sess, frame->ref_num[0], ++ frame->ref_poc_list[0][frame->cur_slice_idx]); ++ ++ if (frame->cur_slice_type == P_SLICE) ++ return; ++ ++ amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, ++ BIT(12) | BIT(0)); ++ codec_hevc_set_ref_list(sess, frame->ref_num[1], ++ frame->ref_poc_list[1][frame->cur_slice_idx]); ++} ++ ++static void codec_hevc_update_col_frame(struct codec_hevc *hevc) ++{ ++ struct hevc_frame *cur_frame = hevc->cur_frame; ++ union rpm_param *param = &hevc->rpm_param; ++ u32 list_no = 0; ++ u32 col_ref = param->p.collocated_ref_idx; ++ u32 col_from_l0 = param->p.collocated_from_l0_flag; ++ u32 cur_slice_idx = cur_frame->cur_slice_idx; ++ ++ if (cur_frame->cur_slice_type == B_SLICE) ++ list_no = 1 - col_from_l0; ++ ++ if (col_ref >= cur_frame->ref_num[list_no]) ++ hevc->col_poc = INVALID_POC; ++ else ++ hevc->col_poc = cur_frame->ref_poc_list[list_no] ++ [cur_slice_idx] ++ [col_ref]; ++ ++ if (cur_frame->cur_slice_type == I_SLICE) ++ goto end; ++ ++ if (hevc->col_poc != INVALID_POC) ++ hevc->col_frame = codec_hevc_get_frame_by_poc(hevc, ++ hevc->col_poc); ++ else ++ hevc->col_frame = hevc->cur_frame; ++ ++end: ++ if (!hevc->col_frame) ++ hevc->col_frame = hevc->cur_frame; ++} ++ ++static void codec_hevc_update_pocs(struct amvdec_session *sess) ++{ ++ struct codec_hevc *hevc = sess->priv; ++ union rpm_param *param = &hevc->rpm_param; ++ u32 nal_unit_type = param->p.m_nalUnitType; ++ u32 temporal_id = param->p.m_temporalId & 0x7; ++ int max_poc_lsb = ++ 1 << (param->p.log2_max_pic_order_cnt_lsb_minus4 + 4); ++ int prev_poc_lsb; ++ int prev_poc_msb; ++ int poc_msb; ++ int poc_lsb = param->p.POClsb; ++ ++ if (nal_unit_type == NAL_UNIT_CODED_SLICE_IDR || ++ nal_unit_type == NAL_UNIT_CODED_SLICE_IDR_N_LP) { ++ hevc->curr_poc = 0; ++ if ((temporal_id - 1) == 0) ++ hevc->prev_tid0_poc = hevc->curr_poc; ++ ++ return; ++ } ++ ++ prev_poc_lsb = hevc->prev_tid0_poc % max_poc_lsb; ++ prev_poc_msb = hevc->prev_tid0_poc - prev_poc_lsb; ++ ++ if ((poc_lsb < prev_poc_lsb) && ++ ((prev_poc_lsb - poc_lsb) >= (max_poc_lsb / 2))) ++ poc_msb = prev_poc_msb + max_poc_lsb; ++ else if ((poc_lsb > prev_poc_lsb) && ++ ((poc_lsb - prev_poc_lsb) > (max_poc_lsb / 2))) ++ poc_msb = prev_poc_msb - max_poc_lsb; ++ else ++ poc_msb = prev_poc_msb; ++ ++ if (nal_unit_type == NAL_UNIT_CODED_SLICE_BLA || ++ nal_unit_type == NAL_UNIT_CODED_SLICE_BLANT || ++ nal_unit_type == NAL_UNIT_CODED_SLICE_BLA_N_LP) ++ poc_msb = 0; ++ ++ hevc->curr_poc = (poc_msb + poc_lsb); ++ if ((temporal_id - 1) == 0) ++ hevc->prev_tid0_poc = hevc->curr_poc; ++} ++ ++static void codec_hevc_process_segment_header(struct amvdec_session *sess) ++{ ++ struct codec_hevc *hevc = sess->priv; ++ union rpm_param *param = &hevc->rpm_param; ++ ++ if (param->p.first_slice_segment_in_pic_flag == 0) { ++ hevc->slice_segment_addr = param->p.slice_segment_address; ++ if (!param->p.dependent_slice_segment_flag) ++ hevc->slice_addr = hevc->slice_segment_addr; ++ } else { ++ hevc->slice_segment_addr = 0; ++ hevc->slice_addr = 0; ++ } ++ ++ codec_hevc_update_pocs(sess); ++} ++ ++static int codec_hevc_process_segment(struct amvdec_session *sess) ++{ ++ struct codec_hevc *hevc = sess->priv; ++ struct amvdec_core *core = sess->core; ++ union rpm_param *param = &hevc->rpm_param; ++ u32 slice_segment_address = param->p.slice_segment_address; ++ ++ /* First slice: new frame */ ++ if (slice_segment_address == 0) { ++ codec_hevc_update_referenced(hevc); ++ codec_hevc_output_frames(sess); ++ ++ hevc->cur_frame = codec_hevc_prepare_new_frame(sess); ++ if (!hevc->cur_frame) ++ return -1; ++ } else { ++ hevc->cur_frame->cur_slice_idx++; ++ } ++ ++ codec_hevc_update_frame_refs(sess, hevc->cur_frame); ++ codec_hevc_update_col_frame(hevc); ++ codec_hevc_update_ldc_flag(hevc); ++ if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap, ++ hevc->is_10bit)) ++ codec_hevc_fill_mmu_map(sess, &hevc->common, ++ &hevc->cur_frame->vbuf->vb2_buf, ++ hevc->is_10bit); ++ codec_hevc_set_mc(sess, hevc->cur_frame); ++ codec_hevc_set_mcrcc(sess); ++ codec_hevc_set_mpred(sess, hevc->cur_frame, hevc->col_frame); ++ codec_hevc_set_sao(sess, hevc->cur_frame); ++ ++ amvdec_write_dos_bits(core, HEVC_WAIT_FLAG, BIT(1)); ++ amvdec_write_dos(core, HEVC_DEC_STATUS_REG, ++ HEVC_CODED_SLICE_SEGMENT_DAT); ++ ++ /* Interrupt the firmware's processor */ ++ amvdec_write_dos(core, HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ); ++ ++ return 0; ++} ++ ++static int codec_hevc_process_rpm(struct codec_hevc *hevc) ++{ ++ union rpm_param *param = &hevc->rpm_param; ++ int src_changed = 0; ++ u32 dst_width, dst_height; ++ u32 lcu_size; ++ u32 is_10bit = 0; ++ ++ if (param->p.slice_segment_address || ++ !param->p.pic_width_in_luma_samples || ++ !param->p.pic_height_in_luma_samples) ++ return 0; ++ ++ if (param->p.bit_depth) ++ is_10bit = 1; ++ ++ hevc->width = param->p.pic_width_in_luma_samples; ++ hevc->height = param->p.pic_height_in_luma_samples; ++ dst_width = hevc->width; ++ dst_height = hevc->height; ++ ++ lcu_size = 1 << (param->p.log2_min_coding_block_size_minus3 + ++ 3 + param->p.log2_diff_max_min_coding_block_size); ++ ++ hevc->lcu_x_num = (hevc->width + lcu_size - 1) / lcu_size; ++ hevc->lcu_y_num = (hevc->height + lcu_size - 1) / lcu_size; ++ hevc->lcu_total = hevc->lcu_x_num * hevc->lcu_y_num; ++ ++ if (param->p.conformance_window_flag) { ++ u32 sub_width = 1, sub_height = 1; ++ ++ switch (param->p.chroma_format_idc) { ++ case 1: ++ sub_height = 2; /* fallthrough */ ++ case 2: ++ sub_width = 2; ++ break; ++ } ++ ++ dst_width -= sub_width * ++ (param->p.conf_win_left_offset + ++ param->p.conf_win_right_offset); ++ dst_height -= sub_height * ++ (param->p.conf_win_top_offset + ++ param->p.conf_win_bottom_offset); ++ } ++ ++ if (dst_width != hevc->dst_width || ++ dst_height != hevc->dst_height || ++ lcu_size != hevc->lcu_size || ++ is_10bit != hevc->is_10bit) ++ src_changed = 1; ++ ++ hevc->dst_width = dst_width; ++ hevc->dst_height = dst_height; ++ hevc->lcu_size = lcu_size; ++ hevc->is_10bit = is_10bit; ++ ++ return src_changed; ++} ++ ++/* ++ * The RPM section within the workspace contains ++ * many information regarding the parsed bitstream ++ */ ++static void codec_hevc_fetch_rpm(struct amvdec_session *sess) ++{ ++ struct codec_hevc *hevc = sess->priv; ++ u16 *rpm_vaddr = hevc->workspace_vaddr + RPM_OFFSET; ++ int i, j; ++ ++ for (i = 0; i < RPM_SIZE; i += 4) ++ for (j = 0; j < 4; j++) ++ hevc->rpm_param.l.data[i + j] = rpm_vaddr[i + 3 - j]; ++} ++ ++static void codec_hevc_resume(struct amvdec_session *sess) ++{ ++ struct codec_hevc *hevc = sess->priv; ++ ++ if (codec_hevc_setup_buffers(sess, &hevc->common, hevc->is_10bit)) { ++ amvdec_abort(sess); ++ return; ++ } ++ ++ codec_hevc_setup_decode_head(sess, hevc->is_10bit); ++ codec_hevc_process_segment_header(sess); ++ if (codec_hevc_process_segment(sess)) ++ amvdec_abort(sess); ++} ++ ++static irqreturn_t codec_hevc_threaded_isr(struct amvdec_session *sess) ++{ ++ struct amvdec_core *core = sess->core; ++ struct codec_hevc *hevc = sess->priv; ++ u32 dec_status = amvdec_read_dos(core, HEVC_DEC_STATUS_REG); ++ ++ if (!hevc) ++ return IRQ_HANDLED; ++ ++ mutex_lock(&hevc->lock); ++ if (dec_status != HEVC_SLICE_SEGMENT_DONE) { ++ dev_err(core->dev_dec, "Unrecognized dec_status: %08X\n", ++ dec_status); ++ amvdec_abort(sess); ++ goto unlock; ++ } ++ ++ sess->keyframe_found = 1; ++ codec_hevc_fetch_rpm(sess); ++ if (codec_hevc_process_rpm(hevc)) { ++ amvdec_src_change(sess, hevc->dst_width, hevc->dst_height, 16, ++ hevc->is_10bit ? 10 : 8); ++ goto unlock; ++ } ++ ++ codec_hevc_process_segment_header(sess); ++ if (codec_hevc_process_segment(sess)) ++ amvdec_abort(sess); ++ ++unlock: ++ mutex_unlock(&hevc->lock); ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t codec_hevc_isr(struct amvdec_session *sess) ++{ ++ return IRQ_WAKE_THREAD; ++} ++ ++struct amvdec_codec_ops codec_hevc_ops = { ++ .start = codec_hevc_start, ++ .stop = codec_hevc_stop, ++ .isr = codec_hevc_isr, ++ .threaded_isr = codec_hevc_threaded_isr, ++ .num_pending_bufs = codec_hevc_num_pending_bufs, ++ .drain = codec_hevc_flush_output, ++ .resume = codec_hevc_resume, ++}; +diff --git a/drivers/staging/media/meson/vdec/codec_hevc.h b/drivers/staging/media/meson/vdec/codec_hevc.h +new file mode 100644 +index 000000000000..f2f9b2464df1 +--- /dev/null ++++ b/drivers/staging/media/meson/vdec/codec_hevc.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2018 Maxime Jourdan ++ */ ++ ++#ifndef __MESON_VDEC_CODEC_HEVC_H_ ++#define __MESON_VDEC_CODEC_HEVC_H_ ++ ++#include "vdec.h" ++ ++extern struct amvdec_codec_ops codec_hevc_ops; ++ ++#endif +diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c +index 610a92b9f6f2..9b6034936d32 100644 +--- a/drivers/staging/media/meson/vdec/esparser.c ++++ b/drivers/staging/media/meson/vdec/esparser.c +@@ -309,7 +309,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf) + * they could pause when there is no capture buffer available and + * resume on this notification. + */ +- if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9) { ++ if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9 || sess->fmt_out->pixfmt ==V4L2_PIX_FMT_HEVC) { + if (codec_ops->num_pending_bufs) + num_dst_bufs = codec_ops->num_pending_bufs(sess); + +diff --git a/drivers/staging/media/meson/vdec/hevc_regs.h b/drivers/staging/media/meson/vdec/hevc_regs.h +index 0392f41a1eed..e7eabdd2b119 100644 +--- a/drivers/staging/media/meson/vdec/hevc_regs.h ++++ b/drivers/staging/media/meson/vdec/hevc_regs.h +@@ -205,6 +205,7 @@ + #define HEVC_CM_HEADER_START_ADDR 0xd8a0 + #define HEVC_CM_HEADER_LENGTH 0xd8a4 + #define HEVC_CM_HEADER_OFFSET 0xd8ac ++#define HEVC_SAO_CTRL9 0xd8b4 + #define HEVC_SAO_MMU_VH0_ADDR 0xd8e8 + #define HEVC_SAO_MMU_VH1_ADDR 0xd8ec + +diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c +index 88c9d72e1c83..8592cb3aaea9 100644 +--- a/drivers/staging/media/meson/vdec/vdec_platform.c ++++ b/drivers/staging/media/meson/vdec/vdec_platform.c +@@ -11,6 +11,7 @@ + #include "vdec_hevc.h" + #include "codec_mpeg12.h" + #include "codec_h264.h" ++#include "codec_hevc.h" + #include "codec_vp9.h" + + static const struct amvdec_format vdec_formats_gxbb[] = { +@@ -64,6 +65,18 @@ static const struct amvdec_format vdec_formats_gxl[] = { + .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, + .flags = V4L2_FMT_FLAG_COMPRESSED | + V4L2_FMT_FLAG_DYN_RESOLUTION, ++ }, { ++ .pixfmt = V4L2_PIX_FMT_HEVC, ++ .min_buffers = 4, ++ .max_buffers = 24, ++ .max_width = 3840, ++ .max_height = 2160, ++ .vdec_ops = &vdec_hevc_ops, ++ .codec_ops = &codec_hevc_ops, ++ .firmware_path = "meson/vdec/gxl_hevc.bin", ++ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, ++ .flags = V4L2_FMT_FLAG_COMPRESSED | ++ V4L2_FMT_FLAG_DYN_RESOLUTION, + }, { + .pixfmt = V4L2_PIX_FMT_H264, + .min_buffers = 2, +@@ -114,6 +127,18 @@ static const struct amvdec_format vdec_formats_gxm[] = { + .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, + .flags = V4L2_FMT_FLAG_COMPRESSED | + V4L2_FMT_FLAG_DYN_RESOLUTION, ++ }, { ++ .pixfmt = V4L2_PIX_FMT_HEVC, ++ .min_buffers = 4, ++ .max_buffers = 24, ++ .max_width = 3840, ++ .max_height = 2160, ++ .vdec_ops = &vdec_hevc_ops, ++ .codec_ops = &codec_hevc_ops, ++ .firmware_path = "meson/vdec/gxl_hevc.bin", ++ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, ++ .flags = V4L2_FMT_FLAG_COMPRESSED | ++ V4L2_FMT_FLAG_DYN_RESOLUTION, + }, { + .pixfmt = V4L2_PIX_FMT_H264, + .min_buffers = 2, +@@ -165,6 +190,18 @@ static const struct amvdec_format vdec_formats_g12a[] = { + .flags = V4L2_FMT_FLAG_COMPRESSED | + V4L2_FMT_FLAG_DYN_RESOLUTION, + }, { ++ .pixfmt = V4L2_PIX_FMT_HEVC, ++ .min_buffers = 4, ++ .max_buffers = 24, ++ .max_width = 3840, ++ .max_height = 2160, ++ .vdec_ops = &vdec_hevc_ops, ++ .codec_ops = &codec_hevc_ops, ++ .firmware_path = "meson/vdec/g12a_hevc_mmu.bin", ++ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, ++ .flags = V4L2_FMT_FLAG_COMPRESSED | ++ V4L2_FMT_FLAG_DYN_RESOLUTION, ++ },{ + .pixfmt = V4L2_PIX_FMT_H264, + .min_buffers = 2, + .max_buffers = 24, +@@ -214,6 +251,18 @@ static const struct amvdec_format vdec_formats_sm1[] = { + .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, + .flags = V4L2_FMT_FLAG_COMPRESSED | + V4L2_FMT_FLAG_DYN_RESOLUTION, ++ }, { ++ .pixfmt = V4L2_PIX_FMT_HEVC, ++ .min_buffers = 4, ++ .max_buffers = 24, ++ .max_width = 3840, ++ .max_height = 2160, ++ .vdec_ops = &vdec_hevc_ops, ++ .codec_ops = &codec_hevc_ops, ++ .firmware_path = "meson/vdec/sm1_hevc_mmu.bin", ++ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, ++ .flags = V4L2_FMT_FLAG_COMPRESSED | ++ V4L2_FMT_FLAG_DYN_RESOLUTION, + }, { + .pixfmt = V4L2_PIX_FMT_H264, + .min_buffers = 2, +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-meson-vdec-add-handling-to-HEVC-decoder-.patch b/patch/kernel/archive/meson64-5.19/general-meson-vdec-add-handling-to-HEVC-decoder-.patch new file mode 100644 index 000000000..93b3af995 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-meson-vdec-add-handling-to-HEVC-decoder-.patch @@ -0,0 +1,157 @@ +From a9f750c672c4c1238cccd1d8d76a138a5602d035 Mon Sep 17 00:00:00 2001 +From: benjamin545 +Date: Mon, 2 Aug 2021 15:18:40 -0400 +Subject: [PATCH 65/90] WIP: drivers: meson: vdec: add handling to HEVC decoder + to show frames when ready + +..rather than when no longer referenced + +the HEVC decode driver would not show the next frame until it was no longer referenced, +this would cause a backup of frames that were ready to render but held up by one or more +frames that were still referenced. The decoded picture buffer would fill up and stall +playback as no new frames could be placed in the decoded picture buffer. +--- + drivers/staging/media/meson/vdec/codec_hevc.c | 52 ++++++++++++------- + 1 file changed, 34 insertions(+), 18 deletions(-) + +diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c +index 3a6fd04a2d33..01218efde99b 100644 +--- a/drivers/staging/media/meson/vdec/codec_hevc.c ++++ b/drivers/staging/media/meson/vdec/codec_hevc.c +@@ -223,6 +223,7 @@ struct hevc_frame { + u32 poc; + + int referenced; ++ int show; + u32 num_reorder_pic; + + u32 cur_slice_idx; +@@ -448,9 +449,11 @@ static void codec_hevc_update_referenced(struct codec_hevc *hevc) + ((1 << (RPS_USED_BIT - 1)) - 1); + if (param->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) { + poc_tmp = curr_poc - +- ((1 << (RPS_USED_BIT - 1)) - delt); +- } else ++ ((1 << (RPS_USED_BIT - 1)) - delt); ++ } else { + poc_tmp = curr_poc + delt; ++ } ++ + if (poc_tmp == frame->poc) { + is_referenced = 1; + break; +@@ -462,13 +465,13 @@ static void codec_hevc_update_referenced(struct codec_hevc *hevc) + } + + static struct hevc_frame * +-codec_hevc_get_lowest_poc_frame(struct codec_hevc *hevc) ++codec_hevc_get_next_ready_frame(struct codec_hevc *hevc) + { + struct hevc_frame *tmp, *ret = NULL; + u32 poc = INT_MAX; + + list_for_each_entry(tmp, &hevc->ref_frames_list, list) { +- if (tmp->poc < poc) { ++ if ((tmp->poc < poc) && tmp->show) { + ret = tmp; + poc = tmp->poc; + } +@@ -478,28 +481,35 @@ codec_hevc_get_lowest_poc_frame(struct codec_hevc *hevc) + } + + /* Try to output as many frames as possible */ +-static void codec_hevc_output_frames(struct amvdec_session *sess) ++static void codec_hevc_show_frames(struct amvdec_session *sess) + { +- struct hevc_frame *tmp; ++ struct hevc_frame *tmp, *n; + struct codec_hevc *hevc = sess->priv; + +- while ((tmp = codec_hevc_get_lowest_poc_frame(hevc))) { ++ while ((tmp = codec_hevc_get_next_ready_frame(hevc))) { + if (hevc->curr_poc && +- (tmp->referenced || +- tmp->num_reorder_pic >= hevc->frames_num)) ++ (hevc->frames_num <= tmp->num_reorder_pic)) + break; + + dev_dbg(sess->core->dev, "DONE frame poc %u; vbuf %u\n", + tmp->poc, tmp->vbuf->vb2_buf.index); + amvdec_dst_buf_done_offset(sess, tmp->vbuf, tmp->offset, + V4L2_FIELD_NONE, false); ++ ++ tmp->show = 0; ++ hevc->frames_num--; ++ } ++ ++ /* clean output frame buffer */ ++ list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) { ++ if (tmp->referenced || tmp->show) ++ continue; ++ + list_del(&tmp->list); + kfree(tmp); +- hevc->frames_num--; + } + } + +- + static int + codec_hevc_setup_workspace(struct amvdec_session *sess, + struct codec_hevc *hevc) +@@ -650,14 +660,17 @@ static int codec_hevc_start(struct amvdec_session *sess) + static void codec_hevc_flush_output(struct amvdec_session *sess) + { + struct codec_hevc *hevc = sess->priv; +- struct hevc_frame *tmp; ++ struct hevc_frame *tmp, *n; + +- while (!list_empty(&hevc->ref_frames_list)) { +- tmp = codec_hevc_get_lowest_poc_frame(hevc); ++ while ((tmp = codec_hevc_get_next_ready_frame(hevc))) { + amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE); ++ tmp->show = 0; ++ hevc->frames_num--; ++ } ++ ++ list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) { + list_del(&tmp->list); + kfree(tmp); +- hevc->frames_num--; + } + } + +@@ -719,6 +732,7 @@ codec_hevc_prepare_new_frame(struct amvdec_session *sess) + + new_frame->vbuf = vbuf; + new_frame->referenced = 1; ++ new_frame->show = 1; + new_frame->poc = hevc->curr_poc; + new_frame->cur_slice_type = params->p.slice_type; + new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0; +@@ -1267,7 +1281,7 @@ static int codec_hevc_process_segment(struct amvdec_session *sess) + /* First slice: new frame */ + if (slice_segment_address == 0) { + codec_hevc_update_referenced(hevc); +- codec_hevc_output_frames(sess); ++ codec_hevc_show_frames(sess); + + hevc->cur_frame = codec_hevc_prepare_new_frame(sess); + if (!hevc->cur_frame) +@@ -1370,9 +1384,11 @@ static void codec_hevc_fetch_rpm(struct amvdec_session *sess) + u16 *rpm_vaddr = hevc->workspace_vaddr + RPM_OFFSET; + int i, j; + +- for (i = 0; i < RPM_SIZE; i += 4) ++ for (i = 0; i < RPM_SIZE; i += 4) { + for (j = 0; j < 4; j++) +- hevc->rpm_param.l.data[i + j] = rpm_vaddr[i + 3 - j]; ++ hevc->rpm_param.l.data[i + j] = ++ rpm_vaddr[i + 3 - j]; ++ } + } + + static void codec_hevc_resume(struct amvdec_session *sess) +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-meson-vdec-check-if-parser-has-really-parser.patch b/patch/kernel/archive/meson64-5.19/general-meson-vdec-check-if-parser-has-really-parser.patch new file mode 100644 index 000000000..7b92ede85 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-meson-vdec-check-if-parser-has-really-parser.patch @@ -0,0 +1,51 @@ +From cb0c20e84a934c66961ace27f340cd7c98188dbe Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Mon, 22 Nov 2021 09:15:21 +0000 +Subject: [PATCH 67/90] WIP: drivers: meson: vdec: check if parser has really + parser before marking input buffer as error + +Signed-off-by: Neil Armstrong +--- + drivers/staging/media/meson/vdec/esparser.c | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c +index 9b6034936d32..bb9480f0a70c 100644 +--- a/drivers/staging/media/meson/vdec/esparser.c ++++ b/drivers/staging/media/meson/vdec/esparser.c +@@ -300,6 +300,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf) + u32 num_dst_bufs = 0; + u32 offset; + u32 pad_size; ++ u32 wp, wp2; + + /* + * When max ref frame is held by VP9, this should be -= 3 to prevent a +@@ -349,15 +350,20 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf) + } + + pad_size = esparser_pad_start_code(core, vb, payload_size); ++ wp = amvdec_read_parser(core, PARSER_VIDEO_WP); + ret = esparser_write_data(core, phy, payload_size + pad_size); ++ wp2 = amvdec_read_parser(core, PARSER_VIDEO_WP); + + if (ret <= 0) { +- dev_warn(core->dev, "esparser: input parsing error\n"); +- amvdec_remove_ts(sess, vb->timestamp); +- v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); + amvdec_write_parser(core, PARSER_FETCH_CMD, 0); + +- return 0; ++ if (ret < 0 || wp2 == wp) { ++ dev_err(core->dev, "esparser: input parsing error ret %d (%x <=> %x)\n", ret, wp, wp2); ++ amvdec_remove_ts(sess, vb->timestamp); ++ v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); ++ ++ return 0; ++ } + } + + atomic_inc(&sess->esparser_queued_bufs); +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-meson-vdec-improve-mmu-and-fbc-handling-.patch b/patch/kernel/archive/meson64-5.19/general-meson-vdec-improve-mmu-and-fbc-handling-.patch new file mode 100644 index 000000000..d174d75e3 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-meson-vdec-improve-mmu-and-fbc-handling-.patch @@ -0,0 +1,586 @@ +From df7d1adad3f60c8cb3f33235b6301093801b7b47 Mon Sep 17 00:00:00 2001 +From: benjamin545 +Date: Thu, 15 Jul 2021 16:32:39 -0400 +Subject: [PATCH 63/90] WIP: drivers: meson: vdec: improve mmu and fbc handling + and add 10 bit handling + +--- + drivers/staging/media/meson/vdec/codec_h264.c | 3 +- + .../media/meson/vdec/codec_hevc_common.c | 164 +++++++++++------- + .../media/meson/vdec/codec_hevc_common.h | 3 +- + drivers/staging/media/meson/vdec/codec_vp9.c | 36 ++-- + drivers/staging/media/meson/vdec/esparser.c | 1 + + drivers/staging/media/meson/vdec/vdec.h | 1 + + .../staging/media/meson/vdec/vdec_helpers.c | 46 +++-- + .../staging/media/meson/vdec/vdec_helpers.h | 10 +- + 8 files changed, 163 insertions(+), 101 deletions(-) + +diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c +index c61128fc4bb9..d53c9a464bde 100644 +--- a/drivers/staging/media/meson/vdec/codec_h264.c ++++ b/drivers/staging/media/meson/vdec/codec_h264.c +@@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess) + frame_width, frame_height, crop_right, crop_bottom); + + codec_h264_set_par(sess); +- amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5); ++ amvdec_src_change(sess, frame_width, frame_height, ++ h264->max_refs + 5, 8); + } + + /* +diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c +index 0315cc0911cd..d6ed82dc93ca 100644 +--- a/drivers/staging/media/meson/vdec/codec_hevc_common.c ++++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c +@@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = { + void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit) + { + struct amvdec_core *core = sess->core; +- u32 body_size = amvdec_am21c_body_size(sess->width, sess->height); +- u32 head_size = amvdec_am21c_head_size(sess->width, sess->height); ++ u32 use_mmu = codec_hevc_use_mmu(core->platform->revision, ++ sess->pixfmt_cap, is_10bit); ++ u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height, ++ is_10bit, use_mmu); ++ u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height); + + if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) { + /* Enable 2-plane reference read mode */ +@@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit) + return; + } + ++ /* enable mem saving mode for 8-bit */ ++ if (!is_10bit) ++ amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9)); ++ else ++ amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9)); ++ + if (codec_hevc_use_mmu(core->platform->revision, + sess->pixfmt_cap, is_10bit)) + amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4)); ++ else if (!is_10bit) ++ amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3)); + else + amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0); + +@@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess, + + idx = vb->index; + +- if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) ++ if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) + buf_y_paddr = comm->fbc_buffer_paddr[idx]; + else + buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0); +@@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess, + { + struct amvdec_core *core = sess->core; + struct v4l2_m2m_buffer *buf; +- u32 revision = core->platform->revision; + u32 pixfmt_cap = sess->pixfmt_cap; ++ const u32 revision = core->platform->revision; + int i; + + amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, +@@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess, + dma_addr_t buf_uv_paddr = 0; + u32 idx = vb->index; + +- if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit)) +- buf_y_paddr = comm->mmu_header_paddr[idx]; +- else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) +- buf_y_paddr = comm->fbc_buffer_paddr[idx]; +- else +- buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0); ++ if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) { ++ if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit)) ++ buf_y_paddr = comm->mmu_header_paddr[idx]; ++ else ++ buf_y_paddr = comm->fbc_buffer_paddr[idx]; ++ } else { ++ buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0); ++ } + + amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA, + buf_y_paddr >> 5); +@@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess, + amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0); + } + +-void codec_hevc_free_fbc_buffers(struct amvdec_session *sess, ++void codec_hevc_free_mmu_headers(struct amvdec_session *sess, + struct codec_hevc_common *comm) + { + struct device *dev = sess->core->dev; +- u32 am21_size = amvdec_am21c_size(sess->width, sess->height); + int i; + + for (i = 0; i < MAX_REF_PIC_NUM; ++i) { +- if (comm->fbc_buffer_vaddr[i]) { +- dma_free_coherent(dev, am21_size, +- comm->fbc_buffer_vaddr[i], +- comm->fbc_buffer_paddr[i]); +- comm->fbc_buffer_vaddr[i] = NULL; ++ if (comm->mmu_header_vaddr[i]) { ++ dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE, ++ comm->mmu_header_vaddr[i], ++ comm->mmu_header_paddr[i]); ++ comm->mmu_header_vaddr[i] = NULL; + } + } + } +-EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers); ++EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers); + +-static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess, ++static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess, + struct codec_hevc_common *comm) + { + struct device *dev = sess->core->dev; + struct v4l2_m2m_buffer *buf; +- u32 am21_size = amvdec_am21c_size(sess->width, sess->height); + + v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) { + u32 idx = buf->vb.vb2_buf.index; + dma_addr_t paddr; +- void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr, +- GFP_KERNEL); ++ void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE, ++ &paddr, GFP_KERNEL); + if (!vaddr) { +- codec_hevc_free_fbc_buffers(sess, comm); ++ codec_hevc_free_mmu_headers(sess, comm); + return -ENOMEM; + } + +- comm->fbc_buffer_vaddr[idx] = vaddr; +- comm->fbc_buffer_paddr[idx] = paddr; ++ comm->mmu_header_vaddr[idx] = vaddr; ++ comm->mmu_header_paddr[idx] = paddr; + } + + return 0; + } + +-void codec_hevc_free_mmu_headers(struct amvdec_session *sess, ++void codec_hevc_free_fbc_buffers(struct amvdec_session *sess, + struct codec_hevc_common *comm) + { + struct device *dev = sess->core->dev; ++ u32 use_mmu; ++ u32 am21_size; + int i; + ++ use_mmu = codec_hevc_use_mmu(sess->core->platform->revision, ++ sess->pixfmt_cap, ++ sess->bitdepth == 10 ? 1 : 0); ++ ++ am21_size = amvdec_amfbc_size(sess->width, sess->height, ++ sess->bitdepth == 10 ? 1 : 0, use_mmu); ++ + for (i = 0; i < MAX_REF_PIC_NUM; ++i) { +- if (comm->mmu_header_vaddr[i]) { +- dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE, +- comm->mmu_header_vaddr[i], +- comm->mmu_header_paddr[i]); +- comm->mmu_header_vaddr[i] = NULL; ++ if (comm->fbc_buffer_vaddr[i]) { ++ dma_free_coherent(dev, am21_size, ++ comm->fbc_buffer_vaddr[i], ++ comm->fbc_buffer_paddr[i]); ++ comm->fbc_buffer_vaddr[i] = NULL; + } + } + +@@ -213,33 +233,49 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess, + comm->mmu_map_paddr); + comm->mmu_map_vaddr = NULL; + } ++ ++ codec_hevc_free_mmu_headers(sess, comm); + } +-EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers); ++EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers); + +-static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess, ++static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess, + struct codec_hevc_common *comm) + { + struct device *dev = sess->core->dev; + struct v4l2_m2m_buffer *buf; ++ u32 use_mmu; ++ u32 am21_size; ++ const u32 revision = sess->core->platform->revision; ++ const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0; ++ int ret; + +- comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE, +- &comm->mmu_map_paddr, +- GFP_KERNEL); +- if (!comm->mmu_map_vaddr) +- return -ENOMEM; ++ use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap, ++ is_10bit); ++ ++ am21_size = amvdec_amfbc_size(sess->width, sess->height, ++ is_10bit, use_mmu); + + v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) { + u32 idx = buf->vb.vb2_buf.index; + dma_addr_t paddr; +- void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE, +- &paddr, GFP_KERNEL); ++ void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr, ++ GFP_KERNEL); + if (!vaddr) { +- codec_hevc_free_mmu_headers(sess, comm); ++ codec_hevc_free_fbc_buffers(sess, comm); + return -ENOMEM; + } + +- comm->mmu_header_vaddr[idx] = vaddr; +- comm->mmu_header_paddr[idx] = paddr; ++ comm->fbc_buffer_vaddr[idx] = vaddr; ++ comm->fbc_buffer_paddr[idx] = paddr; ++ } ++ ++ if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) && ++ codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) { ++ ret = codec_hevc_alloc_mmu_headers(sess, comm); ++ if (ret) { ++ codec_hevc_free_fbc_buffers(sess, comm); ++ return ret; ++ } + } + + return 0; +@@ -250,21 +286,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess, + int is_10bit) + { + struct amvdec_core *core = sess->core; ++ struct device *dev = core->dev; + int ret; + +- if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) { +- ret = codec_hevc_alloc_fbc_buffers(sess, comm); +- if (ret) +- return ret; ++ if (codec_hevc_use_mmu(core->platform->revision, ++ sess->pixfmt_cap, is_10bit)) { ++ comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE, ++ &comm->mmu_map_paddr, ++ GFP_KERNEL); ++ if (!comm->mmu_map_vaddr) ++ return -ENOMEM; + } + + if (codec_hevc_use_mmu(core->platform->revision, +- sess->pixfmt_cap, is_10bit)) { +- ret = codec_hevc_alloc_mmu_headers(sess, comm); +- if (ret) { +- codec_hevc_free_fbc_buffers(sess, comm); +- return ret; +- } ++ sess->pixfmt_cap, is_10bit) || ++ codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) { ++ ret = codec_hevc_alloc_fbc_buffers(sess, comm); ++ if (ret) ++ return ret; + } + + if (core->platform->revision == VDEC_REVISION_GXBB) +@@ -278,19 +317,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers); + + void codec_hevc_fill_mmu_map(struct amvdec_session *sess, + struct codec_hevc_common *comm, +- struct vb2_buffer *vb) ++ struct vb2_buffer *vb, ++ u32 is_10bit) + { +- u32 size = amvdec_am21c_size(sess->width, sess->height); +- u32 nb_pages = size / PAGE_SIZE; ++ u32 use_mmu; ++ u32 size; ++ u32 nb_pages; + u32 *mmu_map = comm->mmu_map_vaddr; + u32 first_page; + u32 i; + +- if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) +- first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT; +- else +- first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT; ++ use_mmu = codec_hevc_use_mmu(sess->core->platform->revision, ++ sess->pixfmt_cap, is_10bit); ++ ++ size = amvdec_amfbc_size(sess->width, sess->height, is_10bit, ++ use_mmu); + ++ nb_pages = size / PAGE_SIZE; ++ first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT; + for (i = 0; i < nb_pages; ++i) + mmu_map[i] = first_page + i; + } +diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h +index cf072b8a9da2..13f9f1d90a94 100644 +--- a/drivers/staging/media/meson/vdec/codec_hevc_common.h ++++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h +@@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess, + + void codec_hevc_fill_mmu_map(struct amvdec_session *sess, + struct codec_hevc_common *comm, +- struct vb2_buffer *vb); ++ struct vb2_buffer *vb, ++ u32 is_10bit); + + #endif +diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c +index 897f5d7a6aad..bfc312ec2a56 100644 +--- a/drivers/staging/media/meson/vdec/codec_vp9.c ++++ b/drivers/staging/media/meson/vdec/codec_vp9.c +@@ -458,12 +458,6 @@ struct codec_vp9 { + struct list_head ref_frames_list; + u32 frames_num; + +- /* In case of downsampling (decoding with FBC but outputting in NV12M), +- * we need to allocate additional buffers for FBC. +- */ +- void *fbc_buffer_vaddr[MAX_REF_PIC_NUM]; +- dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM]; +- + int ref_frame_map[REF_FRAMES]; + int next_ref_frame_map[REF_FRAMES]; + struct vp9_frame *frame_refs[REFS_PER_FRAME]; +@@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess, + buf_y_paddr = + vb2_dma_contig_plane_dma_addr(vb, 0); + +- if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) { +- val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200; +- amvdec_write_dos(core, HEVC_SAO_CTRL5, val); +- amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr); +- } ++ if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) ++ amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr); + + if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) { + buf_y_paddr = +@@ -920,8 +911,12 @@ static void codec_vp9_set_sao(struct amvdec_session *sess, + + if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap, + vp9->is_10bit)) { +- amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, +- vp9->common.mmu_header_paddr[vb->index]); ++ dma_addr_t header_adr; ++ if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit)) ++ header_adr = vp9->common.mmu_header_paddr[vb->index]; ++ else ++ header_adr = vb2_dma_contig_plane_dma_addr(vb, 0); ++ amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr); + /* use HEVC_CM_HEADER_START_ADDR */ + amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10)); + } +@@ -1148,9 +1143,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess, + { + struct amvdec_core *core = sess->core; + u32 scale = 0; ++ u32 use_mmu; + u32 sz; + int i; + ++ use_mmu = codec_hevc_use_mmu(core->platform->revision, ++ sess->pixfmt_cap, vp9->is_10bit); ++ + amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1); + codec_vp9_set_refs(sess, vp9); + amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, +@@ -1166,8 +1165,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess, + vp9->frame_refs[i]->height != vp9->height) + scale = 1; + +- sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width, +- vp9->frame_refs[i]->height); ++ sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width, ++ vp9->frame_refs[i]->height, ++ vp9->is_10bit, use_mmu); + + amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA, + vp9->frame_refs[i]->width); +@@ -1283,7 +1283,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess) + if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap, + vp9->is_10bit)) + codec_hevc_fill_mmu_map(sess, &vp9->common, +- &vp9->cur_frame->vbuf->vb2_buf); ++ &vp9->cur_frame->vbuf->vb2_buf, ++ vp9->is_10bit); + + intra_only = param->p.show_frame ? 0 : param->p.intra_only; + +@@ -2132,7 +2133,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess) + + codec_vp9_fetch_rpm(sess); + if (codec_vp9_process_rpm(vp9)) { +- amvdec_src_change(sess, vp9->width, vp9->height, 16); ++ amvdec_src_change(sess, vp9->width, vp9->height, 16, ++ vp9->is_10bit ? 10 : 8); + + /* No frame is actually processed */ + vp9->cur_frame = NULL; +diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c +index e18334e57fc0..610a92b9f6f2 100644 +--- a/drivers/staging/media/meson/vdec/esparser.c ++++ b/drivers/staging/media/meson/vdec/esparser.c +@@ -319,6 +319,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf) + if (esparser_vififo_get_free_space(sess) < payload_size || + atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs) + return -EAGAIN; ++ + } else if (esparser_vififo_get_free_space(sess) < payload_size) { + return -EAGAIN; + } +diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h +index 0906b8fb5cc6..a48170fe4cff 100644 +--- a/drivers/staging/media/meson/vdec/vdec.h ++++ b/drivers/staging/media/meson/vdec/vdec.h +@@ -244,6 +244,7 @@ struct amvdec_session { + u32 width; + u32 height; + u32 colorspace; ++ u32 bitdepth; + u8 ycbcr_enc; + u8 quantization; + u8 xfer_func; +diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c +index 203d7afa085d..23a69c51c634 100644 +--- a/drivers/staging/media/meson/vdec/vdec_helpers.c ++++ b/drivers/staging/media/meson/vdec/vdec_helpers.c +@@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val) + } + EXPORT_SYMBOL_GPL(amvdec_write_parser); + +-/* 4 KiB per 64x32 block */ +-u32 amvdec_am21c_body_size(u32 width, u32 height) ++/* AMFBC body is made out of 64x32 blocks with varying block size */ ++u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu) + { + u32 width_64 = ALIGN(width, 64) / 64; + u32 height_32 = ALIGN(height, 32) / 32; ++ u32 blk_size = 4096; + +- return SZ_4K * width_64 * height_32; ++ if (!is_10bit) { ++ if (use_mmu) ++ blk_size = 3200; ++ else ++ blk_size = 3072; ++ } ++ ++ return blk_size * width_64 * height_32; + } +-EXPORT_SYMBOL_GPL(amvdec_am21c_body_size); ++EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size); + + /* 32 bytes per 128x64 block */ +-u32 amvdec_am21c_head_size(u32 width, u32 height) ++u32 amvdec_amfbc_head_size(u32 width, u32 height) + { + u32 width_128 = ALIGN(width, 128) / 128; + u32 height_64 = ALIGN(height, 64) / 64; + + return 32 * width_128 * height_64; + } +-EXPORT_SYMBOL_GPL(amvdec_am21c_head_size); ++EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size); + +-u32 amvdec_am21c_size(u32 width, u32 height) ++u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu) + { +- return ALIGN(amvdec_am21c_body_size(width, height) + +- amvdec_am21c_head_size(width, height), SZ_64K); ++ return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) + ++ amvdec_amfbc_head_size(width, height), SZ_64K); + } +-EXPORT_SYMBOL_GPL(amvdec_am21c_size); ++EXPORT_SYMBOL_GPL(amvdec_amfbc_size); + + static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id) + { +@@ -436,7 +444,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess, + EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar); + + void amvdec_src_change(struct amvdec_session *sess, u32 width, +- u32 height, u32 dpb_size) ++ u32 height, u32 dpb_size, u32 bitdepth) + { + static const struct v4l2_event ev = { + .type = V4L2_EVENT_SOURCE_CHANGE, +@@ -444,25 +452,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width, + + v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size); + ++ sess->bitdepth = bitdepth; ++ + /* + * Check if the capture queue is already configured well for our +- * usecase. If so, keep decoding with it and do not send the event ++ * usecase. If so, keep decoding with it. + */ + if (sess->streamon_cap && + sess->width == width && + sess->height == height && + dpb_size <= sess->num_dst_bufs) { + sess->fmt_out->codec_ops->resume(sess); +- return; +- } ++ } else { ++ sess->status = STATUS_NEEDS_RESUME; ++ sess->changed_format = 0; ++ } + +- sess->changed_format = 0; + sess->width = width; + sess->height = height; +- sess->status = STATUS_NEEDS_RESUME; + +- dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n", +- width, height, dpb_size); ++ dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n", ++ width, height, dpb_size, bitdepth); + v4l2_event_queue_fh(&sess->fh, &ev); + } + EXPORT_SYMBOL_GPL(amvdec_src_change); +diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h +index 88137d15aa3a..fca4251f7599 100644 +--- a/drivers/staging/media/meson/vdec/vdec_helpers.h ++++ b/drivers/staging/media/meson/vdec/vdec_helpers.h +@@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val); + u32 amvdec_read_parser(struct amvdec_core *core, u32 reg); + void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val); + +-u32 amvdec_am21c_body_size(u32 width, u32 height); +-u32 amvdec_am21c_head_size(u32 width, u32 height); +-u32 amvdec_am21c_size(u32 width, u32 height); ++/* Helpers for the Amlogic compressed framebuffer format */ ++u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu); ++u32 amvdec_amfbc_head_size(u32 width, u32 height); ++u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu); + + /** + * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding +@@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess, + * @width: picture width detected by the hardware + * @height: picture height detected by the hardware + * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding) ++ * @bitdepth: Bit depth (usually 10 or 8) of the coded content + */ + void amvdec_src_change(struct amvdec_session *sess, u32 width, +- u32 height, u32 dpb_size); ++ u32 height, u32 dpb_size, u32 bitdepth); + + /** + * amvdec_abort() - Abort the current decoding session +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-meson-vdec-remove-redundant-if-statement.patch b/patch/kernel/archive/meson64-5.19/general-meson-vdec-remove-redundant-if-statement.patch new file mode 100644 index 000000000..489b93556 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-meson-vdec-remove-redundant-if-statement.patch @@ -0,0 +1,29 @@ +From 4aca1a59251338a9f98b58fc67e7749fae32b3be Mon Sep 17 00:00:00 2001 +From: benjamin545 +Date: Thu, 15 Jul 2021 14:32:33 -0400 +Subject: [PATCH 62/90] WIP: drivers: meson: vdec: remove redundant if + statement + +checking if sess->fmt_out->pixfmt is V4L2_PIX_FMT_VP9 was already done +as a condition to enter the if statement where this additional check is performed +--- + drivers/staging/media/meson/vdec/esparser.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c +index db7022707ff8..e18334e57fc0 100644 +--- a/drivers/staging/media/meson/vdec/esparser.c ++++ b/drivers/staging/media/meson/vdec/esparser.c +@@ -314,8 +314,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf) + num_dst_bufs = codec_ops->num_pending_bufs(sess); + + num_dst_bufs += v4l2_m2m_num_dst_bufs_ready(sess->m2m_ctx); +- if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9) +- num_dst_bufs -= 3; ++ num_dst_bufs -= 3; + + if (esparser_vififo_get_free_space(sess) < payload_size || + atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs) +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-meson64-overlays.patch b/patch/kernel/archive/meson64-5.19/general-meson64-overlays.patch new file mode 100644 index 000000000..b9b4c2bfa --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-meson64-overlays.patch @@ -0,0 +1,262 @@ +From 58c5526eb1798e61e4e76d37140cf10c8d325bc7 Mon Sep 17 00:00:00 2001 +From: Zhang Ning <832666+zhangn1985@users.noreply.github.com> +Date: Thu, 19 Sep 2019 16:20:31 +0800 +Subject: [PATCH] general: meson64 overlays + +Signed-off-by: Zhang Ning <832666+zhangn1985@users.noreply.github.com> +--- + arch/arm64/boot/dts/amlogic/Makefile | 2 ++ + arch/arm64/boot/dts/amlogic/overlay/Makefile | 20 ++++++++++++ + .../dts/amlogic/overlay/README.meson-overlays | 20 ++++++++++++ + .../dts/amlogic/overlay/meson-fixup.scr-cmd | 4 +++ + .../boot/dts/amlogic/overlay/meson-i2cA.dts | 17 ++++++++++ + .../boot/dts/amlogic/overlay/meson-i2cB.dts | 17 ++++++++++ + .../boot/dts/amlogic/overlay/meson-uartA.dts | 11 +++++++ + .../boot/dts/amlogic/overlay/meson-uartC.dts | 11 +++++++ + .../dts/amlogic/overlay/meson-w1-gpio.dts | 20 ++++++++++++ + .../dts/amlogic/overlay/meson-w1AB-gpio.dts | 32 +++++++++++++++++++ + scripts/Makefile.lib | 3 ++ + 11 files changed, 157 insertions(+) + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/Makefile + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/README.meson-overlays + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/meson-fixup.scr-cmd + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/meson-i2cA.dts + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/meson-i2cB.dts + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/meson-uartA.dts + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/meson-uartC.dts + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/meson-w1-gpio.dts + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/meson-w1AB-gpio.dts + +diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile +index da3225d31e38..5387963c0ee4 100644 +--- a/arch/arm64/boot/dts/amlogic/Makefile ++++ b/arch/arm64/boot/dts/amlogic/Makefile +@@ -67,3 +67,5 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb ++ ++subdir-y := $(dts-dirs) overlay +diff --git a/arch/arm64/boot/dts/amlogic/overlay/Makefile b/arch/arm64/boot/dts/amlogic/overlay/Makefile +new file mode 100644 +index 000000000000..8630fd1a182d +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/Makefile +@@ -0,0 +1,20 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtbo-$(CONFIG_ARCH_MESON) += \ ++ meson-i2cA.dtbo \ ++ meson-i2cB.dtbo \ ++ meson-uartA.dtbo \ ++ meson-uartC.dtbo \ ++ meson-w1-gpio.dtbo \ ++ meson-w1AB-gpio.dtbo ++ ++scr-$(CONFIG_ARCH_MESON) += \ ++ meson-fixup.scr ++ ++dtbotxt-$(CONFIG_ARCH_MESON) += \ ++ README.meson-overlays ++ ++targets += $(dtbo-y) $(scr-y) $(dtbotxt-y) ++ ++always := $(dtbo-y) $(scr-y) $(dtbotxt-y) ++clean-files := *.dtbo *.scr ++ +diff --git a/arch/arm64/boot/dts/amlogic/overlay/README.meson-overlays b/arch/arm64/boot/dts/amlogic/overlay/README.meson-overlays +new file mode 100644 +index 000000000000..1b169a7a1525 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/README.meson-overlays +@@ -0,0 +1,20 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++meson (Amlogic) ++ ++### Provided overlays: ++ ++- i2c8 ++ ++### Overlay details: ++ ++### i2c8 ++ ++Activates TWI/I2C bus 8 ++ ++I2C8 pins (SCL, SDA): GPIO1-C4, GPIO1-C5 ++ +diff --git a/arch/arm64/boot/dts/amlogic/overlay/meson-fixup.scr-cmd b/arch/arm64/boot/dts/amlogic/overlay/meson-fixup.scr-cmd +new file mode 100644 +index 000000000000..d4c39e20a3a2 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/meson-fixup.scr-cmd +@@ -0,0 +1,4 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ +diff --git a/arch/arm64/boot/dts/amlogic/overlay/meson-i2cA.dts b/arch/arm64/boot/dts/amlogic/overlay/meson-i2cA.dts +new file mode 100644 +index 000000000000..bfb72feb7e36 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/meson-i2cA.dts +@@ -0,0 +1,17 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "amlogic,meson-gxbb"; ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2cA = "/soc/bus@c1100000/i2c@8500"; ++ }; ++ }; ++ fragment@1 { ++ target-path = "/soc/bus@c1100000/i2c@8500"; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/amlogic/overlay/meson-i2cB.dts b/arch/arm64/boot/dts/amlogic/overlay/meson-i2cB.dts +new file mode 100644 +index 000000000000..d75867bce99b +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/meson-i2cB.dts +@@ -0,0 +1,17 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "amlogic,meson-gxbb"; ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2cA = "/soc/bus@c1100000/i2c@87c0"; ++ }; ++ }; ++ fragment@1 { ++ target-path = "/soc/bus@c1100000/i2c@87c0"; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/amlogic/overlay/meson-uartA.dts b/arch/arm64/boot/dts/amlogic/overlay/meson-uartA.dts +new file mode 100644 +index 000000000000..3aecd60aaf64 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/meson-uartA.dts +@@ -0,0 +1,11 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "amlogic,meson-gxbb"; ++ fragment@0 { ++ target-path = "/soc/bus@c1100000/serial@84c0"; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/amlogic/overlay/meson-uartC.dts b/arch/arm64/boot/dts/amlogic/overlay/meson-uartC.dts +new file mode 100644 +index 000000000000..2b40ee4c02d3 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/meson-uartC.dts +@@ -0,0 +1,11 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "amlogic,meson-gxbb"; ++ fragment@0 { ++ target-path = "/soc/bus@c1100000/serial@8700"; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/amlogic/overlay/meson-w1-gpio.dts b/arch/arm64/boot/dts/amlogic/overlay/meson-w1-gpio.dts +new file mode 100644 +index 000000000000..ac76a4f20ab7 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/meson-w1-gpio.dts +@@ -0,0 +1,20 @@ ++// Definitions for w1-gpio module (without external pullup) ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "amlogic,meson-gxbb"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ ++ w1: onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ gpios = <&gpio 91 6>; // GPIOY_16 ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/amlogic/overlay/meson-w1AB-gpio.dts b/arch/arm64/boot/dts/amlogic/overlay/meson-w1AB-gpio.dts +new file mode 100644 +index 000000000000..f6b0d7eff158 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/meson-w1AB-gpio.dts +@@ -0,0 +1,32 @@ ++// Definitions for w1-gpio module (without external pullup) ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "amlogic,meson-gxbb"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ ++ w1a: onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ gpios = <&gpio 91 6>; // GPIOY_16 ++ status = "okay"; ++ }; ++ }; ++ }; ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ ++ w1b: onewire@1 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ gpios = <&gpio 90 6>; // GPIOY_15 ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index a28448cebd7c..175e7b53eccf 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -87,6 +87,9 @@ base-dtb-y := $(foreach m, $(multi-dtb-y), $(firstword $(call suffix-search, $m, + + always-y += $(dtb-y) + ++# Overlay targets ++extra-y += $(dtbo-y) $(scr-y) $(dtbotxt-y) ++ + # Add subdir path + + extra-y := $(addprefix $(obj)/,$(extra-y)) +-- +2.30.2 + diff --git a/patch/kernel/archive/meson64-5.19/general-pwm-gpio-Add-a-generic-gpio-based-PWM-.patch b/patch/kernel/archive/meson64-5.19/general-pwm-gpio-Add-a-generic-gpio-based-PWM-.patch new file mode 100644 index 000000000..bb9776677 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-pwm-gpio-Add-a-generic-gpio-based-PWM-.patch @@ -0,0 +1,368 @@ +From 7d1ba33e12252f6661bf91ad28c6f8269bb13ff2 Mon Sep 17 00:00:00 2001 +From: Kevin Kim +Date: Wed, 16 Jan 2019 14:45:10 +0900 +Subject: [PATCH] ODROID-COMMON: pwm: gpio: Add a generic gpio based PWM driver + +From: Olliver Schinagl + +This patch adds a bit-banging gpio PWM driver. It makes use of hrtimers, +to allow nano-second resolution, though it obviously strongly depends on +the switching speed of the gpio pins, hrtimer and system load. + +Each pwm node can have 1 or more "pwm-gpio" entries, which will be +treated as pwm's as part of a pwm chip. + +Change-Id: Idd42bf6d79f8ce52275a15965b02af470f28da7c +Signed-off-by: Olliver Schinagl +--- + .../devicetree/bindings/pwm/pwm-gpio.txt | 18 ++ + MAINTAINERS | 5 + + drivers/pwm/Kconfig | 15 ++ + drivers/pwm/Makefile | 1 + + drivers/pwm/pwm-gpio.c | 255 ++++++++++++++++++ + 5 files changed, 294 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pwm/pwm-gpio.txt + create mode 100644 drivers/pwm/pwm-gpio.c + +diff --git a/Documentation/devicetree/bindings/pwm/pwm-gpio.txt b/Documentation/devicetree/bindings/pwm/pwm-gpio.txt +new file mode 100644 +index 000000000000..336f61faa446 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pwm/pwm-gpio.txt +@@ -0,0 +1,18 @@ ++Generic GPIO bit-banged PWM driver ++ ++Required properties: ++ - compatible: should be "pwm-gpio" ++ - #pwm-cells: should be 3, see pwm.txt in this directory for a general ++ description of the cells format. ++ - pwm-gpios: one or more gpios describing the used gpio, see the gpio ++ bindings for the used gpio driver. ++ ++Example: ++#include ++ ++ pwm: pwm@0 { ++ compatible = "pwm-gpio"; ++ #pwm-cells = 3; ++ pwm-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; ++ pwm-gpios = <&pio 7 2 GPIO_ACTIVE_LOW>; ++ }; +diff --git a/MAINTAINERS b/MAINTAINERS +index dd36acc87ce6..0409221bb9a7 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -7959,6 +7959,11 @@ F: Documentation/i2c/muxes/i2c-mux-gpio.rst + F: drivers/i2c/muxes/i2c-mux-gpio.c + F: include/linux/platform_data/i2c-mux-gpio.h + ++GENERIC GPIO PWM DRIVER ++M: Olliver Schinagl ++S: Maintained ++F: drivers/pwm/pwm-gpio.c ++ + GENERIC HDLC (WAN) DRIVERS + M: Krzysztof Halasa + S: Maintained +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index 21e3b05a5153..35f7bd5fb6b6 100644 +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -195,6 +195,21 @@ config PWM_FSL_FTM + To compile this driver as a module, choose M here: the module + will be called pwm-fsl-ftm. + ++config PWM_GPIO ++ tristate "Generic GPIO bit-banged PWM driver" ++ depends on OF ++ depends on GPIOLIB ++ help ++ Some platforms do not offer any hardware PWM capabilities but do have ++ General Purpose Input Output (GPIO) pins available. Using the kernels ++ High-Resolution Timer API this driver tries to toggle GPIO using the ++ generic kernel PWM framework. The maximum frequency and/or accuracy ++ is dependent on several factors such as system load and the maximum ++ speed a pin can be toggled at the hardware. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called pwm-gpio. ++ + config PWM_HIBVT + tristate "HiSilicon BVT PWM support" + depends on ARCH_HISI || COMPILE_TEST +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index 708840b7fba8..f190bbc3af8d 100644 +--- a/drivers/pwm/Makefile ++++ b/drivers/pwm/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o + obj-$(CONFIG_PWM_DWC) += pwm-dwc.o + obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o + obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o ++obj-$(CONFIG_PWM_GPIO) += pwm-gpio.o + obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o + obj-$(CONFIG_PWM_IMG) += pwm-img.o + obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o +diff --git a/drivers/pwm/pwm-gpio.c b/drivers/pwm/pwm-gpio.c +new file mode 100644 +index 000000000000..6707a5dbe5fb +--- /dev/null ++++ b/drivers/pwm/pwm-gpio.c +@@ -0,0 +1,255 @@ ++/* ++ * Copyright (c) 2015 Olliver Schinagl ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * This driver adds a high-resolution timer based PWM driver. Since this is a ++ * bit-banged driver, accuracy will always depend on a lot of factors, such as ++ * GPIO toggle speed and system load. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRV_NAME "pwm-gpio" ++ ++struct gpio_pwm_data { ++ struct hrtimer timer; ++ struct gpio_desc *gpiod; ++ bool polarity; ++ bool pin_on; ++ int on_time; ++ int off_time; ++ bool run; ++}; ++ ++struct gpio_pwm_chip { ++ struct pwm_chip chip; ++}; ++ ++static void gpio_pwm_off(struct gpio_pwm_data *gpio_data) ++{ ++ gpiod_set_value_cansleep(gpio_data->gpiod, gpio_data->polarity ? 0 : 1); ++} ++ ++static void gpio_pwm_on(struct gpio_pwm_data *gpio_data) ++{ ++ gpiod_set_value_cansleep(gpio_data->gpiod, gpio_data->polarity ? 1 : 0); ++} ++ ++enum hrtimer_restart gpio_pwm_timer(struct hrtimer *timer) ++{ ++ struct gpio_pwm_data *gpio_data = container_of(timer, ++ struct gpio_pwm_data, ++ timer); ++ if (!gpio_data->run) { ++ gpio_pwm_off(gpio_data); ++ gpio_data->pin_on = false; ++ return HRTIMER_NORESTART; ++ } ++ ++ if (!gpio_data->pin_on) { ++ hrtimer_forward_now(&gpio_data->timer, ++ ns_to_ktime(gpio_data->on_time)); ++ gpio_pwm_on(gpio_data); ++ gpio_data->pin_on = true; ++ } else { ++ hrtimer_forward_now(&gpio_data->timer, ++ ns_to_ktime(gpio_data->off_time)); ++ gpio_pwm_off(gpio_data); ++ gpio_data->pin_on = false; ++ } ++ ++ return HRTIMER_RESTART; ++} ++ ++static int gpio_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, ++ int duty_ns, int period_ns) ++{ ++ struct gpio_pwm_data *gpio_data = pwm_get_chip_data(pwm); ++ ++ gpio_data->on_time = duty_ns; ++ gpio_data->off_time = period_ns - duty_ns; ++ ++ return 0; ++} ++ ++static int gpio_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, ++ enum pwm_polarity polarity) ++{ ++ struct gpio_pwm_data *gpio_data = pwm_get_chip_data(pwm); ++ ++ gpio_data->polarity = (polarity != PWM_POLARITY_NORMAL) ? true : false; ++ ++ return 0; ++} ++ ++static int gpio_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct gpio_pwm_data *gpio_data = pwm_get_chip_data(pwm); ++ ++ if (gpio_data->run) ++ return -EBUSY; ++ ++ gpio_data->run = true; ++ if (gpio_data->off_time) { ++ hrtimer_start(&gpio_data->timer, ktime_set(0, 0), ++ HRTIMER_MODE_REL); ++ } else { ++ if (gpio_data->on_time) ++ gpio_pwm_on(gpio_data); ++ else ++ gpio_pwm_off(gpio_data); ++ } ++ ++ return 0; ++} ++ ++static void gpio_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct gpio_pwm_data *gpio_data = pwm_get_chip_data(pwm); ++ ++ gpio_data->run = false; ++ if (!gpio_data->off_time) ++ gpio_pwm_off(gpio_data); ++} ++ ++static const struct pwm_ops gpio_pwm_ops = { ++ .config = gpio_pwm_config, ++ .set_polarity = gpio_pwm_set_polarity, ++ .enable = gpio_pwm_enable, ++ .disable = gpio_pwm_disable, ++ .owner = THIS_MODULE, ++}; ++ ++static int gpio_pwm_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct gpio_pwm_chip *gpio_chip; ++ int npwm, i; ++ int hrtimer = 0; ++ ++ npwm = of_gpio_named_count(pdev->dev.of_node, "pwm-gpios"); ++ if (npwm < 1) ++ return -ENODEV; ++ ++ gpio_chip = devm_kzalloc(&pdev->dev, sizeof(*gpio_chip), GFP_KERNEL); ++ if (!gpio_chip) ++ return -ENOMEM; ++ ++ gpio_chip->chip.dev = &pdev->dev; ++ gpio_chip->chip.ops = &gpio_pwm_ops; ++ gpio_chip->chip.base = -1; ++ gpio_chip->chip.npwm = npwm; ++ gpio_chip->chip.of_xlate = of_pwm_xlate_with_flags; ++ gpio_chip->chip.of_pwm_n_cells = 3; ++ ++ ret = pwmchip_add(&gpio_chip->chip); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); ++ return ret; ++ } ++ ++ for (i = 0; i < npwm; i++) { ++ struct gpio_desc *gpiod; ++ struct gpio_pwm_data *gpio_data; ++ ++ gpiod = devm_gpiod_get_index(&pdev->dev, "pwm", i, ++ GPIOD_OUT_LOW); ++ if (IS_ERR(gpiod)) { ++ int error; ++ ++ error = PTR_ERR(gpiod); ++ if (error != -EPROBE_DEFER) ++ dev_err(&pdev->dev, ++ "failed to get gpio flags, error: %d\n", ++ error); ++ return error; ++ } ++ ++ gpio_data = devm_kzalloc(&pdev->dev, sizeof(*gpio_data), ++ GFP_KERNEL); ++ ++ hrtimer_init(&gpio_data->timer, ++ CLOCK_MONOTONIC, HRTIMER_MODE_REL); ++ gpio_data->timer.function = &gpio_pwm_timer; ++ gpio_data->gpiod = gpiod; ++ gpio_data->pin_on = false; ++ gpio_data->run = false; ++ ++ if (hrtimer_is_hres_active(&gpio_data->timer)) ++ hrtimer++; ++ ++ pwm_set_chip_data(&gpio_chip->chip.pwms[i], gpio_data); ++ } ++ if (!hrtimer) { ++ dev_warn(&pdev->dev, "unable to use High-Resolution timer,"); ++ dev_warn(&pdev->dev, "%s is restricted to low resolution.", ++ DRV_NAME); ++ } ++ ++ platform_set_drvdata(pdev, gpio_chip); ++ ++ dev_info(&pdev->dev, "%d gpio pwms loaded\n", npwm); ++ ++ return 0; ++} ++ ++static int gpio_pwm_remove(struct platform_device *pdev) ++{ ++ struct gpio_pwm_chip *gpio_chip; ++ int i; ++ ++ gpio_chip = platform_get_drvdata(pdev); ++ for (i = 0; i < gpio_chip->chip.npwm; i++) { ++ struct gpio_pwm_data *gpio_data; ++ ++ gpio_data = pwm_get_chip_data(&gpio_chip->chip.pwms[i]); ++ ++ hrtimer_cancel(&gpio_data->timer); ++ } ++ ++ pwmchip_remove(&gpio_chip->chip); ++ ++ return 0; ++} ++ ++static const struct of_device_id gpio_pwm_of_match[] = { ++ { .compatible = DRV_NAME, }, ++ {/* sentinel */}, ++}; ++MODULE_DEVICE_TABLE(of, gpio_pwm_of_match); ++ ++static struct platform_driver gpio_pwm_driver = { ++ .probe = gpio_pwm_probe, ++ .remove = gpio_pwm_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .of_match_table = of_match_ptr(gpio_pwm_of_match), ++ }, ++}; ++module_platform_driver(gpio_pwm_driver); ++ ++MODULE_AUTHOR("Olliver Schinagl "); ++MODULE_DESCRIPTION("Generic GPIO bit-banged PWM driver"); ++MODULE_LICENSE("GPL"); +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-rc-drivers-should-produce-alternate-pulse-and-space-timing-events.patch b/patch/kernel/archive/meson64-5.19/general-rc-drivers-should-produce-alternate-pulse-and-space-timing-events.patch new file mode 100644 index 000000000..cc3c970e8 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-rc-drivers-should-produce-alternate-pulse-and-space-timing-events.patch @@ -0,0 +1,14 @@ +diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c +index 4b769111f78e..dd3aa1332f53 100644 +--- a/drivers/media/rc/meson-ir.c ++++ b/drivers/media/rc/meson-ir.c +@@ -91,7 +91,8 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id) + status = readl_relaxed(ir->reg + IR_DEC_STATUS); + rawir.pulse = !!(status & STATUS_IR_DEC_IN); + +- ir_raw_event_store_with_timeout(ir->rc, &rawir); ++ if (ir_raw_event_store_with_filter(ir->rc, &rawir)) ++ ir_raw_event_handle(ir->rc); + + spin_unlock(&ir->lock); + diff --git a/patch/kernel/archive/meson64-5.19/general-si2168-fix-cmd-timeout.patch b/patch/kernel/archive/meson64-5.19/general-si2168-fix-cmd-timeout.patch new file mode 100644 index 000000000..453b98a36 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-si2168-fix-cmd-timeout.patch @@ -0,0 +1,28 @@ +From 2e01cc074cc426da4b390af025a736eda9aef80c Mon Sep 17 00:00:00 2001 +From: Koumes +Date: Sat, 1 Jun 2019 21:20:26 +0000 +Subject: [PATCH] si2168: fix cmd timeout + +Some demuxer si2168 commands may take 130-140 ms. +(DVB-T/T2 tuner MyGica T230C v2). +Details: https://github.com/CoreELEC/CoreELEC/pull/208 +--- + drivers/media/dvb-frontends/si2168.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/dvb-frontends/si2168.c b/drivers/media/dvb-frontends/si2168.c +index b05e6772c..ffaba6f81 100644 +--- a/drivers/media/dvb-frontends/si2168.c ++++ b/drivers/media/dvb-frontends/si2168.c +@@ -42,7 +42,7 @@ static int si2168_cmd_execute(struct i2c_client *client, struct si2168_cmd *cmd) + + if (cmd->rlen) { + /* wait cmd execution terminate */ +- #define TIMEOUT 70 ++ #define TIMEOUT 200 + timeout = jiffies + msecs_to_jiffies(TIMEOUT); + while (!time_after(jiffies, timeout)) { + ret = i2c_master_recv(client, cmd->args, cmd->rlen); +-- +2.17.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-sound-soc-remove-mono-channel-as-it-curren.patch b/patch/kernel/archive/meson64-5.19/general-sound-soc-remove-mono-channel-as-it-curren.patch new file mode 100644 index 000000000..8861f8f47 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-sound-soc-remove-mono-channel-as-it-curren.patch @@ -0,0 +1,37 @@ +From 79828b7d8ee8674b1538514a754337554cd4f856 Mon Sep 17 00:00:00 2001 +From: ckkim +Date: Thu, 20 Feb 2020 18:52:57 +0900 +Subject: [PATCH] ODROID-N2: sound/soc: remove mono channel as it currently + doesn't work hdmi output. + +Change-Id: I4d43b802815779687ade974f049f2b0517a411d1 +Signed-off-by: ckkim +--- + sound/soc/meson/axg-frddr.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c +index 37f4bb3469b5..b1cbeef98a73 100644 +--- a/sound/soc/meson/axg-frddr.c ++++ b/sound/soc/meson/axg-frddr.c +@@ -106,7 +106,7 @@ static struct snd_soc_dai_driver axg_frddr_dai_drv = { + .name = "FRDDR", + .playback = { + .stream_name = "Playback", +- .channels_min = 1, ++ .channels_min = 2, + .channels_max = AXG_FIFO_CH_MAX, + .rates = AXG_FIFO_RATES, + .formats = AXG_FIFO_FORMATS, +@@ -180,7 +180,7 @@ static struct snd_soc_dai_driver g12a_frddr_dai_drv = { + .name = "FRDDR", + .playback = { + .stream_name = "Playback", +- .channels_min = 1, ++ .channels_min = 2, + .channels_max = AXG_FIFO_CH_MAX, + .rates = AXG_FIFO_RATES, + .formats = AXG_FIFO_FORMATS, +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/general-spi-nor-add-support-for-XT25F128B.patch b/patch/kernel/archive/meson64-5.19/general-spi-nor-add-support-for-XT25F128B.patch new file mode 100644 index 000000000..7492e57ff --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-spi-nor-add-support-for-XT25F128B.patch @@ -0,0 +1,90 @@ +From a5dc8bb92c6b67be7e48d442e821837b03fc129a Mon Sep 17 00:00:00 2001 +From: Andreas Rammhold +Date: Thu, 28 Jan 2021 09:43:36 +0000 +Subject: [PATCH 17/58] FROMLIST(v1): spi-nor: add support for XT25F128B + +This adds support for the XT25F128B as found on the RockPi4b SBC. + +Signed-off-by: Andreas Rammhold +--- + +This continues the efforts done in [1] & [2] that went stale. I've +tested this patch on my RockPi4b which only has the xt25f128b (and not +the xt25f32b as also propsed in [2]). I have tried to obtain a copy of +the datasheets but was unable to find them. Not sure whre you would get +them. + +While [1] was already for the new spi-nor layout it was missing the bits +in the core.{c,h} files. + +[1]: https://patchwork.ozlabs.org/project/linux-mtd/patch/CAMgqO2y9MYDj6antOaWLBRKU8vGEwqCB-Y1TkXTSWsmsed+W6A@mail.gmail.com/ +[2]: https://patchwork.ozlabs.org/project/linux-mtd/patch/20200206171941.GA2398@makrotopia.org/ +--- + drivers/mtd/spi-nor/Makefile | 1 + + drivers/mtd/spi-nor/core.c | 1 + + drivers/mtd/spi-nor/core.h | 1 + + drivers/mtd/spi-nor/xtx.c | 16 ++++++++++++++++ + 4 files changed, 19 insertions(+) + create mode 100644 drivers/mtd/spi-nor/xtx.c + +diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile +index e347b435a038..8992c592a896 100644 +--- a/drivers/mtd/spi-nor/Makefile ++++ b/drivers/mtd/spi-nor/Makefile +@@ -17,6 +17,7 @@ spi-nor-objs += sst.o + spi-nor-objs += winbond.o + spi-nor-objs += xilinx.o + spi-nor-objs += xmc.o ++spi-nor-objs += xtx.o + spi-nor-$(CONFIG_DEBUG_FS) += debugfs.o + obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o + +diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c +index 502967c76c5f..c171da5c8ca1 100644 +--- a/drivers/mtd/spi-nor/core.c ++++ b/drivers/mtd/spi-nor/core.c +@@ -1630,6 +1630,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = { + &spi_nor_winbond, + &spi_nor_xilinx, + &spi_nor_xmc, ++ &spi_nor_xtx, + }; + + static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, +diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h +index 3f841ec36e56..9e29d67b419b 100644 +--- a/drivers/mtd/spi-nor/core.h ++++ b/drivers/mtd/spi-nor/core.h +@@ -622,6 +622,7 @@ extern const struct spi_nor_manufacturer spi_nor_sst; + extern const struct spi_nor_manufacturer spi_nor_winbond; + extern const struct spi_nor_manufacturer spi_nor_xilinx; + extern const struct spi_nor_manufacturer spi_nor_xmc; ++extern const struct spi_nor_manufacturer spi_nor_xtx; + + extern const struct attribute_group *spi_nor_sysfs_groups[]; + +diff --git a/drivers/mtd/spi-nor/xtx.c b/drivers/mtd/spi-nor/xtx.c +new file mode 100644 +index 000000000000..73568854cf1e +--- /dev/null ++++ b/drivers/mtd/spi-nor/xtx.c +@@ -0,0 +1,16 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++ ++#include "core.h" ++ ++static const struct flash_info xtx_parts[] = { ++ /* XTX (Shenzhen Xin Tian Xia Tech) */ ++ { "xt25f128b", INFO(0x0b4018, 0, 64 * 1024, 256) }, ++}; ++ ++const struct spi_nor_manufacturer spi_nor_xtx = { ++ .name = "xtx", ++ .parts = xtx_parts, ++ .nparts = ARRAY_SIZE(xtx_parts), ++}; +-- +2.30.2 + diff --git a/patch/kernel/archive/meson64-5.19/general-usb-core-improve-handling-of-hubs-with-no-ports.patch b/patch/kernel/archive/meson64-5.19/general-usb-core-improve-handling-of-hubs-with-no-ports.patch new file mode 100644 index 000000000..8f553ebfe --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/general-usb-core-improve-handling-of-hubs-with-no-ports.patch @@ -0,0 +1,54 @@ +From 477a4f4816028d590f7b013e04b29319dbe66a24 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Wed, 23 Feb 2022 02:21:19 +0000 +Subject: [PATCH 50/90] FROMLIST(v1): usb: core: improve handling of hubs with + no ports + +I get the "hub doesn't have any ports" error message on a system with +Amlogic S905W SoC. Seems the SoC has internal USB 3.0 supports but +is crippled with regard to USB 3.0 ports. +Maybe we shouldn't consider this scenario an error. So let's change +the message to info level, but otherwise keep the handling of the +scenario as it is today. With the patch it looks like this on my +system. + +dwc2 c9100000.usb: supply vusb_d not found, using dummy regulator +dwc2 c9100000.usb: supply vusb_a not found, using dummy regulator +dwc2 c9100000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM +xhci-hcd xhci-hcd.0.auto: xHCI Host Controller +xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1 +xhci-hcd xhci-hcd.0.auto: hcc params 0x0228f664 hci version 0x100 quirks 0x0000000002010010 +xhci-hcd xhci-hcd.0.auto: irq 49, io mem 0xc9000000 +hub 1-0:1.0: USB hub found +hub 1-0:1.0: 2 ports detected +xhci-hcd xhci-hcd.0.auto: xHCI Host Controller +xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2 +xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed +usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. +hub 2-0:1.0: USB hub found +hub 2-0:1.0: hub has no ports, exiting + +Signed-off-by: Heiner Kallweit +--- + drivers/usb/core/hub.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c +index 588f3ded89cd..4151b960915b 100644 +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -1423,9 +1423,8 @@ static int hub_configure(struct usb_hub *hub, + ret = -ENODEV; + goto fail; + } else if (hub->descriptor->bNbrPorts == 0) { +- message = "hub doesn't have any ports!"; +- ret = -ENODEV; +- goto fail; ++ dev_info(hub_dev, "hub has no ports, exiting\n"); ++ return -ENODEV; + } + + /* +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch b/patch/kernel/archive/meson64-5.19/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch new file mode 100644 index 000000000..55406b7c6 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch @@ -0,0 +1,100 @@ +From 369f3f5b1a0145b876407bd5900a90554cd89a05 Mon Sep 17 00:00:00 2001 +From: usera +Date: Mon, 12 Apr 2021 17:16:42 +0300 +Subject: [PATCH 5/5] Fix:meson64: add gpio irq (patch from + https://lkml.org/lkml/2020/11/27/8) + +Signed-off-by: Vyacheslav Bocharov +--- + drivers/pinctrl/meson/pinctrl-meson.c | 41 +++++++++++++++++++++++++++ + drivers/pinctrl/meson/pinctrl-meson.h | 1 + + 2 files changed, 42 insertions(+) + +diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c +index 49851444a6e3..3f295e9c561d 100644 +--- a/drivers/pinctrl/meson/pinctrl-meson.c ++++ b/drivers/pinctrl/meson/pinctrl-meson.c +@@ -51,6 +51,7 @@ + #include + #include + #include ++#include + + #include "../core.h" + #include "../pinctrl-utils.h" +@@ -601,6 +602,40 @@ static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) + return !!(val & BIT(bit)); + } + ++static int meson_gpio_to_irq(struct gpio_chip *chip, unsigned int gpio) ++{ ++ struct meson_pinctrl *pc = gpiochip_get_data(chip); ++ struct meson_bank *bank; ++ struct irq_fwspec fwspec; ++ int hwirq; ++ ++ if (meson_get_bank(pc, gpio, &bank)) ++ return -EINVAL; ++ ++ if (bank->irq_first < 0) { ++ dev_warn(pc->dev, "no support irq for pin[%d]\n", gpio); ++ return -EINVAL; ++ } ++ if (!pc->of_irq) { ++ dev_err(pc->dev, "invalid device node of gpio INTC\n"); ++ return -EINVAL; ++ } ++ ++ hwirq = gpio - bank->first + bank->irq_first; ++ printk("gpio irq setup: hwirq: 0x%X irqfirst: 0x%X irqlast: 0x%X pin[%d]\n", hwirq, bank->irq_first, bank->irq_last, gpio); ++ if (hwirq > bank->irq_last) ++ { ++ dev_warn(pc->dev, "no more irq for pin[%d]\n", gpio); ++ return -EINVAL; ++ } ++ fwspec.fwnode = of_node_to_fwnode(pc->of_irq); ++ fwspec.param_count = 2; ++ fwspec.param[0] = hwirq; ++ fwspec.param[1] = IRQ_TYPE_NONE; ++ ++ return irq_create_fwspec_mapping(&fwspec); ++} ++ + static int meson_gpiolib_register(struct meson_pinctrl *pc) + { + int ret; +@@ -615,6 +650,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) + pc->chip.direction_output = meson_gpio_direction_output; + pc->chip.get = meson_gpio_get; + pc->chip.set = meson_gpio_set; ++ pc->chip.to_irq = meson_gpio_to_irq; + pc->chip.base = -1; + pc->chip.ngpio = pc->data->num_pins; + pc->chip.can_sleep = false; +@@ -685,6 +721,11 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, + + pc->of_node = gpio_np; + ++ pc->of_irq = of_find_compatible_node(NULL, ++ NULL, "amlogic,meson-gpio-intc"); ++ if (!pc->of_irq) ++ pc->of_irq = of_find_compatible_node(NULL, ++ NULL, "amlogic,meson-gpio-intc-ext"); + pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); + if (IS_ERR_OR_NULL(pc->reg_mux)) { + dev_err(pc->dev, "mux registers not found\n"); +diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h +index ff5372e0a475..07f277946d1b 100644 +--- a/drivers/pinctrl/meson/pinctrl-meson.h ++++ b/drivers/pinctrl/meson/pinctrl-meson.h +@@ -132,6 +132,7 @@ struct meson_pinctrl { + struct regmap *reg_ds; + struct gpio_chip chip; + struct device_node *of_node; ++ struct device_node *of_irq; + }; + + #define FUNCTION(fn) \ +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/jethome-0002-arm64-meson-add-JetHub-D1p-device.patch b/patch/kernel/archive/meson64-5.19/jethome-0002-arm64-meson-add-JetHub-D1p-device.patch new file mode 100644 index 000000000..d37a39bc0 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/jethome-0002-arm64-meson-add-JetHub-D1p-device.patch @@ -0,0 +1,47 @@ +From 2428abb8dd4bc3c176a91a6d53d13b8b0cc67e24 Mon Sep 17 00:00:00 2001 +From: Vyacheslav Bocharov +Date: Wed, 15 Jun 2022 12:47:23 +0300 +Subject: [PATCH] arm64: meson: add JetHub D1p device + +Add support for JetHub D1p variation of D1 series home automation controller. +--- + .../dts/amlogic/meson-axg-jethome-jethub-j100.dts | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +index 8b0d586aa84e..f46b0ec9ec13 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts ++++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +@@ -258,18 +258,14 @@ &sd_emmc_b { + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; +- non-removable; + disable-wp; ++ keep-power-in-suspend; ++ broken-cd;/* cd-gpios = <&gpio GPIOAO_3 GPIO_ACTIVE_LOW>;*/ + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +- +- brcmf: wifi@1 { +- reg = <1>; +- compatible = "brcm,bcm4329-fmac"; +- }; + }; + + /* emmc storage */ +@@ -368,3 +364,8 @@ &cpu2 { + &cpu3 { + #cooling-cells = <2>; + }; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vddio_ao18>; ++}; +-- +2.30.2 + diff --git a/patch/kernel/archive/meson64-5.19/jethome-0003-overlay.patch b/patch/kernel/archive/meson64-5.19/jethome-0003-overlay.patch new file mode 100644 index 000000000..8d19e347b --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/jethome-0003-overlay.patch @@ -0,0 +1,65 @@ +From b47c9e9c9cba1c03fd8d99cca29989f3bde1c83a Mon Sep 17 00:00:00 2001 +From: root +Date: Tue, 24 May 2022 16:43:18 +0300 +Subject: [PATCH] Overlay d1plus + +--- + arch/arm64/boot/dts/amlogic/overlay/Makefile | 3 ++- + .../dts/amlogic/overlay/jethub-d1plus.dts | 23 +++++++++++++++++++ + 2 files changed, 25 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/amlogic/overlay/jethub-d1plus.dts + +diff --git a/arch/arm64/boot/dts/amlogic/overlay/Makefile b/arch/arm64/boot/dts/amlogic/overlay/Makefile +index 8630fd1a182..bcc8130119d 100644 +--- a/arch/arm64/boot/dts/amlogic/overlay/Makefile ++++ b/arch/arm64/boot/dts/amlogic/overlay/Makefile +@@ -5,7 +5,8 @@ dtbo-$(CONFIG_ARCH_MESON) += \ + meson-uartA.dtbo \ + meson-uartC.dtbo \ + meson-w1-gpio.dtbo \ +- meson-w1AB-gpio.dtbo ++ meson-w1AB-gpio.dtbo \ ++ jethub-d1plus.dtbo + + scr-$(CONFIG_ARCH_MESON) += \ + meson-fixup.scr +diff --git a/arch/arm64/boot/dts/amlogic/overlay/jethub-d1plus.dts b/arch/arm64/boot/dts/amlogic/overlay/jethub-d1plus.dts +new file mode 100644 +index 00000000000..a5ea7e98622 +--- /dev/null ++++ b/arch/arm64/boot/dts/amlogic/overlay/jethub-d1plus.dts +@@ -0,0 +1,23 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "jethome,jethub-j100"; ++ fragment@0 { ++ target-path = "/soc/bus@ffd00000/serial@23000"; ++ __overlay__ { ++ /delete-node/ bluetooth; ++ }; ++ }; ++ fragment@1 { ++ target-path = "/soc/bus@ffd00000/serial@23000"; ++ __overlay__ { ++ bluetooth { ++ compatible = "realtek,rtl8822cs-bt"; ++ enable-gpios = <&gpio 7 0>; ++ /* host-wake-gpios = <&gpio 8 0>;*/ ++ device-wake-gpios = <&gpio 6 0>; ++ }; ++ }; ++ }; ++}; +-- +2.30.2 + + ++ bluetooth { ++ compatible = "realtek,rtl8822cs-bt"; ++ enable-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; ++ /* host-wake-gpios = <&gpio GPIOAO_8 GPIO_ACTIVE_HIGH>;*/ ++ device-wake-gpios = <&gpio GPIOZ_6 GPIO_ACTIVE_HIGH>; ++ }; + }; diff --git a/patch/kernel/archive/meson64-5.19/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch b/patch/kernel/archive/meson64-5.19/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch new file mode 100644 index 000000000..854e73490 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch @@ -0,0 +1,41 @@ +From 9c2b8d82e36bf5ce932e6561d13adf5c7c5d367f Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Thu, 3 Nov 2016 15:29:25 +0100 +Subject: [PATCH 06/90] HACK: arm64: dts: meson: add support for GX PM and + Virtual RTC + +Signed-off-by: Neil Armstrong +--- + arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +index 99b8916e0c5d..d6dc407127cd 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +@@ -221,6 +221,10 @@ sm: secure-monitor { + }; + }; + ++ system-suspend { ++ compatible = "amlogic,meson-gx-pm"; ++ }; ++ + efuse: efuse { + compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; + #address-cells = <1>; +@@ -459,6 +463,11 @@ clkc_AO: clock-controller { + }; + }; + ++ vrtc: rtc@a8 { ++ compatible = "amlogic,meson-vrtc"; ++ reg = <0x0 0x000a8 0x0 0x4>; ++ }; ++ + cec_AO: cec@100 { + compatible = "amlogic,meson-gx-ao-cec"; + reg = <0x0 0x00100 0x0 0x14>; +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/meson-gxbb-dts-i2cX-missing-pins.patch b/patch/kernel/archive/meson64-5.19/meson-gxbb-dts-i2cX-missing-pins.patch new file mode 100644 index 000000000..2610f15c8 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/meson-gxbb-dts-i2cX-missing-pins.patch @@ -0,0 +1,22 @@ +diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +index 7c029f552a23..b3c22861b022 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +@@ -333,6 +333,8 @@ &hwrng { + + &i2c_A { + clocks = <&clkc CLKID_I2C>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c_a_pins>; + }; + + &i2c_AO { +@@ -341,6 +343,8 @@ &i2c_AO { + + &i2c_B { + clocks = <&clkc CLKID_I2C>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c_b_pins>; + }; + + &i2c_C { diff --git a/patch/kernel/archive/meson64-5.19/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch b/patch/kernel/archive/meson64-5.19/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch new file mode 100644 index 000000000..d0e4963fe --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch @@ -0,0 +1,39 @@ +From 975c23d02776b023a75e6090b521a839e67a8c42 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Sun, 21 Nov 2021 19:12:07 +0000 +Subject: [PATCH 66/90] WIP: drivers: meson: vdec: add HEVC support to GXBB + +It's not clear whether the GXL firmware is the same one used with GXBB +but let's try it and see! + +Signed-off-by: Christian Hewitt +--- + drivers/staging/media/meson/vdec/vdec_platform.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c +index 8592cb3aaea9..810039a02b44 100644 +--- a/drivers/staging/media/meson/vdec/vdec_platform.c ++++ b/drivers/staging/media/meson/vdec/vdec_platform.c +@@ -16,6 +16,18 @@ + + static const struct amvdec_format vdec_formats_gxbb[] = { + { ++ .pixfmt = V4L2_PIX_FMT_HEVC, ++ .min_buffers = 4, ++ .max_buffers = 24, ++ .max_width = 3840, ++ .max_height = 2160, ++ .vdec_ops = &vdec_hevc_ops, ++ .codec_ops = &codec_hevc_ops, ++ .firmware_path = "meson/vdec/gxl_hevc.bin", ++ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, ++ .flags = V4L2_FMT_FLAG_COMPRESSED | ++ V4L2_FMT_FLAG_DYN_RESOLUTION, ++ }, { + .pixfmt = V4L2_PIX_FMT_H264, + .min_buffers = 2, + .max_buffers = 24, +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/meson-gxm-vdec-add-VP9-support-to-GXM.patch b/patch/kernel/archive/meson64-5.19/meson-gxm-vdec-add-VP9-support-to-GXM.patch new file mode 100644 index 000000000..66013b565 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/meson-gxm-vdec-add-VP9-support-to-GXM.patch @@ -0,0 +1,44 @@ +From fa0fc8498a811c85bace6138f60b7d09f07d18b8 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Thu, 25 Nov 2021 11:31:43 +0000 +Subject: [PATCH 43/90] FROMLIST(v1): drivers: meson: vdec: add VP9 support to + GXM + +VP9 support for GXM appears to have been missed from the original +codec submission [0] but it works well, so let's add support. + +[0] https://github.com/torvalds/linux/commit/00c43088aa680989407b6afbda295f67b3f123f1 + +Signed-off-by: Christian Hewitt +--- + drivers/staging/media/meson/vdec/vdec_platform.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c +index 810039a02b44..38f353c6d27d 100644 +--- a/drivers/staging/media/meson/vdec/vdec_platform.c ++++ b/drivers/staging/media/meson/vdec/vdec_platform.c +@@ -27,7 +27,19 @@ static const struct amvdec_format vdec_formats_gxbb[] = { + .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, + .flags = V4L2_FMT_FLAG_COMPRESSED | + V4L2_FMT_FLAG_DYN_RESOLUTION, +- }, { ++ }, { ++ .pixfmt = V4L2_PIX_FMT_VP9, ++ .min_buffers = 16, ++ .max_buffers = 24, ++ .max_width = 3840, ++ .max_height = 2160, ++ .vdec_ops = &vdec_hevc_ops, ++ .codec_ops = &codec_vp9_ops, ++ .firmware_path = "meson/vdec/gxl_vp9.bin", ++ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 }, ++ .flags = V4L2_FMT_FLAG_COMPRESSED | ++ V4L2_FMT_FLAG_DYN_RESOLUTION, ++ }, { + .pixfmt = V4L2_PIX_FMT_H264, + .min_buffers = 2, + .max_buffers = 24, +-- +2.35.1 + diff --git a/patch/kernel/archive/meson64-5.19/meson-sm1-dts-add-higher-clocks.patch b/patch/kernel/archive/meson64-5.19/meson-sm1-dts-add-higher-clocks.patch new file mode 100644 index 000000000..d367bae19 --- /dev/null +++ b/patch/kernel/archive/meson64-5.19/meson-sm1-dts-add-higher-clocks.patch @@ -0,0 +1,34 @@ +From a11802ecb5686153614aa19a089900c22928988c Mon Sep 17 00:00:00 2001 +From: Igor Pecovnik +Date: Tue, 4 Aug 2020 22:51:56 +0200 +Subject: [PATCH] Add higher clocks for SM1 family + +Signed-off-by: Igor Pecovnik +--- + arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +index d4ec735fb..a35cad1d4 100644 +--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi ++++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +@@ -150,6 +150,16 @@ opp-1908000000 { + opp-hz = /bits/ 64 <1908000000>; + opp-microvolt = <950000>; + }; ++ ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <1000000>; ++ }; ++ ++ opp-2100000000 { ++ opp-hz = /bits/ 64 <2100000000>; ++ opp-microvolt = <1022000>; ++ }; + }; + }; + +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/meson64-edge b/patch/kernel/meson64-edge index cfef2a570..dbfc941be 120000 --- a/patch/kernel/meson64-edge +++ b/patch/kernel/meson64-edge @@ -1 +1 @@ -archive/meson64-5.17 \ No newline at end of file +archive/meson64-5.19 \ No newline at end of file