diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch deleted file mode 100644 index c1a25e969..000000000 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 86ef31fcb116682d399b9723a7ab66c87e6f2cc5 Mon Sep 17 00:00:00 2001 -From: Stephen Graf -Date: Tue, 18 Feb 2025 05:12:44 +0000 -Subject: add TCON global control reg for pad selection - -Signed-off-by: Stephen Graf ---- - drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++++ - drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 + - 2 files changed, 5 insertions(+) - -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c -index af67bf2e6e09..88984572f5c5 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c -@@ -1308,6 +1308,10 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master, - goto err_free_dclk; - } - -+ regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, -+ SUN4I_TCON_GCTL_PAD_SEL, -+ SUN4I_TCON_GCTL_PAD_SEL); -+ - if (tcon->quirks->has_channel_0) { - /* - * If we have an LVDS panel connected to the TCON, we should -diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h -index bd4abc90062b..e8d28bad4060 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.h -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h -@@ -19,6 +19,7 @@ - - #define SUN4I_TCON_GCTL_REG 0x0 - #define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31) -+#define SUN4I_TCON_GCTL_PAD_SEL BIT(1) - #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0) - #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0) - #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0) --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch deleted file mode 100644 index 8a00dac93..000000000 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 02dc976a5f62b393f378c056888f121ba1880fc5 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Fri, 21 Feb 2025 00:58:01 +0000 -Subject: arm64: dts: allwinner: h616: Add Mali GPU node - -The Allwinner H616 SoC contains a Mali-G31 MP2 GPU, which is of the Mali -Bifrost family. There is a power domain specifically for that GPU, which -needs to be enabled to make use of the it. - -Add the DT nodes for those two devices, and link them together through -the "power-domains" property. -Any board wishing to use the GPU would need to enable the GPU node and -specify the "mali-supply" regulator. - -Signed-off-by: Andre Przywara ---- - .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 21 +++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -index cdce3dcb8ec0..ceedae9e399b 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -150,6 +150,21 @@ soc { - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; - -+ gpu: gpu@1800000 { -+ compatible = "allwinner,sun50i-h616-mali", -+ "arm,mali-bifrost"; -+ reg = <0x1800000 0x40000>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "job", "mmu", "gpu"; -+ clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>; -+ clock-names = "core", "bus"; -+ power-domains = <&prcm_ppu 2>; -+ resets = <&ccu RST_BUS_GPU>; -+ status = "disabled"; -+ }; -+ - crypto: crypto@1904000 { - compatible = "allwinner,sun50i-h616-crypto"; - reg = <0x01904000 0x800>; -@@ -874,6 +889,12 @@ r_ccu: clock@7010000 { - #reset-cells = <1>; - }; - -+ prcm_ppu: power-controller@7010250 { -+ compatible = "allwinner,sun50i-h616-prcm-ppu"; -+ reg = <0x07010250 0x10>; -+ #power-domain-cells = <1>; -+ }; -+ - nmi_intc: interrupt-controller@7010320 { - compatible = "allwinner,sun50i-h616-nmi", - "allwinner,sun9i-a80-nmi"; --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch deleted file mode 100644 index 6bd5c7665..000000000 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch +++ /dev/null @@ -1,86 +0,0 @@ -From b41f5a9ec8841c0342f101585c64c292019543d2 Mon Sep 17 00:00:00 2001 -From: Ryan Walklin -Date: Sun, 29 Sep 2024 22:04:54 +1300 -Subject: clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support - -The DE33 is a newer version of the Allwinner Display Engine IP block, -found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already -supported by the mainline driver. - -The DE33 in the H616 has mixer0 and writeback units. The clocks -and resets required are identical to the H3 and H5 respectively, so use -those existing structs for the H616 description. - -There are two additional 32-bit registers (at offsets 0x24 and 0x28) -which require clearing and setting respectively to bring up the -hardware. The function of these registers is currently unknown, and the -values are taken from the out-of-tree driver. - -Add the required clock description struct and compatible string to the -DE2 driver. - -Signed-off-by: Ryan Walklin ---- - drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c -index 7683ea08d8e3..83eab6f132aa 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c -+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -239,6 +240,16 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = { - .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets), - }; - -+static const struct sunxi_ccu_desc sun50i_h616_de33_clk_desc = { -+ .ccu_clks = sun8i_de2_ccu_clks, -+ .num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks), -+ -+ .hw_clks = &sun8i_h3_de2_hw_clks, -+ -+ .resets = sun50i_h5_de2_resets, -+ .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets), -+}; -+ - static int sunxi_de2_clk_probe(struct platform_device *pdev) - { - struct clk *bus_clk, *mod_clk; -@@ -291,6 +302,16 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) - goto err_disable_mod_clk; - } - -+ /* -+ * The DE33 requires these additional (unknown) registers set -+ * during initialisation. -+ */ -+ if (of_device_is_compatible(pdev->dev.of_node, -+ "allwinner,sun50i-h616-de33-clk")) { -+ writel(0, reg + 0x24); -+ writel(0x0000a980, reg + 0x28); -+ } -+ - ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc); - if (ret) - goto err_assert_reset; -@@ -335,6 +356,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { - .compatible = "allwinner,sun50i-h6-de3-clk", - .data = &sun50i_h5_de2_clk_desc, - }, -+ { -+ .compatible = "allwinner,sun50i-h616-de33-clk", -+ .data = &sun50i_h616_de33_clk_desc, -+ }, - { } - }; - MODULE_DEVICE_TABLE(of, sunxi_de2_clk_ids); --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch deleted file mode 100644 index 7284fe0e0..000000000 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch +++ /dev/null @@ -1,111 +0,0 @@ -From ce56f3f385e0830a1e242f9fca9a82c3067ba03f Mon Sep 17 00:00:00 2001 -From: Philippe Simons -Date: Thu, 13 Mar 2025 00:23:18 +0100 -Subject: drm/panfrost: Add PM runtime flags - -Allwinner H616 has a dedicated power domain for its Mali G31. - -Currently after probe, the GPU is put in runtime suspend which -disable the power domain. -On first usage of GPU, the power domain enable hangs the system. - -This series adds the necessary calls to enable the clocks and -deasserting the reset line after the power domain enabling and -asserting the reset line and disabling the clocks prior to the -power domain disabling. - -This allows to use the Mali GPU on all Allwinner H616 -boards and devices. - -When the GPU is the only device attached to a single power domain, -core genpd disable and enable it when gpu enter and leave runtime suspend. - -Some power-domain requires a sequence before disabled, -and the reverse when enabled. - -Add GPU_PM_RT flag, and implement in -panfrost_device_runtime_suspend/resume. - -Signed-off-by: Philippe Simons ---- - drivers/gpu/drm/panfrost/panfrost_device.c | 33 ++++++++++++++++++++++ - drivers/gpu/drm/panfrost/panfrost_device.h | 3 ++ - 2 files changed, 36 insertions(+) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c -index a45e4addcc19..93d48e97ce10 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_device.c -+++ b/drivers/gpu/drm/panfrost/panfrost_device.c -@@ -406,11 +406,36 @@ void panfrost_device_reset(struct panfrost_device *pfdev) - static int panfrost_device_runtime_resume(struct device *dev) - { - struct panfrost_device *pfdev = dev_get_drvdata(dev); -+ int ret; -+ -+ if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) { -+ ret = reset_control_deassert(pfdev->rstc); -+ if (ret) -+ return ret; -+ -+ ret = clk_enable(pfdev->clock); -+ if (ret) -+ goto err_clk; -+ -+ if (pfdev->bus_clock) { -+ ret = clk_enable(pfdev->bus_clock); -+ if (ret) -+ goto err_bus_clk; -+ } -+ } - - panfrost_device_reset(pfdev); - panfrost_devfreq_resume(pfdev); - - return 0; -+ -+err_bus_clk: -+ if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) -+ clk_disable(pfdev->clock); -+err_clk: -+ if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) -+ reset_control_assert(pfdev->rstc); -+ return ret; - } - - static int panfrost_device_runtime_suspend(struct device *dev) -@@ -426,6 +451,14 @@ static int panfrost_device_runtime_suspend(struct device *dev) - panfrost_gpu_suspend_irq(pfdev); - panfrost_gpu_power_off(pfdev); - -+ if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) { -+ if (pfdev->bus_clock) -+ clk_disable(pfdev->bus_clock); -+ -+ clk_disable(pfdev->clock); -+ reset_control_assert(pfdev->rstc); -+ } -+ - return 0; - } - -diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h -index cffcb0ac7c11..861555ceea65 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_device.h -+++ b/drivers/gpu/drm/panfrost/panfrost_device.h -@@ -36,10 +36,13 @@ enum panfrost_drv_comp_bits { - * enum panfrost_gpu_pm - Supported kernel power management features - * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend - * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend -+ * @GPU_PM_RT: Allow disabling clocks and asserting the reset control during -+ * system runtime suspend - */ - enum panfrost_gpu_pm { - GPU_PM_CLK_DIS, - GPU_PM_VREG_OFF, -+ GPU_PM_RT - }; - - struct panfrost_features { --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-panfrost-add-h616-compatible-string.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-panfrost-add-h616-compatible-string.patch deleted file mode 100644 index 57ea76e9a..000000000 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-panfrost-add-h616-compatible-string.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 16e3a927918e0c6349c2bfcbe468ee1690eaaaca Mon Sep 17 00:00:00 2001 -From: Philippe Simons -Date: Thu, 13 Mar 2025 00:23:19 +0100 -Subject: drm/panfrost: add h616 compatible string - -Tie the Allwinner compatible string to the GPU_PM_RT feature bits that will -toggle the clocks and the reset line whenever the power domain is changing -state. - -Signed-off-by: Philippe Simons ---- - drivers/gpu/drm/panfrost/panfrost_drv.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c -index 0f3935556ac7..9470c04c5487 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_drv.c -+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c -@@ -776,6 +776,13 @@ static const struct panfrost_compatible default_data = { - .pm_domain_names = NULL, - }; - -+static const struct panfrost_compatible allwinner_h616_data = { -+ .num_supplies = ARRAY_SIZE(default_supplies) - 1, -+ .supply_names = default_supplies, -+ .num_pm_domains = 1, -+ .pm_features = BIT(GPU_PM_RT), -+}; -+ - static const struct panfrost_compatible amlogic_data = { - .num_supplies = ARRAY_SIZE(default_supplies) - 1, - .supply_names = default_supplies, -@@ -859,6 +866,7 @@ static const struct of_device_id dt_match[] = { - { .compatible = "mediatek,mt8186-mali", .data = &mediatek_mt8186_data }, - { .compatible = "mediatek,mt8188-mali", .data = &mediatek_mt8188_data }, - { .compatible = "mediatek,mt8192-mali", .data = &mediatek_mt8192_data }, -+ { .compatible = "allwinner,sun50i-h616-mali", .data = &allwinner_h616_data }, - {} - }; - MODULE_DEVICE_TABLE(of, dt_match); --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch deleted file mode 100644 index a63c07fef..000000000 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 37f8be7eaca786f85cf2a17dfd33227e2ff45780 Mon Sep 17 00:00:00 2001 -From: Philippe Simons -Date: Thu, 3 Apr 2025 07:52:10 +0200 -Subject: drm/panfrost: reorder pd/clk/rst sequence - -According to Mali manuals, the powerup sequence should be -enable pd, asserting the reset then enabling the clock and -the reverse for powerdown. - -Signed-off-by: Philippe Simons ---- - drivers/gpu/drm/panfrost/panfrost_device.c | 38 +++++++++++----------- - 1 file changed, 19 insertions(+), 19 deletions(-) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c -index 93d48e97ce10..5d35076b2e6d 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_device.c -+++ b/drivers/gpu/drm/panfrost/panfrost_device.c -@@ -209,10 +209,20 @@ int panfrost_device_init(struct panfrost_device *pfdev) - - spin_lock_init(&pfdev->cycle_counter.lock); - -+ err = panfrost_pm_domain_init(pfdev); -+ if (err) -+ return err; -+ -+ err = panfrost_reset_init(pfdev); -+ if (err) { -+ dev_err(pfdev->dev, "reset init failed %d\n", err); -+ goto out_pm_domain; -+ } -+ - err = panfrost_clk_init(pfdev); - if (err) { - dev_err(pfdev->dev, "clk init failed %d\n", err); -- return err; -+ goto out_reset; - } - - err = panfrost_devfreq_init(pfdev); -@@ -229,25 +239,15 @@ int panfrost_device_init(struct panfrost_device *pfdev) - goto out_devfreq; - } - -- err = panfrost_reset_init(pfdev); -- if (err) { -- dev_err(pfdev->dev, "reset init failed %d\n", err); -- goto out_regulator; -- } -- -- err = panfrost_pm_domain_init(pfdev); -- if (err) -- goto out_reset; -- - pfdev->iomem = devm_platform_ioremap_resource(pfdev->pdev, 0); - if (IS_ERR(pfdev->iomem)) { - err = PTR_ERR(pfdev->iomem); -- goto out_pm_domain; -+ goto out_regulator; - } - - err = panfrost_gpu_init(pfdev); - if (err) -- goto out_pm_domain; -+ goto out_regulator; - - err = panfrost_mmu_init(pfdev); - if (err) -@@ -268,16 +268,16 @@ int panfrost_device_init(struct panfrost_device *pfdev) - panfrost_mmu_fini(pfdev); - out_gpu: - panfrost_gpu_fini(pfdev); --out_pm_domain: -- panfrost_pm_domain_fini(pfdev); --out_reset: -- panfrost_reset_fini(pfdev); - out_regulator: - panfrost_regulator_fini(pfdev); - out_devfreq: - panfrost_devfreq_fini(pfdev); - out_clk: - panfrost_clk_fini(pfdev); -+out_reset: -+ panfrost_reset_fini(pfdev); -+out_pm_domain: -+ panfrost_pm_domain_fini(pfdev); - return err; - } - -@@ -287,11 +287,11 @@ void panfrost_device_fini(struct panfrost_device *pfdev) - panfrost_job_fini(pfdev); - panfrost_mmu_fini(pfdev); - panfrost_gpu_fini(pfdev); -- panfrost_pm_domain_fini(pfdev); -- panfrost_reset_fini(pfdev); - panfrost_devfreq_fini(pfdev); - panfrost_regulator_fini(pfdev); - panfrost_clk_fini(pfdev); -+ panfrost_reset_fini(pfdev); -+ panfrost_pm_domain_fini(pfdev); - } - - #define PANFROST_EXCEPTION(id) \ --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.16/0003-drm-sun4i-Report-page-flip-after-vsync-is-complete-n.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-Report-page-flip-after-vsync-is-complete-n.patch similarity index 100% rename from patch/kernel/archive/sunxi-6.16/0003-drm-sun4i-Report-page-flip-after-vsync-is-complete-n.patch rename to patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-Report-page-flip-after-vsync-is-complete-n.patch diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch index f5555d4b0..94a4e75c5 100644 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch +++ b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch @@ -17,7 +17,7 @@ Reviewed-by: Chen-Yu Tsai 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c -index aa987bca1dbb..cb9b694fef10 100644 +index fd25316a6d65..3840242dfaf3 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -295,6 +295,11 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, @@ -29,10 +29,10 @@ index aa987bca1dbb..cb9b694fef10 100644 + layer->channel = channel; + layer->overlay = 0; + - if (index == 0) - type = DRM_PLANE_TYPE_PRIMARY; - -@@ -325,10 +330,6 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, + /* possible crtcs are set later */ + ret = drm_universal_plane_init(drm, &layer->plane, 0, + &sun8i_ui_layer_funcs, +@@ -322,10 +327,6 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, } drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs); diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch index 2757ba5e2..c5a24b0f1 100644 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch +++ b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch @@ -1,4 +1,4 @@ -From 45d06599927825fe1fa3c374508d6d0c8c9f9f52 Mon Sep 17 00:00:00 2001 +From 7e2082f55e6595ca976245d7a7ac1d89d5b1258b Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 29 Sep 2024 22:04:48 +1300 Subject: drm: sun4i: de2/de3: add generic blender register reference function @@ -17,10 +17,10 @@ Signed-off-by: Ryan Walklin 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h -index 82956cb97cfd..75facc7d1fa6 100644 +index 258f528202c1..ecba096c553b 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h -@@ -224,6 +224,12 @@ sun8i_blender_base(struct sun8i_mixer *mixer) +@@ -227,6 +227,12 @@ sun8i_blender_base(struct sun8i_mixer *mixer) return mixer->cfg->de_type == sun8i_mixer_de3 ? DE3_BLD_BASE : DE2_BLD_BASE; } @@ -34,5 +34,5 @@ index 82956cb97cfd..75facc7d1fa6 100644 sun8i_channel_base(struct sun8i_mixer *mixer, int channel) { -- -2.35.3 +2.51.0 diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch index 0df4a242c..169051377 100644 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch +++ b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch @@ -35,19 +35,19 @@ index e12a81fa9108..2d5a2cf7cba2 100644 fmt_type, encoding, range); return; diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index a50c583852ed..16e018aa4aae 100644 +index fb5348388eb5..c38ea430a149 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -584,7 +584,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, - base = sun8i_blender_base(mixer); +@@ -629,7 +629,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, + if (!mixer->hw_preconfigured) { /* Reset registers and disable unused sub-engines */ - if (mixer->cfg->is_de3) { + if (mixer->cfg->de_type == sun8i_mixer_de3) { for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4) regmap_write(mixer->engine.regs, i, 0); -@@ -675,6 +675,7 @@ static void sun8i_mixer_remove(struct platform_device *pdev) +@@ -732,6 +732,7 @@ static void sun8i_mixer_remove(struct platform_device *pdev) static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { .ccsc = CCSC_MIXER0_LAYOUT, @@ -55,7 +55,7 @@ index a50c583852ed..16e018aa4aae 100644 .scaler_mask = 0xf, .scanline_yuv = 2048, .ui_num = 3, -@@ -683,6 +684,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { +@@ -740,6 +741,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { .ccsc = CCSC_MIXER1_LAYOUT, @@ -63,7 +63,7 @@ index a50c583852ed..16e018aa4aae 100644 .scaler_mask = 0x3, .scanline_yuv = 2048, .ui_num = 1, -@@ -691,6 +693,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { +@@ -748,6 +750,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { .ccsc = CCSC_MIXER0_LAYOUT, @@ -71,7 +71,7 @@ index a50c583852ed..16e018aa4aae 100644 .mod_rate = 432000000, .scaler_mask = 0xf, .scanline_yuv = 2048, -@@ -700,6 +703,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { +@@ -757,6 +760,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { .ccsc = CCSC_MIXER0_LAYOUT, @@ -79,7 +79,7 @@ index a50c583852ed..16e018aa4aae 100644 .mod_rate = 297000000, .scaler_mask = 0xf, .scanline_yuv = 2048, -@@ -709,6 +713,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { +@@ -766,6 +770,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { .ccsc = CCSC_MIXER1_LAYOUT, @@ -87,7 +87,7 @@ index a50c583852ed..16e018aa4aae 100644 .mod_rate = 297000000, .scaler_mask = 0x3, .scanline_yuv = 2048, -@@ -717,6 +722,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { +@@ -774,6 +779,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { }; static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { @@ -95,7 +95,7 @@ index a50c583852ed..16e018aa4aae 100644 .vi_num = 2, .ui_num = 1, .scaler_mask = 0x3, -@@ -727,6 +733,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { +@@ -784,6 +790,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = { .ccsc = CCSC_D1_MIXER0_LAYOUT, @@ -103,7 +103,7 @@ index a50c583852ed..16e018aa4aae 100644 .mod_rate = 297000000, .scaler_mask = 0x3, .scanline_yuv = 2048, -@@ -736,6 +743,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = { +@@ -793,6 +800,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = { static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = { .ccsc = CCSC_MIXER1_LAYOUT, @@ -111,7 +111,7 @@ index a50c583852ed..16e018aa4aae 100644 .mod_rate = 297000000, .scaler_mask = 0x1, .scanline_yuv = 1024, -@@ -745,6 +753,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = { +@@ -802,6 +810,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = { static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { .ccsc = CCSC_MIXER0_LAYOUT, @@ -119,7 +119,7 @@ index a50c583852ed..16e018aa4aae 100644 .mod_rate = 297000000, .scaler_mask = 0xf, .scanline_yuv = 4096, -@@ -754,6 +763,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { +@@ -811,6 +820,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { .ccsc = CCSC_MIXER1_LAYOUT, @@ -127,7 +127,7 @@ index a50c583852ed..16e018aa4aae 100644 .mod_rate = 297000000, .scaler_mask = 0x3, .scanline_yuv = 2048, -@@ -763,7 +773,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { +@@ -820,7 +830,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { .ccsc = CCSC_MIXER0_LAYOUT, @@ -137,7 +137,7 @@ index a50c583852ed..16e018aa4aae 100644 .mod_rate = 600000000, .scaler_mask = 0xf, diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h -index 8417b8fef2e1..82956cb97cfd 100644 +index 860a2f2cec24..258f528202c1 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -151,6 +151,11 @@ enum { @@ -161,7 +161,7 @@ index 8417b8fef2e1..82956cb97cfd 100644 unsigned int has_formatter : 1; unsigned int scanline_yuv; }; -@@ -216,13 +221,13 @@ engine_to_sun8i_mixer(struct sunxi_engine *engine) +@@ -219,13 +224,13 @@ engine_to_sun8i_mixer(struct sunxi_engine *engine) static inline u32 sun8i_blender_base(struct sun8i_mixer *mixer) { diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch index 4357b5b77..0ff70fbef 100644 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch +++ b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch @@ -1,4 +1,4 @@ -From 18890b5c9dbf9270b7f0e42875d6b8bd14ee6624 Mon Sep 17 00:00:00 2001 +From 52a7d96a033601a9cee79fe217e895cfb860b872 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 29 Sep 2024 22:04:46 +1300 Subject: drm: sun4i: de2/de3: refactor mixer initialisation @@ -10,14 +10,14 @@ Signed-off-by: Jernej Skrabec Signed-off-by: Ryan Walklin Reviewed-by: Andre Przywara --- - drivers/gpu/drm/sun4i/sun8i_mixer.c | 64 +++++++++++++++-------------- - 1 file changed, 34 insertions(+), 30 deletions(-) + drivers/gpu/drm/sun4i/sun8i_mixer.c | 70 ++++++++++++++++------------- + 1 file changed, 38 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index 16e018aa4aae..18745af08954 100644 +index c38ea430a149..0419859a9f89 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -468,6 +468,38 @@ static int sun8i_mixer_of_get_id(struct device_node *node) +@@ -503,6 +503,42 @@ static int sun8i_mixer_of_get_id(struct device_node *node) return of_ep.id; } @@ -26,9 +26,11 @@ index 16e018aa4aae..18745af08954 100644 + unsigned int base = sun8i_blender_base(mixer); + int plane_cnt, i; + ++ if (!mixer->hw_preconfigured) { + /* Enable the mixer */ + regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, + SUN8I_MIXER_GLOBAL_CTL_RT_EN); ++ } + + /* Set background color to black */ + regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), @@ -49,14 +51,16 @@ index 16e018aa4aae..18745af08954 100644 + SUN8I_MIXER_BLEND_MODE(base, i), + SUN8I_MIXER_BLEND_MODE_DEF); + ++ if (!mixer->hw_preconfigured) { + regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), + SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); ++ } +} + static int sun8i_mixer_bind(struct device *dev, struct device *master, void *data) { -@@ -476,8 +508,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, +@@ -511,8 +547,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, struct sun4i_drv *drv = drm->dev_private; struct sun8i_mixer *mixer; void __iomem *regs; @@ -65,16 +69,16 @@ index 16e018aa4aae..18745af08954 100644 int i, ret; /* -@@ -581,8 +611,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, +@@ -625,8 +659,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, list_add_tail(&mixer->engine.list, &drv->engine_list); - base = sun8i_blender_base(mixer); - + if (!mixer->hw_preconfigured) { /* Reset registers and disable unused sub-engines */ if (mixer->cfg->de_type == sun8i_mixer_de3) { - for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4) -@@ -598,7 +626,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, +@@ -643,7 +675,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0); regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0); regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0); @@ -83,14 +87,15 @@ index 16e018aa4aae..18745af08954 100644 for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4) regmap_write(mixer->engine.regs, i, 0); -@@ -611,31 +639,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, +@@ -656,35 +688,9 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0); } - /* Enable the mixer */ - regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, - SUN8I_MIXER_GLOBAL_CTL_RT_EN); -- + } /* hw_preconfigured */ + - /* Set background color to black */ - regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), - SUN8I_MIXER_BLEND_COLOR_BLACK); @@ -110,12 +115,15 @@ index 16e018aa4aae..18745af08954 100644 - SUN8I_MIXER_BLEND_MODE(base, i), - SUN8I_MIXER_BLEND_MODE_DEF); - +- if (!mixer->hw_preconfigured) { - regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), - SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); +- } +- + sun8i_mixer_init(mixer); - return 0; + err_disable_bus_clk: -- -2.35.3 +2.51.0 diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch index ae503d937..6888aa39d 100644 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch +++ b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch @@ -1,4 +1,4 @@ -From a756d6b4ac645ac3c18d5758faec068b3c8819a6 Mon Sep 17 00:00:00 2001 +From 91877bc54df84b7fabe8265b152ac38032193403 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 29 Sep 2024 22:04:49 +1300 Subject: drm: sun4i: de2/de3: use generic register reference function for @@ -16,10 +16,10 @@ Signed-off-by: Ryan Walklin 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index 18745af08954..600084286b39 100644 +index 0419859a9f89..a319db11cc68 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -277,6 +277,7 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, +@@ -280,6 +280,7 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, { struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); u32 bld_base = sun8i_blender_base(mixer); @@ -27,7 +27,7 @@ index 18745af08954..600084286b39 100644 struct drm_plane_state *plane_state; struct drm_plane *plane; u32 route = 0, pipe_en = 0; -@@ -316,8 +317,8 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, +@@ -346,8 +347,8 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); } @@ -39,7 +39,7 @@ index 18745af08954..600084286b39 100644 regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF, diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c -index cb9b694fef10..7f1231cf0f01 100644 +index 3840242dfaf3..70218b7132ad 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -24,6 +24,7 @@ @@ -113,5 +113,5 @@ index e348fd0a3d81..d19349eecc9d 100644 outsize); -- -2.35.3 +2.51.0 diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch index 8a814bcaf..2fcb8a183 100644 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch +++ b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch @@ -1,4 +1,4 @@ -From 3b6462ebad249f4762acfd8e262442bb0cda95b4 Mon Sep 17 00:00:00 2001 +From 1a66bdf301ea483f5c3993fb6795bc0236bab5c1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 29 Sep 2024 22:04:40 +1300 Subject: drm: sun4i: de3: add YUV support to the DE3 mixer @@ -12,26 +12,27 @@ encoding in engine variables. Signed-off-by: Jernej Skrabec Signed-off-by: Ryan Walklin --- - drivers/gpu/drm/sun4i/sun8i_mixer.c | 53 ++++++++++++++++++++++++++-- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 47 ++++++++++++++++++++++++++++ drivers/gpu/drm/sun4i/sunxi_engine.h | 5 +++ - 2 files changed, 55 insertions(+), 3 deletions(-) + 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index 252827715de1..a50c583852ed 100644 +index 45a218121310..fb5348388eb5 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -23,7 +23,10 @@ +@@ -23,8 +23,11 @@ #include #include +#include + #include "sun4i_drv.h" + #include "sun4i_tcon.h" +#include "sun50i_fmt.h" #include "sun8i_mixer.h" #include "sun8i_ui_layer.h" #include "sun8i_vi_layer.h" -@@ -390,12 +393,52 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, +@@ -425,12 +428,52 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", interlaced ? "on" : "off"); @@ -77,20 +78,17 @@ index 252827715de1..a50c583852ed 100644 } static const struct sunxi_engine_ops sun8i_engine_ops = { -- .commit = sun8i_mixer_commit, -- .layers_init = sun8i_layers_init, -- .mode_set = sun8i_mixer_mode_set, -+ .commit = sun8i_mixer_commit, -+ .layers_init = sun8i_layers_init, -+ .mode_set = sun8i_mixer_mode_set, + .commit = sun8i_mixer_commit, + .layers_init = sun8i_layers_init, + .mode_set = sun8i_mixer_mode_set, + .get_supported_fmts = sun8i_mixer_get_supported_fmts, }; static const struct regmap_config sun8i_mixer_regmap_config = { -@@ -456,6 +499,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, - dev_set_drvdata(dev, mixer); +@@ -492,6 +535,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, mixer->engine.ops = &sun8i_engine_ops; mixer->engine.node = dev->of_node; + mixer->drv = drv; + /* default output format, supported by all mixers */ + mixer->engine.format = MEDIA_BUS_FMT_RGB888_1X24; + /* default color encoding, ignored with RGB I/O */ @@ -122,5 +120,5 @@ index c48cbc1aceb8..ffafc29b3a0c 100644 struct list_head list; }; -- -2.35.3 +2.51.0 diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch index 5fb39d4f0..adcc09e1d 100644 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch +++ b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch @@ -1,4 +1,4 @@ -From ff794822d56721795fec59dea66164cc19ba792c Mon Sep 17 00:00:00 2001 +From 1000fdf61f22e06c607f003ef500d75266bc3920 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 29 Sep 2024 22:04:43 +1300 Subject: drm: sun4i: de3: add YUV support to the TCON @@ -14,10 +14,10 @@ Signed-off-by: Ryan Walklin 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c -index 3675c87461e9..af67bf2e6e09 100644 +index 221df37406d8..43cc8908a03f 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c -@@ -649,14 +649,26 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, +@@ -679,14 +679,26 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, const struct drm_display_mode *mode) { @@ -46,7 +46,7 @@ index 3675c87461e9..af67bf2e6e09 100644 /* Adjust clock delay */ clk_delay = sun4i_tcon_get_clk_delay(mode, 1); -@@ -675,17 +687,17 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, +@@ -705,17 +717,17 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, /* Set the input resolution */ regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, @@ -67,7 +67,7 @@ index 3675c87461e9..af67bf2e6e09 100644 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); /* Set horizontal display timings */ -@@ -693,8 +705,8 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, +@@ -723,8 +735,8 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", mode->htotal, bp); regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, @@ -79,5 +79,5 @@ index 3675c87461e9..af67bf2e6e09 100644 bp = mode->crtc_vtotal - mode->crtc_vsync_start; DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", -- -2.35.3 +2.51.0 diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch index 90f86befd..ec60c1eee 100644 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch +++ b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch @@ -1,4 +1,4 @@ -From f9a39553dcf5e87eba968d2aac4f5acf52baa392 Mon Sep 17 00:00:00 2001 +From 67de80fb6dce1b60822731628cba536c07fa2e10 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 29 Sep 2024 22:04:39 +1300 Subject: drm: sun4i: de3: add formatter flag to mixer config @@ -17,10 +17,10 @@ Signed-off-by: Ryan Walklin 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index bd0fe2c6624e..252827715de1 100644 +index 20a78d48ccdf..45a218121310 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -717,6 +717,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { +@@ -774,6 +774,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { .ccsc = CCSC_MIXER0_LAYOUT, .is_de3 = true, @@ -29,7 +29,7 @@ index bd0fe2c6624e..252827715de1 100644 .scaler_mask = 0xf, .scanline_yuv = 4096, diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h -index d7898c9c9cc0..8417b8fef2e1 100644 +index 68e2741b0962..860a2f2cec24 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -163,6 +163,7 @@ enum { @@ -49,5 +49,5 @@ index d7898c9c9cc0..8417b8fef2e1 100644 }; -- -2.35.3 +2.51.0 diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch index 84e9458fb..a7fe3aaf6 100644 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch +++ b/patch/kernel/archive/sunxi-6.16/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch @@ -26,10 +26,10 @@ Signed-off-by: Ryan Walklin 2 files changed, 108 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c -index 600084286b39..204fc8055b32 100644 +index a319db11cc68..bfed8a6b453f 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c -@@ -321,8 +321,12 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, +@@ -351,8 +351,12 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); @@ -44,7 +44,7 @@ index 600084286b39..204fc8055b32 100644 } static struct drm_plane **sun8i_layers_init(struct drm_device *drm, -@@ -371,25 +375,33 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, +@@ -406,25 +410,33 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, const struct drm_display_mode *mode) { struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); @@ -81,7 +81,7 @@ index 600084286b39..204fc8055b32 100644 SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", -@@ -400,10 +412,8 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, +@@ -435,10 +447,8 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, else val = 0xff108080; @@ -94,7 +94,7 @@ index 600084286b39..204fc8055b32 100644 if (mixer->cfg->has_formatter) sun50i_fmt_setup(mixer, mode->hdisplay, -@@ -443,12 +453,29 @@ static const struct sunxi_engine_ops sun8i_engine_ops = { +@@ -478,12 +488,29 @@ static const struct sunxi_engine_ops sun8i_engine_ops = { }; static const struct regmap_config sun8i_mixer_regmap_config = { @@ -124,7 +124,7 @@ index 600084286b39..204fc8055b32 100644 static int sun8i_mixer_of_get_id(struct device_node *node) { struct device_node *ep, *remote; -@@ -471,33 +498,45 @@ static int sun8i_mixer_of_get_id(struct device_node *node) +@@ -506,36 +533,48 @@ static int sun8i_mixer_of_get_id(struct device_node *node) static void sun8i_mixer_init(struct sun8i_mixer *mixer) { @@ -140,10 +140,12 @@ index 600084286b39..204fc8055b32 100644 + disp_regs = mixer->engine.regs; + } + + if (!mixer->hw_preconfigured) { /* Enable the mixer */ - regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, + regmap_write(top_regs, SUN8I_MIXER_GLOBAL_CTL, SUN8I_MIXER_GLOBAL_CTL_RT_EN); + } + if (mixer->cfg->de_type == sun8i_mixer_de33) + regmap_write(top_regs, SUN50I_MIXER_GLOBAL_CLK, 1); @@ -171,12 +173,13 @@ index 600084286b39..204fc8055b32 100644 SUN8I_MIXER_BLEND_MODE(base, i), SUN8I_MIXER_BLEND_MODE_DEF); + if (!mixer->hw_preconfigured) { - regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), + regmap_update_bits(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); + } } - -@@ -573,6 +612,30 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, +@@ -618,6 +657,30 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, return PTR_ERR(mixer->engine.regs); } @@ -207,7 +210,7 @@ index 600084286b39..204fc8055b32 100644 mixer->reset = devm_reset_control_get(dev, NULL); if (IS_ERR(mixer->reset)) { dev_err(dev, "Couldn't get our reset line\n"); -@@ -787,6 +850,18 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { +@@ -846,6 +909,18 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { .vi_num = 1, }; @@ -226,7 +229,7 @@ index 600084286b39..204fc8055b32 100644 static const struct of_device_id sun8i_mixer_of_table[] = { { .compatible = "allwinner,sun8i-a83t-de2-mixer-0", -@@ -832,6 +907,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = { +@@ -891,6 +966,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = { .compatible = "allwinner,sun50i-h6-de3-mixer-0", .data = &sun50i_h6_mixer0_cfg, }, @@ -238,7 +241,7 @@ index 600084286b39..204fc8055b32 100644 }; MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table); diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h -index 75facc7d1fa6..26b001164647 100644 +index ecba096c553b..f67f4b124a19 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -21,6 +21,10 @@ @@ -268,17 +271,17 @@ index 75facc7d1fa6..26b001164647 100644 }; struct sun8i_mixer { -@@ -191,6 +197,9 @@ struct sun8i_mixer { - +@@ -192,6 +198,9 @@ struct sun8i_mixer { struct clk *bus_clk; struct clk *mod_clk; -+ + + struct regmap *top_regs; + struct regmap *disp_regs; ++ + struct sun4i_drv *drv; + bool hw_preconfigured; }; - - enum { -@@ -227,13 +236,16 @@ sun8i_blender_base(struct sun8i_mixer *mixer) +@@ -230,13 +239,16 @@ sun8i_blender_base(struct sun8i_mixer *mixer) static inline struct regmap * sun8i_blender_regmap(struct sun8i_mixer *mixer) { diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch deleted file mode 100644 index 65411eb51..000000000 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 58a606c8136c57d23b4e35f0f50cb140f1d65d9b Mon Sep 17 00:00:00 2001 -From: Ryan Walklin -Date: Sun, 29 Sep 2024 22:04:52 +1300 -Subject: dt-bindings: allwinner: add H616 DE33 clock binding - -The Allwinner H616 and variants have a new display engine revision -(DE33). - -Add a clock binding for the DE33. - -Signed-off-by: Ryan Walklin -Acked-by: Conor Dooley -Reviewed-by: Chen-Yu Tsai ---- - .../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml -index 70369bd633e4..7fcd55d468d4 100644 ---- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml -+++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml -@@ -25,6 +25,7 @@ properties: - - const: allwinner,sun50i-a64-de2-clk - - const: allwinner,sun50i-h5-de2-clk - - const: allwinner,sun50i-h6-de3-clk -+ - const: allwinner,sun50i-h616-de33-clk - - items: - - const: allwinner,sun8i-r40-de2-clk - - const: allwinner,sun8i-h3-de2-clk --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch deleted file mode 100644 index 87ec283f9..000000000 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch +++ /dev/null @@ -1,67 +0,0 @@ -From af0be61ac5ff0f86567ddbf3924c46eaa211e07f Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Fri, 21 Feb 2025 00:57:58 +0000 -Subject: dt-bindings: power: Add Allwinner H6/H616 PRCM PPU - -The Allwinner H6 and some later SoCs contain some bits in the PRCM (Power -Reset Clock Management) block that control some power domains. -Those power domains include the one for the GPU, the PLLs and some -analogue circuits. - -Signed-off-by: Andre Przywara ---- - .../power/allwinner,sun50i-h6-prcm-ppu.yaml | 42 +++++++++++++++++++ - 1 file changed, 42 insertions(+) - create mode 100644 Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml - -diff --git a/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml -new file mode 100644 -index 000000000000..7eaff9baf726 ---- /dev/null -+++ b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml -@@ -0,0 +1,42 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/power/allwinner,sun50i-h6-prcm-ppu.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Allwinner SoCs PRCM power domain controller -+ -+maintainers: -+ - Andre Przywara -+ -+description: -+ The Allwinner Power Reset Clock Management (PRCM) unit contains bits to -+ control a few power domains. -+ -+properties: -+ compatible: -+ enum: -+ - allwinner,sun50i-h6-prcm-ppu -+ - allwinner,sun50i-h616-prcm-ppu -+ - allwinner,sun55i-a523-prcm-ppu -+ -+ reg: -+ maxItems: 1 -+ -+ '#power-domain-cells': -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - '#power-domain-cells' -+ -+additionalProperties: false -+ -+examples: -+ - | -+ prcm_ppu: power-controller@7010210 { -+ compatible = "allwinner,sun50i-h616-prcm-ppu"; -+ reg = <0x07010250 0x10>; -+ #power-domain-cells = <1>; -+ }; --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.16/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch b/patch/kernel/archive/sunxi-6.16/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch deleted file mode 100644 index 2e7eccbb3..000000000 --- a/patch/kernel/archive/sunxi-6.16/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch +++ /dev/null @@ -1,249 +0,0 @@ -From 9fb1314045a676823428efa503b581c2910169d7 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Fri, 21 Feb 2025 00:57:59 +0000 -Subject: pmdomain: sunxi: add H6 PRCM PPU driver - -The Allwinner Power Reset Clock Management (RPCM) block contains a few -bits that control some power domains. The most prominent one is the one -for the Mali GPU. On the Allwinner H6 this domain is enabled at reset, so -we didn't care about it so far, but the H616 defaults to it being disabled. - -Add a power domain driver for those bits. Some BSP code snippets and -some spare documentation describe three bits, slightly different between -the H6 and H616, so add three power domains for each SoC, connected to -their compatible string. - -Signed-off-by: Andre Przywara ---- - drivers/pmdomain/sunxi/Kconfig | 10 + - drivers/pmdomain/sunxi/Makefile | 1 + - drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c | 191 ++++++++++++++++++++ - 3 files changed, 202 insertions(+) - create mode 100644 drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c - -diff --git a/drivers/pmdomain/sunxi/Kconfig b/drivers/pmdomain/sunxi/Kconfig -index 17781bf8d86d..43eecb3ea981 100644 ---- a/drivers/pmdomain/sunxi/Kconfig -+++ b/drivers/pmdomain/sunxi/Kconfig -@@ -8,3 +8,13 @@ config SUN20I_PPU - help - Say y to enable the PPU power domain driver. This saves power - when certain peripherals, such as the video engine, are idle. -+ -+config SUN50I_H6_PRCM_PPU -+ tristate "Allwinner H6 PRCM power domain driver" -+ depends on ARCH_SUNXI || COMPILE_TEST -+ depends on PM -+ select PM_GENERIC_DOMAINS -+ help -+ Say y to enable the Allwinner H6/H616 PRCM power domain driver. -+ This is required to enable the Mali GPU in the H616 SoC, it is -+ optional for the H6. -diff --git a/drivers/pmdomain/sunxi/Makefile b/drivers/pmdomain/sunxi/Makefile -index ec1d7a2fb21d..c1343e123759 100644 ---- a/drivers/pmdomain/sunxi/Makefile -+++ b/drivers/pmdomain/sunxi/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_SUN20I_PPU) += sun20i-ppu.o -+obj-$(CONFIG_SUN50I_H6_PRCM_PPU) += sun50i-h6-prcm-ppu.o -diff --git a/drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c b/drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c -new file mode 100644 -index 000000000000..1c6b0c78b222 ---- /dev/null -+++ b/drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c -@@ -0,0 +1,191 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) Arm Ltd. 2024 -+ * -+ * Allwinner H6/H616 PRCM power domain driver. -+ * This covers a few registers inside the PRCM (Power Reset Clock Management) -+ * block that control some power rails, most prominently for the Mali GPU. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * The PRCM block covers multiple devices, starting with some clocks, -+ * then followed by the power rails. -+ * The clocks are covered by a different driver, so this driver's MMIO range -+ * starts later in the PRCM MMIO frame, not at the beginning of it. -+ * To keep the register offsets consistent with other PRCM documentation, -+ * express the registers relative to the beginning of the whole PRCM, and -+ * subtract the PPU offset this driver is bound to. -+ */ -+#define PD_H6_PPU_OFFSET 0x250 -+#define PD_H6_VDD_SYS_REG 0x250 -+#define PD_H616_ANA_VDD_GATE BIT(4) -+#define PD_H6_CPUS_VDD_GATE BIT(3) -+#define PD_H6_AVCC_VDD_GATE BIT(2) -+#define PD_H6_GPU_REG 0x254 -+#define PD_H6_GPU_GATE BIT(0) -+ -+struct sun50i_h6_ppu_pd { -+ struct generic_pm_domain genpd; -+ void __iomem *reg; -+ u32 gate_mask; -+ bool negated; -+}; -+ -+#define FLAG_PPU_ALWAYS_ON BIT(0) -+#define FLAG_PPU_NEGATED BIT(1) -+ -+struct sun50i_h6_ppu_desc { -+ const char *name; -+ u32 offset; -+ u32 mask; -+ unsigned int flags; -+}; -+ -+struct sun50i_h6_ppu_desc sun50i_h6_ppus[] = { -+ { "AVCC", PD_H6_VDD_SYS_REG, PD_H6_AVCC_VDD_GATE }, -+ { "CPUS", PD_H6_VDD_SYS_REG, PD_H6_CPUS_VDD_GATE }, -+ { "GPU", PD_H6_GPU_REG, PD_H6_GPU_GATE }, -+ {} -+}; -+ -+struct sun50i_h6_ppu_desc sun50i_h616_ppus[] = { -+ { "PLL", PD_H6_VDD_SYS_REG, PD_H6_AVCC_VDD_GATE, -+ FLAG_PPU_ALWAYS_ON | FLAG_PPU_NEGATED }, -+ { "ANA", PD_H6_VDD_SYS_REG, PD_H616_ANA_VDD_GATE, FLAG_PPU_ALWAYS_ON }, -+ { "GPU", PD_H6_GPU_REG, PD_H6_GPU_GATE, FLAG_PPU_NEGATED }, -+ {} -+}; -+#define to_sun50i_h6_ppu_pd(_genpd) \ -+ container_of(_genpd, struct sun50i_h6_ppu_pd, genpd) -+ -+static bool sun50i_h6_ppu_power_status(const struct sun50i_h6_ppu_pd *pd) -+{ -+ bool bit = readl(pd->reg) & pd->gate_mask; -+ -+ return bit ^ pd->negated; -+} -+ -+static int sun50i_h6_ppu_pd_set_power(const struct sun50i_h6_ppu_pd *pd, -+ bool set_bit) -+{ -+ u32 reg = readl(pd->reg); -+ -+ if (set_bit) -+ writel(reg | pd->gate_mask, pd->reg); -+ else -+ writel(reg & ~pd->gate_mask, pd->reg); -+ -+ return 0; -+} -+ -+static int sun50i_h6_ppu_pd_power_on(struct generic_pm_domain *genpd) -+{ -+ const struct sun50i_h6_ppu_pd *pd = to_sun50i_h6_ppu_pd(genpd); -+ -+ return sun50i_h6_ppu_pd_set_power(pd, !pd->negated); -+} -+ -+static int sun50i_h6_ppu_pd_power_off(struct generic_pm_domain *genpd) -+{ -+ const struct sun50i_h6_ppu_pd *pd = to_sun50i_h6_ppu_pd(genpd); -+ -+ return sun50i_h6_ppu_pd_set_power(pd, pd->negated); -+} -+ -+static int sun50i_h6_ppu_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct genpd_onecell_data *ppu; -+ struct sun50i_h6_ppu_pd *pds; -+ const struct sun50i_h6_ppu_desc *desc; -+ void __iomem *base; -+ int ret, i, count; -+ -+ desc = of_device_get_match_data(dev); -+ if (!desc) -+ return -EINVAL; -+ -+ for (count = 0; desc[count].name; count++) -+ ; -+ -+ pds = devm_kcalloc(dev, count, sizeof(*pds), GFP_KERNEL); -+ if (!pds) -+ return -ENOMEM; -+ -+ ppu = devm_kzalloc(dev, sizeof(*ppu), GFP_KERNEL); -+ if (!ppu) -+ return -ENOMEM; -+ -+ ppu->num_domains = count; -+ ppu->domains = devm_kcalloc(dev, count, sizeof(*ppu->domains), -+ GFP_KERNEL); -+ if (!ppu->domains) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, ppu); -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ for (i = 0; i < count; i++) { -+ struct sun50i_h6_ppu_pd *pd = &pds[i]; -+ -+ pd->genpd.name = desc[i].name; -+ pd->genpd.power_off = sun50i_h6_ppu_pd_power_off; -+ pd->genpd.power_on = sun50i_h6_ppu_pd_power_on; -+ if (desc[i].flags & FLAG_PPU_ALWAYS_ON) -+ pd->genpd.flags = GENPD_FLAG_ALWAYS_ON; -+ pd->negated = !!(desc[i].flags & FLAG_PPU_NEGATED); -+ pd->reg = base + desc[i].offset - PD_H6_PPU_OFFSET; -+ pd->gate_mask = desc[i].mask; -+ -+ ret = pm_genpd_init(&pd->genpd, NULL, -+ !sun50i_h6_ppu_power_status(pd)); -+ if (ret) { -+ dev_warn(dev, "Failed to add GPU power domain: %d\n", ret); -+ return ret; -+ } -+ ppu->domains[i] = &pd->genpd; -+ } -+ -+ ret = of_genpd_add_provider_onecell(dev->of_node, ppu); -+ if (ret) -+ dev_warn(dev, "Failed to add provider: %d\n", ret); -+ -+ return 0; -+} -+ -+static const struct of_device_id sun50i_h6_ppu_of_match[] = { -+ { .compatible = "allwinner,sun50i-h6-prcm-ppu", -+ .data = &sun50i_h6_ppus }, -+ { .compatible = "allwinner,sun50i-h616-prcm-ppu", -+ .data = &sun50i_h616_ppus }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, sun50i_h6_ppu_of_match); -+ -+static struct platform_driver sun50i_h6_ppu_driver = { -+ .probe = sun50i_h6_ppu_probe, -+ .driver = { -+ .name = "sun50i-h6-prcm-ppu", -+ .of_match_table = sun50i_h6_ppu_of_match, -+ /* Power domains cannot be removed while they are in use. */ -+ .suppress_bind_attrs = true, -+ }, -+}; -+module_platform_driver(sun50i_h6_ppu_driver); -+ -+MODULE_AUTHOR("Andre Przywara "); -+MODULE_DESCRIPTION("Allwinner H6 PRCM power domain driver"); -+MODULE_LICENSE("GPL"); --- -2.35.3 - diff --git a/patch/kernel/archive/sunxi-6.16/series.conf b/patch/kernel/archive/sunxi-6.16/series.conf index af793d439..a7936b18f 100644 --- a/patch/kernel/archive/sunxi-6.16/series.conf +++ b/patch/kernel/archive/sunxi-6.16/series.conf @@ -241,3 +241,35 @@ patches.megous/Revert-ASoC-soc-core-merge-snd_soc_unregister_compon.patch patches.megous/Revert-usb-dwc3-Abort-suspend-on-soft-disconnect-fai.patch patches.megous/Defconfigs-for-all-my-devices.patch + +################################################################################ +# +# drivers/gpu/drm/sun4i/ +# +################################################################################ + patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch + patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch + patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch + patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch + patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch + patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch + patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch + patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch + patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch + patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch + patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch + patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch + patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch + patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch + patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch + patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch + patches.drm/drm-sun4i-Report-page-flip-after-vsync-is-complete-n.patch diff --git a/patch/kernel/archive/sunxi-6.16/series.drm b/patch/kernel/archive/sunxi-6.16/series.drm new file mode 100644 index 000000000..235c784bb --- /dev/null +++ b/patch/kernel/archive/sunxi-6.16/series.drm @@ -0,0 +1,31 @@ +################################################################################ +# +# drivers/gpu/drm/sun4i/ +# +################################################################################ + patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch + patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch + patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch + patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch + patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch + patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch + patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch + patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch + patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch + patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch + patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch + patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch + patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch + patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch + patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch + patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch + patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch + patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch + patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch + patches.drm/drm-sun4i-Report-page-flip-after-vsync-is-complete-n.patch