Switched rockchip64 u-boot to v2021.07 (#3233)

* Switched rockchip64 u-boot to v2021.07 * Switched OrangePi R1 Plus to include mainline's R2S device tree * Added unsingned signed comparison patch from Paolo to fix rk3328 reboots
2025-09-24 19:47:06 +07:00 · 2021-11-11 23:49:52 +01:00
parent 29335b0c99
commit 71ff7b3b98
11 changed files with 83 additions and 1111 deletions
--- a/config/sources/families/include/rockchip64_common.inc
+++ b/config/sources/families/include/rockchip64_common.inc
@@ -9,7 +9,7 @@ OVERLAY_PREFIX='rockchip'
 SERIALCON=${SERIALCON:=$([ $BRANCH == "legacy" ] && echo "ttyFIQ0:1500000" || echo "ttyS2:1500000")}
 GOVERNOR="ondemand"
 ATFPATCHDIR='atf-rockchip64'
-BOOTBRANCH="tag:v2020.10"
+BOOTBRANCH="tag:v2021.07"
 BOOTPATCHDIR="u-boot-rockchip64"
 PACKAGE_LIST_FAMILY="ethtool"

--- a/patch/u-boot/u-boot-rockchip64/add-board-nanopi-m4v2.patch
+++ b/patch/u-boot/u-boot-rockchip64/add-board-nanopi-m4v2.patch
@@ -3,9 +3,9 @@ index 9900b442..afa9ec81 100644
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
@@ -128,6 +128,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
- 	rk3399-nanopc-t4.dtb \
 	rk3399-nanopi-m4.dtb \
 	rk3399-nanopi-m4-2gb.dtb \
+ 	rk3399-nanopi-m4b.dtb \
 +	rk3399-nanopi-m4v2.dtb \
 	rk3399-nanopi-neo4.dtb \
 	rk3399-orangepi.dtb \
--- a/patch/u-boot/u-boot-rockchip64/add-board-nanopi-r2s.patch
+++ b/patch/u-boot/u-boot-rockchip64/add-board-nanopi-r2s.patch
@@ -1,916 +0,0 @@
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index afa9ec81..0ba45ff7 100644
--- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
- 
- dtb-$(CONFIG_ROCKCHIP_RK3328) += \
- 	rk3328-evb.dtb \
-+	rk3328-nanopi-r2-rev00.dtb \
- 	rk3328-roc-cc.dtb \
- 	rk3328-rock64.dtb \
- 	rk3328-rock-pi-e.dtb
-diff --git a/arch/arm/dts/rk3328-nanopi-r2-common.dtsi b/arch/arm/dts/rk3328-nanopi-r2-common.dtsi
-new file mode 100644
-index 00000000..186b51f6
--- /dev/null
-+++ b/arch/arm/dts/rk3328-nanopi-r2-common.dtsi
-@@ -0,0 +1,624 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
-+ */
-+
-+/dts-v1/;
-+/*#include "rk3328-dram-default-timing.dtsi"*/
-+#include "rk3328.dtsi"
-+
-+/ {
-+	model = "FriendlyElec boards based on Rockchip RK3328";
-+	compatible = "friendlyelec,nanopi-r2",
-+		   "rockchip,rk3328";
-+
-+	aliases {
-+/*		ethernet1 = &r8153;*/
-+	};
-+
-+	chosen {
-+		bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0";
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	gmac_clkin: external-gmac-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "gmac_clkin";
-+		#clock-cells = <0>;
-+	};
-+
-+	mach: board {
-+		compatible = "friendlyelec,board";
-+		machine = "NANOPI-R2";
-+		hwrev = <255>;
-+		model = "NanoPi R2 Series";
-+		nvmem-cells = <&efuse_id>, <&efuse_cpu_version>;
-+		nvmem-cell-names = "id", "cpu-version";
-+	};
-+
-+	leds: gpio-leds {
-+		compatible = "gpio-leds";
-+		pinctrl-names = "default";
-+		pinctrl-0 =<&leds_gpio>;
-+		status = "disabled";
-+
-+		led@1 {
-+			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
-+			label = "status_led";
-+			linux,default-trigger = "heartbeat";
-+			linux,default-trigger-delay-ms = <0>;
-+		};
-+	};
-+
-+	sdio_pwrseq: sdio-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk805 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_enable_h>;
-+
-+		/*
-+		 * On the module itself this is one of these (depending
-+		 * on the actual card populated):
-+		 * - SDIO_RESET_L_WL_REG_ON
-+		 * - PDN (power down when low)
-+		 */
-+		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
-+	};
-+
-+/*	sdmmc_ext: dwmmc@ff5f0000 {
-+		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
-+		reg = <0x0 0xff5f0000 0x0 0x4000>;
-+		clock-freq-min-max = <400000 150000000>;
-+		clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
-+			 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
-+		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
-+		fifo-depth = <0x100>;
-+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-+		status = "disabled";
-+	};*/
-+
-+	vcc_sd: sdmmc-regulator {
-+		compatible = "regulator-fixed";
-+		gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&sdmmc0m1_gpio>;
-+		regulator-name = "vcc_sd";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc_io>;
-+	};
-+
-+	vccio_sd: sdmmcio-regulator {
-+		compatible = "regulator-gpio";
-+		gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
-+		states = <1800000 0x1
-+			  3300000 0x0>;
-+		regulator-name = "vccio_sd";
-+		regulator-type = "voltage";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-always-on;
-+		vin-supply = <&vcc_io>;
-+		startup-delay-us = <2000>;
-+		regulator-settling-time-us = <5000>;
-+		enable-active-high;
-+		status = "disabled";
-+	};
-+
-+	vcc_sys: vcc-sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	vcc_phy: vcc-phy-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc_phy";
-+		regulator-always-on;
-+		regulator-boot-on;
-+	};
-+
-+	vcc_host_vbus: host-vbus-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc_host_vbus";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	dfi: dfi@ff790000 {
-+		reg = <0x00 0xff790000 0x00 0x400>;
-+		compatible = "rockchip,rk3328-dfi";
-+		rockchip,grf = <&grf>;
-+		status = "disabled";
-+	};
-+
-+/*	dmc: dmc {
-+		compatible = "rockchip,rk3328-dmc";
-+		devfreq-events = <&dfi>;
-+		clocks = <&cru SCLK_DDRCLK>;
-+		clock-names = "dmc_clk";
-+		operating-points-v2 = <&dmc_opp_table>;
-+		ddr_timing = <&ddr_timing>;
-+		upthreshold = <40>;
-+		downdifferential = <20>;
-+		auto-min-freq = <786000>;
-+		auto-freq-en = <0>;
-+		#cooling-cells = <2>;
-+		status = "disabled";
-+
-+		ddr_power_model: ddr_power_model {
-+			compatible = "ddr_power_model";
-+			dynamic-power-coefficient = <120>;
-+			static-power-coefficient = <200>;
-+			ts = <32000 4700 (-80) 2>;
-+			thermal-zone = "soc-thermal";
-+		};
-+	};
-+
-+	dmc_opp_table: dmc-opp-table {
-+		compatible = "operating-points-v2";
-+
-+		rockchip,leakage-voltage-sel = <
-+			1   10    0
-+			11  254   1
-+		>;
-+		nvmem-cells = <&logic_leakage>;
-+		nvmem-cell-names = "ddr_leakage";
-+
-+		opp-786000000 {
-+			opp-hz = /bits/ 64 <786000000>;
-+			opp-microvolt = <1075000>;
-+			opp-microvolt-L0 = <1075000>;
-+			opp-microvolt-L1 = <1050000>;
-+		};
-+		opp-798000000 {
-+			opp-hz = /bits/ 64 <798000000>;
-+			opp-microvolt = <1075000>;
-+			opp-microvolt-L0 = <1075000>;
-+			opp-microvolt-L1 = <1050000>;
-+		};
-+		opp-840000000 {
-+			opp-hz = /bits/ 64 <840000000>;
-+			opp-microvolt = <1075000>;
-+			opp-microvolt-L0 = <1075000>;
-+			opp-microvolt-L1 = <1050000>;
-+		};
-+		opp-924000000 {
-+			opp-hz = /bits/ 64 <924000000>;
-+			opp-microvolt = <1100000>;
-+			opp-microvolt-L0 = <1100000>;
-+			opp-microvolt-L1 = <1075000>;
-+		};
-+		opp-1056000000 {
-+			opp-hz = /bits/ 64 <1056000000>;
-+			opp-microvolt = <1175000>;
-+			opp-microvolt-L0 = <1175000>;
-+			opp-microvolt-L1 = <1150000>;
-+		};
-+	};
-+*/};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&dfi {
-+	status = "okay";
-+};
-+
-+/*&dmc {
-+	center-supply = <&vdd_logic>;
-+	status = "okay";
-+};*/
-+
-+&emmc {
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	max-frequency = <150000000>;
-+	mmc-hs200-1_8v;
-+	no-sd;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-+	vmmc-supply = <&vcc_io>;
-+	vqmmc-supply = <&vcc18_emmc>;
-+	status = "okay";
-+};
-+
-+&gmac2phy {
-+	phy-supply = <&vcc_phy>;
-+	clock_in_out = "output";
-+	assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
-+	assigned-clock-rate = <50000000>;
-+	assigned-clocks = <&cru SCLK_MAC2PHY>;
-+	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
-+	status = "disabled";
-+};
-+
-+&gmac2io {
-+	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
-+	assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
-+	clock_in_out = "input";
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&rgmiim1_pins>;
-+	phy-handle = <&rtl8211e>;
-+	phy-mode = "rgmii";
-+	phy-supply = <&vcc_phy>;
-+	snps,reset-active-low;
-+	snps,reset-delays-us = <0 10000 30000>;
-+	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+	snps,aal;
-+	snps,rxpbl = <0x4>;
-+	snps,txpbl = <0x4>;
-+	tx_delay = <0x24>;
-+	rx_delay = <0x18>;
-+	status = "okay";
-+
-+	mdio {
-+		compatible = "snps,dwmac-mdio";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		rtl8211e: phy@0 {
-+			reg = <0>;
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <30000>;
-+			/* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */
-+		};
-+	};
-+};
-+
-+&i2c1 {
-+	status = "okay";
-+
-+	rk805: rk805@18 {
-+		compatible = "rockchip,rk805";
-+		reg = <0x18>;
-+		interrupt-parent = <&gpio2>;
-+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <1>;
-+		clock-output-names = "xin32k", "rk805-clkout2";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int_l>;
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+
-+		vcc1-supply = <&vcc_sys>;
-+		vcc2-supply = <&vcc_sys>;
-+		vcc3-supply = <&vcc_sys>;
-+		vcc4-supply = <&vcc_sys>;
-+		vcc5-supply = <&vcc_io>;
-+		vcc6-supply = <&vcc_io>;
-+
-+		regulators {
-+			vdd_logic: DCDC_REG1 {
-+				regulator-name = "vdd_logic";
-+				regulator-init-microvolt = <1075000>;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+
-+			vdd_arm: DCDC_REG2 {
-+				regulator-name = "vdd_arm";
-+				regulator-init-microvolt = <1225000>;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <950000>;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vcc_io: DCDC_REG4 {
-+				regulator-name = "vcc_io";
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcc_18: LDO_REG1 {
-+				regulator-name = "vcc_18";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc18_emmc: LDO_REG2 {
-+				regulator-name = "vcc18_emmc";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vdd_10: LDO_REG3 {
-+				regulator-name = "vdd_10";
-+				regulator-min-microvolt = <1000000>;
-+				regulator-max-microvolt = <1000000>;
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&io_domains {
-+	status = "okay";
-+
-+	vccio1-supply = <&vcc_io>;
-+	vccio2-supply = <&vcc18_emmc>;
-+	vccio3-supply = <&vcc_io>;
-+	vccio4-supply = <&vcc_io>;
-+	vccio5-supply = <&vcc_io>;
-+	vccio6-supply = <&vcc_18>;
-+	pmuio-supply = <&vcc_io>;
-+};
-+
-+&pinctrl {
-+	pmic {
-+		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	sdio-pwrseq {
-+		wifi_enable_h: wifi-enable-h {
-+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	sdmmc0 {
-+		sdmmc0_clk: sdmmc0-clk {
-+			rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
-+		};
-+
-+		sdmmc0_cmd: sdmmc0-cmd {
-+			rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
-+		};
-+
-+		sdmmc0_dectn: sdmmc0-dectn {
-+			rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
-+		};
-+
-+		sdmmc0_bus4: sdmmc0-bus4 {
-+			rockchip,pins =
-+				<1 RK_PA0 1 &pcfg_pull_up_4ma>,
-+				<1 RK_PA1 1 &pcfg_pull_up_4ma>,
-+				<1 RK_PA2 1 &pcfg_pull_up_4ma>,
-+				<1 RK_PA3 1 &pcfg_pull_up_4ma>;
-+		};
-+	};
-+
-+	sdmmc0ext {
-+		sdmmc0ext_clk: sdmmc0ext-clk {
-+			rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>;
-+		};
-+
-+		sdmmc0ext_cmd: sdmmc0ext-cmd {
-+			rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>;
-+		};
-+
-+		sdmmc0ext_bus4: sdmmc0ext-bus4 {
-+			rockchip,pins =
-+				<3 RK_PA4 3 &pcfg_pull_up_2ma>,
-+				<3 RK_PA5 3 &pcfg_pull_up_2ma>,
-+				<3 RK_PA6 3 &pcfg_pull_up_2ma>,
-+				<3 RK_PA7 3 &pcfg_pull_up_2ma>;
-+		};
-+	};
-+
-+	gmac-1 {
-+		rgmiim1_pins: rgmiim1-pins {
-+			rockchip,pins =
-+				/* mac_txclk */
-+				<1 RK_PB4 2 &pcfg_pull_none_4ma>,
-+				/* mac_rxclk */
-+				<1 RK_PB5 2 &pcfg_pull_none>,
-+				/* mac_mdio */
-+				<1 RK_PC3 2 &pcfg_pull_none_2ma>,
-+				/* mac_txen */
-+				<1 RK_PD1 2 &pcfg_pull_none_4ma>,
-+				/* mac_clk */
-+				<1 RK_PC5 2 &pcfg_pull_none_2ma>,
-+				/* mac_rxdv */
-+				<1 RK_PC6 2 &pcfg_pull_none>,
-+				/* mac_mdc */
-+				<1 RK_PC7 2 &pcfg_pull_none_2ma>,
-+				/* mac_rxd1 */
-+				<1 RK_PB2 2 &pcfg_pull_none>,
-+				/* mac_rxd0 */
-+				<1 RK_PB3 2 &pcfg_pull_none>,
-+				/* mac_txd1 */
-+				<1 RK_PB0 2 &pcfg_pull_none_4ma>,
-+				/* mac_txd0 */
-+				<1 RK_PB1 2 &pcfg_pull_none_4ma>,
-+				/* mac_rxd3 */
-+				<1 RK_PB6 2 &pcfg_pull_none>,
-+				/* mac_rxd2 */
-+				<1 RK_PB7 2 &pcfg_pull_none>,
-+				/* mac_txd3 */
-+				<1 RK_PC0 2 &pcfg_pull_none_4ma>,
-+				/* mac_txd2 */
-+				<1 RK_PC1 2 &pcfg_pull_none_4ma>,
-+
-+				/* mac_txclk */
-+				<0 RK_PB0 1 &pcfg_pull_none>,
-+				/* mac_txen */
-+				<0 RK_PB4 1 &pcfg_pull_none>,
-+				/* mac_clk */
-+				<0 RK_PD0 1 &pcfg_pull_none>,
-+				/* mac_txd1 */
-+				<0 RK_PC0 1 &pcfg_pull_none>,
-+				/* mac_txd0 */
-+				<0 RK_PC1 1 &pcfg_pull_none>,
-+				/* mac_txd3 */
-+				<0 RK_PC7 1 &pcfg_pull_none>,
-+				/* mac_txd2 */
-+				<0 RK_PC6 1 &pcfg_pull_none>;
-+		};
-+	};
-+
-+	usb {
-+		host_vbus_drv: host-vbus-drv {
-+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		otg_vbus_drv: otg-vbus-drv {
-+			rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	gpio-leds {
-+		leds_gpio: leds-gpio {
-+			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&sdmmc {
-+	bus-width = <4>;
-+	cap-mmc-highspeed;
-+	cap-sd-highspeed;
-+	disable-wp;
-+	max-frequency = <150000000>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
-+	vmmc-supply = <&vcc_sd>;
-+	status = "okay";
-+};
-+
-+/*&sdmmc_ext {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cap-sdio-irq;
-+	disable-wp;
-+	keep-power-in-suspend;
-+	max-frequency = <100000000>;
-+	mmc-pwrseq = <&sdio_pwrseq>;
-+	non-removable;
-+	num-slots = <1>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>;
-+	rockchip,default-sample-phase = <120>;
-+	supports-sdio;
-+	sd-uhs-sdr104;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	status = "okay";
-+
-+	brcmf: bcrmf@1 {
-+		reg = <1>;
-+		compatible = "brcm,bcm4329-fmac";
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <RK_PD2 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "host-wake";
-+	};
-+};*/
-+
-+/*&tsadc {
-+	status = "okay";
-+};*/
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+/*&u2phy {
-+	status = "okay";
-+};
-+
-+&u2phy_host {
-+	status = "okay";
-+};
-+
-+&u2phy_otg {
-+	status = "okay";
-+};
-+
-+&u3phy {
-+	vbus-supply = <&vcc_host_vbus>;
-+	status = "okay";
-+};
-+
-+&u3phy_utmi {
-+	status = "okay";
-+};
-+
-+&u3phy_pipe {
-+	status = "okay";
-+};
-+
-+&usb20_otg {
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usbdrd3 {
-+	status = "okay";
-+};
-+
-+&usbdrd_dwc3 {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	r8153: device@2 {
-+		compatible = "usbbda:8153";
-+		reg = <2>;
-+		local-mac-address = [00 00 00 00 00 00];
-+	};
-+};*/
-diff --git a/arch/arm/dts/rk3328-nanopi-r2-rev00-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2-rev00-u-boot.dtsi
-new file mode 100644
-index 00000000..cf3452ea
--- /dev/null
-+++ b/arch/arm/dts/rk3328-nanopi-r2-rev00-u-boot.dtsi
-@@ -0,0 +1,16 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
-+ */
-+
-+#include "rk3328-u-boot.dtsi"
-+#include "rk3328-sdram-ddr4-666.dtsi"
-+/ {
-+	chosen {
-+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
-+	};
-+};
-+
-+&usb_host0_xhci {
-+	status = "okay";
-+};
-diff --git a/arch/arm/dts/rk3328-nanopi-r2-rev00.dts b/arch/arm/dts/rk3328-nanopi-r2-rev00.dts
-new file mode 100644
-index 00000000..c02412b6
--- /dev/null
-+++ b/arch/arm/dts/rk3328-nanopi-r2-rev00.dts
-@@ -0,0 +1,145 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/input/linux-event-codes.h>
-+#include "rk3328-nanopi-r2-common.dtsi"
-+
-+/ {
-+	model = "FriendlyElec NanoPi R2S";
-+	compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328";
-+
-+	gpio-keys {
-+		compatible = "gpio-keys";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		autorepeat;
-+
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&gpio_key1>;
-+
-+		button@0 {
-+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
-+			label = "reset";
-+			linux,code = <BTN_1>;
-+			linux,input-type = <1>;
-+			gpio-key,wakeup = <1>;
-+			debounce-interval = <100>;
-+		};
-+	};
-+
-+	vcc_rtl8153: vcc-rtl8153-regulator {
-+		compatible = "regulator-fixed";
-+		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&usb30_en_drv>;
-+		regulator-always-on;
-+		regulator-name = "vcc_rtl8153";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		off-on-delay-us = <5000>;
-+		enable-active-high;
-+	};
-+};
-+
-+&mach {
-+	hwrev = <0>;
-+	model = "NanoPi R2S";
-+};
-+
-+&emmc {
-+	status = "disabled";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+};
-+
-+&leds {
-+	status = "okay";
-+
-+	led@2 {
-+		gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+		label = "lan_led";
-+	};
-+
-+	led@3 {
-+		gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-+		label = "wan_led";
-+	};
-+};
-+
-+&leds_gpio {
-+	rockchip,pins =
-+		<0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
-+		<2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
-+		<2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+};
-+
-+/*&pwm2 {
-+	pinctrl-names = "default", "sleep";
-+	pinctrl-1 = <&pwm2_sleep_pin>;
-+	status = "okay";
-+};*/
-+
-+&rk805 {
-+	interrupt-parent = <&gpio1>;
-+	interrupts = <RK_PD0 IRQ_TYPE_LEVEL_LOW>;
-+};
-+
-+&vccio_sd {
-+	status = "okay";
-+};
-+
-+&io_domains {
-+	vccio3-supply = <&vccio_sd>;
-+};
-+
-+&sdmmc {
-+	vqmmc-supply = <&vccio_sd>;
-+	max-frequency = <150000000>;
-+	sd-uhs-sdr50;
-+	sd-uhs-sdr104;
-+	status = "okay";
-+};
-+
-+/*&sdmmc_ext {
-+	status = "disabled";
-+};*/
-+
-+&sdio_pwrseq {
-+	status = "disabled";
-+};
-+
-+&pinctrl {
-+	pmic {
-+		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	pwm {
-+		pwm2_sleep_pin: pwm2-sleep-pin {
-+			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>;
-+		};
-+	};
-+
-+	rockchip-key {
-+		gpio_key1: gpio-key1 {
-+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	usb {
-+		otg_vbus_drv: otg-vbus-drv {
-+			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		usb30_en_drv: usb30-en-drv {
-+			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
-new file mode 100644
-index 00000000..f57658e2
--- /dev/null
-+++ b/configs/nanopi-r2s-rk3328_defconfig
-@@ -0,0 +1,95 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SYS_TEXT_BASE=0x00200000
-+CONFIG_ROCKCHIP_RK3328=y
-+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-+CONFIG_TPL_LIBCOMMON_SUPPORT=y
-+CONFIG_TPL_LIBGENERIC_SUPPORT=y
-+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-+CONFIG_ENV_OFFSET=0x3F8000
-+CONFIG_SPL_STACK_R_ADDR=0x600000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_DEBUG_UART_BASE=0xFF130000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328"
-+CONFIG_DEBUG_UART=y
-+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-+# CONFIG_ANDROID_BOOT_IMAGE is not set
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_SPL_LOAD_FIT=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2-rev00.dtb"
-+CONFIG_MISC_INIT_R=y
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_DISPLAY_BOARDINFO_LATE=y
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
-+CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_ATF=y
-+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-+CONFIG_CMD_BOOTZ=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_USB=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_TIME=y
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_TPL_OF_CONTROL=y
-+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2-rev00"
-+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_TPL_OF_PLATDATA=y
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_TPL_DM=y
-+CONFIG_REGMAP=y
-+CONFIG_SPL_REGMAP=y
-+CONFIG_TPL_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_SPL_SYSCON=y
-+CONFIG_TPL_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_SPL_CLK=y
-+CONFIG_FASTBOOT_BUF_ADDR=0x800800
-+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_SPEED=20000000
-+CONFIG_DM_ETH=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_GMAC_ROCKCHIP=y
-+CONFIG_PHY=y
-+CONFIG_PINCTRL=y
-+CONFIG_SPL_PINCTRL=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_DM_REGULATOR_FIXED=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_RAM=y
-+CONFIG_SPL_RAM=y
-+CONFIG_TPL_RAM=y
-+CONFIG_DM_RESET=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYSRESET=y
-+# CONFIG_TPL_SYSRESET is not set
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_DWC3=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_GENERIC=y
-+CONFIG_USB_DWC2=y
-+CONFIG_USB_DWC3=y
-+# CONFIG_USB_DWC3_GADGET is not set
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DWC2_OTG=y
-+CONFIG_SPL_TINY_MEMSET=y
-+CONFIG_TPL_TINY_MEMSET=y
-+CONFIG_ERRNO_STR=y
-+CONFIG_SMBIOS_MANUFACTURER="pine64"
--- a/patch/u-boot/u-boot-rockchip64/add-board-orangepi-r1plus.patch
+++ b/patch/u-boot/u-boot-rockchip64/add-board-orangepi-r1plus.patch
@@ -5,7 +5,7 @@ index 06ccc03e..a2657ebe 100644
@@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
 	rk3328-evb.dtb \
- 	rk3328-nanopi-r2-rev00.dtb \
+ 	rk3328-nanopi-r2s.dtb \
 +	rk3328-orangepi-r1-plus.dtb \
 	rk3328-roc-cc.dtb \
 	rk3328-rock64.dtb \
@@ -37,7 +37,7 @@ new file mode 100644
 index 00000000..23023ad0
 --- /dev/null
 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
-@@ -0,0 +1,48 @@
+@@ -0,0 +1,45 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
 + * Copyright (c) 2020 Shenzhen Xunlong Software CO.,Limited
@@ -46,32 +46,29 @@ index 00000000..23023ad0
 + * Based on Nanopi R2S
 + */
 +
-+#include "rk3328-nanopi-r2-rev00.dts"
+#include "rk3328-nanopi-r2s.dts"
 +
 +/ {
 +	model = "Xunlong Orange Pi R1 Plus";
 +	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
 +};
 +
-+&leds_gpio {
-+	rockchip,pins =
-+		<2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
-+		<2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
-+		<3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+&sys_led_pin {
+	rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 +};
 +
-+&leds {
-+	led@1 {
-+		gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-+	};
+&sys_led {
+	gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
 +};
 +
+/* No support in mainline u-boot for mach node
 +&mach {
 +	compatible = "orangepi,board";
 +	hwrev = <2>;
 +	machine = "ORANGEPI-R1PLUS";
 +	model = "OrangePi R1PLUS";
 +};
+*/
 +
 +&spi0 {
 +	status = "okay";
--- a/patch/u-boot/u-boot-rockchip64/board-roc-rk3399-pc-fix-boot-from-spi-flash.patch
+++ b/patch/u-boot/u-boot-rockchip64/board-roc-rk3399-pc-fix-boot-from-spi-flash.patch
@@ -1,42 +0,0 @@
-From 0ad85609017068d93c0311c34438db4e43588090 Mon Sep 17 00:00:00 2001
-From: Markus Reichl <m.reichl@fivetechno.de>
-Date: Thu, 17 Dec 2020 15:32:56 +0100
-Subject: [PATCH] rockchip: roc-pc-rk3399: fix boot from SPI flash on spi1
-
-Set the default bus for the onboard SPI flash to 1.
-This fixes booting from U-Boot in SPI flash on the
-roc-pc-rk3399 board and it's mezzanine variant.
-
-Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
---
- configs/roc-pc-mezzanine-rk3399_defconfig | 1 +
- configs/roc-pc-rk3399_defconfig           | 1 +
- 2 files changed, 2 insertions(+)
-
-diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
-index ae16f3558a..8aa5a15518 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
-+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
-@@ -42,6 +42,7 @@ CONFIG_MMC_DW=y
- CONFIG_MMC_DW_ROCKCHIP=y
- CONFIG_MMC_SDHCI=y
- CONFIG_MMC_SDHCI_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_BUS=1
- CONFIG_SPI_FLASH_WINBOND=y
- CONFIG_DM_ETH=y
- CONFIG_ETH_DESIGNWARE=y
-diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
-index 774707b115..927b57685d 100644
--- a/configs/roc-pc-rk3399_defconfig
-+++ b/configs/roc-pc-rk3399_defconfig
-@@ -41,6 +41,7 @@ CONFIG_MMC_DW=y
- CONFIG_MMC_DW_ROCKCHIP=y
- CONFIG_MMC_SDHCI=y
- CONFIG_MMC_SDHCI_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_BUS=1
- CONFIG_SPI_FLASH_WINBOND=y
- CONFIG_DM_ETH=y
- CONFIG_ETH_DESIGNWARE=y
-- 
-2.29.2
-
--- a/patch/u-boot/u-boot-rockchip64/board-rock-pi-4-enable-spi-flash.patch
+++ b/patch/u-boot/u-boot-rockchip64/board-rock-pi-4-enable-spi-flash.patch
@@ -42,11 +42,11 @@ index 764e2b56..11b57434 100644
 +CONFIG_ENV_SIZE=0x6000
 CONFIG_ENV_OFFSET=0x3F8000
 +CONFIG_ENV_SECT_SIZE=0x1000
+ CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4b"
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_EVB_RK3399=y
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
- CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4b"
 +CONFIG_SPL_SPI_FLASH_SUPPORT=y
 +CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEBUG_UART=y
@@ -101,11 +101,11 @@ index 671c0c10..874f4061 100644
 +CONFIG_ENV_SIZE=0x6000
 CONFIG_ENV_OFFSET=0x3F8000
 +CONFIG_ENV_SECT_SIZE=0x1000
+ CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"
 CONFIG_ROCKCHIP_RK3399=y
 CONFIG_TARGET_EVB_RK3399=y
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
- CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"
 +CONFIG_SPL_SPI_FLASH_SUPPORT=y
 +CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEBUG_UART=y
--- a/patch/u-boot/u-boot-rockchip64/board-rockpro64-fix-boot-from-spi-flash.patch
+++ b/patch/u-boot/u-boot-rockchip64/board-rockpro64-fix-boot-from-spi-flash.patch
@@ -1,61 +0,0 @@
-From c180e2939d3ccb43f89565d6660a0d6f912712b6 Mon Sep 17 00:00:00 2001
-From: Hugh Cole-Baker <sigmaris@gmail.com>
-Date: Sun, 8 Nov 2020 14:00:23 +0000
-Subject: [PATCH] rockchip: rockpro64: fix boot from SPI flash on spi1
-
-Commit c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob")
-added an alias spi1 referring to spi@ff1d0000, however there was already
-an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and
-having both aliases present broke booting from SPI flash for this board.
-
-Remove the spi0 alias, set the default bus for SPI flash to 1, and
-enable support for numbered aliases in SPL so that it uses the same bus
-numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash
-on the rockpro64 board.
-
-Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
-Suggested-by: Simon Glass <sjg@chromium.org>
-Fixes: c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob")
-Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
---
- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ----
- configs/rockpro64-rk3399_defconfig        | 2 ++
- 2 files changed, 2 insertions(+), 4 deletions(-)
-
-This patch is already included in v2021.01
-
-diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
-index cb8991aa..6317b47e 100644
--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
-+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
-@@ -6,10 +6,6 @@
- #include "rk3399-u-boot.dtsi"
- #include "rk3399-sdram-lpddr4-100.dtsi"
- / {
-	aliases {
-		spi0 = &spi1;
-	};
-
- 	chosen {
- 		u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci;
- 	};
-diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
-index b07140ba..4c80f1f4 100644
--- a/configs/rockpro64-rk3399_defconfig
-+++ b/configs/rockpro64-rk3399_defconfig
-@@ -36,6 +36,7 @@ CONFIG_SPL_OF_CONTROL=y
- CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
- CONFIG_ENV_IS_IN_SPI_FLASH=y
- CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_SPL_DM_SEQ_ALIAS=y
- CONFIG_ROCKCHIP_GPIO=y
- CONFIG_SYS_I2C_ROCKCHIP=y
- CONFIG_DM_KEYBOARD=y
-@@ -45,6 +46,7 @@ CONFIG_MMC_DW=y
- CONFIG_MMC_DW_ROCKCHIP=y
- CONFIG_MMC_SDHCI=y
- CONFIG_MMC_SDHCI_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_BUS=1
- CONFIG_SPI_FLASH_GIGADEVICE=y
- CONFIG_DM_ETH=y
- CONFIG_ETH_DESIGNWARE=y
--- a/patch/u-boot/u-boot-rockchip64/general-fix-unsigned-comparison-causing-rk3328-reboot-issues.patch
+++ b/patch/u-boot/u-boot-rockchip64/general-fix-unsigned-comparison-causing-rk3328-reboot-issues.patch
@@ -0,0 +1,26 @@
+From 3f12642b5947ee63e1e6fe08df558206d1b4daff Mon Sep 17 00:00:00 2001
+From: Paolo Sabatino <paolo.sabatino@gmail.com>
+Date: Sat, 3 Apr 2021 19:38:20 +0000
+Subject: [PATCH] Fix signed/unsigned comparison causing massive headache on
+ gcc-arm >= 8.0 due to valid images being unable to boot
+
+---
+ drivers/core/lists.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/core/lists.c b/drivers/core/lists.c
+index e06e4e853d..c355f0752f 100644
+--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
+@@ -58,7 +58,7 @@ static int bind_drivers_pass(struct udevice *parent, bool pre_reloc_only)
+ 	const int n_ents = ll_entry_count(struct driver_info, driver_info);
+ 	bool missing_parent = false;
+ 	int result = 0;
+-	uint idx;
+	int idx;
+ 
+ 	/*
+ 	 * Do one iteration through the driver_info records. For of-platdata,
+-- 
+2.25.1
+
--- a/patch/u-boot/u-boot-rockchip64/general-support-rmii-integrated-phy.patch
+++ b/patch/u-boot/u-boot-rockchip64/general-support-rmii-integrated-phy.patch
@@ -319,8 +319,8 @@ index e152faf083..d3f6973043 100644
 #include <phy.h>
 +#include <reset.h>
 #include <syscon.h>
+ #include <asm/global_data.h>
 #include <asm/io.h>
- #include <asm/arch-rockchip/periph.h>
@@ -23,6 +24,8 @@
 #include <asm/arch-rockchip/grf_rk3399.h>
 #include <asm/arch-rockchip/grf_rv1108.h>
@@ -331,7 +331,7 @@ index e152faf083..d3f6973043 100644
 #include "designware.h"
 
@@ -39,21 +41,29 @@ DECLARE_GLOBAL_DATA_PTR;
- struct gmac_rockchip_platdata {
+ struct gmac_rockchip_plat {
 	struct dw_eth_pdata dw_eth_pdata;
 	bool clock_input;
 +	bool integrated_phy;
@@ -342,26 +342,26 @@ index e152faf083..d3f6973043 100644
 
 struct rk_gmac_ops {
 -	int (*fix_mac_speed)(struct dw_eth_dev *priv);
-+	int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata,
+	int (*fix_rmii_speed)(struct gmac_rockchip_plat *pdata,
 +			      struct dw_eth_dev *priv);
-+	int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata,
+	int (*fix_rgmii_speed)(struct gmac_rockchip_plat *pdata,
 +			       struct dw_eth_dev *priv);
- 	void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
- 	void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
-+	void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata);
+ 	void (*set_to_rmii)(struct gmac_rockchip_plat *pdata);
+ 	void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata);
+	void (*integrated_phy_powerup)(struct gmac_rockchip_plat *pdata);
 };
 
 
- static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
+ static int gmac_rockchip_of_to_plat(struct udevice *dev)
 {
- 	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ 	struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
 +	struct ofnode_phandle_args args;
 	const char *string;
 +	int ret;
 
 	string = dev_read_string(dev, "clock_in_out");
 	if (!strcmp(string, "input"))
-@@ -61,6 +71,25 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
+@@ -61,6 +71,25 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev)
 	else
 		pdata->clock_input = false;
 
@@ -387,12 +387,12 @@ index e152faf083..d3f6973043 100644
 	/* Check the new naming-style first... */
 	pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
 	pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
-@@ -74,7 +103,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
- 	return designware_eth_ofdata_to_platdata(dev);
+@@ -74,7 +103,8 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev)
+ 	return designware_eth_of_to_plat(dev);
 }
 
 -static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
-+static int px30_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int px30_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
 +				      struct dw_eth_dev *priv)
 {
 	struct px30_grf *grf;
@@ -402,7 +402,7 @@ index e152faf083..d3f6973043 100644
 }
 
 -static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
-+static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
 +				      struct dw_eth_dev *priv)
 +{
 +	struct rk322x_grf *grf;
@@ -437,7 +437,7 @@ index e152faf083..d3f6973043 100644
 +	return 0;
 +}
 +
-+static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
 +				       struct dw_eth_dev *priv)
 {
 	struct rk322x_grf *grf;
@@ -447,7 +447,7 @@ index e152faf083..d3f6973043 100644
 }
 
 -static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
-+static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
 +				       struct dw_eth_dev *priv)
 {
 	struct rk3288_grf *grf;
@@ -457,7 +457,7 @@ index e152faf083..d3f6973043 100644
 }
 
 -static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
-+static int rk3308_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3308_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
 +				       struct dw_eth_dev *priv)
 {
 	struct rk3308_grf *grf;
@@ -467,7 +467,7 @@ index e152faf083..d3f6973043 100644
 }
 
 -static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
-+static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
 +				      struct dw_eth_dev *priv)
 +{
 +	struct rk3328_grf_regs *grf;
@@ -502,7 +502,7 @@ index e152faf083..d3f6973043 100644
 +	return 0;
 +}
 +
-+static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
 +				       struct dw_eth_dev *priv)
 {
 	struct rk3328_grf_regs *grf;
@@ -512,7 +512,7 @@ index e152faf083..d3f6973043 100644
 }
 
 -static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
-+static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
 +				       struct dw_eth_dev *priv)
 {
 	struct rk3368_grf *grf;
@@ -522,7 +522,7 @@ index e152faf083..d3f6973043 100644
 }
 
 -static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
-+static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata,
 +				       struct dw_eth_dev *priv)
 {
 	struct rk3399_grf_regs *grf;
@@ -532,16 +532,16 @@ index e152faf083..d3f6973043 100644
 }
 
 -static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
-+static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata,
 +				       struct dw_eth_dev *priv)
 {
 	struct rv1108_grf *grf;
 	int clk, speed;
-@@ -357,6 +464,28 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+@@ -357,6 +464,28 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
 		     PX30_GMAC_PHY_INTF_SEL_RMII);
 }
 
-+static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
 +{
 +	struct rk322x_grf *grf;
 +	enum {
@@ -563,14 +563,14 @@ index e152faf083..d3f6973043 100644
 +		     RK3228_GMAC_PHY_INTF_SEL_RMII);
 +}
 +
- static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
 {
 	struct rk322x_grf *grf;
-@@ -435,6 +564,25 @@ static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+@@ -435,6 +564,25 @@ static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
 		     RK3308_GMAC_PHY_INTF_SEL_RMII);
 }
 
-+static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
 +{
 +	struct rk3328_grf_regs *grf;
 +	enum {
@@ -589,14 +589,14 @@ index e152faf083..d3f6973043 100644
 +		     RK3328_RMII_MODE);
 +}
 +
- static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata)
 {
 	struct rk3328_grf_regs *grf;
-@@ -550,6 +698,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+@@ -550,6 +698,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata)
 		     RV1108_GMAC_PHY_INTF_SEL_RMII);
 }
 
-+static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
+static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_plat *pdata)
 +{
 +	struct rk322x_grf *grf;
 +	enum {
@@ -656,7 +656,7 @@ index e152faf083..d3f6973043 100644
 +	udelay(30 * 1000);
 +}
 +
-+static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
+static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_plat *pdata)
 +{
 +	struct rk3328_grf_regs *grf;
 +	enum {
@@ -718,7 +718,7 @@ index e152faf083..d3f6973043 100644
 +
 static int gmac_rockchip_probe(struct udevice *dev)
 {
- 	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ 	struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
@@ -569,6 +837,9 @@ static int gmac_rockchip_probe(struct udevice *dev)
 	if (ret)
 		return ret;
@@ -742,12 +742,12 @@ index e152faf083..d3f6973043 100644
 
 static int gmac_rockchip_eth_start(struct udevice *dev)
 {
-	struct eth_pdata *pdata = dev_get_platdata(dev);
-+	struct eth_pdata *eth_pdata = dev_get_platdata(dev);
+-	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct eth_pdata *eth_pdata = dev_get_plat(dev);
 	struct dw_eth_dev *priv = dev_get_priv(dev);
 	struct rk_gmac_ops *ops =
 		(struct rk_gmac_ops *)dev_get_driver_data(dev);
-+	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+	struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
 	int ret;
 
 -	ret = designware_eth_init(priv, pdata->enetaddr);
--- a/patch/u-boot/u-boot-rockchip64/rk3328-efuse-driver.patch
+++ b/patch/u-boot/u-boot-rockchip64/rk3328-efuse-driver.patch
@@ -41,7 +41,7 @@ index 2520c6a3..c3e58188 100644
 +	u32 auto_ctrl; /* 0x24 */
 };
 
- struct rockchip_efuse_platdata {
+ struct rockchip_efuse_plat {
@@ -83,6 +100,57 @@ U_BOOT_CMD(
 );
 #endif
@@ -49,7 +49,7 @@ index 2520c6a3..c3e58188 100644
 +static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset,
 +				      void *buf, int size)
 +{
-+	struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
+	struct rockchip_efuse_plat *plat = dev_get_plat(dev);
 +	struct rockchip_efuse_regs *efuse =
 +		(struct rockchip_efuse_regs *)plat->base;
 +	unsigned int addr_start, addr_end, addr_offset, addr_len;
--- a/patch/u-boot/u-boot-rockchip64/rk3399-always-init-rkclk.patch
+++ b/patch/u-boot/u-boot-rockchip64/rk3399-always-init-rkclk.patch
@@ -1,4 +1,4 @@
-This patch enables clk initialisation of rk3399 cpu in u-boot proper.
+This patch forces clk initialisation of rk3399 cpu in u-boot proper.

 Normally it should only be initialised in SPL as it is "time consuming".
 Doing so however leaves cpus clocked to low frequencies
@@ -8,47 +8,15 @@ which does not involve SPL phase.
 Signed-off-by: Piotr Szczepanik <piter75@gmail.com>

 diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
-index 865b80cc..fe546436 100644
+index f8cbda44..687c3ad7 100644
 --- a/drivers/clk/rockchip/clk_rk3399.c
 +++ b/drivers/clk/rockchip/clk_rk3399.c
-@@ -47,12 +47,9 @@ struct pll_div {
- 	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
- 	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
- 
-#if defined(CONFIG_SPL_BUILD)
- static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
- static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
-#else
- static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
-#endif
- 
- static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
- static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
-@@ -1071,7 +1068,6 @@ static struct clk_ops rk3399_clk_ops = {
+@@ -1394,7 +1394,7 @@ static int rk3399_clk_probe(struct udevice *dev)
+ 	}
 #endif
- };
 
-#ifdef CONFIG_SPL_BUILD
- static void rkclk_init(struct rockchip_cru *cru)
- {
- 	u32 aclk_div;
-@@ -1149,11 +1145,9 @@ static void rkclk_init(struct rockchip_cru *cru)
- 		     hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
- 		     HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
- }
-#endif
+-	if (init_clocks)
+	if (init_clocks || 1 == 1)
+		rkclk_init(priv->cru);
 
- static int rk3399_clk_probe(struct udevice *dev)
- {
-#ifdef CONFIG_SPL_BUILD
- 	struct rk3399_clk_priv *priv = dev_get_priv(dev);
- 
- #if CONFIG_IS_ENABLED(OF_PLATDATA)
-@@ -1162,7 +1156,6 @@ static int rk3399_clk_probe(struct udevice *dev)
- 	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
- #endif
- 	rkclk_init(priv->cru);
-#endif
 	return 0;
- }
-