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Split ATF compilation into a separate function

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This commit is contained in:
zador-blood-stained
2017-08-06 16:52:24 +03:00
parent f0e47d15a6
commit 634110e787
9 changed files with 102 additions and 13 deletions
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21
patch/atf/atf-sun50iw1/board_pine64so/set-lpddr3-dram-voltage.patch Normal file
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@@ -0,0 +1,21 @@
diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
index 0c2487e..30708f4 100644
--- a/plat/sun50iw1p1/sunxi_power.c
+++ b/plat/sun50iw1p1/sunxi_power.c
@@ -258,12 +258,10 @@ static int pmic_setup(void)
* changes. This should be further confined once we are able to
* reliably detect a Pine64 board.
*/
- ret = sunxi_pmic_read(0x24); /* read DCDC5 register */
- if ((ret & 0x7f) == 0x26) { /* check for 1.24V value */
- NOTICE("PMIC: fixing DRAM voltage from 1.24V to 1.36V\n");
- sunxi_pmic_write(0x24, 0x2c);
- }
-
+
+ NOTICE("PMIC: setting DRAM voltage to 1.24V\n");
+ sunxi_pmic_write(0x24, 0x25); /* DCDC5 = LPDDR RAM voltage = 1.24V */
+
sunxi_pmic_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */
return 0;

21
patch/atf/atf-sun50iw1/board_pinebook-a64/set-lpddr3-dram-voltage.patch Normal file
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@@ -0,0 +1,21 @@
diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c
index 0c2487e..30708f4 100644
--- a/plat/sun50iw1p1/sunxi_power.c
+++ b/plat/sun50iw1p1/sunxi_power.c
@@ -258,12 +258,10 @@ static int pmic_setup(void)
* changes. This should be further confined once we are able to
* reliably detect a Pine64 board.
*/
- ret = sunxi_pmic_read(0x24); /* read DCDC5 register */
- if ((ret & 0x7f) == 0x26) { /* check for 1.24V value */
- NOTICE("PMIC: fixing DRAM voltage from 1.24V to 1.36V\n");
- sunxi_pmic_write(0x24, 0x2c);
- }
-
+
+ NOTICE("PMIC: setting DRAM voltage to 1.24V\n");
+ sunxi_pmic_write(0x24, 0x25); /* DCDC5 = LPDDR RAM voltage = 1.24V */
+
sunxi_pmic_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */
return 0;

65
patch/atf/atf-sun50iw2/add-pc2-shutdown.patch Normal file
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@@ -0,0 +1,65 @@
diff --git a/plat/sun50iw1p1/plat_pm.c b/plat/sun50iw1p1/plat_pm.c
index ec26248..ed53871 100644
--- a/plat/sun50iw1p1/plat_pm.c
+++ b/plat/sun50iw1p1/plat_pm.c
@@ -254,7 +254,59 @@ static int32_t sunxi_affinst_suspend_finish(uint64_t mpidr,
******************************************************************************/
static void __dead2 sunxi_system_off(void)
{
- sunxi_pmic_write(0x32, sunxi_pmic_read(0x32) | 0x80);
+ uint16_t soc_id;
+ uint32_t reg;
+ soc_id = sunxi_get_socid();
+
+ switch (soc_id) {
+ case 0x1689:
+ sunxi_pmic_write(0x32, sunxi_pmic_read(0x32) | 0x80);
+ break;
+ case 0x1718:
+ /* Disable EMAC power: PD6 to low */
+ reg = mmio_read_32(0x01c20800 + 0x6c);
+ reg &= ~(0x7 << 24);
+ reg |= (0x1 << 24);
+ mmio_write_32(0x01f02c00 + 0x6c, reg);
+
+ reg = mmio_read_32(0x01c20800 + 0x7c);
+ reg &= ~(0x1 << 6);
+ mmio_write_32(0x01f02c00 + 0x7c, reg);
+
+ /* Disable DRAM regulator: PL9 to low */
+ reg = mmio_read_32(0x01f02c00 + 0x04);
+ reg &= ~(0x7 << 4);
+ reg |= (0x1 << 4);
+ mmio_write_32(0x01f02c00 + 0x04, reg);
+
+ reg = mmio_read_32(0x01f02c00 + 0x10);
+ reg &= ~(0x1 << 9);
+ mmio_write_32(0x01f02c00 + 0x10, reg);
+
+ /* Disable I/O regulator: PL5 to low - Edit: not needed
+ reg = mmio_read_32(0x01f02c00 + 0x00);
+ reg &= ~(0x7 << 20);
+ reg |= (0x1 << 20);
+ mmio_write_32(0x01f02c00 + 0x00, reg);
+
+ reg = mmio_read_32(0x01f02c00 + 0x10);
+ reg &= ~(0x1 << 5);
+ mmio_write_32(0x01f02c00 + 0x10, reg); */
+
+ /* Disable CPU regulator: PL8 to low */
+ reg = mmio_read_32(0x01f02c00 + 0x04);
+ reg &= ~0x7;
+ reg |= 0x1;
+ mmio_write_32(0x01f02c00 + 0x04, reg);
+
+ reg = mmio_read_32(0x01f02c00 + 0x10);
+ reg &= ~(0x1 << 8);
+ mmio_write_32(0x01f02c00 + 0x10, reg);
+
+ udelay(100);
+ break;
+ }
+
ERROR("PSCI system shutdown: still alive ...\n");
wfi();