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Add board NanoPi R3S LTS U-Boot Support
Signed-off-by: Patrick Yavitz <pyavitz@gmail.com>
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Patrick Yavitz
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c0rnelius
c0rnelius
parent
5921322e6a
commit
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@@ -0,0 +1,161 @@
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From bea4b2ca743e63edb9b926f54d040a185399e0dc Mon Sep 17 00:00:00 2001
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From: Patrick Yavitz <pyavitz@gmail.com>
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Date: Sun, 15 Jun 2025 09:36:33 -0400
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Subject: [PATCH] Add board NanoPi R3S LTS
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Signed-off-by: Patrick Yavitz <pyavitz@gmail.com>
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---
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configs/nanopi-r3s-lts-rk3566_defconfig | 74 +++++++++++++++++++
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.../arm64/rockchip/rk3566-nanopi-r3s-lts.dts | 59 +++++++++++++++
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2 files changed, 133 insertions(+)
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create mode 100644 configs/nanopi-r3s-lts-rk3566_defconfig
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create mode 100644 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s-lts.dts
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diff --git a/configs/nanopi-r3s-lts-rk3566_defconfig b/configs/nanopi-r3s-lts-rk3566_defconfig
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new file mode 100644
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index 00000000000..af983228048
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--- /dev/null
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+++ b/configs/nanopi-r3s-lts-rk3566_defconfig
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@@ -0,0 +1,74 @@
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+CONFIG_ARM=y
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+CONFIG_SKIP_LOWLEVEL_INIT=y
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+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
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+CONFIG_COUNTER_FREQUENCY=24000000
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+CONFIG_ARCH_ROCKCHIP=y
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+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s-lts"
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+CONFIG_ROCKCHIP_RK3568=y
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+CONFIG_SPL_SERIAL=y
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+CONFIG_SYS_LOAD_ADDR=0xc00800
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+CONFIG_DEBUG_UART_BASE=0xFE660000
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+CONFIG_DEBUG_UART_CLOCK=24000000
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+CONFIG_PCI=y
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+CONFIG_DEBUG_UART=y
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_SPL_FIT_SIGNATURE=y
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+CONFIG_SPL_LOAD_FIT=y
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+CONFIG_LEGACY_IMAGE_FORMAT=y
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+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s-lts.dtb"
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+# CONFIG_DISPLAY_CPUINFO is not set
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+CONFIG_DISPLAY_BOARDINFO_LATE=y
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+CONFIG_SPL_MAX_SIZE=0x40000
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+CONFIG_SPL_PAD_TO=0x7f8000
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+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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+CONFIG_SPL_ATF=y
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+CONFIG_CMD_GPIO=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_I2C=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_PCI=y
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+CONFIG_CMD_USB=y
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+CONFIG_CMD_PMIC=y
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+CONFIG_CMD_REGULATOR=y
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+# CONFIG_SPL_DOS_PARTITION is not set
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+CONFIG_SPL_OF_CONTROL=y
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+CONFIG_OF_LIVE=y
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+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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+CONFIG_SPL_DM_SEQ_ALIAS=y
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+CONFIG_SPL_REGMAP=y
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+CONFIG_SPL_SYSCON=y
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+CONFIG_SPL_CLK=y
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+CONFIG_ROCKCHIP_GPIO=y
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+CONFIG_SYS_I2C_ROCKCHIP=y
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+CONFIG_LED=y
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+CONFIG_LED_GPIO=y
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+CONFIG_MISC=y
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+CONFIG_SUPPORT_EMMC_RPMB=y
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+CONFIG_MMC_DW=y
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+CONFIG_MMC_DW_ROCKCHIP=y
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+CONFIG_MMC_SDHCI=y
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+CONFIG_MMC_SDHCI_SDMA=y
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+CONFIG_MMC_SDHCI_ROCKCHIP=y
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+CONFIG_PHY_REALTEK=y
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+CONFIG_DWC_ETH_QOS=y
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+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
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+CONFIG_RTL8169=y
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+CONFIG_PCIE_DW_ROCKCHIP=y
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+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
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+CONFIG_SPL_PINCTRL=y
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+CONFIG_DM_PMIC=y
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+CONFIG_PMIC_RK8XX=y
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+CONFIG_REGULATOR_RK8XX=y
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+CONFIG_PWM_ROCKCHIP=y
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+CONFIG_SPL_RAM=y
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+CONFIG_BAUDRATE=1500000
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+CONFIG_DEBUG_UART_SHIFT=2
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+CONFIG_SYS_NS16550_MEM32=y
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+CONFIG_SYSRESET=y
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+CONFIG_USB=y
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+CONFIG_USB_XHCI_HCD=y
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+CONFIG_USB_DWC3=y
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+CONFIG_USB_DWC3_GENERIC=y
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+CONFIG_ERRNO_STR=y
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diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s-lts.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s-lts.dts
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new file mode 100644
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index 00000000000..e3305f4044d
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--- /dev/null
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+++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s-lts.dts
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@@ -0,0 +1,59 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
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+ * (http://www.friendlyelec.com)
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+ */
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+
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+/dts-v1/;
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+
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+#include "rk3566-nanopi-r3s.dts"
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+
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+/ {
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+ compatible = "friendlyarm,nanopi-r3s-lts", "rockchip,rk3566";
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+ model = "FriendlyElec NanoPi R3S LTS";
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+
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+ hdmi-con {
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+ compatible = "hdmi-connector";
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+ type = "d";
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+
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+ port {
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+ hdmi_con_in: endpoint {
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+ remote-endpoint = <&hdmi_out_con>;
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+ };
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+ };
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+ };
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+};
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+
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+&hdmi {
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+ avdd-0v9-supply = <&vdda_0v9>;
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+ avdd-1v8-supply = <&vcca1v8_image>;
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+ status = "okay";
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+};
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+
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+&hdmi_in {
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+ hdmi_in_vp0: endpoint {
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+ remote-endpoint = <&vp0_out_hdmi>;
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+ };
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+};
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+
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+&hdmi_out {
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+ hdmi_out_con: endpoint {
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+ remote-endpoint = <&hdmi_con_in>;
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+ };
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+};
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+
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+&hdmi_sound {
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+ status = "okay";
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+};
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+
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+&i2s0_8ch {
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+ status = "okay";
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+};
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+
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+&vp0 {
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+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
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+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
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+ remote-endpoint = <&hdmi_in_vp0>;
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+ };
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+};
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--
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2.43.0
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