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rk322x: fix emmc/sdio clock selection
This commit is contained in:
Paolo Sabatino
@@ -0,0 +1,38 @@
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From 9e105544fcb63f8f79b199d1b194a36a354519b3 Mon Sep 17 00:00:00 2001
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From: Paolo Sabatino <paolo.sabatino@gmail.com>
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Date: Sun, 2 Apr 2023 10:53:07 +0000
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Subject: [PATCH 2/2] rk322x: better handle mmc/sdio clocks
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---
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drivers/clk/rockchip/clk-rk3228.c | 10 ++++------
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1 file changed, 4 insertions(+), 6 deletions(-)
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diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
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index 996f8bfee..0f690dd84 100644
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--- a/drivers/clk/rockchip/clk-rk3228.c
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+++ b/drivers/clk/rockchip/clk-rk3228.c
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@@ -371,17 +371,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
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RK2928_CLKGATE_CON(2), 11, GFLAGS),
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- COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
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+ COMPOSITE_DIV_OFFSET(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
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RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
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+ RK2928_CLKSEL_CON(12), 0, 8, DFLAGS,
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RK2928_CLKGATE_CON(2), 13, GFLAGS),
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- DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
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- RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
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- COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
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+ COMPOSITE_DIV_OFFSET(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
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RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
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+ RK2928_CLKSEL_CON(12), 8, 8, DFLAGS,
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RK2928_CLKGATE_CON(2), 14, GFLAGS),
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- DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
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- RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
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/*
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* Clock-Architecture Diagram 2
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--
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2.34.1
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@@ -1,87 +0,0 @@
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diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
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index 2a99f15f5..d36991acd 100644
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--- a/drivers/mmc/host/dw_mmc-rockchip.c
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+++ b/drivers/mmc/host/dw_mmc-rockchip.c
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@@ -15,9 +15,7 @@
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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-#define RK3288_CLKGEN_DIV 2
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-
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-static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
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+#define RK3288_CLKGEN_DIV 2
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struct dw_mci_rockchip_priv_data {
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struct clk *drv_clk;
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@@ -53,7 +51,7 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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ret = clk_set_rate(host->ciu_clk, cclkin);
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if (ret)
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- dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
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+ dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
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bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
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if (bus_hz != host->bus_hz) {
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@@ -292,39 +290,31 @@ static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
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static int dw_mci_rockchip_init(struct dw_mci *host)
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{
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- int ret, i;
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-
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/* It is slot 8 on Rockchip SoCs */
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host->sdio_id0 = 8;
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- if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
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+ if (of_device_is_compatible(host->dev->of_node,
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+ "rockchip,rk3288-dw-mshc"))
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host->bus_hz /= RK3288_CLKGEN_DIV;
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- /* clock driver will fail if the clock is less than the lowest source clock
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- * divided by the internal clock divider. Test for the lowest available
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- * clock and set the minimum freq to clock / clock divider.
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- */
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-
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- for (i = 0; i < ARRAY_SIZE(freqs); i++) {
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- ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
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- if (ret > 0) {
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- host->minimum_speed = ret / RK3288_CLKGEN_DIV;
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- break;
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- }
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- }
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- if (ret < 0)
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- dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
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- }
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-
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return 0;
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}
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+/* Common capabilities of RK3288 SoC */
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+static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
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+ MMC_CAP_CMD23,
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+ MMC_CAP_CMD23,
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+ MMC_CAP_CMD23,
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+ MMC_CAP_CMD23,
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+};
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+
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static const struct dw_mci_drv_data rk2928_drv_data = {
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.init = dw_mci_rockchip_init,
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};
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static const struct dw_mci_drv_data rk3288_drv_data = {
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- .common_caps = MMC_CAP_CMD23,
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+ .caps = dw_mci_rk3288_dwmmc_caps,
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+ .num_caps = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
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.set_ios = dw_mci_rk3288_set_ios,
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.execute_tuning = dw_mci_rk3288_execute_tuning,
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.parse_dt = dw_mci_rk3288_parse_dt,
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@@ -377,9 +367,7 @@ static int dw_mci_rockchip_remove(struct platform_device *pdev)
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pm_runtime_disable(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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- dw_mci_pltfm_remove(pdev);
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-
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- return 0;
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+ return dw_mci_pltfm_remove(pdev);
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}
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static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
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@@ -0,0 +1,38 @@
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From 9e105544fcb63f8f79b199d1b194a36a354519b3 Mon Sep 17 00:00:00 2001
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From: Paolo Sabatino <paolo.sabatino@gmail.com>
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Date: Sun, 2 Apr 2023 10:53:07 +0000
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Subject: [PATCH 2/2] rk322x: better handle mmc/sdio clocks
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---
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drivers/clk/rockchip/clk-rk3228.c | 10 ++++------
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1 file changed, 4 insertions(+), 6 deletions(-)
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diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
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index 996f8bfee..0f690dd84 100644
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--- a/drivers/clk/rockchip/clk-rk3228.c
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+++ b/drivers/clk/rockchip/clk-rk3228.c
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@@ -371,17 +371,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
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RK2928_CLKGATE_CON(2), 11, GFLAGS),
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- COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
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+ COMPOSITE_DIV_OFFSET(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
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RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
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+ RK2928_CLKSEL_CON(12), 0, 8, DFLAGS,
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RK2928_CLKGATE_CON(2), 13, GFLAGS),
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- DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
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- RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
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- COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
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+ COMPOSITE_DIV_OFFSET(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
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RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
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+ RK2928_CLKSEL_CON(12), 8, 8, DFLAGS,
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RK2928_CLKGATE_CON(2), 14, GFLAGS),
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- DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
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- RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
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/*
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* Clock-Architecture Diagram 2
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--
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2.34.1
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@@ -1,87 +0,0 @@
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diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
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index 2a99f15f5..d36991acd 100644
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--- a/drivers/mmc/host/dw_mmc-rockchip.c
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+++ b/drivers/mmc/host/dw_mmc-rockchip.c
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@@ -15,9 +15,7 @@
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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-#define RK3288_CLKGEN_DIV 2
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-
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-static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
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+#define RK3288_CLKGEN_DIV 2
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struct dw_mci_rockchip_priv_data {
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struct clk *drv_clk;
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@@ -53,7 +51,7 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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ret = clk_set_rate(host->ciu_clk, cclkin);
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if (ret)
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- dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
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+ dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
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bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
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if (bus_hz != host->bus_hz) {
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@@ -292,39 +290,31 @@ static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
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static int dw_mci_rockchip_init(struct dw_mci *host)
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{
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- int ret, i;
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-
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/* It is slot 8 on Rockchip SoCs */
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host->sdio_id0 = 8;
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- if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
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+ if (of_device_is_compatible(host->dev->of_node,
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+ "rockchip,rk3288-dw-mshc"))
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host->bus_hz /= RK3288_CLKGEN_DIV;
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- /* clock driver will fail if the clock is less than the lowest source clock
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- * divided by the internal clock divider. Test for the lowest available
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- * clock and set the minimum freq to clock / clock divider.
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- */
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-
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- for (i = 0; i < ARRAY_SIZE(freqs); i++) {
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- ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
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- if (ret > 0) {
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- host->minimum_speed = ret / RK3288_CLKGEN_DIV;
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- break;
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- }
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- }
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- if (ret < 0)
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- dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
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- }
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-
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return 0;
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}
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+/* Common capabilities of RK3288 SoC */
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+static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
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+ MMC_CAP_CMD23,
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+ MMC_CAP_CMD23,
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+ MMC_CAP_CMD23,
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+ MMC_CAP_CMD23,
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+};
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+
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static const struct dw_mci_drv_data rk2928_drv_data = {
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.init = dw_mci_rockchip_init,
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};
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static const struct dw_mci_drv_data rk3288_drv_data = {
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- .common_caps = MMC_CAP_CMD23,
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+ .caps = dw_mci_rk3288_dwmmc_caps,
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+ .num_caps = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
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.set_ios = dw_mci_rk3288_set_ios,
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.execute_tuning = dw_mci_rk3288_execute_tuning,
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.parse_dt = dw_mci_rk3288_parse_dt,
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@@ -377,9 +367,7 @@ static int dw_mci_rockchip_remove(struct platform_device *pdev)
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pm_runtime_disable(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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- dw_mci_pltfm_remove(pdev);
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-
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- return 0;
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+ return dw_mci_pltfm_remove(pdev);
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}
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static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
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