diff --git a/config/sources/families/include/rockchip64_common.inc b/config/sources/families/include/rockchip64_common.inc index 1f2e2f767..c575b789f 100644 --- a/config/sources/families/include/rockchip64_common.inc +++ b/config/sources/families/include/rockchip64_common.inc @@ -151,8 +151,9 @@ case $BRANCH in edge) KERNELPATCHDIR='rockchip64-'$BRANCH - declare -g KERNEL_MAJOR_MINOR="6.5" # Major and minor versions of this kernel. - KERNELBRANCH="branch:linux-6.5.y" + declare -g KERNEL_MAJOR_MINOR="6.6" # Major and minor versions of this kernel. + #KERNELBRANCH="branch:linux-6.6.y" + KERNELBRANCH='tag:v6.6-rc4' LINUXFAMILY=rockchip64 LINUXCONFIG='linux-rockchip64-'$BRANCH diff --git a/patch/kernel/archive/rockchip64-6.6/0000.patching_config.yaml b/patch/kernel/archive/rockchip64-6.6/0000.patching_config.yaml new file mode 100644 index 000000000..e4ab95940 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/0000.patching_config.yaml @@ -0,0 +1,36 @@ +config: # This is file 'patch/kernel/archive/meson64-6.4/0000.patching_config.yaml' + + # Just some info stuff; not used by the patching scripts + name: rockchip64-6.5 + kind: kernel + type: mainline # or: vendor + branch: linux-6.5.y + last-known-good-tag: v6.5 + maintainers: + - { github: rpardini, name: Ricardo Pardini, email: ricardo@pardini.net, armbian-forum: rpardini } + + # .dts files in these directories will be copied as-is to the build tree; later ones overwrite earlier ones. + # This is meant to provide a way to "add a board DTS" without having to null-patch them in. + dts-directories: + - { source: "dt", target: "arch/arm64/boot/dts/rockchip" } + + # every file in these directories will be copied as-is to the build tree; later ones overwrite earlier ones + # This is meant as a way to have overlays, bare, in a directory, without having to null-patch them in. + # @TODO need a solution to auto-Makefile the overlays as well + overlay-directories: + - { source: "overlay", target: "arch/arm64/boot/dts/rockchip/overlay" } + + # the Makefile in each of these directories will be magically patched to include the dts files copied + # or patched-in; overlay subdir will be included "-y" if it exists. + # No more Makefile patching needed, yay! + auto-patch-dt-makefile: + - { directory: "arch/arm64/boot/dts/rockchip", config-var: "CONFIG_ARCH_ROCKCHIP" } + + # configuration for when applying patches to git / auto-rewriting patches (development cycle helpers) + patches-to-git: + do-not-commit-files: + - "MAINTAINERS" # constant churn, drop them. sorry. + - "Documentation/devicetree/bindings/arm/rockchip.yaml" # constant churn, conflicts on every bump, drop it. sorry. + do-not-commit-regexes: # Python-style regexes + - "^arch/([a-zA-Z0-9]+)/boot/dts/([a-zA-Z0-9]+)/Makefile$" # ignore DT Makefile patches, we've an auto-patcher now + diff --git a/patch/kernel/archive/rockchip64-6.6/add-board-helios64.patch b/patch/kernel/archive/rockchip64-6.6/add-board-helios64.patch new file mode 100644 index 000000000..e5746433f --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/add-board-helios64.patch @@ -0,0 +1,1343 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Aditya Prayoga +Date: Tue, 15 Sep 2020 20:04:22 +0700 +Subject: Add board Helios64 + +note: rpardini: this patch was rebased on top of 6.3.1, finally admitting +that it used to blindly overwrite the mainline dts (it was added when helios64 +was not in the tree, and thus a "file addition"). the resulting patch +is the complete set of changes actually done. + +Signed-off-by: Aditya Prayoga +--- + arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 996 +++++++--- + 1 file changed, 764 insertions(+), 232 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index 1eb287a3f8c0..ac0da7b7f43c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -1,53 +1,37 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* +- * Copyright (c) 2020 Aditya Prayoga +- */ +- +-/* +- * The Kobol Helios64 is a board designed to operate as a NAS and optionally +- * ships with an enclosing that can host five 2.5" hard disks. +- * +- * See https://wiki.kobol.io/helios64/intro/ for further details. ++ * Copyright (c) 2020 Aditya Prayoga (aditya@kobol.io) + */ + + /dts-v1/; ++#include ++#include ++#include ++#include + #include "rk3399.dtsi" + #include "rk3399-opp.dtsi" + + / { +- model = "Kobol Helios64"; ++ model = "Helios64"; + compatible = "kobol,helios64", "rockchip,rk3399"; + +- aliases { +- mmc0 = &sdmmc; +- mmc1 = &sdhci; +- spi1 = &spi1; +- spi2 = &spi2; +- spi5 = &spi5; +- }; +- +- avdd_0v9_s0: avdd-0v9-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "avdd_0v9_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; +- vin-supply = <&vcc1v8_sys_s3>; +- }; +- +- avdd_1v8_s0: avdd-1v8-s0 { +- compatible = "regulator-fixed"; +- regulator-name = "avdd_1v8_s0"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc3v3_sys_s3>; ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 1>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <100>; ++ ++ user2-button { ++ label = "User Button 2"; ++ linux,code = ; ++ press-threshold-microvolt = <100000>; ++ }; + }; + +- chosen { +- stdout-path = "serial2:1500000n8"; ++ beeper: beeper { ++ compatible = "gpio-beeper"; ++ gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + }; + + clkin_gmac: external-gmac-clock { +@@ -57,107 +41,86 @@ clkin_gmac: external-gmac-clock { + #clock-cells = <0>; + }; + +- fan1 { +- /* fan connected to P7 */ +- compatible = "pwm-fan"; +- pwms = <&pwm0 0 40000 0>; +- cooling-levels = <0 80 170 255>; +- }; +- +- fan2 { +- /* fan connected to P6 */ +- compatible = "pwm-fan"; +- pwms = <&pwm1 0 40000 0>; +- cooling-levels = <0 80 170 255>; ++ vcc12v_dcin: vcc12v-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; + }; + +- leds { +- compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>; +- +- led-0 { +- label = "helios64:green:status"; +- gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +- default-state = "on"; +- }; +- +- led-1 { +- label = "helios64:red:fault"; +- gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; +- default-state = "keep"; +- }; ++ vcc12v_dcin_bkup: vcc12v-dcin-bkup { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin_bkup"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ vin-supply = <&vcc12v_dcin>; + }; + +- hdd_a_power: hdd-a-power { ++ vcc12v_hdd: vcc12v-hdd { + compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&hdd_a_power_en>; +- pinctrl-names = "default"; ++ regulator-name = "vcc12v_hdd"; + regulator-always-on; + regulator-boot-on; +- regulator-name = "hdd_a_power"; +- startup-delay-us = <2000000>; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ vin-supply = <&vcc12v_dcin_bkup>; + }; + +- hdd_b_power: hdd-b-power { ++ /* switched by pmic_sleep */ ++ vcc1v8_sys_s0: vcc1v8-sys-s0 { + compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&hdd_b_power_en>; +- pinctrl-names = "default"; ++ regulator-name = "vcc1v8_sys_s0"; + regulator-always-on; + regulator-boot-on; +- regulator-name = "hdd_b_power"; +- startup-delay-us = <2000000>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc1v8_sys_s3>; + }; + +- pcie_power: pcie-power { ++ vcc0v9_s3: vcc0v9-s3 { + compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&pcie_pwr>; +- pinctrl-names = "default"; ++ regulator-name = "vcc0v9_s3"; ++ regulator-always-on; + regulator-boot-on; +- regulator-name = "pcie_power"; +- startup-delay-us = <10000>; +- vin-supply = <&vcc5v0_perdev>; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys_s3>; + }; + +- usblan_power: usblan-power { ++ avdd_0v9_s0: avdd-0v9-s0 { + compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&usb_lan_en>; +- regulator-name = "usblan_power"; ++ regulator-name = "avdd_0v9_s0"; + regulator-always-on; + regulator-boot-on; +- vin-supply = <&vcc5v0_usb>; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc1v8_sys_s3>; + }; + +- vcc1v8_sys_s0: vcc1v8-sys-s0 { ++ avdd_1v8_s0: avdd-1v8-s0 { + compatible = "regulator-fixed"; +- regulator-name = "vcc1v8_sys_s0"; ++ regulator-name = "avdd_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc1v8_sys_s3>; ++ vin-supply = <&vcc3v3_sys_s3>; + }; + +- vcc3v0_sd: vcc3v0-sd { ++ pcie_power: pcie-power { + compatible = "regulator-fixed"; + enable-active-high; +- gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; +- regulator-name = "vcc3v0_sd"; +- regulator-boot-on; +- regulator-min-microvolt = <3000000>; +- regulator-max-microvolt = <3000000>; ++ gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc0_pwr_h>; +- vin-supply = <&vcc3v3_sys_s3>; ++ pinctrl-0 = <&pcie_pwr_en>; ++ regulator-name = "pcie_power"; ++ regulator-boot-on; ++ startup-delay-us = <10000>; ++ vin-supply = <&vcc5v0_perdev>; + }; + + vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { +@@ -174,6 +137,39 @@ regulator-state-mem { + }; + }; + ++ vcc3v0_sd: vcc3v0-sd { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v0_sd"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ vin-supply = <&vcc3v3_sys_s3>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_en>; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_perdev>; ++ }; ++ ++ vcc5v0_typec: vcc5v0-typec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_vbus_en>; ++ regulator-name = "vcc5v0_typec"; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ + vcc5v0_perdev: vcc5v0-perdev { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_perdev"; +@@ -184,6 +180,16 @@ vcc5v0_perdev: vcc5v0-perdev { + vin-supply = <&vcc12v_dcin_bkup>; + }; + ++ vcc5v0_hdd: vcc5v0-hdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_hdd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin_bkup>; ++ }; ++ + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; +@@ -198,68 +204,213 @@ regulator-state-mem { + }; + }; + +- vcc5v0_usb: vcc5v0-usb { ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 1>; ++ pwm-supply = <&vcc5v0_sys>; ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <830000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ power_hdd_a: power-hdd-a { + compatible = "regulator-fixed"; + enable-active-high; +- gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; ++ gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_usb_en>; +- regulator-name = "vcc5v0_usb"; ++ pinctrl-0 = <&hdd_a_power>; ++ regulator-name = "power_hdd_a"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- vin-supply = <&vcc5v0_perdev>; + }; + +- vcc12v_dcin: vcc12v-dcin { ++ power_hdd_b: power-hdd-b { + compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdd_b_power>; ++ regulator-name = "power_hdd_b"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; + }; + +- vcc12v_dcin_bkup: vcc12v-dcin-bkup { ++ usblan_power: usblan-power { + compatible = "regulator-fixed"; +- regulator-name = "vcc12v_dcin_bkup"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_lan_en>; ++ regulator-name = "usblan_power"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <12000000>; +- regulator-max-microvolt = <12000000>; +- vin-supply = <&vcc12v_dcin>; ++ vin-supply = <&vcc5v0_usb>; + }; +-}; + +-/* +- * The system doesn't run stable with cpu freq enabled, so disallow the lower +- * frequencies until this problem is properly understood and resolved. +- */ +-&cluster0_opp { +- /delete-node/ opp00; +- /delete-node/ opp01; +- /delete-node/ opp02; +- /delete-node/ opp03; +- /delete-node/ opp04; +-}; ++ fan1: p7-fan { ++ compatible = "pwm-fan"; ++ pwms = <&pwm0 0 40000 0>; ++ cooling-min-state = <0>; ++ cooling-max-state = <3>; ++ #cooling-cells = <2>; ++ cooling-levels = <0 80 170 255>; ++ }; + +-&cluster1_opp { +- /delete-node/ opp00; +- /delete-node/ opp01; +- /delete-node/ opp02; +- /delete-node/ opp03; +- /delete-node/ opp04; +- /delete-node/ opp05; +- /delete-node/ opp06; +-}; ++ fan2: p6-fan { ++ compatible = "pwm-fan"; ++ pwms = <&pwm1 0 40000 0>; ++ cooling-min-state = <0>; ++ cooling-max-state = <3>; ++ #cooling-cells = <2>; ++ cooling-levels = <0 80 170 255>; ++ }; + +-&cpu_b0 { +- cpu-supply = <&vdd_cpu_b>; ++ gpio-charger { ++ compatible = "gpio-charger"; ++ charger-type = "mains"; ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ charge-status-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ac_present_ap>, <&charger_status>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ autorepeat; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwrbtn>, <&user1btn>, <&wake_on_lan>; ++ ++ power { ++ debounce-interval = <100>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "Power"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ ++ user1-button { ++ debounce-interval = <100>; ++ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; ++ label = "User Button 1"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ hdmi_dp_sound: hdmi-dp-sound { ++ status = "okay"; ++ compatible = "rockchip,rk3399-hdmi-dp"; ++ rockchip,cpu = <&i2s2>; ++ rockchip,codec = <&cdn_dp>; ++ }; ++ ++ io_leds: io-gpio-leds { ++ status = "okay"; ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&network_act>, <&usb3_act>, ++ <&sata_act>, <&sata_err_led>; ++ ++ network { ++ label = "helios64:blue:net"; ++ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "netdev"; ++ default-state = "off"; ++ }; ++ ++ sata { ++ label = "helios64:blue:hdd-status"; ++ gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "disk-activity"; ++ default-state = "off"; ++ }; ++ ++ sata_err1 { ++ label = "helios64:red:ata1-err"; ++ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ sata_err2 { ++ label = "helios64:red:ata2-err"; ++ gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ sata_err3 { ++ label = "helios64:red:ata3-err"; ++ gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ sata_err4 { ++ label = "helios64:red:ata4-err"; ++ gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ sata_err5 { ++ label = "helios64:red:ata5-err"; ++ gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ usb3 { ++ label = "helios64:blue:usb3"; ++ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&int_hub_port1>, ++ <&int_hub_port2>, ++ <&int_hub_port3>; ++ linux,default-trigger = "usbport"; ++ default-state = "off"; ++ }; ++ }; ++ ++ pwmleds { ++ compatible = "pwm-leds"; ++ status = "okay"; ++ ++ power-led { ++ label = "helios64:blue:power-status"; ++ pwms = <&pwm3 0 2000000000 0>; ++ max-brightness = <255>; ++ }; ++ }; ++ ++ system_leds: system-gpio-leds { ++ status = "okay"; ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&system_led>; ++ ++ status-led { ++ label = "helios64::status"; ++ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "none"; ++ default-state = "on"; ++ mode = <0x23>; ++ }; ++ ++ fault-led { ++ label = "helios64:red:fault"; ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "panic"; ++ default-state = "keep"; ++ mode = <0x23>; ++ }; ++ }; + }; + +-&cpu_b1 { +- cpu-supply = <&vdd_cpu_b>; ++&cdn_dp { ++ status = "okay"; ++ extcon = <&fusb0>; ++ phys = <&tcphy0_dp>; + }; + + &cpu_l0 { +@@ -278,23 +429,36 @@ &cpu_l3 { + cpu-supply = <&vdd_cpu_l>; + }; + ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ + &emmc_phy { + status = "okay"; + }; + + &gmac { +- assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; +- phy-mode = "rgmii"; + phy-supply = <&vcc_lan>; ++ phy-mode = "rgmii"; + pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins &gphy_reset>; +- rx_delay = <0x20>; +- tx_delay = <0x28>; ++ pinctrl-0 = <&rgmii_pins &rgmii_phy_reset>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ tx_delay = <0x28>; ++ rx_delay = <0x20>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; + status = "okay"; + }; + +@@ -307,12 +471,15 @@ &i2c0 { + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; +- clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; ++ wakeup-source; ++ + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; +@@ -325,10 +492,21 @@ rk808: pmic@1b { + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys_s3>; + vddio-supply = <&vcc3v0_s3>; +- wakeup-source; +- #clock-cells = <1>; + + regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; +@@ -336,19 +514,48 @@ vdd_cpu_l: DCDC_REG2 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; +- + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + ++ vcc_ddr_s3: DCDC_REG3 { ++ regulator-name = "vcc_ddr_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ + vcc1v8_sys_s3: DCDC_REG4 { + regulator-name = "vcc1v8_sys_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ /* not used */ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ }; ++ ++ /* not used */ ++ vcc3v0_touch: LDO_REG2 { ++ regulator-name = "vcc3v0_touch"; ++ }; + ++ vcc1v8_s3: LDO_REG3 { ++ regulator-name = "vcc1v8_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; +@@ -361,25 +568,61 @@ vcc_sdio_s0: LDO_REG4 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; +- + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + ++ /* not used */ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-name = "vcca3v0_codec"; ++ }; ++ ++ vcc1v5_s3: LDO_REG6 { ++ regulator-name = "vcc1v5_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ /* not used */ ++ vcca1v8_codec: LDO_REG7 { ++ regulator-name = "vcca1v8_codec"; ++ }; ++ + vcc3v0_s3: LDO_REG8 { + regulator-name = "vcc3v0_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +- + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; ++ ++ vcc3v3_sys_s0: SWITCH_REG1 { ++ regulator-name = "vcc3v3_sys_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ /* not used */ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ }; + }; + }; + +@@ -387,12 +630,33 @@ vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <40000>; + regulator-always-on; + regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel2_gpio>; ++ regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { +@@ -407,56 +671,222 @@ &i2c2 { + i2c-scl-falling-time-ns = <30>; + status = "okay"; + ++ gpio-expander@20 { ++ compatible = "nxp,pca9555"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pca0_pins>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ vcc-supply = <&vcc3v3_sys_s3>; ++ }; ++ + temp@4c { +- compatible = "national,lm75"; ++ compatible = "onnn,lm75"; + reg = <0x4c>; + }; + }; + +-&io_domains { +- audio-supply = <&vcc1v8_sys_s0>; +- bt656-supply = <&vcc1v8_sys_s0>; +- gpio1830-supply = <&vcc3v0_s3>; +- sdmmc-supply = <&vcc_sdio_s0>; ++&i2c4 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <160>; ++ i2c-scl-falling-time-ns = <30>; ++ status = "okay"; ++ ++ fusb0: typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_int>; ++ vbus-supply = <&vcc5v0_typec>; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ power-role = "dual"; ++ data-role = "dual"; ++ try-power-role = "sink"; ++ source-pdos = ; ++ sink-pdos = ; ++ op-sink-microwatt = <5000000>; ++ ++ extcon-cables = <1 2 5 6 9 10 12 44>; ++ typec-altmodes = <0xff01 1 0x001c0000 1>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usb_con_hs: endpoint { ++ remote-endpoint = <&u2phy0_typec_hs>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ usb_con_ss: endpoint { ++ remote-endpoint = <&tcphy0_typec_ss>; ++ }; ++ }; ++ port@2 { ++ reg = <2>; ++ usb_con_sbu: endpoint { ++ remote-endpoint = <&tcphy0_typec_dp>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++/* I2C on UEXT */ ++&i2c7 { + status = "okay"; + }; + +-&pcie_phy { ++/* External I2C */ ++&i2c8 { ++ status = "okay"; ++}; ++ ++&i2s2 { ++ #sound-dai-cells = <0>; + status = "okay"; + }; + ++&io_domains { ++ status = "okay"; ++ bt656-supply = <&vcc1v8_sys_s0>; ++ audio-supply = <&vcc1v8_sys_s0>; ++ sdmmc-supply = <&vcc_sdio_s0>; ++ gpio1830-supply = <&vcc3v0_s3>; ++}; ++ + &pcie0 { + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; +- max-link-speed = <2>; + num-lanes = <2>; ++ max-link-speed = <2>; + pinctrl-names = "default"; +- status = "okay"; +- ++ pinctrl-0 = <&pcie_prst &pcie_clkreqn_cpm>; + vpcie12v-supply = <&vcc12v_dcin>; + vpcie3v3-supply = <&pcie_power>; + vpcie1v8-supply = <&avdd_1v8_s0>; + vpcie0v9-supply = <&avdd_0v9_s0>; ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ status = "okay"; + }; + + &pinctrl { ++ buttons { ++ pwrbtn: pwrbtn { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ user1btn: usr1btn { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ charger { ++ ac_present_ap: ac-present-ap { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ charger_status: charger-status { ++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fan { ++ fan1_sense: fan1-sense { ++ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ fan2_sense: fan2-sense { ++ rockchip,pins = <4 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fusb30x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = ++ <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ fusb0_vbus_en: fusb0-vbus-en { ++ rockchip,pins = ++ <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ + gmac { +- gphy_reset: gphy-reset { +- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; ++ rgmii_phy_reset: rgmii-phy-reset { ++ rockchip,pins = ++ <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + leds { +- sys_grn_led_on: sys-grn-led-on { +- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; ++ network_act: network-act { ++ rockchip,pins = ++ <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ usb3_act: usb3-act { ++ rockchip,pins = ++ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ sata_act: sata-act { ++ rockchip,pins = ++ <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ system_led: sys-led { ++ rockchip,pins = ++ <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>, ++ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ sata_err_led: sata-err-led { ++ rockchip,pins = ++ <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>, ++ <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>, ++ <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, ++ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, ++ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ misc { ++ pca0_pins: pca0-pins { ++ rockchip,pins = ++ <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + +- sys_red_led_on: sys-red-led-on { +- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; ++ wake_on_lan: wake-on-lan { ++ rockchip,pins = ++ <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { +- pcie_pwr: pcie-pwr { ++ pcie_prst: pcie-prst { ++ rockchip,pins = ++ <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_pwr_en: pcie-pwr-en { + rockchip,pins = + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; +@@ -464,31 +894,45 @@ pcie_pwr: pcie-pwr { + + pmic { + pmic_int_l: pmic-int-l { +- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = ++ <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = ++ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = ++ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + +- power { +- hdd_a_power_en: hdd-a-power-en { +- rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ power { ++ hdd_a_power: hdd-a-power { ++ rockchip,pins = ++ <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + +- hdd_b_power_en: hdd-b-power-en { +- rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ hdd_b_power: hdd-b-power { ++ rockchip,pins = ++ <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_en: vcc5v0-usb-en { +- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ rockchip,pins = ++ <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + +- usb_lan_en: usb-lan-en { +- rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ sdmmc0_pwr_h: sdmmc0-pwr-h { ++ rockchip,pins = ++ <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; + }; +- }; + +- vcc3v0-sd { +- sdmmc0_pwr_h: sdmmc0-pwr-h { +- rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; ++ usb_lan_en: usb-lan-en { ++ rockchip,pins = ++ <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; +@@ -499,28 +943,46 @@ &pmu_io_domains { + }; + + &pwm0 { +- /* pwm-fan on P7 */ + status = "okay"; + }; + + &pwm1 { +- /* pwm-fan on P6 */ ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&pwm3 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcc1v8_s3>; + status = "okay"; + }; + + &sdhci { ++ assigned-clock-rates = <150000000>; + bus-width = <8>; + mmc-hs200-1_8v; ++ // hs400 is broken on Helios64 since 5.10.60 ++ // mmc-hs400-1_8v; ++ // mmc-hs400-enhanced-strobe; ++ supports-emmc; + non-removable; +- vqmmc-supply = <&vcc1v8_sys_s0>; ++ disable-wp; + status = "okay"; ++ vqmmc-supply = <&vcc1v8_sys_s0>; + }; + + &sdmmc { + bus-width = <4>; + cap-sd-highspeed; +- cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; // TODO: verify what needs to be done to use implicit CD definition + disable-wp; ++ sd-uhs-sdr104; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; +@@ -530,14 +992,6 @@ &sdmmc { + + &spi1 { + status = "okay"; +- +- spiflash: flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0x0>; +- spi-max-frequency = <25000000>; +- status = "okay"; +- m25p,fast-read; +- }; + }; + + /* UEXT connector */ +@@ -549,8 +1003,28 @@ &spi5 { + status = "okay"; + }; + ++&tcphy0 { ++ extcon = <&fusb0>; ++ status = "okay"; ++}; ++ ++&tcphy0_dp { ++ port { ++ tcphy0_typec_dp: endpoint { ++ remote-endpoint = <&usb_con_sbu>; ++ }; ++ }; ++}; ++ ++&tcphy0_usb3 { ++ port { ++ tcphy0_typec_ss: endpoint { ++ remote-endpoint = <&usb_con_ss>; ++ }; ++ }; ++}; ++ + &tcphy1 { +- /* phy for &usbdrd_dwc3_1 */ + status = "okay"; + }; + +@@ -562,61 +1036,119 @@ &tsadc { + status = "okay"; + }; + +-&u2phy1 { ++&u2phy0 { + status = "okay"; + +- otg-port { +- /* phy for &usbdrd_dwc3_1 */ ++ u2phy0_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; ++ ++ port { ++ u2phy0_typec_hs: endpoint { ++ remote-endpoint = <&usb_con_hs>; ++ }; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer>; ++ status = "okay"; + }; + + &uart2 { + status = "okay"; + }; + ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++ dr_mode = "otg"; ++}; ++ + &usbdrd3_1 { + status = "okay"; ++}; + +- usb@fe900000 { +- dr_mode = "host"; +- status = "okay"; ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ int_hub: hub@1 { ++ compatible = "usb2109,0815"; ++ reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + +- hub@1 { +- compatible = "usb2109,0815"; ++ int_hub_port1: port@1 { + reg = <1>; +- #address-cells = <1>; +- #size-cells = <0>; ++ #trigger-source-cells = <0>; ++ }; + +- port@1 { +- reg = <1>; +- #trigger-source-cells = <0>; +- }; ++ int_hub_port2: port@2 { ++ reg = <2>; ++ #trigger-source-cells = <0>; ++ }; + +- port@2 { +- reg = <2>; +- #trigger-source-cells = <0>; +- }; ++ int_hub_port3: port@3 { ++ reg = <3>; ++ #trigger-source-cells = <0>; ++ }; + +- port@3 { +- reg = <3>; +- #trigger-source-cells = <0>; +- }; ++ usb_lan: device@4 { ++ compatible = "usbbda,8156"; ++ reg = <4>; + +- device@4 { +- compatible = "usbbda,8156"; +- reg = <4>; +- #address-cells = <2>; +- #size-cells = <0>; ++ #address-cells = <2>; ++ #size-cells = <0>; + +- interface@0 { /* interface 0 of configuration 1 */ +- compatible = "usbbda,8156.config1.0"; +- reg = <0 1>; +- }; ++ interface@0 { /* interface 0 of configuration 1 */ ++ compatible = "usbbda,8156.config1.0"; ++ reg = <0 1>; + }; + }; + }; + }; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; +\ No newline at end of file +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/add-maker-friendlyarm.patch b/patch/kernel/archive/rockchip64-6.6/add-maker-friendlyarm.patch new file mode 100644 index 000000000..5cf7999d2 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/add-maker-friendlyarm.patch @@ -0,0 +1,211 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Sat, 11 Jan 2020 19:35:03 +0800 +Subject: soc: friendlyelec: Add board info driver + +Change-Id: I122adb4f99c816b5c177f16392fb2df9c10a47be +Signed-off-by: hmz007 +--- + drivers/soc/Kconfig | 1 + + drivers/soc/Makefile | 1 + + drivers/soc/friendlyelec/Kconfig | 11 + + drivers/soc/friendlyelec/Makefile | 1 + + drivers/soc/friendlyelec/board.c | 143 ++++++++++ + 5 files changed, 157 insertions(+) + +diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig +index 4e176280113a..8dabe409f072 100644 +--- a/drivers/soc/Kconfig ++++ b/drivers/soc/Kconfig +@@ -30,5 +30,6 @@ source "drivers/soc/ti/Kconfig" + source "drivers/soc/ux500/Kconfig" + source "drivers/soc/versatile/Kconfig" + source "drivers/soc/xilinx/Kconfig" ++source "drivers/soc/friendlyelec/Kconfig" + + endmenu +diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile +index 3b0f9fb3b5c8..9652d3a514af 100644 +--- a/drivers/soc/Makefile ++++ b/drivers/soc/Makefile +@@ -36,3 +36,4 @@ obj-y += ti/ + obj-$(CONFIG_ARCH_U8500) += ux500/ + obj-$(CONFIG_PLAT_VERSATILE) += versatile/ + obj-y += xilinx/ ++obj-$(CONFIG_VENDOR_FRIENDLYELEC) += friendlyelec/ +diff --git a/drivers/soc/friendlyelec/Kconfig b/drivers/soc/friendlyelec/Kconfig +new file mode 100644 +index 000000000000..9e21c663e6c8 +--- /dev/null ++++ b/drivers/soc/friendlyelec/Kconfig +@@ -0,0 +1,11 @@ ++# ++# Machine drivers ++# ++ ++if ARCH_ROCKCHIP ++ ++config VENDOR_FRIENDLYELEC ++ bool "FriendlyElec board based on RK33XX SoCs" ++ default n ++ ++endif +diff --git a/drivers/soc/friendlyelec/Makefile b/drivers/soc/friendlyelec/Makefile +new file mode 100644 +index 000000000000..870542f05177 +--- /dev/null ++++ b/drivers/soc/friendlyelec/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_VENDOR_FRIENDLYELEC) += board.o +diff --git a/drivers/soc/friendlyelec/board.c b/drivers/soc/friendlyelec/board.c +new file mode 100644 +index 000000000000..886a8e1f7dc0 +--- /dev/null ++++ b/drivers/soc/friendlyelec/board.c +@@ -0,0 +1,143 @@ ++/* ++ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, you can access it online at ++ * http://www.gnu.org/licenses/gpl-2.0.html. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BOARD_MANF "FriendlyELEC Computer Tech. Co., Ltd." ++ ++static const char *board_mach; ++static const char *board_name; ++static u32 board_rev; ++static u32 board_serial_high, board_serial_low; ++ ++static ssize_t board_sys_info_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ char *s = buf; ++ ++ s += sprintf(s, "Hardware\t: %s\n", board_mach); ++ s += sprintf(s, "Revision\t: %04x\n", board_rev); ++ s += sprintf(s, "Serial\t\t: %08x%08x\n", ++ board_serial_high, board_serial_low); ++ s += sprintf(s, "\nModel\t\t: %s\n", board_name); ++ s += sprintf(s, "Manufacturer\t: %s\n", BOARD_MANF); ++ ++ return (s - buf); ++} ++ ++static struct device_attribute board_attr_info = ++ __ATTR(info, S_IRUGO, board_sys_info_show, NULL); ++ ++static int rockchip_cpuinfo_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct nvmem_cell *cell; ++ unsigned char *efuse_buf, buf[16]; ++ size_t len; ++ int i; ++ ++ cell = nvmem_cell_get(dev, "id"); ++ if (IS_ERR(cell)) { ++ dev_err(dev, "failed to get id cell: %ld\n", PTR_ERR(cell)); ++ return PTR_ERR(cell); ++ } ++ ++ efuse_buf = nvmem_cell_read(cell, &len); ++ nvmem_cell_put(cell); ++ ++ if (len != 16) { ++ kfree(efuse_buf); ++ dev_err(dev, "invalid id len: %zu\n", len); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < 8; i++) { ++ buf[i] = efuse_buf[1 + (i << 1)]; ++ buf[i + 8] = efuse_buf[i << 1]; ++ } ++ ++ kfree(efuse_buf); ++ ++ board_serial_low = crc32(0, buf, 8); ++ board_serial_high = crc32(board_serial_low, buf + 8, 8); ++ ++ dev_info(dev, "Serial\t\t: %08x%08x\n", ++ board_serial_high, board_serial_low); ++ ++ return 0; ++} ++ ++static int board_sys_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct device_node *root; ++ ++ root = of_find_node_by_path("/"); ++ ++ of_property_read_u32(np, "hwrev", &board_rev); ++ ++ if (of_property_read_string(np, "machine", &board_mach)) ++ of_property_read_string(root, "compatible", &board_mach); ++ ++ if (of_property_read_string(np, "model", &board_name)) ++ of_property_read_string(root, "model", &board_name); ++ ++ of_node_put(root); ++ ++ rockchip_cpuinfo_probe(pdev); ++ ++ device_create_file(&pdev->dev, &board_attr_info); ++ ++ return 0; ++} ++ ++static const struct of_device_id board_sys_of_match[] = { ++ { .compatible = "friendlyelec,board" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, board_sys_of_match); ++ ++static struct platform_driver board_sys_driver = { ++ .probe = board_sys_probe, ++ .driver = { ++ .name = "friendlyelec-board", ++ .of_match_table = board_sys_of_match, ++ }, ++}; ++ ++static int __init board_sys_init(void) ++{ ++ return platform_driver_register(&board_sys_driver); ++} ++late_initcall(board_sys_init); ++ ++MODULE_AUTHOR("support@friendlyarm.com"); ++MODULE_DESCRIPTION("FriendlyElec NanoPi Series Machine Driver"); ++MODULE_LICENSE("GPL v2"); +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/add-rockchip-iep-driver.patch b/patch/kernel/archive/rockchip64-6.6/add-rockchip-iep-driver.patch new file mode 100644 index 000000000..b3820bf1f --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/add-rockchip-iep-driver.patch @@ -0,0 +1,1808 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paolo +Date: Thu, 9 Sep 2021 22:59:12 +0200 +Subject: Rockchip IEP driver + +> X-Git-Archeology: - Revision 4425589e15c3b1593731703c379df0fa1b4432fb: https://github.com/armbian/build/commit/4425589e15c3b1593731703c379df0fa1b4432fb +> X-Git-Archeology: Date: Thu, 09 Sep 2021 22:59:12 +0200 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: rk322x: bump edge kernel to 5.14, u-boot to 2021.07 (#3133) +> X-Git-Archeology: +> X-Git-Archeology: - Revision a1d044de8e0bb6ca504386bc31f5615a9d169067: https://github.com/armbian/build/commit/a1d044de8e0bb6ca504386bc31f5615a9d169067 +> X-Git-Archeology: Date: Tue, 12 Oct 2021 15:59:01 +0200 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rockchip: update support for edge kernel 5.14 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 682e4085ab8faa278db21a41ed23a6b12f8868ea: https://github.com/armbian/build/commit/682e4085ab8faa278db21a41ed23a6b12f8868ea +> X-Git-Archeology: Date: Thu, 21 Oct 2021 22:55:25 +0200 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: rockchip64: add IEP driver (#3215) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + Documentation/devicetree/bindings/media/rockchip-iep.yaml | 73 + + arch/arm/boot/dts/rockchip/rk3288.dtsi | 13 +- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 22 + + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 13 + + drivers/media/platform/rockchip/Kconfig | 1 + + drivers/media/platform/rockchip/Makefile | 1 + + drivers/media/platform/rockchip/iep/Kconfig | 13 + + drivers/media/platform/rockchip/iep/Makefile | 5 + + drivers/media/platform/rockchip/iep/iep-regs.h | 291 +++ + drivers/media/platform/rockchip/iep/iep.c | 1089 ++++++++++ + drivers/media/platform/rockchip/iep/iep.h | 112 + + 11 files changed, 1632 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml +new file mode 100644 +index 000000000000..a9efcda13fc1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml +@@ -0,0 +1,73 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/rockchip-iep.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip Image Enhancement Processor (IEP) ++ ++description: ++ Rockchip IEP supports various image enhancement operations for YUV and RGB domains. ++ Deinterlacing, spatial and temporal sampling noise reduction are supported by the ++ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in ++ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for ++ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB. ++ ++maintainers: ++ - Heiko Stuebner ++ ++properties: ++ compatible: ++ oneOf: ++ - const: rockchip,rk3228-iep ++ - items: ++ - enum: ++ - rockchip,rk3288-iep ++ - rockchip,rk3328-iep ++ - rockchip,rk3368-iep ++ - rockchip,rk3399-iep ++ - const: rockchip,rk3228-iep ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: axi ++ - const: ahb ++ ++ power-domains: ++ maxItems: 1 ++ ++ iommus: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ iep: iep@20070000 { ++ compatible = "rockchip,rk3228-iep"; ++ reg = <0x20070000 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ iommus = <&iep_mmu>; ++ power-domains = <&power RK3228_PD_VIO>; ++ }; +diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi +index cb9cdaddffd4..54bf9ae3ab4b 100644 +--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi ++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi +@@ -984,14 +984,25 @@ crypto: crypto@ff8a0000 { + reset-names = "crypto-rst"; + }; + ++ iep: iep@ff90000 { ++ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff900000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3288_PD_VIO>; ++ iommus = <&iep_mmu>; ++ }; ++ + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3288_PD_VIO>; + #iommu-cells = <0>; +- status = "disabled"; + }; + + isp_mmu: iommu@ff914000 { +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index e729e7a22b23..4e30c5279ac6 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -722,6 +722,28 @@ vop_mmu: iommu@ff373f00 { + status = "disabled"; + }; + ++ iep: iep@ff3a0000 { ++ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff3a0000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3328_PD_VIDEO>; ++ iommus = <&iep_mmu>; ++ }; ++ ++ iep_mmu: iommu@ff3a0800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff3a0800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "iep_mmu"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3328_PD_VIDEO>; ++ #iommu-cells = <0>; ++ }; ++ + hdmi: hdmi@ff3c0000 { + compatible = "rockchip,rk3328-dw-hdmi"; + reg = <0x0 0xff3c0000 0x0 0x20000>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 928948e7c7bb..63fed464a660 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1377,12 +1377,25 @@ vdec_mmu: iommu@ff660480 { + #iommu-cells = <0>; + }; + ++ ++ iep: iep@ff670000 { ++ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff670000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3399_PD_IEP>; ++ iommus = <&iep_mmu>; ++ }; ++ + iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3399_PD_IEP>; + #iommu-cells = <0>; + status = "disabled"; + }; +diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig +index b41d3960c1b4..862590be7916 100644 +--- a/drivers/media/platform/rockchip/Kconfig ++++ b/drivers/media/platform/rockchip/Kconfig +@@ -4,3 +4,4 @@ comment "Rockchip media platform drivers" + + source "drivers/media/platform/rockchip/rga/Kconfig" + source "drivers/media/platform/rockchip/rkisp1/Kconfig" ++source "drivers/media/platform/rockchip/iep/Kconfig" +diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile +index 4f782b876ac9..be8015c6d9e4 100644 +--- a/drivers/media/platform/rockchip/Makefile ++++ b/drivers/media/platform/rockchip/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-y += rga/ + obj-y += rkisp1/ ++obj-y += iep/ +diff --git a/drivers/media/platform/rockchip/iep/Kconfig b/drivers/media/platform/rockchip/iep/Kconfig +new file mode 100644 +index 000000000000..e513fa7f45f2 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/Kconfig +@@ -0,0 +1,13 @@ ++config VIDEO_ROCKCHIP_IEP ++ tristate "Rockchip Image Enhancement Processor" ++ depends on VIDEO_DEV && VIDEO_V4L2 ++ depends on ARCH_ROCKCHIP || COMPILE_TEST ++ select VIDEOBUF2_DMA_CONTIG ++ select V4L2_MEM2MEM_DEV ++ help ++ This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP) ++ found in most Rockchip RK3xxx SoCs. ++ Rockchip IEP supports various enhancement operations for RGB and YUV ++ images. The driver currently implements YUV deinterlacing only. ++ To compile this driver as a module, choose M here: the module ++ will be called rockchip-iep +diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile +new file mode 100644 +index 000000000000..5c89b3277469 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++rockchip-iep-objs := iep.o ++ ++obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o +diff --git a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/platform/rockchip/iep/iep-regs.h +new file mode 100644 +index 000000000000..a68685ef3604 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep-regs.h +@@ -0,0 +1,291 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ */ ++ ++#ifndef __IEP_REGS_H__ ++#define __IEP_REGS_H__ ++ ++/* IEP Registers addresses */ ++#define IEP_CONFIG0 0x000 /* Configuration register0 */ ++#define IEP_VOP_DIRECT_PATH BIT(0) ++#define IEP_DEIN_HIGH_FREQ_SHFT 1 ++#define IEP_DEIN_HIGH_FREQ_MASK (0x7f << IEP_DEIN_HIGH_FREQ_SHFT) ++#define IEP_DEIN_MODE_SHFT 8 ++#define IEP_DEIN_MODE_MASK (7 << IEP_DEIN_MODE_SHFT) ++#define IEP_DEIN_HIGH_FREQ_EN BIT(11) ++#define IEP_DEIN_EDGE_INTPOL_EN BIT(12) ++#define IEP_YUV_DENOISE_EN BIT(13) ++#define IEP_YUV_ENHNC_EN BIT(14) ++#define IEP_DEIN_EDGE_INTPOL_SMTH_EN BIT(15) ++#define IEP_RGB_CLR_ENHNC_EN BIT(16) ++#define IEP_RGB_CNTRST_ENHNC_EN BIT(17) ++#define IEP_RGB_ENHNC_MODE_BYPASS (0 << 18) ++#define IEP_RGB_ENHNC_MODE_DNS BIT(18) ++#define IEP_RGB_ENHNC_MODE_DTL (2 << 18) ++#define IEP_RGB_ENHNC_MODE_EDG (3 << 18) ++#define IEP_RGB_ENHNC_MODE_MASK (3 << 18) ++#define IEP_RGB_CNTRST_ENHNC_DDE_FRST BIT(20) ++#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT 21 ++#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK (3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) ++#define IEP_DEIN_EDGE_INTPOL_SELECT BIT(23) ++ ++#define IEP_CONFIG1 0x004 /* Configuration register1 */ ++#define IEP_SRC_FMT_SHFT 0 ++#define IEP_SRC_FMT_MASK (3 << IEP_SRC_FMT_SHFT) ++#define IEP_SRC_RGB_SWP_SHFT 2 ++#define IEP_SRC_RGB_SWP_MASK (2 << IEP_SRC_RGB_SWP_SHFT) ++#define IEP_SRC_YUV_SWP_SHFT 4 ++#define IEP_SRC_YUV_SWP_MASK (3 << IEP_SRC_YUV_SWP_SHFT) ++#define IEP_DST_FMT_SHFT 8 ++#define IEP_DST_FMT_MASK (3 << IEP_DST_FMT_SHFT) ++#define IEP_DST_RGB_SWP_SHFT 10 ++#define IEP_DST_RGB_SWP_MASK (2 << IEP_DST_RGB_SWP_SHFT) ++#define IEP_DST_YUV_SWP_SHFT 12 ++#define IEP_DST_YUV_SWP_MASK (3 << IEP_DST_YUV_SWP_SHFT) ++#define IEP_DTH_UP_EN BIT(14) ++#define IEP_DTH_DWN_EN BIT(15) ++#define IEP_YUV2RGB_COE_BT601_1 (0 << 16) ++#define IEP_YUV2RGB_COE_BT601_F BIT(16) ++#define IEP_YUV2RGB_COE_BT709_1 (2 << 16) ++#define IEP_YUV2RGB_COE_BT709_F (3 << 16) ++#define IEP_YUV2RGB_COE_MASK (3 << 16) ++#define IEP_RGB2YUV_COE_BT601_1 (0 << 18) ++#define IEP_RGB2YUV_COE_BT601_F BIT(18) ++#define IEP_RGB2YUV_COE_BT709_1 (2 << 18) ++#define IEP_RGB2YUV_COE_BT709_F (3 << 18) ++#define IEP_RGB2YUV_COE_MASK (3 << 18) ++#define IEP_YUV2RGB_EN BIT(20) ++#define IEP_RGB2YUV_EN BIT(21) ++#define IEP_YUV2RGB_CLIP_EN BIT(22) ++#define IEP_RGB2YUV_CLIP_EN BIT(23) ++#define IEP_GLB_ALPHA_SHFT 24 ++#define IEP_GLB_ALPHA_MASK (0x7f << IEP_GLB_ALPHA_SHFT) ++ ++#define IEP_STATUS 0x008 /* Status register */ ++#define IEP_STATUS_YUV_DNS BIT(0) ++#define IEP_STATUS_SCL BIT(1) ++#define IEP_STATUS_DIL BIT(2) ++#define IEP_STATUS_DDE BIT(3) ++#define IEP_STATUS_DMA_WR_YUV BIT(4) ++#define IEP_STATUS_DMA_RE_YUV BIT(5) ++#define IEP_STATUS_DMA_WR_RGB BIT(6) ++#define IEP_STATUS_DMA_RE_RGB BIT(7) ++#define IEP_STATUS_VOP_DIRECT_PATH BIT(8) ++#define IEP_STATUS_DMA_IA_WR_YUV BIT(16) ++#define IEP_STATUS_DMA_IA_RE_YUV BIT(17) ++#define IEP_STATUS_DMA_IA_WR_RGB BIT(18) ++#define IEP_STATUS_DMA_IA_RE_RGB BIT(19) ++ ++#define IEP_INT 0x00c /* Interrupt register*/ ++#define IEP_INT_FRAME_DONE BIT(0) /* Frame process done interrupt */ ++#define IEP_INT_FRAME_DONE_EN BIT(8) /* Frame process done interrupt enable */ ++#define IEP_INT_FRAME_DONE_CLR BIT(16) /* Frame process done interrupt clear */ ++ ++#define IEP_FRM_START 0x010 /* Frame start */ ++#define IEP_SRST 0x014 /* Soft reset */ ++#define IEP_CONFIG_DONE 0x018 /* Configuration done */ ++#define IEP_FRM_CNT 0x01c /* Frame counter */ ++ ++#define IEP_VIR_IMG_WIDTH 0x020 /* Image virtual width */ ++#define IEP_IMG_SCL_FCT 0x024 /* Scaling factor */ ++#define IEP_SRC_IMG_SIZE 0x028 /* src image width/height */ ++#define IEP_DST_IMG_SIZE 0x02c /* dst image width/height */ ++#define IEP_DST_IMG_WIDTH_TILE0 0x030 /* dst image tile0 width */ ++#define IEP_DST_IMG_WIDTH_TILE1 0x034 /* dst image tile1 width */ ++#define IEP_DST_IMG_WIDTH_TILE2 0x038 /* dst image tile2 width */ ++#define IEP_DST_IMG_WIDTH_TILE3 0x03c /* dst image tile3 width */ ++ ++#define IEP_ENH_YUV_CNFG_0 0x040 /* Brightness, contrast, saturation adjustment */ ++#define IEP_YUV_BRIGHTNESS_SHFT 0 ++#define IEP_YUV_BRIGHTNESS_MASK (0x3f << IEP_YUV_BRIGHTNESS_SHFT) ++#define IEP_YUV_CONTRAST_SHFT 8 ++#define IEP_YUV_CONTRAST_MASK (0xff << IEP_YUV_CONTRAST_SHFT) ++#define IEP_YUV_SATURATION_SHFT 16 ++#define IEP_YUV_SATURATION_MASK (0x1ff << IEP_YUV_SATURATION_SHFT) ++ ++#define IEP_ENH_YUV_CNFG_1 0x044 /* Hue configuration */ ++#define IEP_YUV_COS_HUE_SHFT 0 ++#define IEP_YUV_COS_HUE_MASK (0xff << IEP_YUV_COS_HUE_SHFT) ++#define IEP_YUV_SIN_HUE_SHFT 8 ++#define IEP_YUV_SIN_HUE_MASK (0xff << IEP_YUV_SIN_HUE_SHFT) ++ ++#define IEP_ENH_YUV_CNFG_2 0x048 /* Color bar configuration */ ++#define IEP_YUV_COLOR_BAR_Y_SHFT 0 ++#define IEP_YUV_COLOR_BAR_Y_MASK (0xff << IEP_YUV_COLOR_BAR_Y_SHFT) ++#define IEP_YUV_COLOR_BAR_U_SHFT 8 ++#define IEP_YUV_COLOR_BAR_U_MASK (0xff << IEP_YUV_COLOR_BAR_U_SHFT) ++#define IEP_YUV_COLOR_BAR_V_SHFT 16 ++#define IEP_YUV_COLOR_BAR_V_MASK (0xff << IEP_YUV_COLOR_BAR_V_SHFT) ++#define IEP_YUV_VIDEO_MODE_SHFT 24 ++#define IEP_YUV_VIDEO_MODE_MASK (3 << IEP_YUV_VIDEO_MODE_SHFT) ++ ++#define IEP_ENH_RGB_CNFG 0x04c /* RGB enhancement configuration */ ++#define IEP_ENH_RGB_C_COE 0x050 /* RGB color enhancement coefficient */ ++ ++#define IEP_RAW_CONFIG0 0x058 /* Raw configuration register0 */ ++#define IEP_RAW_CONFIG1 0x05c /* Raw configuration register1 */ ++#define IEP_RAW_VIR_IMG_WIDTH 0x060 /* Raw image virtual width */ ++#define IEP_RAW_IMG_SCL_FCT 0x064 /* Raw scaling factor */ ++#define IEP_RAW_SRC_IMG_SIZE 0x068 /* Raw src image width/height */ ++#define IEP_RAW_DST_IMG_SIZE 0x06c /* Raw src image width/height */ ++#define IEP_RAW_ENH_YUV_CNFG_0 0x070 /* Raw brightness,contrast,saturation adjustment */ ++#define IEP_RAW_ENH_YUV_CNFG_1 0x074 /* Raw hue configuration */ ++#define IEP_RAW_ENH_YUV_CNFG_2 0x078 /* Raw color bar configuration */ ++#define IEP_RAW_ENH_RGB_CNFG 0x07c /* Raw RGB enhancement configuration */ ++ ++#define IEP_SRC_ADDR_Y_RGB 0x080 /* Start addr. of src image 0 (Y/RGB) */ ++#define IEP_SRC_ADDR_CBCR 0x084 /* Start addr. of src image 0 (Cb/Cr) */ ++#define IEP_SRC_ADDR_CR 0x088 /* Start addr. of src image 0 (Cr) */ ++#define IEP_SRC_ADDR_Y1 0x08c /* Start addr. of src image 1 (Y) */ ++#define IEP_SRC_ADDR_CBCR1 0x090 /* Start addr. of src image 1 (Cb/Cr) */ ++#define IEP_SRC_ADDR_CR1 0x094 /* Start addr. of src image 1 (Cr) */ ++#define IEP_SRC_ADDR_Y_ITEMP 0x098 /* Start addr. of src image(Y int part) */ ++#define IEP_SRC_ADDR_CBCR_ITEMP 0x09c /* Start addr. of src image(CBCR int part) */ ++#define IEP_SRC_ADDR_CR_ITEMP 0x0a0 /* Start addr. of src image(CR int part) */ ++#define IEP_SRC_ADDR_Y_FTEMP 0x0a4 /* Start addr. of src image(Y frac part) */ ++#define IEP_SRC_ADDR_CBCR_FTEMP 0x0a8 /* Start addr. of src image(CBCR frac part) */ ++#define IEP_SRC_ADDR_CR_FTEMP 0x0ac /* Start addr. of src image(CR frac part) */ ++ ++#define IEP_DST_ADDR_Y_RGB 0x0b0 /* Start addr. of dst image 0 (Y/RGB) */ ++#define IEP_DST_ADDR_CBCR 0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */ ++#define IEP_DST_ADDR_CR 0x0b8 /* Start addr. of dst image 0 (Cr) */ ++#define IEP_DST_ADDR_Y1 0x0bc /* Start addr. of dst image 1 (Y) */ ++#define IEP_DST_ADDR_CBCR1 0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */ ++#define IEP_DST_ADDR_CR1 0x0c4 /* Start addr. of dst image 1 (Cr) */ ++#define IEP_DST_ADDR_Y_ITEMP 0x0c8 /* Start addr. of dst image(Y int part) */ ++#define IEP_DST_ADDR_CBCR_ITEMP 0x0cc /* Start addr. of dst image(CBCR int part)*/ ++#define IEP_DST_ADDR_CR_ITEMP 0x0d0 /* Start addr. of dst image(CR int part) */ ++#define IEP_DST_ADDR_Y_FTEMP 0x0d4 /* Start addr. of dst image(Y frac part) */ ++#define IEP_DST_ADDR_CBCR_FTEMP 0x0d8 /* Start addr. of dst image(CBCR frac part) */ ++#define IEP_DST_ADDR_CR_FTEMP 0x0dc /* Start addr. of dst image(CR frac part)*/ ++ ++#define IEP_DEIN_MTN_TAB0 0x0e0 /* Deinterlace motion table0 */ ++#define IEP_DEIN_MTN_TAB1 0x0e4 /* Deinterlace motion table1 */ ++#define IEP_DEIN_MTN_TAB2 0x0e8 /* Deinterlace motion table2 */ ++#define IEP_DEIN_MTN_TAB3 0x0ec /* Deinterlace motion table3 */ ++#define IEP_DEIN_MTN_TAB4 0x0f0 /* Deinterlace motion table4 */ ++#define IEP_DEIN_MTN_TAB5 0x0f4 /* Deinterlace motion table5 */ ++#define IEP_DEIN_MTN_TAB6 0x0f8 /* Deinterlace motion table6 */ ++#define IEP_DEIN_MTN_TAB7 0x0fc /* Deinterlace motion table7 */ ++ ++#define IEP_ENH_CG_TAB 0x100 /* Contrast and gamma enhancement table */ ++#define IEP_ENH_DDE_COE0 0x400 /* Denoise,detail and edge enhancement coefficient */ ++#define IEP_ENH_DDE_COE1 0x500 /* Denoise,detail and edge enhancement coefficient1 */ ++ ++#define IEP_INT_MASK (IEP_INT_FRAME_DONE) ++ ++/* IEP colorformats */ ++#define IEP_COLOR_FMT_XRGB 0U ++#define IEP_COLOR_FMT_RGB565 1U ++#define IEP_COLOR_FMT_YUV422 2U ++#define IEP_COLOR_FMT_YUV420 3U ++ ++/* IEP YUV color swaps */ ++#define IEP_YUV_SWP_SP_UV 0U ++#define IEP_YUV_SWP_SP_VU 1U ++#define IEP_YUV_SWP_P 2U ++ ++/* IEP XRGB color swaps */ ++#define XRGB_SWP_XRGB 0U ++#define XRGB_SWP_XBGR 1U ++#define XRGB_SWP_BGRX 2U ++ ++/* IEP RGB565 color swaps */ ++#define RGB565_SWP_RGB 0U ++#define RGB565_SWP_BGR 1U ++ ++#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1) ++ ++#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \ ++ ((h - 1) & 0x1fff) << 16) ++ ++#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \ ++ ((dst_w / 4) & 0x1fff) << 16) ++ ++#define IEP_Y_STRIDE(w, h) (w * h) ++#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac) ++ ++#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK) ++#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK) ++ ++#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \ ++ (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT))) ++#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \ ++ (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT))) ++ ++/* IEP DEINTERLACE MODES */ ++#define IEP_DEIN_MODE_YUV 0U ++#define IEP_DEIN_MODE_I4O2 1U ++#define IEP_DEIN_MODE_I4O1B 2U ++#define IEP_DEIN_MODE_I4O1T 3U ++#define IEP_DEIN_MODE_I2O1B 4U ++#define IEP_DEIN_MODE_I2O1T 5U ++#define IEP_DEIN_MODE_BYPASS 6U ++ ++#define IEP_DEIN_IN_FIELDS_2 2U ++#define IEP_DEIN_IN_FIELDS_4 4U ++ ++#define IEP_DEIN_OUT_FRAMES_1 1U ++#define IEP_DEIN_OUT_FRAMES_2 2U ++ ++/* values taken from BSP driver */ ++static const u32 default_dein_motion_tbl[][2] = { ++ { IEP_DEIN_MTN_TAB0, 0x40404040 }, ++ { IEP_DEIN_MTN_TAB1, 0x3c3e3f3f }, ++ { IEP_DEIN_MTN_TAB2, 0x3336393b }, ++ { IEP_DEIN_MTN_TAB3, 0x272a2d31 }, ++ { IEP_DEIN_MTN_TAB4, 0x181c2023 }, ++ { IEP_DEIN_MTN_TAB5, 0x0c0e1215 }, ++ { IEP_DEIN_MTN_TAB6, 0x03040609 }, ++ { IEP_DEIN_MTN_TAB7, 0x00000001 }, ++ ++}; ++ ++#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1) ++#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1) ++#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1) ++#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff)) ++#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff)) ++#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff)) ++ ++#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB) ++#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR) ++#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR) ++#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff)) ++#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff)) ++#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff)) ++ ++#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT) ++ ++#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \ ++ || m == IEP_DEIN_MODE_I4O2) \ ++ ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2) ++ ++#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \ ++ ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1) ++ ++#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \ ++ ? 1 : 0) ++ ++#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) ++ ++#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT) ++ ++/* YUV Enhance video modes */ ++#define VIDEO_MODE_BLACK_SCREEN 0U ++#define VIDEO_MODE_BLUE_SCREEN 1U ++#define VIDEO_MODE_COLOR_BARS 2U ++#define VIDEO_MODE_NORMAL_VIDEO 3U ++ ++#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK) ++#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK) ++#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK) ++#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK) ++#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK) ++#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK) ++ ++#endif +diff --git a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c +new file mode 100644 +index 000000000000..f4b9320733be +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep.c +@@ -0,0 +1,1089 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ * Based on Allwinner sun8i deinterlacer with scaler driver ++ * Copyright (C) 2019 Jernej Skrabec ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "iep-regs.h" ++#include "iep.h" ++ ++static struct iep_fmt formats[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_NV12, ++ .color_swap = IEP_YUV_SWP_SP_UV, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV21, ++ .color_swap = IEP_YUV_SWP_SP_VU, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV16, ++ .color_swap = IEP_YUV_SWP_SP_UV, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV61, ++ .color_swap = IEP_YUV_SWP_SP_VU, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV420, ++ .color_swap = IEP_YUV_SWP_P, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV422P, ++ .color_swap = IEP_YUV_SWP_P, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++}; ++ ++static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) { ++ if (formats[i].fourcc == pix_fmt->pixelformat) ++ return &formats[i]; ++ } ++ ++ return NULL; ++} ++ ++static bool iep_check_pix_format(u32 pixelformat) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) ++ if (formats[i].fourcc == pixelformat) ++ return true; ++ ++ return false; ++} ++ ++static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx) ++{ ++ struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); ++ ++ /* application has set a dst sequence: take it as start point */ ++ if (ctx->dst_sequence == 0 && dst_buf->sequence > 0) ++ ctx->dst_sequence = dst_buf->sequence; ++ ++ dst_buf->sequence = ctx->dst_sequence++; ++ ++ return dst_buf; ++} ++ ++static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state) ++{ ++ if (ctx->dst0_buf) { ++ v4l2_m2m_buf_done(ctx->dst0_buf, state); ++ ctx->dst_buffs_done++; ++ ctx->dst0_buf = NULL; ++ } ++ ++ if (ctx->dst1_buf) { ++ v4l2_m2m_buf_done(ctx->dst1_buf, state); ++ ctx->dst_buffs_done++; ++ ctx->dst1_buf = NULL; ++ } ++} ++ ++static void iep_setup_formats(struct iep_ctx *ctx) ++{ ++ /* setup src dimensions */ ++ iep_write(ctx->iep, IEP_SRC_IMG_SIZE, ++ IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height)); ++ ++ /* setup dst dimensions */ ++ iep_write(ctx->iep, IEP_DST_IMG_SIZE, ++ IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height)); ++ ++ /* setup virtual width */ ++ iep_write(ctx->iep, IEP_VIR_IMG_WIDTH, ++ IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width)); ++ ++ /* setup src format */ ++ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, ++ IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format), ++ IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format, ++ ctx->src_fmt.hw_fmt->color_swap)); ++ /* setup dst format */ ++ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, ++ IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format), ++ IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format, ++ ctx->dst_fmt.hw_fmt->color_swap)); ++ ++ ctx->fmt_changed = false; ++} ++ ++static void iep_dein_init(struct rockchip_iep *iep) ++{ ++ unsigned int i; ++ ++ /* values taken from BSP driver */ ++ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, ++ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | ++ IEP_DEIN_EDGE_INTPOL_RADIUS_MASK | ++ IEP_DEIN_HIGH_FREQ_EN | ++ IEP_DEIN_HIGH_FREQ_MASK), ++ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | ++ IEP_DEIN_EDGE_INTPOL_RADIUS(3) | ++ IEP_DEIN_HIGH_FREQ_EN | ++ IEP_DEIN_HIGH_FREQ(64))); ++ ++ for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++) ++ iep_write(iep, default_dein_motion_tbl[i][0], ++ default_dein_motion_tbl[i][1]); ++} ++ ++static void iep_init(struct rockchip_iep *iep) ++{ ++ iep_write(iep, IEP_CONFIG0, ++ IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // | ++ //IEP_YUV_ENHNC_EN ++ ); ++ ++ /* TODO: B/S/C/H works ++ * only in 1-frame-out modes ++ iep_write(iep, IEP_ENH_YUV_CNFG_0, ++ YUV_BRIGHTNESS(0) | ++ YUV_CONTRAST(128) | ++ YUV_SATURATION(128)); ++ ++ iep_write(iep, IEP_ENH_YUV_CNFG_1, ++ YUV_COS_HUE(255) | ++ YUV_SIN_HUE(255)); ++ ++ iep_write(iep, IEP_ENH_YUV_CNFG_2, ++ YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO)); ++ ++ */ ++ ++ /* reset frame counter */ ++ iep_write(iep, IEP_FRM_CNT, 0); ++} ++ ++static void iep_device_run(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ struct rockchip_iep *iep = ctx->iep; ++ struct vb2_v4l2_buffer *src, *dst; ++ unsigned int dein_mode; ++ dma_addr_t addr; ++ ++ if (ctx->fmt_changed) ++ iep_setup_formats(ctx); ++ ++ if (ctx->prev_src_buf) ++ dein_mode = IEP_DEIN_MODE_I4O2; ++ else ++ dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T; ++ ++ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, ++ IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode)); ++ ++ /* sync RAW_xxx registers with actual used */ ++ iep_write(iep, IEP_CONFIG_DONE, 1); ++ ++ /* setup src buff(s)/addresses */ ++ src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff), ++ addr + ctx->src_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff), ++ addr + ctx->src_fmt.uv_stride); ++ ++ if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4) ++ addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff), ++ addr + ctx->src_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff), ++ addr + ctx->src_fmt.uv_stride); ++ ++ /* setup dst buff(s)/addresses */ ++ dst = iep_m2m_next_dst_buf(ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); ++ ++ if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) { ++ v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff), ++ addr + ctx->dst_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff), ++ addr + ctx->dst_fmt.uv_stride); ++ ++ ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ dst = iep_m2m_next_dst_buf(ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); ++ } ++ ++ v4l2_m2m_buf_copy_metadata(src, dst, true); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff), ++ addr + ctx->dst_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff), ++ addr + ctx->dst_fmt.uv_stride); ++ ++ ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN, ++ IEP_INT_FRAME_DONE_EN); ++ ++ /* start HW */ ++ iep_write(iep, IEP_FRM_START, 1); ++} ++ ++static int iep_job_ready(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ ++ return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 && ++ v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1; ++} ++ ++static void iep_job_abort(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ ++ /* Will cancel the transaction in the next interrupt handler */ ++ ctx->job_abort = true; ++} ++ ++static const struct v4l2_m2m_ops iep_m2m_ops = { ++ .device_run = iep_device_run, ++ .job_ready = iep_job_ready, ++ .job_abort = iep_job_abort, ++}; ++ ++static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, ++ unsigned int *nplanes, unsigned int sizes[], ++ struct device *alloc_devs[]) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt.pix; ++ else ++ pix_fmt = &ctx->dst_fmt.pix; ++ ++ if (*nplanes) { ++ if (sizes[0] < pix_fmt->sizeimage) ++ return -EINVAL; ++ } else { ++ sizes[0] = pix_fmt->sizeimage; ++ *nplanes = 1; ++ } ++ ++ return 0; ++} ++ ++static int iep_buf_prepare(struct vb2_buffer *vb) ++{ ++ struct vb2_queue *vq = vb->vb2_queue; ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt.pix; ++ else ++ pix_fmt = &ctx->dst_fmt.pix; ++ ++ if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage) ++ return -EINVAL; ++ ++ /* set bytesused for capture buffers */ ++ if (!V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage); ++ ++ return 0; ++} ++ ++static void iep_buf_queue(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); ++ ++ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); ++} ++ ++static void iep_queue_cleanup(struct vb2_queue *vq, u32 state) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct vb2_v4l2_buffer *vbuf; ++ ++ do { ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ else ++ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ if (vbuf) ++ v4l2_m2m_buf_done(vbuf, state); ++ } while (vbuf); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf) ++ v4l2_m2m_buf_done(ctx->prev_src_buf, state); ++ else ++ iep_m2m_dst_bufs_done(ctx, state); ++} ++ ++static int iep_start_streaming(struct vb2_queue *vq, unsigned int count) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct device *dev = ctx->iep->dev; ++ int ret; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ ret = pm_runtime_get_sync(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to enable module\n"); ++ goto err_runtime_get; ++ } ++ ++ ctx->field_order_bff = ++ ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT; ++ ctx->field_bff = ctx->field_order_bff; ++ ++ ctx->src_sequence = 0; ++ ctx->dst_sequence = 0; ++ ++ ctx->prev_src_buf = NULL; ++ ++ ctx->dst0_buf = NULL; ++ ctx->dst1_buf = NULL; ++ ctx->dst_buffs_done = 0; ++ ++ ctx->job_abort = false; ++ ++ iep_init(ctx->iep); ++ //if (ctx->src_fmt.pix.field != ctx->dst_fmt.pix.field) ++ iep_dein_init(ctx->iep); ++ } ++ ++ return 0; ++ ++err_runtime_get: ++ iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED); ++ ++ return ret; ++} ++ ++static void iep_stop_streaming(struct vb2_queue *vq) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ pm_runtime_mark_last_busy(ctx->iep->dev); ++ pm_runtime_put_autosuspend(ctx->iep->dev); ++ } ++ ++ iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR); ++} ++ ++static const struct vb2_ops iep_qops = { ++ .queue_setup = iep_queue_setup, ++ .buf_prepare = iep_buf_prepare, ++ .buf_queue = iep_buf_queue, ++ .start_streaming = iep_start_streaming, ++ .stop_streaming = iep_stop_streaming, ++ .wait_prepare = vb2_ops_wait_prepare, ++ .wait_finish = vb2_ops_wait_finish, ++}; ++ ++static int iep_queue_init(void *priv, struct vb2_queue *src_vq, ++ struct vb2_queue *dst_vq) ++{ ++ struct iep_ctx *ctx = priv; ++ int ret; ++ ++ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; ++ src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | ++ DMA_ATTR_NO_KERNEL_MAPPING; ++ src_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ src_vq->drv_priv = ctx; ++ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ src_vq->min_buffers_needed = 1; ++ src_vq->ops = &iep_qops; ++ src_vq->mem_ops = &vb2_dma_contig_memops; ++ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ src_vq->lock = &ctx->iep->mutex; ++ src_vq->dev = ctx->iep->v4l2_dev.dev; ++ ++ ret = vb2_queue_init(src_vq); ++ if (ret) ++ return ret; ++ ++ dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | ++ DMA_ATTR_NO_KERNEL_MAPPING; ++ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ dst_vq->drv_priv = ctx; ++ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ dst_vq->min_buffers_needed = 2; ++ dst_vq->ops = &iep_qops; ++ dst_vq->mem_ops = &vb2_dma_contig_memops; ++ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ dst_vq->lock = &ctx->iep->mutex; ++ dst_vq->dev = ctx->iep->v4l2_dev.dev; ++ ++ ret = vb2_queue_init(dst_vq); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void iep_prepare_format(struct v4l2_pix_format *pix_fmt) ++{ ++ unsigned int height = pix_fmt->height; ++ unsigned int width = pix_fmt->width; ++ unsigned int sizeimage, bytesperline; ++ ++ struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt); ++ ++ if (!hw_fmt) { ++ hw_fmt = &formats[0]; ++ pix_fmt->pixelformat = hw_fmt->fourcc; ++ } ++ ++ width = ALIGN(clamp(width, IEP_MIN_WIDTH, ++ IEP_MAX_WIDTH), 16); ++ height = ALIGN(clamp(height, IEP_MIN_HEIGHT, ++ IEP_MAX_HEIGHT), 16); ++ ++ bytesperline = FMT_IS_YUV(hw_fmt->hw_format) ++ ? width : (width * hw_fmt->depth) >> 3; ++ ++ sizeimage = height * (width * hw_fmt->depth) >> 3; ++ ++ pix_fmt->width = width; ++ pix_fmt->height = height; ++ pix_fmt->bytesperline = bytesperline; ++ pix_fmt->sizeimage = sizeimage; ++} ++ ++static int iep_open(struct file *file) ++{ ++ struct rockchip_iep *iep = video_drvdata(file); ++ struct iep_ctx *ctx = NULL; ++ ++ int ret; ++ ++ if (mutex_lock_interruptible(&iep->mutex)) ++ return -ERESTARTSYS; ++ ++ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); ++ if (!ctx) { ++ mutex_unlock(&iep->mutex); ++ return -ENOMEM; ++ } ++ ++ /* default output format */ ++ ctx->src_fmt.pix.pixelformat = formats[0].fourcc; ++ ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED; ++ ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH; ++ ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT; ++ iep_prepare_format(&ctx->src_fmt.pix); ++ ctx->src_fmt.hw_fmt = &formats[0]; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height, ++ ctx->src_fmt.hw_fmt->uv_factor); ++ ++ /* default capture format */ ++ ctx->dst_fmt.pix.pixelformat = formats[0].fourcc; ++ ctx->dst_fmt.pix.field = V4L2_FIELD_NONE; ++ ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH; ++ ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT; ++ iep_prepare_format(&ctx->dst_fmt.pix); ++ ctx->dst_fmt.hw_fmt = &formats[0]; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ /* ensure fmts are written to HW */ ++ ctx->fmt_changed = true; ++ ++ v4l2_fh_init(&ctx->fh, video_devdata(file)); ++ file->private_data = &ctx->fh; ++ ctx->iep = iep; ++ ++ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx, ++ &iep_queue_init); ++ ++ if (IS_ERR(ctx->fh.m2m_ctx)) { ++ ret = PTR_ERR(ctx->fh.m2m_ctx); ++ goto err_free; ++ } ++ ++ v4l2_fh_add(&ctx->fh); ++ ++ mutex_unlock(&iep->mutex); ++ ++ return 0; ++ ++err_free: ++ kfree(ctx); ++ mutex_unlock(&iep->mutex); ++ ++ return ret; ++} ++ ++static int iep_release(struct file *file) ++{ ++ struct rockchip_iep *iep = video_drvdata(file); ++ struct iep_ctx *ctx = container_of(file->private_data, ++ struct iep_ctx, fh); ++ ++ mutex_lock(&iep->mutex); ++ ++ v4l2_fh_del(&ctx->fh); ++ v4l2_fh_exit(&ctx->fh); ++ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); ++ kfree(ctx); ++ ++ mutex_unlock(&iep->mutex); ++ return 0; ++} ++ ++static const struct v4l2_file_operations iep_fops = { ++ .owner = THIS_MODULE, ++ .open = iep_open, ++ .release = iep_release, ++ .poll = v4l2_m2m_fop_poll, ++ .unlocked_ioctl = video_ioctl2, ++ .mmap = v4l2_m2m_fop_mmap, ++}; ++ ++static int iep_querycap(struct file *file, void *priv, ++ struct v4l2_capability *cap) ++{ ++ strscpy(cap->driver, IEP_NAME, sizeof(cap->driver)); ++ strscpy(cap->card, IEP_NAME, sizeof(cap->card)); ++ snprintf(cap->bus_info, sizeof(cap->bus_info), ++ "platform:%s", IEP_NAME); ++ ++ return 0; ++} ++ ++static int iep_enum_fmt(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ struct iep_fmt *fmt; ++ ++ if (f->index < ARRAY_SIZE(formats)) { ++ fmt = &formats[f->index]; ++ f->pixelformat = fmt->fourcc; ++ ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int iep_enum_framesizes(struct file *file, void *priv, ++ struct v4l2_frmsizeenum *fsize) ++{ ++ if (fsize->index != 0) ++ return -EINVAL; ++ ++ if (!iep_check_pix_format(fsize->pixel_format)) ++ return -EINVAL; ++ ++ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; ++ ++ fsize->stepwise.min_width = IEP_MIN_WIDTH; ++ fsize->stepwise.max_width = IEP_MAX_WIDTH; ++ fsize->stepwise.step_width = 16; ++ ++ fsize->stepwise.min_height = IEP_MIN_HEIGHT; ++ fsize->stepwise.max_height = IEP_MAX_HEIGHT; ++ fsize->stepwise.step_height = 16; ++ ++ return 0; ++} ++ ++static inline struct iep_ctx *iep_file2ctx(struct file *file) ++{ ++ return container_of(file->private_data, struct iep_ctx, fh); ++} ++ ++static int iep_g_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ ++ f->fmt.pix = ctx->dst_fmt.pix; ++ ++ return 0; ++} ++ ++static int iep_g_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ ++ f->fmt.pix = ctx->src_fmt.pix; ++ ++ return 0; ++} ++ ++static int iep_try_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ f->fmt.pix.field = V4L2_FIELD_NONE; ++ iep_prepare_format(&f->fmt.pix); ++ ++ return 0; ++} ++ ++static int iep_try_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED) ++ f->fmt.pix.field = V4L2_FIELD_INTERLACED; ++ ++ iep_prepare_format(&f->fmt.pix); ++ ++ return 0; ++} ++ ++static int iep_s_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ struct vb2_queue *vq; ++ ++ int ret; ++ ++ ret = iep_try_fmt_vid_out(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ ctx->src_fmt.pix = f->fmt.pix; ++ ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); ++ ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->src_fmt.hw_fmt->uv_factor); ++ ++ /* Propagate colorspace information to capture. */ ++ ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace; ++ ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func; ++ ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc; ++ ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization; ++ ++ /* scaling is not supported */ ++ ctx->dst_fmt.pix.width = f->fmt.pix.width; ++ ctx->dst_fmt.pix.height = f->fmt.pix.height; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ ++ ctx->fmt_changed = true; ++ ++ return 0; ++} ++ ++static int iep_s_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ struct vb2_queue *vq; ++ int ret; ++ ++ ret = iep_try_fmt_vid_cap(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ /* scaling is not supported */ ++ f->fmt.pix.width = ctx->src_fmt.pix.width; ++ f->fmt.pix.height = ctx->src_fmt.pix.height; ++ ++ ctx->dst_fmt.pix = f->fmt.pix; ++ ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); ++ ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ ++ ctx->fmt_changed = true; ++ ++ return 0; ++} ++ ++static const struct v4l2_ioctl_ops iep_ioctl_ops = { ++ .vidioc_querycap = iep_querycap, ++ ++ .vidioc_enum_framesizes = iep_enum_framesizes, ++ ++ .vidioc_enum_fmt_vid_cap = iep_enum_fmt, ++ .vidioc_g_fmt_vid_cap = iep_g_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = iep_try_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = iep_s_fmt_vid_cap, ++ ++ .vidioc_enum_fmt_vid_out = iep_enum_fmt, ++ .vidioc_g_fmt_vid_out = iep_g_fmt_vid_out, ++ .vidioc_try_fmt_vid_out = iep_try_fmt_vid_out, ++ .vidioc_s_fmt_vid_out = iep_s_fmt_vid_out, ++ ++ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, ++ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, ++ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, ++ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, ++ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, ++ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, ++ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, ++ ++ .vidioc_streamon = v4l2_m2m_ioctl_streamon, ++ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, ++}; ++ ++static const struct video_device iep_video_device = { ++ .name = IEP_NAME, ++ .vfl_dir = VFL_DIR_M2M, ++ .fops = &iep_fops, ++ .ioctl_ops = &iep_ioctl_ops, ++ .minor = -1, ++ .release = video_device_release_empty, ++ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, ++}; ++ ++static int iep_parse_dt(struct rockchip_iep *iep) ++{ ++ int ret = 0; ++ ++ iep->axi_clk = devm_clk_get(iep->dev, "axi"); ++ if (IS_ERR(iep->axi_clk)) { ++ dev_err(iep->dev, "failed to get aclk clock\n"); ++ return PTR_ERR(iep->axi_clk); ++ } ++ ++ iep->ahb_clk = devm_clk_get(iep->dev, "ahb"); ++ if (IS_ERR(iep->ahb_clk)) { ++ dev_err(iep->dev, "failed to get hclk clock\n"); ++ return PTR_ERR(iep->ahb_clk); ++ } ++ ++ ret = clk_set_rate(iep->axi_clk, 300000000); ++ ++ if (ret) ++ dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n"); ++ ++ return ret; ++} ++ ++static irqreturn_t iep_isr(int irq, void *prv) ++{ ++ struct rockchip_iep *iep = prv; ++ struct iep_ctx *ctx; ++ u32 val; ++ enum vb2_buffer_state state = VB2_BUF_STATE_DONE; ++ ++ ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev); ++ if (!ctx) { ++ v4l2_err(&iep->v4l2_dev, ++ "Instance released before the end of transaction\n"); ++ return IRQ_NONE; ++ } ++ ++ /* ++ * The irq is shared with the iommu. If the runtime-pm state of the ++ * iep-device is disabled or the interrupt status doesn't match the ++ * expeceted mask the irq has been targeted to the iommu. ++ */ ++ ++ if (!pm_runtime_active(iep->dev) || ++ !(iep_read(iep, IEP_INT) & IEP_INT_MASK)) ++ return IRQ_NONE; ++ ++ /* disable interrupt - will be re-enabled at next iep_device_run */ ++ iep_mod(ctx->iep, IEP_INT, ++ IEP_INT_FRAME_DONE_EN, 0); ++ ++ iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR, ++ IEP_INT_FRAME_DONE_CLR); ++ ++ /* wait for all status regs to show "idle" */ ++ val = readl_poll_timeout(iep->regs + IEP_STATUS, val, ++ (val == 0), 100, IEP_TIMEOUT); ++ ++ if (val) { ++ dev_err(iep->dev, ++ "Failed to wait for job to finish: status: %u\n", val); ++ state = VB2_BUF_STATE_ERROR; ++ ctx->job_abort = true; ++ } ++ ++ iep_m2m_dst_bufs_done(ctx, state); ++ ++ ctx->field_bff = (ctx->dst_buffs_done % 2 == 0) ++ ? ctx->field_order_bff : !ctx->field_order_bff; ++ ++ if (ctx->dst_buffs_done == 2 || ctx->job_abort) { ++ if (ctx->prev_src_buf) ++ v4l2_m2m_buf_done(ctx->prev_src_buf, state); ++ ++ /* current src buff will be next prev */ ++ ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ ++ v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx); ++ ctx->dst_buffs_done = 0; ++ ++ } else { ++ iep_device_run(ctx); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int iep_probe(struct platform_device *pdev) ++{ ++ struct rockchip_iep *iep; ++ struct video_device *vfd; ++ struct resource *res; ++ int ret = 0; ++ int irq; ++ ++ if (!pdev->dev.of_node) ++ return -ENODEV; ++ ++ iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL); ++ if (!iep) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, iep); ++ iep->dev = &pdev->dev; ++ iep->vfd = iep_video_device; ++ ++ ret = iep_parse_dt(iep); ++ if (ret) ++ dev_err(&pdev->dev, "Unable to parse OF data\n"); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ iep->regs = devm_ioremap_resource(iep->dev, res); ++ if (IS_ERR(iep->regs)) { ++ ret = PTR_ERR(iep->regs); ++ goto err_put_clk; ++ } ++ ++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n"); ++ goto err_put_clk; ++ } ++ ++ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ ret = irq; ++ goto err_put_clk; ++ } ++ ++ /* IRQ is shared with IOMMU */ ++ ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED, ++ dev_name(iep->dev), iep); ++ if (ret < 0) { ++ dev_err(iep->dev, "failed to request irq\n"); ++ goto err_put_clk; ++ } ++ ++ mutex_init(&iep->mutex); ++ ++ ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev); ++ if (ret) { ++ dev_err(iep->dev, "Failed to register V4L2 device\n"); ++ ++ return ret; ++ } ++ ++ vfd = &iep->vfd; ++ vfd->lock = &iep->mutex; ++ vfd->v4l2_dev = &iep->v4l2_dev; ++ ++ snprintf(vfd->name, sizeof(vfd->name), "%s", ++ iep_video_device.name); ++ ++ video_set_drvdata(vfd, iep); ++ ++ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); ++ if (ret) { ++ v4l2_err(&iep->v4l2_dev, "Failed to register video device\n"); ++ ++ goto err_v4l2; ++ } ++ ++ v4l2_info(&iep->v4l2_dev, ++ "Device %s registered as /dev/video%d\n", vfd->name, vfd->num); ++ ++ iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops); ++ if (IS_ERR(iep->m2m_dev)) { ++ v4l2_err(&iep->v4l2_dev, ++ "Failed to initialize V4L2 M2M device\n"); ++ ret = PTR_ERR(iep->m2m_dev); ++ ++ goto err_video; ++ } ++ ++ pm_runtime_set_autosuspend_delay(iep->dev, 100); ++ pm_runtime_use_autosuspend(iep->dev); ++ pm_runtime_enable(iep->dev); ++ ++ return ret; ++ ++err_video: ++ video_unregister_device(&iep->vfd); ++err_v4l2: ++ v4l2_device_unregister(&iep->v4l2_dev); ++err_put_clk: ++ pm_runtime_dont_use_autosuspend(iep->dev); ++ pm_runtime_disable(iep->dev); ++ ++return ret; ++} ++ ++static int iep_remove(struct platform_device *pdev) ++{ ++ struct rockchip_iep *iep = platform_get_drvdata(pdev); ++ ++ pm_runtime_dont_use_autosuspend(iep->dev); ++ pm_runtime_disable(iep->dev); ++ ++ v4l2_m2m_release(iep->m2m_dev); ++ video_unregister_device(&iep->vfd); ++ v4l2_device_unregister(&iep->v4l2_dev); ++ ++ return 0; ++} ++ ++static int __maybe_unused iep_runtime_suspend(struct device *dev) ++{ ++ struct rockchip_iep *iep = dev_get_drvdata(dev); ++ ++ clk_disable_unprepare(iep->ahb_clk); ++ clk_disable_unprepare(iep->axi_clk); ++ ++ return 0; ++} ++ ++static int __maybe_unused iep_runtime_resume(struct device *dev) ++{ ++ struct rockchip_iep *iep; ++ int ret = 0; ++ ++ iep = dev_get_drvdata(dev); ++ ++ ret = clk_prepare_enable(iep->axi_clk); ++ if (ret) { ++ dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(iep->ahb_clk); ++ if (ret) { ++ dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret); ++ goto err_disable_axi_clk; ++ } ++ ++ return ret; ++ ++err_disable_axi_clk: ++ clk_disable_unprepare(iep->axi_clk); ++ return ret; ++} ++ ++static const struct dev_pm_ops iep_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++ SET_RUNTIME_PM_OPS(iep_runtime_suspend, ++ iep_runtime_resume, NULL) ++}; ++ ++static const struct of_device_id rockchip_iep_match[] = { ++ { ++ .compatible = "rockchip,rk3228-iep", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, rockchip_iep_match); ++ ++static struct platform_driver iep_pdrv = { ++ .probe = iep_probe, ++ .remove = iep_remove, ++ .driver = { ++ .name = IEP_NAME, ++ .pm = &iep_pm_ops, ++ .of_match_table = rockchip_iep_match, ++ }, ++}; ++ ++module_platform_driver(iep_pdrv); ++ ++MODULE_AUTHOR("Alex Bee "); ++MODULE_DESCRIPTION("Rockchip Image Enhancement Processor"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/media/platform/rockchip/iep/iep.h b/drivers/media/platform/rockchip/iep/iep.h +new file mode 100644 +index 000000000000..7d9fc61624b6 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep.h +@@ -0,0 +1,112 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ */ ++#ifndef __IEP_H__ ++#define __IEP_H__ ++ ++#include ++#include ++#include ++#include ++ ++#define IEP_NAME "rockchip-iep" ++ ++/* Hardware limits */ ++#define IEP_MIN_WIDTH 320U ++#define IEP_MAX_WIDTH 1920U ++ ++#define IEP_MIN_HEIGHT 240U ++#define IEP_MAX_HEIGHT 1088U ++ ++/* Hardware defaults */ ++#define IEP_DEFAULT_WIDTH 320U ++#define IEP_DEFAULT_HEIGHT 240U ++ ++//ns ++#define IEP_TIMEOUT 250000 ++ ++struct iep_fmt { ++ u32 fourcc; ++ u8 depth; ++ u8 uv_factor; ++ u8 color_swap; ++ u8 hw_format; ++}; ++ ++struct iep_frm_fmt { ++ struct iep_fmt *hw_fmt; ++ struct v4l2_pix_format pix; ++ ++ unsigned int y_stride; ++ unsigned int uv_stride; ++}; ++ ++struct iep_ctx { ++ struct v4l2_fh fh; ++ struct rockchip_iep *iep; ++ ++ struct iep_frm_fmt src_fmt; ++ struct iep_frm_fmt dst_fmt; ++ ++ struct vb2_v4l2_buffer *prev_src_buf; ++ struct vb2_v4l2_buffer *dst0_buf; ++ struct vb2_v4l2_buffer *dst1_buf; ++ ++ u32 dst_sequence; ++ u32 src_sequence; ++ ++ /* bff = bottom field first */ ++ bool field_order_bff; ++ bool field_bff; ++ ++ unsigned int dst_buffs_done; ++ ++ bool fmt_changed; ++ bool job_abort; ++}; ++ ++struct rockchip_iep { ++ struct v4l2_device v4l2_dev; ++ struct v4l2_m2m_dev *m2m_dev; ++ struct video_device vfd; ++ ++ struct device *dev; ++ ++ void __iomem *regs; ++ ++ struct clk *axi_clk; ++ struct clk *ahb_clk; ++ ++ /* vfd lock */ ++ struct mutex mutex; ++}; ++ ++static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value) ++{ ++ writel(value, iep->regs + reg); ++}; ++ ++static inline u32 iep_read(struct rockchip_iep *iep, u32 reg) ++{ ++ return readl(iep->regs + reg); ++}; ++ ++static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg, ++ u32 shadow_reg, u32 mask, u32 val) ++{ ++ u32 temp = iep_read(iep, shadow_reg) & ~(mask); ++ ++ temp |= val & mask; ++ iep_write(iep, reg, temp); ++}; ++ ++static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val) ++{ ++ iep_shadow_mod(iep, reg, reg, mask, val); ++}; ++ ++#endif +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-helios64-dts-fix-stability-issues.patch b/patch/kernel/archive/rockchip64-6.6/board-helios64-dts-fix-stability-issues.patch new file mode 100644 index 000000000..4c53e0fe8 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-helios64-dts-fix-stability-issues.patch @@ -0,0 +1,72 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Aditya Prayoga +Date: Thu, 4 Mar 2021 10:39:40 +0700 +Subject: [ARCHEOLOGY] Attempt to improve stability on Helios64 (#2680) + +> X-Git-Archeology: > recovered message: > * Adjust the RK808 buck step to improve stability +> X-Git-Archeology: > recovered message: > * Adjust vdd_log and enable vdd_center init voltage +> X-Git-Archeology: > recovered message: > For some reason, regulator-init-microvolt property under PMIC does not applied. Set the voltage on board file. +> X-Git-Archeology: - Revision eefad69215557708b151a5d9244617a4ffd1281c: https://github.com/armbian/build/commit/eefad69215557708b151a5d9244617a4ffd1281c +> X-Git-Archeology: Date: Thu, 04 Mar 2021 10:39:40 +0700 +> X-Git-Archeology: From: Aditya Prayoga +> X-Git-Archeology: Subject: Attempt to improve stability on Helios64 (#2680) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index ac0da7b7f43c..38bf0f583f44 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -478,6 +478,7 @@ rk808: pmic@1b { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; ++ max-buck-steps-per-change = <4>; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-helios64-remove-overclock.patch b/patch/kernel/archive/rockchip64-6.6/board-helios64-remove-overclock.patch new file mode 100644 index 000000000..20ac4c33a --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-helios64-remove-overclock.patch @@ -0,0 +1,32 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Aditya Prayoga +Date: Mon, 7 Sep 2020 20:29:43 +0700 +Subject: Remove overclock from helios64 + +Signed-off-by: Aditya Prayoga +--- + arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index 38bf0f583f44..e1994a72e308 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -1152,4 +1152,12 @@ &vopl { + + &vopl_mmu { + status = "okay"; +-}; +\ No newline at end of file ++}; ++ ++&cluster0_opp { ++ /delete-node/ opp06; ++}; ++ ++&cluster1_opp { ++ /delete-node/ opp08; ++}; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-helios64-remove-pcie-ep-gpios.patch b/patch/kernel/archive/rockchip64-6.6/board-helios64-remove-pcie-ep-gpios.patch new file mode 100644 index 000000000..3b4d31a5d --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-helios64-remove-pcie-ep-gpios.patch @@ -0,0 +1,25 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Aditya Prayoga +Date: Tue, 15 Sep 2020 13:42:02 +0700 +Subject: Remove PCIE ep-gpios from Helios64 + +Signed-off-by: Aditya Prayoga +--- + arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index e1994a72e308..f4c50e5ce896 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -771,7 +771,6 @@ &io_domains { + }; + + &pcie0 { +- ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + num-lanes = <2>; + max-link-speed = <2>; + pinctrl-names = "default"; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-nanopc-t4-add-typec-dp.patch b/patch/kernel/archive/rockchip64-6.6/board-nanopc-t4-add-typec-dp.patch new file mode 100644 index 000000000..b6a2dc3d6 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-nanopc-t4-add-typec-dp.patch @@ -0,0 +1,147 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: tonymac32 +Date: Wed, 17 Feb 2021 00:54:00 -0500 +Subject: Patching something + +Signed-off-by: tonymac32 +--- + arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts | 96 ++++++++++ + 1 file changed, 96 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts +index 3bf8f959e42c..2b1220beabd5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts +@@ -9,6 +9,7 @@ + */ + + /dts-v1/; ++#include + #include "rk3399-nanopi4.dtsi" + + / { +@@ -66,6 +67,12 @@ fan: pwm-fan { + }; + }; + ++&cdn_dp { ++ status = "okay"; ++ extcon = <&fusb0>; ++ phys = <&tcphy0_dp>; ++}; ++ + &cpu_thermal { + trips { + cpu_warm: cpu_warm { +@@ -94,6 +101,50 @@ map3 { + }; + }; + ++&fusb0 { ++ ++ connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ power-role = "dual"; ++ data-role = "dual"; ++ try-power-role = "sink"; ++ source-pdos = ; ++ sink-pdos = ; ++ op-sink-microwatt = <5000000>; ++ ++ extcon-cables = <1 2 5 6 9 10 12 44>; ++ typec-altmodes = <0xff01 1 0x001c0000 1>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ usb_con_hs: endpoint { ++ remote-endpoint = ++ <&u2phy0_typec_hs>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ ++ usb_con_ss: endpoint { ++ remote-endpoint = ++ <&tcphy0_typec_ss>; ++ }; ++ }; ++ port@2 { ++ reg = <2>; ++ usb_con_dp: endpoint { ++ remote-endpoint = ++ <&tcphy0_typec_dp>; ++ }; ++ }; ++ }; ++ }; ++}; ++ + &pcie0 { + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; +@@ -114,12 +165,57 @@ &sdhci { + mmc-hs400-enhanced-strobe; + }; + ++&tcphy0 { ++ extcon = <&fusb0>; ++ status = "okay"; ++}; ++ ++&tcphy0_dp { ++ port { ++ tcphy0_typec_dp: endpoint { ++ remote-endpoint = <&usb_con_dp>; ++ }; ++ }; ++}; ++ ++&tcphy0_usb3 { ++ port { ++ tcphy0_typec_ss: endpoint { ++ remote-endpoint = <&usb_con_ss>; ++ }; ++ }; ++}; ++ ++&u2phy0 { ++ extcon = <&fusb0>; ++}; ++ + &u2phy0_host { + phy-supply = <&vcc5v0_host0>; ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++ ++ port { ++ u2phy0_typec_hs: endpoint { ++ remote-endpoint = <&usb_con_hs>; ++ }; ++ }; + }; + + &u2phy1_host { + phy-supply = <&vcc5v0_host0>; ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ extcon = <&fusb0>; + }; + + &vcc5v0_sys { +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-nanopi-m4v2-dts-add-sound-card.patch b/patch/kernel/archive/rockchip64-6.6/board-nanopi-m4v2-dts-add-sound-card.patch new file mode 100644 index 000000000..8c03adf2b --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-nanopi-m4v2-dts-add-sound-card.patch @@ -0,0 +1,190 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Piotr Szczepanik +Date: Thu, 28 Nov 2019 22:29:54 +0000 +Subject: [ARCHEOLOGY] Initial addition of NanoPi M4V2 + +> X-Git-Archeology: - Revision c4eecbcef0d4dc499baf0155449e71dc774bc7c4: https://github.com/armbian/build/commit/c4eecbcef0d4dc499baf0155449e71dc774bc7c4 +> X-Git-Archeology: Date: Thu, 28 Nov 2019 22:29:54 +0000 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Initial addition of NanoPi M4V2 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 40a3d4ecb9a75c17183e2129491b7bc03060a315: https://github.com/armbian/build/commit/40a3d4ecb9a75c17183e2129491b7bc03060a315 +> X-Git-Archeology: Date: Sun, 17 May 2020 18:42:24 +0200 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Fixed rt5651 codec probing after its driver was changed to module (#1969) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 +> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 +> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 401fb1fde426c93121c4639b34a450d8ff551c85: https://github.com/armbian/build/commit/401fb1fde426c93121c4639b34a450d8ff551c85 +> X-Git-Archeology: Date: Sat, 20 Nov 2021 19:49:22 +0100 +> X-Git-Archeology: From: simple <991605149@qq.com> +> X-Git-Archeology: Subject: Fixed rt5651 codec build module (#3270) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 51 ++++++++++ + sound/soc/rockchip/Kconfig | 9 ++ + 2 files changed, 60 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +index 7c5f441a2219..3e899f584871 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +@@ -132,6 +132,27 @@ status_led: led-0 { + }; + }; + ++ rt5651-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "realtek,rt5651-codec"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Headphone", "Headphone Jack"; ++ simple-audio-card,routing = ++ "Mic Jack", "micbias1", ++ "IN1P", "Mic Jack", ++ "Headphone Jack", "HPOL", ++ "Headphone Jack", "HPOR"; ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&rt5651>; ++ }; ++ }; ++ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; +@@ -216,6 +237,10 @@ &hdmi_sound { + status = "okay"; + }; + ++&hdmi_sound { ++ status = "okay"; ++}; ++ + &i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; +@@ -463,6 +488,16 @@ &i2c1 { + i2c-scl-rising-time-ns = <150>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; ++ ++ rt5651: rt5651@1a { ++ compatible = "realtek,rt5651"; ++ reg = <0x1a>; ++ clocks = <&cru SCLK_I2S_8CH_OUT>; ++ clock-names = "mclk"; ++ hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; ++ // spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; ++ #sound-dai-cells = <0>; ++ }; + }; + + &i2c2 { +@@ -494,6 +529,16 @@ &i2s2 { + status = "okay"; + }; + ++&i2s1 { ++ rockchip,playback-channels = <8>; ++ rockchip,capture-channels = <8>; ++ status = "okay"; ++}; ++ ++&i2s2 { ++ status = "okay"; ++}; ++ + &io_domains { + bt656-supply = <&vcc_1v8>; + audio-supply = <&vcca1v8_codec>; +@@ -759,3 +804,9 @@ &vopl { + &vopl_mmu { + status = "okay"; + }; ++ ++&spdif { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; +diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig +index f98a2fa85edd..be36e36c8783 100644 +--- a/sound/soc/rockchip/Kconfig ++++ b/sound/soc/rockchip/Kconfig +@@ -65,6 +65,15 @@ config SND_SOC_ROCKCHIP_RT5645 + Say Y or M here if you want to add support for SoC audio on Rockchip + boards using the RT5645/RT5650 codec, such as Veyron. + ++config SND_SOC_ROCKCHIP_RT5651 ++ tristate "ASoC support for Rockchip boards using a RT5651 codec" ++ depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK ++ select SND_SOC_ROCKCHIP_I2S ++ select SND_SOC_RT5651 ++ help ++ Say Y or M here if you want to add support for SoC audio on Rockchip ++ boards using the RT5651 codec, such as FriendlyARM's Nano{Pi,PC} family. ++ + config SND_SOC_RK3288_HDMI_ANALOG + tristate "ASoC support multiple codecs for Rockchip RK3288 boards" + depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-nanopi-r2c-plus.patch b/patch/kernel/archive/rockchip64-6.6/board-nanopi-r2c-plus.patch new file mode 100644 index 000000000..72fe01212 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-nanopi-r2c-plus.patch @@ -0,0 +1,30 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: amazingfate +Date: Thu, 31 Aug 2023 11:41:37 +0200 +Subject: [ARCHEOLOGY] rockchip64: bump rockchip64-edge kernel to 6.5 + +> X-Git-Archeology: - Revision 8254411054a99f9750770bb6055facfbdedacbba: https://github.com/armbian/build/commit/8254411054a99f9750770bb6055facfbdedacbba +> X-Git-Archeology: Date: Thu, 31 Aug 2023 11:41:37 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: rockchip64: bump rockchip64-edge kernel to 6.5 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts +index 16a1958e4572..45954295d51d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts +@@ -27,7 +27,7 @@ &emmc { + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +- vmmc-supply = <&vcc_io_33>; ++ vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; + }; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-nanopi-r2s.patch b/patch/kernel/archive/rockchip64-6.6/board-nanopi-r2s.patch new file mode 100644 index 000000000..fb270fc69 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-nanopi-r2s.patch @@ -0,0 +1,733 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sat, 7 Jan 2023 11:59:47 +0000 +Subject: rockchip64: consolidate nanopi r2s device trees + +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 493 ++++++---- + 1 file changed, 328 insertions(+), 165 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +index 1445b879ac7a..7ebf21d7faac 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -1,118 +1,166 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* +- * Copyright (c) 2020 David Bauer ++ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + + /dts-v1/; +- +-#include +-#include ++#include "rk3328-dram-default-timing.dtsi" + #include "rk3328.dtsi" + + / { +- model = "FriendlyElec NanoPi R2S"; +- compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; ++ model = "FriendlyElec boards based on Rockchip RK3328"; ++ compatible = "friendlyelec,nanopi-r2", ++ "rockchip,rk3328"; + + aliases { +- ethernet1 = &rtl8153; +- mmc0 = &sdmmc; ++ ethernet1 = &r8153; + }; + + chosen { ++ bootargs = "swiotlb=1 coherent_pool=1m consoleblank=0"; + stdout-path = "serial2:1500000n8"; + }; + +- gmac_clk: gmac-clock { ++ gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + +- keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&reset_button_pin>; +- pinctrl-names = "default"; +- +- key-reset { +- label = "reset"; +- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; +- linux,code = ; +- debounce-interval = <50>; +- }; ++ mach: board { ++ compatible = "friendlyelec,board"; ++ machine = "NANOPI-R2"; ++ hwrev = <255>; ++ model = "NanoPi R2 Series"; ++ nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; ++ nvmem-cell-names = "id", "cpu-version"; + }; + +- leds { ++ leds: gpio-leds { + compatible = "gpio-leds"; +- pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; ++ pinctrl-0 =<&leds_gpio>; ++ status = "disabled"; + +- lan_led: led-0 { +- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:lan"; +- }; +- +- sys_led: led-1 { ++ led@1 { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:red:sys"; +- default-state = "on"; +- }; +- +- wan_led: led-2 { +- gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:wan"; ++ label = "status_led"; ++ linux,default-trigger = "heartbeat"; ++ linux,default-trigger-delay-ms = <0>; + }; + }; + +- vcc_io_sdio: sdmmcio-regulator { +- compatible = "regulator-gpio"; +- enable-active-high; +- gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&sdio_vcc_pin>; ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk805 1>; ++ clock-names = "ext_clock"; + pinctrl-names = "default"; +- regulator-name = "vcc_io_sdio"; +- regulator-always-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-settling-time-us = <5000>; +- regulator-type = "voltage"; +- startup-delay-us = <2000>; +- states = <1800000 0x1>, +- <3300000 0x0>; +- vin-supply = <&vcc_io_33>; ++ pinctrl-0 = <&wifi_enable_h>; ++ ++ /* ++ * On the module itself this is one of these (depending ++ * on the actual card populated): ++ * - SDIO_RESET_L_WL_REG_ON ++ * - PDN (power down when low) ++ */ ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sdmmc_ext: dwmmc@ff5f0000 { ++ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xff5f0000 0x0 0x4000>; ++ clock-freq-min-max = <400000 150000000>; ++ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, ++ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; ++ fifo-depth = <0x100>; ++ interrupts = ; ++ status = "disabled"; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; +- gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; +- pinctrl-0 = <&sdmmc0m1_pin>; ++ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; +- regulator-name = "vcc_sd"; ++ pinctrl-0 = <&sdmmc0m1_pin>; + regulator-boot-on; ++ regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +- vin-supply = <&vcc_io_33>; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vccio_sd: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ regulator-name = "vccio_sd"; ++ regulator-type = "voltage"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <&vcc_io>; ++ startup-delay-us = <2000>; ++ regulator-settling-time-us = <5000>; ++ enable-active-high; ++ status = "disabled"; + }; + +- vdd_5v: vdd-5v { ++ vcc_sys: vcc-sys { + compatible = "regulator-fixed"; +- regulator-name = "vdd_5v"; ++ regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + +- vdd_5v_lan: vdd-5v-lan { ++ vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; +- pinctrl-0 = <&lan_vdd_pin>; +- pinctrl-names = "default"; +- regulator-name = "vdd_5v_lan"; ++ regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; +- vin-supply = <&vdd_5v>; ++ }; ++ ++ vcc_host_vbus: host-vbus-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_host_vbus"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ /delete-node/ dmc-opp-table; ++ ++ dmc_opp_table: dmc_opp_table { ++ compatible = "operating-points-v2"; ++ ++ opp-786000000 { ++ opp-hz = /bits/ 64 <786000000>; ++ opp-microvolt = <1075000 1075000 1200000>; ++ }; ++ opp-798000000 { ++ opp-hz = /bits/ 64 <798000000>; ++ opp-microvolt = <1075000 1075000 1200000>; ++ }; ++ opp-840000000 { ++ opp-hz = /bits/ 64 <840000000>; ++ opp-microvolt = <1075000 1075000 1200000>; ++ }; ++ opp-924000000 { ++ opp-hz = /bits/ 64 <924000000>; ++ opp-microvolt = <1100000 1100000 1200000>; ++ }; ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1175000 1175000 1200000>; ++ }; + }; + }; + +@@ -120,34 +168,57 @@ &cpu0 { + cpu-supply = <&vdd_arm>; + }; + +-&cpu1 { +- cpu-supply = <&vdd_arm>; ++&dfi { ++ status = "okay"; + }; + +-&cpu2 { +- cpu-supply = <&vdd_arm>; ++&dmc { ++ center-supply = <&vdd_logic>; ++ ddr_timing = <&ddr_timing>; ++ status = "okay"; + }; + +-&cpu3 { +- cpu-supply = <&vdd_arm>; ++&emmc { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <150000000>; ++ mmc-hs200-1_8v; ++ no-sd; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; ++ vmmc-supply = <&vcc_io>; ++ vqmmc-supply = <&vcc18_emmc>; ++ status = "okay"; + }; + +-&display_subsystem { ++&gmac2phy { ++ phy-supply = <&vcc_phy>; ++ clock_in_out = "output"; ++ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; ++ assigned-clock-rate = <50000000>; ++ assigned-clocks = <&cru SCLK_MAC2PHY>; ++ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + status = "disabled"; + }; + + &gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; +- assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; ++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmiim1_pins>; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; +- phy-supply = <&vcc_io_33>; +- pinctrl-0 = <&rgmiim1_pins>; +- pinctrl-names = "default"; +- rx_delay = <0x18>; ++ phy-supply = <&vcc_phy>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 30000>; ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,aal; ++ snps,rxpbl = <0x4>; ++ snps,txpbl = <0x4>; + tx_delay = <0x24>; ++ rx_delay = <0x18>; + status = "okay"; + + mdio { +@@ -155,13 +226,11 @@ mdio { + #address-cells = <1>; + #size-cells = <0>; + +- rtl8211e: ethernet-phy@1 { +- reg = <1>; +- pinctrl-0 = <ð_phy_reset_pin>; +- pinctrl-names = "default"; ++ rtl8211e: phy@0 { ++ reg = <0>; + reset-assert-us = <10000>; +- reset-deassert-us = <50000>; +- reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ reset-deassert-us = <30000>; ++ /* reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; */ + }; + }; + }; +@@ -169,36 +238,35 @@ rtl8211e: ethernet-phy@1 { + &i2c1 { + status = "okay"; + +- rk805: pmic@18 { ++ rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; +- interrupt-parent = <&gpio1>; +- interrupts = <24 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; +- pinctrl-0 = <&pmic_int_l>; + pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + +- vcc1-supply = <&vdd_5v>; +- vcc2-supply = <&vdd_5v>; +- vcc3-supply = <&vdd_5v>; +- vcc4-supply = <&vdd_5v>; +- vcc5-supply = <&vcc_io_33>; +- vcc6-supply = <&vdd_5v>; ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_io>; + + regulators { +- vdd_log: DCDC_REG1 { +- regulator-name = "vdd_log"; +- regulator-always-on; +- regulator-boot-on; ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-init-microvolt = <1075000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <12500>; +- ++ regulator-always-on; ++ regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; +@@ -207,12 +275,11 @@ regulator-state-mem { + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; +- regulator-always-on; +- regulator-boot-on; ++ regulator-init-microvolt = <1225000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; +- regulator-ramp-delay = <12500>; +- ++ regulator-always-on; ++ regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; +@@ -223,19 +290,17 @@ vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; +- + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + +- vcc_io_33: DCDC_REG4 { +- regulator-name = "vcc_io_33"; +- regulator-always-on; +- regulator-boot-on; ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +- ++ regulator-always-on; ++ regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; +@@ -244,11 +309,10 @@ regulator-state-mem { + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; +- regulator-always-on; +- regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +- ++ regulator-always-on; ++ regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; +@@ -257,11 +321,10 @@ regulator-state-mem { + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; +- regulator-always-on; +- regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +- ++ regulator-always-on; ++ regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; +@@ -270,11 +333,10 @@ regulator-state-mem { + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; +- regulator-always-on; +- regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; +- ++ regulator-always-on; ++ regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; +@@ -285,20 +347,21 @@ regulator-state-mem { + }; + + &io_domains { +- pmuio-supply = <&vcc_io_33>; +- vccio1-supply = <&vcc_io_33>; +- vccio2-supply = <&vcc18_emmc>; +- vccio3-supply = <&vcc_io_sdio>; +- vccio4-supply = <&vcc_18>; +- vccio5-supply = <&vcc_io_33>; +- vccio6-supply = <&vcc_io_33>; + status = "okay"; ++ ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_io>; ++ vccio4-supply = <&vcc_io>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_18>; ++ pmuio-supply = <&vcc_io>; + }; + + &pinctrl { +- button { +- reset_button_pin: reset-button-pin { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +@@ -308,61 +371,165 @@ eth_phy_reset_pin: eth-phy-reset-pin { + }; + }; + +- leds { +- lan_led_pin: lan-led-pin { +- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; ++ }; + +- sys_led_pin: sys-led-pin { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ sdmmc0 { ++ sdmmc0_clk: sdmmc0-clk { ++ rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>; ++ }; ++ ++ sdmmc0_cmd: sdmmc0-cmd { ++ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>; + }; + +- wan_led_pin: wan-led-pin { +- rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ sdmmc0_dectn: sdmmc0-dectn { ++ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; ++ }; ++ ++ sdmmc0_bus4: sdmmc0-bus4 { ++ rockchip,pins = ++ <1 RK_PA0 1 &pcfg_pull_up_4ma>, ++ <1 RK_PA1 1 &pcfg_pull_up_4ma>, ++ <1 RK_PA2 1 &pcfg_pull_up_4ma>, ++ <1 RK_PA3 1 &pcfg_pull_up_4ma>; + }; + }; + +- lan { +- lan_vdd_pin: lan-vdd-pin { +- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ sdmmc0ext { ++ sdmmc0ext_clk: sdmmc0ext-clk { ++ rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_2ma>; ++ }; ++ ++ sdmmc0ext_cmd: sdmmc0ext-cmd { ++ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_2ma>; ++ }; ++ ++ sdmmc0ext_bus4: sdmmc0ext-bus4 { ++ rockchip,pins = ++ <3 RK_PA4 3 &pcfg_pull_up_2ma>, ++ <3 RK_PA5 3 &pcfg_pull_up_2ma>, ++ <3 RK_PA6 3 &pcfg_pull_up_2ma>, ++ <3 RK_PA7 3 &pcfg_pull_up_2ma>; + }; + }; + +- pmic { +- pmic_int_l: pmic-int-l { +- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; ++ gmac-1 { ++ rgmiim1_pins: rgmiim1-pins { ++ rockchip,pins = ++ /* mac_txclk */ ++ <1 RK_PB4 2 &pcfg_pull_none_4ma>, ++ /* mac_rxclk */ ++ <1 RK_PB5 2 &pcfg_pull_none>, ++ /* mac_mdio */ ++ <1 RK_PC3 2 &pcfg_pull_none_2ma>, ++ /* mac_txen */ ++ <1 RK_PD1 2 &pcfg_pull_none_4ma>, ++ /* mac_clk */ ++ <1 RK_PC5 2 &pcfg_pull_none_2ma>, ++ /* mac_rxdv */ ++ <1 RK_PC6 2 &pcfg_pull_none>, ++ /* mac_mdc */ ++ <1 RK_PC7 2 &pcfg_pull_none_2ma>, ++ /* mac_rxd1 */ ++ <1 RK_PB2 2 &pcfg_pull_none>, ++ /* mac_rxd0 */ ++ <1 RK_PB3 2 &pcfg_pull_none>, ++ /* mac_txd1 */ ++ <1 RK_PB0 2 &pcfg_pull_none_4ma>, ++ /* mac_txd0 */ ++ <1 RK_PB1 2 &pcfg_pull_none_4ma>, ++ /* mac_rxd3 */ ++ <1 RK_PB6 2 &pcfg_pull_none>, ++ /* mac_rxd2 */ ++ <1 RK_PB7 2 &pcfg_pull_none>, ++ /* mac_txd3 */ ++ <1 RK_PC0 2 &pcfg_pull_none_4ma>, ++ /* mac_txd2 */ ++ <1 RK_PC1 2 &pcfg_pull_none_4ma>, ++ ++ /* mac_txclk */ ++ <0 RK_PB0 1 &pcfg_pull_none>, ++ /* mac_txen */ ++ <0 RK_PB4 1 &pcfg_pull_none>, ++ /* mac_clk */ ++ <0 RK_PD0 1 &pcfg_pull_none>, ++ /* mac_txd1 */ ++ <0 RK_PC0 1 &pcfg_pull_none>, ++ /* mac_txd0 */ ++ <0 RK_PC1 1 &pcfg_pull_none>, ++ /* mac_txd3 */ ++ <0 RK_PC7 1 &pcfg_pull_none>, ++ /* mac_txd2 */ ++ <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + +- sd { +- sdio_vcc_pin: sdio-vcc-pin { +- rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; ++ usb { ++ host_vbus_drv: host-vbus-drv { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ otg_vbus_drv: otg-vbus-drv { ++ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; ++ ++ gpio-leds { ++ leds_gpio: leds-gpio { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + +-&pwm2 { ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; ++ vmmc-supply = <&vcc_sd>; + status = "okay"; + }; + +-&sdmmc { ++&sdmmc_ext { + bus-width = <4>; + cap-sd-highspeed; ++ cap-sdio-irq; + disable-wp; +- pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; ++ keep-power-in-suspend; ++ max-frequency = <100000000>; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ num-slots = <1>; + pinctrl-names = "default"; +- sd-uhs-sdr12; +- sd-uhs-sdr25; +- sd-uhs-sdr50; ++ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_bus4>; ++ rockchip,default-sample-phase = <120>; ++ supports-sdio; + sd-uhs-sdr104; +- vmmc-supply = <&vcc_sd>; +- vqmmc-supply = <&vcc_io_sdio>; ++ #address-cells = <1>; ++ #size-cells = <0>; + status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ }; + }; + + &tsadc { +- rockchip,hw-tshut-mode = <0>; +- rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { + status = "okay"; + }; + +@@ -378,13 +545,16 @@ &u2phy_otg { + status = "okay"; + }; + +-&uart2 { ++&usb20_otg { + status = "okay"; + }; + +-&usb20_otg { ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { + status = "okay"; +- dr_mode = "host"; + }; + + &usbdrd3 { +@@ -393,17 +563,10 @@ &usbdrd3 { + #address-cells = <1>; + #size-cells = <0>; + +- /* Second port is for USB 3.0 */ +- rtl8153: device@2 { ++ r8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; ++ realtek,led-data = <0x87>; ++ local-mac-address = [00 00 00 00 00 00]; + }; + }; +- +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-nanopi-r4s-pwmfan.patch b/patch/kernel/archive/rockchip64-6.6/board-nanopi-r4s-pwmfan.patch new file mode 100644 index 000000000..2fb280e54 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-nanopi-r4s-pwmfan.patch @@ -0,0 +1,58 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Bochun Bai +Date: Sun, 18 Jun 2023 11:56:34 +0200 +Subject: Add pwm-fan support to nanopi r4s + +--- + arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 35 ++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +index fe5b52610010..10cc254fd1dc 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -62,6 +62,41 @@ vdd_5v: vdd-5v { + regulator-always-on; + regulator-boot-on; + }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ cooling-levels = <0 18 102 170 255>; ++ fan-supply = <&vdd_5v>; ++ pwms = <&pwm1 0 50000 0>; ++ }; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_warm: cpu_warm { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu_hot { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map2 { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map3 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; + }; + + &emmc_phy { +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-orangepi-r1-plus.patch b/patch/kernel/archive/rockchip64-6.6/board-orangepi-r1-plus.patch new file mode 100644 index 000000000..847286563 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-orangepi-r1-plus.patch @@ -0,0 +1,335 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Igor Pecovnik +Date: Sat, 20 Jun 2020 22:39:57 +0200 +Subject: [ARCHEOLOGY] Initial ROCK Pi E support (as WIP) (#2042) + +note: rpardini: rebased on top of v6.3.1. this patch used to overwrite +a file, and is now a complete diff. + +> X-Git-Archeology: > recovered message: > * WIP: Adding RockpiE config +> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik +> X-Git-Archeology: > recovered message: > * Mainline u-boot for ROCK Pi E +> X-Git-Archeology: > recovered message: > * Initial ROCK Pi E device tree in kernel +> X-Git-Archeology: > recovered message: > * Fixed supplies for ROCK Pi E device tree +> X-Git-Archeology: > recovered message: > * Adjusted u-boot load address for rockchip64 boards with 256MB eg. ROCK Pi E +> X-Git-Archeology: > recovered message: > * Blacklisted lima on ROCK Pi E +> X-Git-Archeology: > recovered message: > * Fixed ROCK Pi E patch after merge from master +> X-Git-Archeology: > recovered message: > * Removed mode settings from rk805 regulators +> X-Git-Archeology: > recovered message: > * Fixed issues with offloading for gigabit interface of RockPi E +> X-Git-Archeology: > recovered message: > * Adjusted ROCK Pi E board config +> X-Git-Archeology: > recovered message: > * Added dev branch for ROCK Pi E +> X-Git-Archeology: > recovered message: > * Add build targets +> X-Git-Archeology: > recovered message: > Signed-off-by: Igor Pecovnik +> X-Git-Archeology: > recovered message: > * Exchange legacy to current in ROCK Pi E build targets +> X-Git-Archeology: > recovered message: > Co-authored-by: Piotr Szczepanik +> X-Git-Archeology: - Revision e1ecb098330dc372740371dc2386f911833a0529: https://github.com/armbian/build/commit/e1ecb098330dc372740371dc2386f911833a0529 +> X-Git-Archeology: Date: Sat, 20 Jun 2020 22:39:57 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Initial ROCK Pi E support (as WIP) (#2042) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 72257bd0648c28fca32962126bb885a4a2c188cc: https://github.com/armbian/build/commit/72257bd0648c28fca32962126bb885a4a2c188cc +> X-Git-Archeology: Date: Tue, 23 Jun 2020 16:37:54 +0200 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Make USB3 support of ROCK Pi E on par with other rk3328 boards (#2050) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e36ce875b025e112127cf8cc2d34825ebfe36569: https://github.com/armbian/build/commit/e36ce875b025e112127cf8cc2d34825ebfe36569 +> X-Git-Archeology: Date: Tue, 10 Nov 2020 21:43:13 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switched rockchip64-current to linux 5.9.y (#2309) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ccbc888b3f5731790128684959b55b6552e26190: https://github.com/armbian/build/commit/ccbc888b3f5731790128684959b55b6552e26190 +> X-Git-Archeology: Date: Sat, 28 Nov 2020 16:52:34 +0100 +> X-Git-Archeology: From: Oleg +> X-Git-Archeology: Subject: add dts rk3328-roc-pc, fix WIFI and USB 3.0 rk3328 (#2390) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 25bd76527e1276c4c00829f68c0ca0742ecc94c1: https://github.com/armbian/build/commit/25bd76527e1276c4c00829f68c0ca0742ecc94c1 +> X-Git-Archeology: Date: Sat, 28 Nov 2020 18:10:53 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Fix roc-rk3328-pc device tree reference to missing RK_FUNC_1 +> X-Git-Archeology: +> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070 +> X-Git-Archeology: Date: Sun, 13 Dec 2020 22:13:03 -0500 +> X-Git-Archeology: From: tonymac32 +> X-Git-Archeology: Subject: [ rockchip64 ] Clean up patchset +> X-Git-Archeology: +> X-Git-Archeology: - Revision 25e0f1633467c020f6ae68d09964a522fbfbe613: https://github.com/armbian/build/commit/25e0f1633467c020f6ae68d09964a522fbfbe613 +> X-Git-Archeology: Date: Mon, 18 Jan 2021 23:21:40 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Adjusted power and pmic configuration for Station M1 in current/dev +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision d8dbefd61838e5b0cfc2b93d2d168f3fb2666dfb: https://github.com/armbian/build/commit/d8dbefd61838e5b0cfc2b93d2d168f3fb2666dfb +> X-Git-Archeology: Date: Tue, 27 Jul 2021 00:05:09 -0400 +> X-Git-Archeology: From: tonymac32 +> X-Git-Archeology: Subject: [ rockchip64 ] rk3328 change to mainline USB3 +> X-Git-Archeology: +> X-Git-Archeology: - Revision a16699260fb786a4d89a1c335722e9fed49d19d2: https://github.com/armbian/build/commit/a16699260fb786a4d89a1c335722e9fed49d19d2 +> X-Git-Archeology: Date: Fri, 08 Jul 2022 22:35:59 +1200 +> X-Git-Archeology: From: schwar3kat <61094841+schwar3kat@users.noreply.github.com> +> X-Git-Archeology: Subject: Refactored orangepi-r1plus-lts dts in kernel add board patch +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8648dde23ff090b5fb704adab036ed14cd944ba3: https://github.com/armbian/build/commit/8648dde23ff090b5fb704adab036ed14cd944ba3 +> X-Git-Archeology: Date: Thu, 22 Sep 2022 10:25:28 +0200 +> X-Git-Archeology: From: aiamadeus <42570690+aiamadeus@users.noreply.github.com> +> X-Git-Archeology: Subject: rockchip: fixes support for orangepi-r1plus (#4215) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 109 +++++++--- + 1 file changed, 73 insertions(+), 36 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +index dc83d74045a3..4fe8eb39b64f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -1,13 +1,10 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * Based on rk3328-nanopi-r2s.dts, which is: +- * Copyright (c) 2020 David Bauer +- */ + + /dts-v1/; + ++#include + #include +-#include ++#include "rk3328-dram-default-timing.dtsi" + #include "rk3328.dtsi" + + / { +@@ -35,23 +32,20 @@ leds { + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; + +- led-0 { +- function = LED_FUNCTION_LAN; +- color = ; ++ lan_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; ++ label = "orangepi-r1-plus:green:lan"; + }; + +- led-1 { +- function = LED_FUNCTION_STATUS; +- color = ; ++ sys_led: led-1 { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; ++ label = "orangepi-r1-plus:red:status"; + linux,default-trigger = "heartbeat"; + }; + +- led-2 { +- function = LED_FUNCTION_WAN; +- color = ; ++ wan_led: led-2 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ label = "orangepi-r1-plus:green:wan"; + }; + }; + +@@ -62,19 +56,19 @@ vcc_sd: sdmmc-regulator { + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-boot-on; +- vin-supply = <&vcc_io>; ++ vin-supply = <&vcc_io_33>; + }; + +- vcc_sys: vcc-sys-regulator { ++ vdd_5v: vdd-5v { + compatible = "regulator-fixed"; +- regulator-name = "vcc_sys"; ++ regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + +- vdd_5v_lan: vdd-5v-lan-regulator { ++ vdd_5v_lan: vdd-5v-lan { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; +@@ -83,7 +77,34 @@ vdd_5v_lan: vdd-5v-lan-regulator { + regulator-name = "vdd_5v_lan"; + regulator-always-on; + regulator-boot-on; +- vin-supply = <&vcc_sys>; ++ vin-supply = <&vdd_5v>; ++ }; ++ ++ /delete-node/ dmc-opp-table; ++ ++ dmc_opp_table: dmc_opp_table { ++ compatible = "operating-points-v2"; ++ ++ opp-786000000 { ++ opp-hz = /bits/ 64 <786000000>; ++ opp-microvolt = <1075000 1075000 1200000>; ++ }; ++ opp-798000000 { ++ opp-hz = /bits/ 64 <798000000>; ++ opp-microvolt = <1075000 1075000 1200000>; ++ }; ++ opp-840000000 { ++ opp-hz = /bits/ 64 <840000000>; ++ opp-microvolt = <1075000 1075000 1200000>; ++ }; ++ opp-924000000 { ++ opp-hz = /bits/ 64 <924000000>; ++ opp-microvolt = <1100000 1100000 1200000>; ++ }; ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1175000 1175000 1200000>; ++ }; + }; + }; + +@@ -103,6 +124,16 @@ &cpu3 { + cpu-supply = <&vdd_arm>; + }; + ++&dfi { ++ status = "okay"; ++}; ++ ++&dmc { ++ center-supply = <&vdd_log>; ++ ddr_timing = <&ddr_timing>; ++ status = "okay"; ++}; ++ + &display_subsystem { + status = "disabled"; + }; +@@ -113,7 +144,7 @@ &gmac2io { + clock_in_out = "input"; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; +- phy-supply = <&vcc_io>; ++ phy-supply = <&vcc_io_33>; + pinctrl-0 = <&rgmiim1_pins>; + pinctrl-names = "default"; + snps,aal; +@@ -137,6 +168,10 @@ rtl8211e: ethernet-phy@1 { + }; + }; + ++&i2c0 { ++ status = "okay"; ++}; ++ + &i2c1 { + status = "okay"; + +@@ -154,18 +189,19 @@ rk805: pmic@18 { + rockchip,system-power-controller; + wakeup-source; + +- vcc1-supply = <&vcc_sys>; +- vcc2-supply = <&vcc_sys>; +- vcc3-supply = <&vcc_sys>; +- vcc4-supply = <&vcc_sys>; +- vcc5-supply = <&vcc_io>; +- vcc6-supply = <&vcc_sys>; ++ vcc1-supply = <&vdd_5v>; ++ vcc2-supply = <&vdd_5v>; ++ vcc3-supply = <&vdd_5v>; ++ vcc4-supply = <&vdd_5v>; ++ vcc5-supply = <&vcc_io_33>; ++ vcc6-supply = <&vdd_5v>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; ++ regulator-init-microvolt = <1075000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; +@@ -180,6 +216,7 @@ vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; ++ regulator-init-microvolt = <1225000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; +@@ -200,8 +237,8 @@ regulator-state-mem { + }; + }; + +- vcc_io: DCDC_REG4 { +- regulator-name = "vcc_io"; ++ vcc_io_33: DCDC_REG4 { ++ regulator-name = "vcc_io_33"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; +@@ -256,13 +293,13 @@ regulator-state-mem { + }; + + &io_domains { +- pmuio-supply = <&vcc_io>; +- vccio1-supply = <&vcc_io>; ++ pmuio-supply = <&vcc_io_33>; ++ vccio1-supply = <&vcc_io_33>; + vccio2-supply = <&vcc18_emmc>; +- vccio3-supply = <&vcc_io>; +- vccio4-supply = <&vcc_io>; +- vccio5-supply = <&vcc_io>; +- vccio6-supply = <&vcc_io>; ++ vccio3-supply = <&vcc_io_33>; ++ vccio4-supply = <&vcc_io_33>; ++ vccio5-supply = <&vcc_io_33>; ++ vccio6-supply = <&vcc_io_33>; + status = "okay"; + }; + +@@ -347,8 +384,8 @@ &uart2 { + }; + + &usb20_otg { +- dr_mode = "host"; + status = "okay"; ++ dr_mode = "host"; + }; + + &usbdrd3 { +@@ -357,10 +394,10 @@ &usbdrd3 { + #address-cells = <1>; + #size-cells = <0>; + +- /* Second port is for USB 3.0 */ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; ++ realtek,led-data = <0x87>; + }; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-pbp-add-dp-alt-mode.patch b/patch/kernel/archive/rockchip64-6.6/board-pbp-add-dp-alt-mode.patch new file mode 100644 index 000000000..dd57ce104 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-pbp-add-dp-alt-mode.patch @@ -0,0 +1,416 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dan Johansen +Date: Tue, 2 Jun 2020 20:20:29 +0200 +Subject: add-dp-alt-mode-to-PBP + +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 5 + + drivers/phy/rockchip/phy-rockchip-typec.c | 17 ++ + drivers/usb/typec/altmodes/displayport.c | 52 +++- + drivers/usb/typec/tcpm/tcpm.c | 139 +++++++++- + 4 files changed, 210 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 054c6a4d1a45..48b865d30b14 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -422,6 +422,7 @@ edp_out_panel: endpoint@0 { + + &emmc_phy { + status = "okay"; ++ extcon = <&fusb0>; + }; + + &gpu { +@@ -706,6 +707,9 @@ connector { + ; + try-power-role = "sink"; + ++ extcon-cables = <1 2 5 6 9 10 12 44>; ++ typec-altmodes = <0xff01 1 0x001c0000 1>; ++ + ports { + #address-cells = <1>; + #size-cells = <0>; +@@ -972,6 +976,7 @@ spiflash: flash@0 { + }; + + &tcphy0 { ++ extcon = <&fusb0>; + status = "okay"; + }; + +diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c +index 8b1667be4915..aae021e192a4 100644 +--- a/drivers/phy/rockchip/phy-rockchip-typec.c ++++ b/drivers/phy/rockchip/phy-rockchip-typec.c +@@ -40,6 +40,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1157,6 +1158,22 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev) + dev_err(dev, "Invalid or missing extcon\n"); + return PTR_ERR(tcphy->extcon); + } ++ } else { ++ extcon_set_property_capability(tcphy->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_sync(tcphy->extcon, EXTCON_USB); ++ extcon_sync(tcphy->extcon, EXTCON_USB_HOST); ++ extcon_sync(tcphy->extcon, EXTCON_DISP_DP); + } + + pm_runtime_enable(dev); +diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c +index cdf8261e22db..05172e17b2bf 100644 +--- a/drivers/usb/typec/altmodes/displayport.c ++++ b/drivers/usb/typec/altmodes/displayport.c +@@ -9,6 +9,8 @@ + */ + + #include ++#include ++#include + #include + #include + #include +@@ -69,6 +71,8 @@ struct dp_altmode { + struct fwnode_handle *connector_fwnode; + }; + ++void dp_altmode_update_extcon(struct dp_altmode *dp, bool disconnect); ++ + static int dp_altmode_notify(struct dp_altmode *dp) + { + unsigned long conf; +@@ -77,7 +81,9 @@ static int dp_altmode_notify(struct dp_altmode *dp) + if (dp->data.conf) { + state = get_count_order(DP_CONF_GET_PIN_ASSIGN(dp->data.conf)); + conf = TYPEC_MODAL_STATE(state); ++ dp_altmode_update_extcon(dp, false); + } else { ++ dp_altmode_update_extcon(dp, true); + conf = TYPEC_STATE_USB; + } + +@@ -163,6 +169,40 @@ static int dp_altmode_status_update(struct dp_altmode *dp) + return ret; + } + ++void dp_altmode_update_extcon(struct dp_altmode *dp, bool disconnect) { ++ const struct device *dev = &dp->port->dev; ++ struct extcon_dev* edev = NULL; ++ ++ while (dev) { ++ edev = extcon_find_edev_by_node(dev->of_node); ++ if(!IS_ERR(edev)) { ++ break; ++ } ++ dev = dev->parent; ++ } ++ ++ if (IS_ERR_OR_NULL(edev)) { ++ return; ++ } ++ ++ if (disconnect || !dp->data.conf) { ++ extcon_set_state_sync(edev, EXTCON_DISP_DP, false); ++ } else { ++ union extcon_property_value extcon_true = { .intval = true }; ++ extcon_set_state(edev, EXTCON_DISP_DP, true); ++ if (DP_CONF_GET_PIN_ASSIGN(dp->data.conf) & DP_PIN_ASSIGN_MULTI_FUNC_MASK) { ++ extcon_set_state_sync(edev, EXTCON_USB_HOST, true); ++ extcon_set_property(edev, EXTCON_DISP_DP, EXTCON_PROP_USB_SS, ++ extcon_true); ++ } else { ++ extcon_set_state_sync(edev, EXTCON_USB_HOST, false); ++ } ++ extcon_sync(edev, EXTCON_DISP_DP); ++ extcon_set_state_sync(edev, EXTCON_USB, false); ++ } ++ ++} ++ + static int dp_altmode_configured(struct dp_altmode *dp) + { + sysfs_notify(&dp->alt->dev.kobj, "displayport", "configuration"); +@@ -242,6 +282,8 @@ static void dp_altmode_work(struct work_struct *work) + case DP_STATE_EXIT: + if (typec_altmode_exit(dp->alt)) + dev_err(&dp->alt->dev, "Exit Mode Failed!\n"); ++ else ++ dp_altmode_update_extcon(dp, true); + break; + default: + break; +@@ -574,8 +616,14 @@ int dp_altmode_probe(struct typec_altmode *alt) + if (!(DP_CAP_PIN_ASSIGN_DFP_D(port->vdo) & + DP_CAP_PIN_ASSIGN_UFP_D(alt->vdo)) && + !(DP_CAP_PIN_ASSIGN_UFP_D(port->vdo) & +- DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo))) +- return -ENODEV; ++ DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo))) { ++ dev_err(&alt->dev, "No compatible pin configuration found:"\ ++ "%04lx -> %04lx, %04lx <- %04lx", ++ DP_CAP_PIN_ASSIGN_DFP_D(port->vdo), DP_CAP_PIN_ASSIGN_UFP_D(alt->vdo), ++ DP_CAP_PIN_ASSIGN_UFP_D(port->vdo), DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo)); ++ return -ENODEV; ++ } ++ + + ret = sysfs_create_group(&alt->dev.kobj, &dp_altmode_group); + if (ret) +diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c +index 1596afee6c86..f4c41de58f17 100644 +--- a/drivers/usb/typec/tcpm/tcpm.c ++++ b/drivers/usb/typec/tcpm/tcpm.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -492,6 +493,12 @@ struct tcpm_port { + * transitions. + */ + bool potential_contaminant; ++ ++#ifdef CONFIG_EXTCON ++ struct extcon_dev *extcon; ++ unsigned int *extcon_cables; ++#endif ++ + #ifdef CONFIG_DEBUG_FS + struct dentry *dentry; + struct mutex logbuffer_lock; /* log buffer access lock */ +@@ -879,6 +886,35 @@ static void tcpm_ams_finish(struct tcpm_port *port) + port->ams = NONE_AMS; + } + ++static void tcpm_update_extcon_data(struct tcpm_port *port, bool attached) { ++#ifdef CONFIG_EXTCON ++ unsigned int *capability = port->extcon_cables; ++ if (port->data_role == TYPEC_HOST) { ++ extcon_set_state(port->extcon, EXTCON_USB, false); ++ extcon_set_state(port->extcon, EXTCON_USB_HOST, attached); ++ } else { ++ extcon_set_state(port->extcon, EXTCON_USB, true); ++ extcon_set_state(port->extcon, EXTCON_USB_HOST, attached); ++ } ++ while (*capability != EXTCON_NONE) { ++ if (attached) { ++ union extcon_property_value val; ++ val.intval = (port->polarity == TYPEC_POLARITY_CC2); ++ extcon_set_property(port->extcon, *capability, ++ EXTCON_PROP_USB_TYPEC_POLARITY, val); ++ } else { ++ extcon_set_state(port->extcon, *capability, false); ++ } ++ extcon_sync(port->extcon, *capability); ++ capability++; ++ } ++ tcpm_log(port, "Extcon update (%s): %s, %s", ++ attached ? "attached" : "detached", ++ port->data_role == TYPEC_HOST ? "host" : "device", ++ port->polarity == TYPEC_POLARITY_CC1 ? "normal" : "flipped"); ++#endif ++} ++ + static int tcpm_pd_transmit(struct tcpm_port *port, + enum tcpm_transmit_type type, + const struct pd_message *msg) +@@ -1091,6 +1127,8 @@ static int tcpm_set_roles(struct tcpm_port *port, bool attached, + typec_set_data_role(port->typec_port, data); + typec_set_pwr_role(port->typec_port, role); + ++ tcpm_update_extcon_data(port, attached); ++ + return 0; + } + +@@ -1562,7 +1600,7 @@ static void svdm_consume_modes(struct tcpm_port *port, const u32 *p, int cnt) + paltmode->mode = i; + paltmode->vdo = p[i]; + +- tcpm_log(port, " Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x", ++ tcpm_log(port, "Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x", + pmdata->altmodes, paltmode->svid, + paltmode->mode, paltmode->vdo); + +@@ -1583,6 +1621,8 @@ static void tcpm_register_partner_altmodes(struct tcpm_port *port) + tcpm_log(port, "Failed to register partner SVID 0x%04x", + modep->altmode_desc[i].svid); + altmode = NULL; ++ } else { ++ tcpm_log(port, "Registered altmode 0x%04x", modep->altmode_desc[i].svid); + } + port->partner_altmode[i] = altmode; + } +@@ -1717,9 +1757,11 @@ static int tcpm_pd_svdm(struct tcpm_port *port, struct typec_altmode *adev, + modep->svid_index++; + if (modep->svid_index < modep->nsvids) { + u16 svid = modep->svids[modep->svid_index]; ++ tcpm_log(port, "More modes available, sending discover"); + response[0] = VDO(svid, 1, svdm_version, CMD_DISCOVER_MODES); + rlen = 1; + } else { ++ tcpm_log(port, "Got all patner modes, registering"); + tcpm_register_partner_altmodes(port); + } + break; +@@ -3720,6 +3762,7 @@ static int tcpm_src_attach(struct tcpm_port *port) + static void tcpm_typec_disconnect(struct tcpm_port *port) + { + if (port->connected) { ++ tcpm_update_extcon_data(port, false); + typec_partner_set_usb_power_delivery(port->partner, NULL); + typec_unregister_partner(port->partner); + port->partner = NULL; +@@ -3806,6 +3849,8 @@ static void tcpm_detach(struct tcpm_port *port) + } + + tcpm_reset_port(port); ++ ++ tcpm_update_extcon_data(port, false); + } + + static void tcpm_src_detach(struct tcpm_port *port) +@@ -6179,6 +6224,64 @@ static int tcpm_port_register_pd(struct tcpm_port *port) + return ret; + } + ++unsigned int default_supported_cables[] = { ++ EXTCON_NONE ++}; ++ ++static int tcpm_fw_get_caps_late(struct tcpm_port *port, ++ struct fwnode_handle *fwnode) ++{ ++ int ret, i; ++ ret = fwnode_property_count_u32(fwnode, "typec-altmodes"); ++ if (ret > 0) { ++ u32 *props; ++ if (ret % 4) { ++ dev_err(port->dev, "Length of typec altmode array must be divisible by 4"); ++ return -EINVAL; ++ } ++ ++ props = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL); ++ if (!props) { ++ dev_err(port->dev, "Failed to allocate memory for altmode properties"); ++ return -ENOMEM; ++ } ++ ++ if(fwnode_property_read_u32_array(fwnode, "typec-altmodes", props, ret) < 0) { ++ dev_err(port->dev, "Failed to read altmodes from port"); ++ return -EINVAL; ++ } ++ ++ i = 0; ++ while (ret > 0 && i < ARRAY_SIZE(port->port_altmode)) { ++ struct typec_altmode *alt; ++ struct typec_altmode_desc alt_desc = { ++ .svid = props[i * 4], ++ .mode = props[i * 4 + 1], ++ .vdo = props[i * 4 + 2], ++ .roles = props[i * 4 + 3], ++ }; ++ ++ ++ tcpm_log(port, "Adding altmode SVID: 0x%04x, mode: %d, vdo: %u, role: %d", ++ alt_desc.svid, alt_desc.mode, alt_desc.vdo, alt_desc.roles); ++ alt = typec_port_register_altmode(port->typec_port, ++ &alt_desc); ++ if (IS_ERR(alt)) { ++ tcpm_log(port, ++ "%s: failed to register port alternate mode 0x%x", ++ dev_name(port->dev), alt_desc.svid); ++ break; ++ } ++ typec_altmode_set_drvdata(alt, port); ++ alt->ops = &tcpm_altmode_ops; ++ port->port_altmode[i] = alt; ++ i++; ++ ret -= 4; ++ } ++ } ++ return 0; ++} ++ + static int tcpm_fw_get_caps(struct tcpm_port *port, + struct fwnode_handle *fwnode) + { +@@ -6189,6 +6292,23 @@ static int tcpm_fw_get_caps(struct tcpm_port *port, + if (!fwnode) + return -EINVAL; + ++#ifdef CONFIG_EXTCON ++ ret = fwnode_property_count_u32(fwnode, "extcon-cables"); ++ if (ret > 0) { ++ port->extcon_cables = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL); ++ if (!port->extcon_cables) { ++ dev_err(port->dev, "Failed to allocate memory for extcon cable types. "\ ++ "Using default tyes"); ++ goto extcon_default; ++ } ++ fwnode_property_read_u32_array(fwnode, "extcon-cables", port->extcon_cables, ret); ++ } else { ++extcon_default: ++ dev_info(port->dev, "No cable types defined, using default cables"); ++ port->extcon_cables = default_supported_cables; ++ } ++#endif ++ + /* + * This fwnode has a "compatible" property, but is never populated as a + * struct device. Instead we simply parse it to read the properties. +@@ -6645,6 +6765,17 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc) + goto out_destroy_wq; + + port->try_role = port->typec_caps.prefer_role; ++#ifdef CONFIG_EXTCON ++ port->extcon = devm_extcon_dev_allocate(dev, port->extcon_cables); ++ if (IS_ERR(port->extcon)) { ++ dev_err(dev, "Failed to allocate extcon device: %ld", PTR_ERR(port->extcon)); ++ goto out_destroy_wq; ++ } ++ if((err = devm_extcon_dev_register(dev, port->extcon))) { ++ dev_err(dev, "Failed to register extcon device: %d", err); ++ goto out_destroy_wq; ++ } ++#endif + + port->typec_caps.fwnode = tcpc->fwnode; + port->typec_caps.revision = 0x0120; /* Type-C spec release 1.2 */ +@@ -6687,6 +6818,12 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc) + port->port_altmode, ALTMODE_DISCOVERY_MAX); + port->registered = true; + ++ err = tcpm_fw_get_caps_late(port, tcpc->fwnode); ++ if (err < 0) { ++ dev_err(dev, "Failed to get altmodes from fwnode"); ++ goto out_destroy_wq; ++ } ++ + mutex_lock(&port->lock); + tcpm_init(port); + mutex_unlock(&port->lock); +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-radxa-e25-sdmmc0-fix.patch b/patch/kernel/archive/rockchip64-6.6/board-radxa-e25-sdmmc0-fix.patch new file mode 100644 index 000000000..41758a620 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-radxa-e25-sdmmc0-fix.patch @@ -0,0 +1,35 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: krachlatte +Date: Wed, 17 May 2023 00:55:30 +0200 +Subject: [ARCHEOLOGY] Improve SD card compatibility on Radxa E25 (#5165) + +> X-Git-Archeology: - Revision 45c85878613108c238e491aa69650fcad1fba4bb: https://github.com/armbian/build/commit/45c85878613108c238e491aa69650fcad1fba4bb +> X-Git-Archeology: Date: Wed, 17 May 2023 00:55:30 +0200 +> X-Git-Archeology: From: krachlatte +> X-Git-Archeology: Subject: Improve SD card compatibility on Radxa E25 (#5165) +> X-Git-Archeology: +> X-Git-Archeology: - Revision f6a0c53d08f53aadd0588a571662dc199232825b: https://github.com/armbian/build/commit/f6a0c53d08f53aadd0588a571662dc199232825b +> X-Git-Archeology: Date: Wed, 24 May 2023 10:39:21 +0200 +> X-Git-Archeology: From: Ricardo Pardini +> X-Git-Archeology: Subject: manual e25 patch fix +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +index 72ad74c38a2b..5751dc7e2ebc 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +@@ -194,7 +194,7 @@ &sdmmc0 { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; +- sd-uhs-sdr104; ++ sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-radxa-e25-usb3-and-emmc-fix.patch b/patch/kernel/archive/rockchip64-6.6/board-radxa-e25-usb3-and-emmc-fix.patch new file mode 100644 index 000000000..afd5918a0 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-radxa-e25-usb3-and-emmc-fix.patch @@ -0,0 +1,64 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: krachlatte +Date: Wed, 17 May 2023 00:55:30 +0200 +Subject: [ARCHEOLOGY] Improve SD card compatibility on Radxa E25 (#5165) + +> X-Git-Archeology: - Revision 45c85878613108c238e491aa69650fcad1fba4bb: https://github.com/armbian/build/commit/45c85878613108c238e491aa69650fcad1fba4bb +> X-Git-Archeology: Date: Wed, 17 May 2023 00:55:30 +0200 +> X-Git-Archeology: From: krachlatte +> X-Git-Archeology: Subject: Improve SD card compatibility on Radxa E25 (#5165) +> X-Git-Archeology: +> X-Git-Archeology: - Revision f6a0c53d08f53aadd0588a571662dc199232825b: https://github.com/armbian/build/commit/f6a0c53d08f53aadd0588a571662dc199232825b +> X-Git-Archeology: Date: Wed, 24 May 2023 10:39:21 +0200 +> X-Git-Archeology: From: Ricardo Pardini +> X-Git-Archeology: Subject: manual e25 patch fix +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 12 ++++++++++ + arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 ++ + 2 files changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi +index 45b03dcbbad4..ffae714d56dc 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi +@@ -389,6 +389,17 @@ &sdhci { + status = "okay"; + }; + ++&sfc { ++ status = "okay"; ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <108000000>; ++ spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <2>; ++ }; ++}; ++ + &tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; +@@ -409,4 +420,5 @@ &usb2phy1 { + + &usb_host0_xhci { + extcon = <&usb2phy0>; ++ dr_mode = "host"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +index 5751dc7e2ebc..7d7d00adf10a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +@@ -209,6 +209,8 @@ &usb_host0_ohci { + }; + + &usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ dr_mode = "host"; + status = "okay"; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-cc-dts-enable-dmc.patch b/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-cc-dts-enable-dmc.patch new file mode 100644 index 000000000..658c3e15c --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-cc-dts-enable-dmc.patch @@ -0,0 +1,75 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Tue, 12 Oct 2021 18:31:28 +0000 +Subject: enable roc-cc dmc + +--- + arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 38 ++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +index 5d5d9574088c..be5d064d6a93 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -4,6 +4,7 @@ + */ + + /dts-v1/; ++#include "rk3328-dram-renegade-timing.dtsi" + #include "rk3328.dtsi" + + / { +@@ -19,6 +20,32 @@ chosen { + stdout-path = "serial2:1500000n8"; + }; + ++ /delete-node/ dmc-opp-table; ++ dmc_opp_table: dmc-opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-786000000 { ++ opp-hz = /bits/ 64 <786000000>; ++ opp-microvolt = <1075000 1075000 12000000>; ++ }; ++ opp-798000000 { ++ opp-hz = /bits/ 64 <798000000>; ++ opp-microvolt = <1075000 1075000 12000000>; ++ }; ++ opp-840000000 { ++ opp-hz = /bits/ 64 <840000000>; ++ opp-microvolt = <1075000 1075000 12000000>; ++ }; ++ opp-924000000 { ++ opp-hz = /bits/ 64 <924000000>; ++ opp-microvolt = <1100000 1100000 12000000>; ++ }; ++ opp-1068000000 { ++ opp-hz = /bits/ 64 <1068000000>; ++ opp-microvolt = <1175000 1175000 12000000>; ++ }; ++ }; ++ + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; +@@ -115,6 +142,17 @@ &codec { + status = "okay"; + }; + ++&dfi { ++ status = "okay"; ++}; ++ ++&dmc { ++ center-supply = <&vdd_logic>; ++ ddr_timing = <&ddr_timing>; ++ status = "okay"; ++}; ++ ++ + &cpu0 { + cpu-supply = <&vdd_arm>; + }; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-cc-dts-ram-profile.patch b/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-cc-dts-ram-profile.patch new file mode 100644 index 000000000..71b23c423 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-cc-dts-ram-profile.patch @@ -0,0 +1,330 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: tonymac32 +Date: Wed, 7 Oct 2020 23:39:54 -0400 +Subject: board-rk3328-roc-cc-adjust-DMC-opps + +Signed-off-by: tonymac32 +--- + arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi | 311 ++++++++++ + 1 file changed, 311 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi +new file mode 100644 +index 000000000000..303428153094 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-dram-renegade-timing.dtsi +@@ -0,0 +1,311 @@ ++/* ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++ ++/ { ++ ddr_timing: ddr_timing { ++ compatible = "rockchip,ddr-timing"; ++ ddr3_speed_bin = ; ++ ddr4_speed_bin = ; ++ pd_idle = <0>; ++ sr_idle = <0>; ++ sr_mc_gate_idle = <0>; ++ srpd_lite_idle = <0>; ++ standby_idle = <0>; ++ ++ auto_pd_dis_freq = <1066>; ++ auto_sr_dis_freq = <800>; ++ ddr3_dll_dis_freq = <300>; ++ ddr4_dll_dis_freq = <625>; ++ phy_dll_dis_freq = <400>; ++ ++ ddr3_odt_dis_freq = <100>; ++ phy_ddr3_odt_dis_freq = <100>; ++ ddr3_drv = ; ++ ddr3_odt = ; ++ phy_ddr3_ca_drv = ; ++ phy_ddr3_ck_drv = ; ++ phy_ddr3_dq_drv = ; ++ phy_ddr3_odt = ; ++ ++ lpddr3_odt_dis_freq = <666>; ++ phy_lpddr3_odt_dis_freq = <666>; ++ lpddr3_drv = ; ++ lpddr3_odt = ; ++ phy_lpddr3_ca_drv = ; ++ phy_lpddr3_ck_drv = ; ++ phy_lpddr3_dq_drv = ; ++ phy_lpddr3_odt = ; ++ ++ lpddr4_odt_dis_freq = <800>; ++ phy_lpddr4_odt_dis_freq = <800>; ++ lpddr4_drv = ; ++ lpddr4_dq_odt = ; ++ lpddr4_ca_odt = ; ++ phy_lpddr4_ca_drv = ; ++ phy_lpddr4_ck_cs_drv = ; ++ phy_lpddr4_dq_drv = ; ++ phy_lpddr4_odt = ; ++ ++ ddr4_odt_dis_freq = <666>; ++ phy_ddr4_odt_dis_freq = <666>; ++ ddr4_drv = ; ++ ddr4_odt = ; ++ phy_ddr4_ca_drv = ; ++ phy_ddr4_ck_drv = ; ++ phy_ddr4_dq_drv = ; ++ phy_ddr4_odt = ; ++ ++ /* CA de-skew, one step is 47.8ps, range 0-15 */ ++ ddr3a1_ddr4a9_de-skew = <0>; ++ ddr3a0_ddr4a10_de-skew = <0>; ++ ddr3a3_ddr4a6_de-skew = <1>; ++ ddr3a2_ddr4a4_de-skew = <1>; ++ ddr3a5_ddr4a8_de-skew = <0>; ++ ddr3a4_ddr4a5_de-skew = <2>; ++ ddr3a7_ddr4a11_de-skew = <0>; ++ ddr3a6_ddr4a7_de-skew = <2>; ++ ddr3a9_ddr4a0_de-skew = <1>; ++ ddr3a8_ddr4a13_de-skew = <0>; ++ ddr3a11_ddr4a3_de-skew = <2>; ++ ddr3a10_ddr4cs0_de-skew = <0>; ++ ddr3a13_ddr4a2_de-skew = <1>; ++ ddr3a12_ddr4ba1_de-skew = <0>; ++ ddr3a15_ddr4odt0_de-skew = <0>; ++ ddr3a14_ddr4a1_de-skew = <1>; ++ ddr3ba1_ddr4a15_de-skew = <0>; ++ ddr3ba0_ddr4bg0_de-skew = <0>; ++ ddr3ras_ddr4cke_de-skew = <0>; ++ ddr3ba2_ddr4ba0_de-skew = <1>; ++ ddr3we_ddr4bg1_de-skew = <1>; ++ ddr3cas_ddr4a12_de-skew = <0>; ++ ddr3ckn_ddr4ckn_de-skew = <5>; ++ ddr3ckp_ddr4ckp_de-skew = <5>; ++ ddr3cke_ddr4a16_de-skew = <1>; ++ ddr3odt0_ddr4a14_de-skew = <0>; ++ ddr3cs0_ddr4act_de-skew = <1>; ++ ddr3reset_ddr4reset_de-skew = <0>; ++ ddr3cs1_ddr4cs1_de-skew = <0>; ++ ddr3odt1_ddr4odt1_de-skew = <0>; ++ ++ /* DATA de-skew ++ * RX one step is 25.1ps, range 0-15 ++ * TX one step is 47.8ps, range 0-15 ++ */ ++ cs0_dm0_rx_de-skew = <7>; ++ cs0_dm0_tx_de-skew = <8>; ++ cs0_dq0_rx_de-skew = <7>; ++ cs0_dq0_tx_de-skew = <8>; ++ cs0_dq1_rx_de-skew = <7>; ++ cs0_dq1_tx_de-skew = <8>; ++ cs0_dq2_rx_de-skew = <7>; ++ cs0_dq2_tx_de-skew = <8>; ++ cs0_dq3_rx_de-skew = <7>; ++ cs0_dq3_tx_de-skew = <8>; ++ cs0_dq4_rx_de-skew = <7>; ++ cs0_dq4_tx_de-skew = <8>; ++ cs0_dq5_rx_de-skew = <7>; ++ cs0_dq5_tx_de-skew = <8>; ++ cs0_dq6_rx_de-skew = <7>; ++ cs0_dq6_tx_de-skew = <8>; ++ cs0_dq7_rx_de-skew = <7>; ++ cs0_dq7_tx_de-skew = <8>; ++ cs0_dqs0_rx_de-skew = <6>; ++ cs0_dqs0p_tx_de-skew = <9>; ++ cs0_dqs0n_tx_de-skew = <9>; ++ ++ cs0_dm1_rx_de-skew = <7>; ++ cs0_dm1_tx_de-skew = <7>; ++ cs0_dq8_rx_de-skew = <7>; ++ cs0_dq8_tx_de-skew = <8>; ++ cs0_dq9_rx_de-skew = <7>; ++ cs0_dq9_tx_de-skew = <7>; ++ cs0_dq10_rx_de-skew = <7>; ++ cs0_dq10_tx_de-skew = <8>; ++ cs0_dq11_rx_de-skew = <7>; ++ cs0_dq11_tx_de-skew = <7>; ++ cs0_dq12_rx_de-skew = <7>; ++ cs0_dq12_tx_de-skew = <8>; ++ cs0_dq13_rx_de-skew = <7>; ++ cs0_dq13_tx_de-skew = <7>; ++ cs0_dq14_rx_de-skew = <7>; ++ cs0_dq14_tx_de-skew = <8>; ++ cs0_dq15_rx_de-skew = <7>; ++ cs0_dq15_tx_de-skew = <7>; ++ cs0_dqs1_rx_de-skew = <7>; ++ cs0_dqs1p_tx_de-skew = <9>; ++ cs0_dqs1n_tx_de-skew = <9>; ++ ++ cs0_dm2_rx_de-skew = <7>; ++ cs0_dm2_tx_de-skew = <8>; ++ cs0_dq16_rx_de-skew = <7>; ++ cs0_dq16_tx_de-skew = <8>; ++ cs0_dq17_rx_de-skew = <7>; ++ cs0_dq17_tx_de-skew = <8>; ++ cs0_dq18_rx_de-skew = <7>; ++ cs0_dq18_tx_de-skew = <8>; ++ cs0_dq19_rx_de-skew = <7>; ++ cs0_dq19_tx_de-skew = <8>; ++ cs0_dq20_rx_de-skew = <7>; ++ cs0_dq20_tx_de-skew = <8>; ++ cs0_dq21_rx_de-skew = <7>; ++ cs0_dq21_tx_de-skew = <8>; ++ cs0_dq22_rx_de-skew = <7>; ++ cs0_dq22_tx_de-skew = <8>; ++ cs0_dq23_rx_de-skew = <7>; ++ cs0_dq23_tx_de-skew = <8>; ++ cs0_dqs2_rx_de-skew = <6>; ++ cs0_dqs2p_tx_de-skew = <9>; ++ cs0_dqs2n_tx_de-skew = <9>; ++ ++ cs0_dm3_rx_de-skew = <7>; ++ cs0_dm3_tx_de-skew = <7>; ++ cs0_dq24_rx_de-skew = <7>; ++ cs0_dq24_tx_de-skew = <8>; ++ cs0_dq25_rx_de-skew = <7>; ++ cs0_dq25_tx_de-skew = <7>; ++ cs0_dq26_rx_de-skew = <7>; ++ cs0_dq26_tx_de-skew = <7>; ++ cs0_dq27_rx_de-skew = <7>; ++ cs0_dq27_tx_de-skew = <7>; ++ cs0_dq28_rx_de-skew = <7>; ++ cs0_dq28_tx_de-skew = <7>; ++ cs0_dq29_rx_de-skew = <7>; ++ cs0_dq29_tx_de-skew = <7>; ++ cs0_dq30_rx_de-skew = <7>; ++ cs0_dq30_tx_de-skew = <7>; ++ cs0_dq31_rx_de-skew = <7>; ++ cs0_dq31_tx_de-skew = <7>; ++ cs0_dqs3_rx_de-skew = <7>; ++ cs0_dqs3p_tx_de-skew = <9>; ++ cs0_dqs3n_tx_de-skew = <9>; ++ ++ cs1_dm0_rx_de-skew = <7>; ++ cs1_dm0_tx_de-skew = <8>; ++ cs1_dq0_rx_de-skew = <7>; ++ cs1_dq0_tx_de-skew = <8>; ++ cs1_dq1_rx_de-skew = <7>; ++ cs1_dq1_tx_de-skew = <8>; ++ cs1_dq2_rx_de-skew = <7>; ++ cs1_dq2_tx_de-skew = <8>; ++ cs1_dq3_rx_de-skew = <7>; ++ cs1_dq3_tx_de-skew = <8>; ++ cs1_dq4_rx_de-skew = <7>; ++ cs1_dq4_tx_de-skew = <8>; ++ cs1_dq5_rx_de-skew = <7>; ++ cs1_dq5_tx_de-skew = <8>; ++ cs1_dq6_rx_de-skew = <7>; ++ cs1_dq6_tx_de-skew = <8>; ++ cs1_dq7_rx_de-skew = <7>; ++ cs1_dq7_tx_de-skew = <8>; ++ cs1_dqs0_rx_de-skew = <6>; ++ cs1_dqs0p_tx_de-skew = <9>; ++ cs1_dqs0n_tx_de-skew = <9>; ++ ++ cs1_dm1_rx_de-skew = <7>; ++ cs1_dm1_tx_de-skew = <7>; ++ cs1_dq8_rx_de-skew = <7>; ++ cs1_dq8_tx_de-skew = <8>; ++ cs1_dq9_rx_de-skew = <7>; ++ cs1_dq9_tx_de-skew = <7>; ++ cs1_dq10_rx_de-skew = <7>; ++ cs1_dq10_tx_de-skew = <8>; ++ cs1_dq11_rx_de-skew = <7>; ++ cs1_dq11_tx_de-skew = <7>; ++ cs1_dq12_rx_de-skew = <7>; ++ cs1_dq12_tx_de-skew = <8>; ++ cs1_dq13_rx_de-skew = <7>; ++ cs1_dq13_tx_de-skew = <7>; ++ cs1_dq14_rx_de-skew = <7>; ++ cs1_dq14_tx_de-skew = <8>; ++ cs1_dq15_rx_de-skew = <7>; ++ cs1_dq15_tx_de-skew = <7>; ++ cs1_dqs1_rx_de-skew = <7>; ++ cs1_dqs1p_tx_de-skew = <9>; ++ cs1_dqs1n_tx_de-skew = <9>; ++ ++ cs1_dm2_rx_de-skew = <7>; ++ cs1_dm2_tx_de-skew = <8>; ++ cs1_dq16_rx_de-skew = <7>; ++ cs1_dq16_tx_de-skew = <8>; ++ cs1_dq17_rx_de-skew = <7>; ++ cs1_dq17_tx_de-skew = <8>; ++ cs1_dq18_rx_de-skew = <7>; ++ cs1_dq18_tx_de-skew = <8>; ++ cs1_dq19_rx_de-skew = <7>; ++ cs1_dq19_tx_de-skew = <8>; ++ cs1_dq20_rx_de-skew = <7>; ++ cs1_dq20_tx_de-skew = <8>; ++ cs1_dq21_rx_de-skew = <7>; ++ cs1_dq21_tx_de-skew = <8>; ++ cs1_dq22_rx_de-skew = <7>; ++ cs1_dq22_tx_de-skew = <8>; ++ cs1_dq23_rx_de-skew = <7>; ++ cs1_dq23_tx_de-skew = <8>; ++ cs1_dqs2_rx_de-skew = <6>; ++ cs1_dqs2p_tx_de-skew = <9>; ++ cs1_dqs2n_tx_de-skew = <9>; ++ ++ cs1_dm3_rx_de-skew = <7>; ++ cs1_dm3_tx_de-skew = <7>; ++ cs1_dq24_rx_de-skew = <7>; ++ cs1_dq24_tx_de-skew = <8>; ++ cs1_dq25_rx_de-skew = <7>; ++ cs1_dq25_tx_de-skew = <7>; ++ cs1_dq26_rx_de-skew = <7>; ++ cs1_dq26_tx_de-skew = <7>; ++ cs1_dq27_rx_de-skew = <7>; ++ cs1_dq27_tx_de-skew = <7>; ++ cs1_dq28_rx_de-skew = <7>; ++ cs1_dq28_tx_de-skew = <7>; ++ cs1_dq29_rx_de-skew = <7>; ++ cs1_dq29_tx_de-skew = <7>; ++ cs1_dq30_rx_de-skew = <7>; ++ cs1_dq30_tx_de-skew = <7>; ++ cs1_dq31_rx_de-skew = <7>; ++ cs1_dq31_tx_de-skew = <7>; ++ cs1_dqs3_rx_de-skew = <7>; ++ cs1_dqs3p_tx_de-skew = <9>; ++ cs1_dqs3n_tx_de-skew = <9>; ++ }; ++}; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-pc-dts-ram-profile.patch b/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-pc-dts-ram-profile.patch new file mode 100644 index 000000000..872a1574b --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-pc-dts-ram-profile.patch @@ -0,0 +1,301 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tony +Date: Thu, 8 Oct 2020 01:56:28 -0400 +Subject: [ARCHEOLOGY] Add files via upload + +> X-Git-Archeology: - Revision 8fc20a15b12561e76e92d5bd29b5afd1c62f08ac: https://github.com/armbian/build/commit/8fc20a15b12561e76e92d5bd29b5afd1c62f08ac +> X-Git-Archeology: Date: Thu, 08 Oct 2020 01:56:28 -0400 +> X-Git-Archeology: From: Tony +> X-Git-Archeology: Subject: Add files via upload +> X-Git-Archeology: +> X-Git-Archeology: - Revision 2788adccedc25f12fc9e71e01a92863d97683979: https://github.com/armbian/build/commit/2788adccedc25f12fc9e71e01a92863d97683979 +> X-Git-Archeology: Date: Tue, 26 Jan 2021 21:22:04 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Enable DMC for Station M1 in current and dev (#2575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 +> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 +> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi | 223 ++++++++++ + 1 file changed, 223 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi +new file mode 100644 +index 000000000000..8b2077d086f5 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi +@@ -0,0 +1,223 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ */ ++#include ++#include ++ ++/ { ++ ddr_timing: ddr_timing { ++ /* CA de-skew, one step is 47.8ps, range 0-15 */ ++ ddr3a1_ddr4a9_de-skew = <0>; ++ ddr3a0_ddr4a10_de-skew = <0>; ++ ddr3a3_ddr4a6_de-skew = <1>; ++ ddr3a2_ddr4a4_de-skew = <1>; ++ ddr3a5_ddr4a8_de-skew = <0>; ++ ddr3a4_ddr4a5_de-skew = <2>; ++ ddr3a7_ddr4a11_de-skew = <0>; ++ ddr3a6_ddr4a7_de-skew = <2>; ++ ddr3a9_ddr4a0_de-skew = <1>; ++ ddr3a8_ddr4a13_de-skew = <0>; ++ ddr3a11_ddr4a3_de-skew = <2>; ++ ddr3a10_ddr4cs0_de-skew = <0>; ++ ddr3a13_ddr4a2_de-skew = <1>; ++ ddr3a12_ddr4ba1_de-skew = <0>; ++ ddr3a15_ddr4odt0_de-skew = <0>; ++ ddr3a14_ddr4a1_de-skew = <1>; ++ ddr3ba1_ddr4a15_de-skew = <0>; ++ ddr3ba0_ddr4bg0_de-skew = <0>; ++ ddr3ras_ddr4cke_de-skew = <0>; ++ ddr3ba2_ddr4ba0_de-skew = <1>; ++ ddr3we_ddr4bg1_de-skew = <1>; ++ ddr3cas_ddr4a12_de-skew = <0>; ++ ddr3ckn_ddr4ckn_de-skew = <5>; ++ ddr3ckp_ddr4ckp_de-skew = <5>; ++ ddr3cke_ddr4a16_de-skew = <1>; ++ ddr3odt0_ddr4a14_de-skew = <0>; ++ ddr3cs0_ddr4act_de-skew = <1>; ++ ddr3reset_ddr4reset_de-skew = <0>; ++ ddr3cs1_ddr4cs1_de-skew = <0>; ++ ddr3odt1_ddr4odt1_de-skew = <0>; ++ ++ /* DATA de-skew ++ * RX one step is 25.1ps, range 0-15 ++ * TX one step is 47.8ps, range 0-15 ++ */ ++ cs0_dm0_rx_de-skew = <7>; ++ cs0_dm0_tx_de-skew = <8>; ++ cs0_dq0_rx_de-skew = <7>; ++ cs0_dq0_tx_de-skew = <8>; ++ cs0_dq1_rx_de-skew = <7>; ++ cs0_dq1_tx_de-skew = <8>; ++ cs0_dq2_rx_de-skew = <7>; ++ cs0_dq2_tx_de-skew = <8>; ++ cs0_dq3_rx_de-skew = <7>; ++ cs0_dq3_tx_de-skew = <8>; ++ cs0_dq4_rx_de-skew = <7>; ++ cs0_dq4_tx_de-skew = <8>; ++ cs0_dq5_rx_de-skew = <7>; ++ cs0_dq5_tx_de-skew = <8>; ++ cs0_dq6_rx_de-skew = <7>; ++ cs0_dq6_tx_de-skew = <8>; ++ cs0_dq7_rx_de-skew = <7>; ++ cs0_dq7_tx_de-skew = <8>; ++ cs0_dqs0_rx_de-skew = <6>; ++ cs0_dqs0p_tx_de-skew = <9>; ++ cs0_dqs0n_tx_de-skew = <9>; ++ ++ cs0_dm1_rx_de-skew = <7>; ++ cs0_dm1_tx_de-skew = <7>; ++ cs0_dq8_rx_de-skew = <7>; ++ cs0_dq8_tx_de-skew = <8>; ++ cs0_dq9_rx_de-skew = <7>; ++ cs0_dq9_tx_de-skew = <7>; ++ cs0_dq10_rx_de-skew = <7>; ++ cs0_dq10_tx_de-skew = <8>; ++ cs0_dq11_rx_de-skew = <7>; ++ cs0_dq11_tx_de-skew = <7>; ++ cs0_dq12_rx_de-skew = <7>; ++ cs0_dq12_tx_de-skew = <8>; ++ cs0_dq13_rx_de-skew = <7>; ++ cs0_dq13_tx_de-skew = <7>; ++ cs0_dq14_rx_de-skew = <7>; ++ cs0_dq14_tx_de-skew = <8>; ++ cs0_dq15_rx_de-skew = <7>; ++ cs0_dq15_tx_de-skew = <7>; ++ cs0_dqs1_rx_de-skew = <7>; ++ cs0_dqs1p_tx_de-skew = <9>; ++ cs0_dqs1n_tx_de-skew = <9>; ++ ++ cs0_dm2_rx_de-skew = <7>; ++ cs0_dm2_tx_de-skew = <8>; ++ cs0_dq16_rx_de-skew = <7>; ++ cs0_dq16_tx_de-skew = <8>; ++ cs0_dq17_rx_de-skew = <7>; ++ cs0_dq17_tx_de-skew = <8>; ++ cs0_dq18_rx_de-skew = <7>; ++ cs0_dq18_tx_de-skew = <8>; ++ cs0_dq19_rx_de-skew = <7>; ++ cs0_dq19_tx_de-skew = <8>; ++ cs0_dq20_rx_de-skew = <7>; ++ cs0_dq20_tx_de-skew = <8>; ++ cs0_dq21_rx_de-skew = <7>; ++ cs0_dq21_tx_de-skew = <8>; ++ cs0_dq22_rx_de-skew = <7>; ++ cs0_dq22_tx_de-skew = <8>; ++ cs0_dq23_rx_de-skew = <7>; ++ cs0_dq23_tx_de-skew = <8>; ++ cs0_dqs2_rx_de-skew = <6>; ++ cs0_dqs2p_tx_de-skew = <9>; ++ cs0_dqs2n_tx_de-skew = <9>; ++ ++ cs0_dm3_rx_de-skew = <7>; ++ cs0_dm3_tx_de-skew = <7>; ++ cs0_dq24_rx_de-skew = <7>; ++ cs0_dq24_tx_de-skew = <8>; ++ cs0_dq25_rx_de-skew = <7>; ++ cs0_dq25_tx_de-skew = <7>; ++ cs0_dq26_rx_de-skew = <7>; ++ cs0_dq26_tx_de-skew = <7>; ++ cs0_dq27_rx_de-skew = <7>; ++ cs0_dq27_tx_de-skew = <7>; ++ cs0_dq28_rx_de-skew = <7>; ++ cs0_dq28_tx_de-skew = <7>; ++ cs0_dq29_rx_de-skew = <7>; ++ cs0_dq29_tx_de-skew = <7>; ++ cs0_dq30_rx_de-skew = <7>; ++ cs0_dq30_tx_de-skew = <7>; ++ cs0_dq31_rx_de-skew = <7>; ++ cs0_dq31_tx_de-skew = <7>; ++ cs0_dqs3_rx_de-skew = <7>; ++ cs0_dqs3p_tx_de-skew = <9>; ++ cs0_dqs3n_tx_de-skew = <9>; ++ ++ cs1_dm0_rx_de-skew = <7>; ++ cs1_dm0_tx_de-skew = <8>; ++ cs1_dq0_rx_de-skew = <7>; ++ cs1_dq0_tx_de-skew = <8>; ++ cs1_dq1_rx_de-skew = <7>; ++ cs1_dq1_tx_de-skew = <8>; ++ cs1_dq2_rx_de-skew = <7>; ++ cs1_dq2_tx_de-skew = <8>; ++ cs1_dq3_rx_de-skew = <7>; ++ cs1_dq3_tx_de-skew = <8>; ++ cs1_dq4_rx_de-skew = <7>; ++ cs1_dq4_tx_de-skew = <8>; ++ cs1_dq5_rx_de-skew = <7>; ++ cs1_dq5_tx_de-skew = <8>; ++ cs1_dq6_rx_de-skew = <7>; ++ cs1_dq6_tx_de-skew = <8>; ++ cs1_dq7_rx_de-skew = <7>; ++ cs1_dq7_tx_de-skew = <8>; ++ cs1_dqs0_rx_de-skew = <6>; ++ cs1_dqs0p_tx_de-skew = <9>; ++ cs1_dqs0n_tx_de-skew = <9>; ++ ++ cs1_dm1_rx_de-skew = <7>; ++ cs1_dm1_tx_de-skew = <7>; ++ cs1_dq8_rx_de-skew = <7>; ++ cs1_dq8_tx_de-skew = <8>; ++ cs1_dq9_rx_de-skew = <7>; ++ cs1_dq9_tx_de-skew = <7>; ++ cs1_dq10_rx_de-skew = <7>; ++ cs1_dq10_tx_de-skew = <8>; ++ cs1_dq11_rx_de-skew = <7>; ++ cs1_dq11_tx_de-skew = <7>; ++ cs1_dq12_rx_de-skew = <7>; ++ cs1_dq12_tx_de-skew = <8>; ++ cs1_dq13_rx_de-skew = <7>; ++ cs1_dq13_tx_de-skew = <7>; ++ cs1_dq14_rx_de-skew = <7>; ++ cs1_dq14_tx_de-skew = <8>; ++ cs1_dq15_rx_de-skew = <7>; ++ cs1_dq15_tx_de-skew = <7>; ++ cs1_dqs1_rx_de-skew = <7>; ++ cs1_dqs1p_tx_de-skew = <9>; ++ cs1_dqs1n_tx_de-skew = <9>; ++ ++ cs1_dm2_rx_de-skew = <7>; ++ cs1_dm2_tx_de-skew = <8>; ++ cs1_dq16_rx_de-skew = <7>; ++ cs1_dq16_tx_de-skew = <8>; ++ cs1_dq17_rx_de-skew = <7>; ++ cs1_dq17_tx_de-skew = <8>; ++ cs1_dq18_rx_de-skew = <7>; ++ cs1_dq18_tx_de-skew = <8>; ++ cs1_dq19_rx_de-skew = <7>; ++ cs1_dq19_tx_de-skew = <8>; ++ cs1_dq20_rx_de-skew = <7>; ++ cs1_dq20_tx_de-skew = <8>; ++ cs1_dq21_rx_de-skew = <7>; ++ cs1_dq21_tx_de-skew = <8>; ++ cs1_dq22_rx_de-skew = <7>; ++ cs1_dq22_tx_de-skew = <8>; ++ cs1_dq23_rx_de-skew = <7>; ++ cs1_dq23_tx_de-skew = <8>; ++ cs1_dqs2_rx_de-skew = <6>; ++ cs1_dqs2p_tx_de-skew = <9>; ++ cs1_dqs2n_tx_de-skew = <9>; ++ ++ cs1_dm3_rx_de-skew = <7>; ++ cs1_dm3_tx_de-skew = <7>; ++ cs1_dq24_rx_de-skew = <7>; ++ cs1_dq24_tx_de-skew = <8>; ++ cs1_dq25_rx_de-skew = <7>; ++ cs1_dq25_tx_de-skew = <7>; ++ cs1_dq26_rx_de-skew = <7>; ++ cs1_dq26_tx_de-skew = <7>; ++ cs1_dq27_rx_de-skew = <7>; ++ cs1_dq27_tx_de-skew = <7>; ++ cs1_dq28_rx_de-skew = <7>; ++ cs1_dq28_tx_de-skew = <7>; ++ cs1_dq29_rx_de-skew = <7>; ++ cs1_dq29_tx_de-skew = <7>; ++ cs1_dq30_rx_de-skew = <7>; ++ cs1_dq30_tx_de-skew = <7>; ++ cs1_dq31_rx_de-skew = <7>; ++ cs1_dq31_tx_de-skew = <7>; ++ cs1_dqs3_rx_de-skew = <7>; ++ cs1_dqs3p_tx_de-skew = <9>; ++ cs1_dqs3n_tx_de-skew = <9>; ++ }; ++}; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-pc.patch b/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-pc.patch new file mode 100644 index 000000000..43892ae48 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rk3328-roc-pc.patch @@ -0,0 +1,593 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Tue, 12 Oct 2021 19:34:29 +0000 +Subject: enable dmc for rk3328-roc-pc + +--- + arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 525 ++++++++-- + 1 file changed, 466 insertions(+), 59 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts +index e3e3984d01d4..02047f049822 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts +@@ -1,110 +1,517 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd ++/* ++ * SPDX-License-Identifier: (GPL-2.0+ or MIT) ++ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd ++ */ + + /dts-v1/; +- ++#include "rk3328-roc-pc-dram-timing.dtsi" ++#include "rk3328.dtsi" + #include + +-#include "rk3328-roc-cc.dts" +- + / { +- model = "Firefly ROC-RK3328-PC"; ++ model = "Firefly roc-rk3328-pc"; + compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328"; + +- adc-keys { +- compatible = "adc-keys"; +- io-channels = <&saradc 0>; +- io-channel-names = "buttons"; +- keyup-threshold-microvolt = <1750000>; ++ aliases { ++ mmc0 = &sdmmc; ++ mmc1 = &emmc; /* MMC boot device */ ++ }; ++ ++ gmac_clkin: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,name = "rockchip,rk3328"; ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&codec>; ++ }; ++ }; + +- /* This button is unpopulated out of the factory. */ +- button-recovery { +- label = "Recovery"; +- linux,code = ; +- press-threshold-microvolt = <10000>; ++ hdmi-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,name = "rockchip,hdmi"; ++ simple-audio-card,cpu { ++ sound-dai = <&i2s0>; + }; ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ }; ++ ++ vcc_host_5v: vcc-host-5v-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb30_host_drv>; ++ regulator-name = "vcc_host_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_phy"; ++ regulator-always-on; ++ regulator-boot-on; + }; + +- ir-receiver { +- compatible = "gpio-ir-receiver"; +- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; +- linux,rc-map-name = "rc-khadas"; ++ vcc_phy: vcc-phy-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; +- pinctrl-0 = <&ir_int>; ++ pinctrl-0 = <&usb20_host_drv>; ++ regulator-name = "vcc_host1_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; + }; + +- sdio_pwrseq: sdio-pwrseq { +- compatible = "mmc-pwrseq-simple"; ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; +- pinctrl-0 = <&wifi_en>, <&wifi_host_wake>; +- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_pin>; ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ xin32k: xin32k { ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "xin32k"; ++ #clock-cells = <0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ power_led: led-0 { ++ label = "firefly:blue:power"; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&rk805 1 GPIO_ACTIVE_LOW>; ++ default-state = "on"; ++ mode = <0x23>; ++ }; ++ ++ user_led: led-1 { ++ label = "firefly:yellow:user"; ++ linux,default-trigger = "mmc1"; ++ gpios = <&rk805 0 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ mode = <0x05>; ++ }; ++ }; ++ ++ /delete-node/ dmc-opp-table; ++ dmc_opp_table: dmc-opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-786000000 { ++ opp-hz = /bits/ 64 <786000000>; ++ opp-microvolt = <1075000 1075000 1200000>; ++ }; ++ opp-798000000 { ++ opp-hz = /bits/ 64 <798000000>; ++ opp-microvolt = <1075000 1075000 1200000>; ++ }; ++ opp-840000000 { ++ opp-hz = /bits/ 64 <840000000>; ++ opp-microvolt = <1075000 1075000 1200000>; ++ }; ++ opp-924000000 { ++ status = "disabled"; // unstable ++ opp-hz = /bits/ 64 <924000000>; ++ opp-microvolt = <1100000 1100000 1200000>; ++ }; + }; + }; + +-&codec { +- mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; ++&dfi { ++ status = "okay"; ++}; ++ ++&dmc { ++ center-supply = <&vdd_logic>; ++ ddr_timing = <&ddr_timing>; ++ status = "okay"; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ vccio1-supply = <&vcc_io>; ++ vccio2-supply = <&vcc_18emmc>; ++ vccio3-supply = <&vcc_io>; ++ vccio4-supply = <&vcc_io>; ++ vccio5-supply = <&vcc_io>; ++ vccio6-supply = <&vcc_io>; ++ pmuio-supply = <&vcc_io>; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; + }; + + &gpu { ++ status = "okay"; + mali-supply = <&vdd_logic>; + }; + +-&pinctrl { +- ir { +- ir_int: ir-int { +- rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++&gmac2phy { ++ phy-supply = <&vcc_phy>; ++ clock_in_out = "output"; ++ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; ++ assigned-clock-rate = <50000000>; ++ assigned-clocks = <&cru SCLK_MAC2PHY>; ++ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; ++ status = "disabled"; ++}; ++ ++&gmac2io { ++ phy-supply = <&vcc_io>; ++ phy-mode = "rgmii"; ++ clock_in_out = "input"; ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmiim1_pins>; ++ snps,aal; ++ snps,rxpbl = <0x4>; ++ snps,txpbl = <0x4>; ++ tx_delay = <0x24>; ++ rx_delay = <0x18>; ++ status = "okay"; ++}; ++ ++&display_subsystem { ++ status = "okay"; ++}; ++ ++&hdmi { ++ #sound-dai-cells = <0>; ++ ddc-i2c-scl-high-time-ns = <9625>; ++ ddc-i2c-scl-low-time-ns = <10000>; ++ status = "okay"; ++}; ++ ++&hdmiphy { ++ status = "okay"; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++/*&h265e { ++ status = "okay"; ++}; ++ ++&vdec { ++ status = "okay"; ++}; ++ ++&vepu { ++ status = "okay"; ++};*/ ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++/*&vpu_service { ++ status = "okay"; ++};*/ ++ ++&i2s0 { ++ #sound-dai-cells = <0>; ++ rockchip,bclk-fs = <128>; ++ status = "okay"; ++}; ++ ++&i2s1 { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&codec { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&emmc { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ supports-emmc; ++ disable-wp; ++ non-removable; ++ num-slots = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ num-slots = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; ++ supports-sd; ++ status = "okay"; ++ vmmc-supply = <&vcc_sd>; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: rk805@18 { ++ compatible = "rockchip,rk805"; ++ status = "okay"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ gpio-controller; ++ #gpio-cells = <2>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_io>; ++ vcc6-supply = <&vcc_io>; ++ ++ rtc { ++ status = "okay"; + }; +- }; + +- sdmmcio { +- sdio_per_pin: sdio-per-pin { +- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; ++ pwrkey { ++ status = "okay"; ++ }; ++ ++ gpio { ++ status = "okay"; ++ }; ++ ++ regulators { ++ compatible = "rk805-regulator"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io: DCDC_REG4 { ++ regulator-name = "vcc_io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vdd_18: LDO_REG1 { ++ regulator-name = "vdd_18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_18emmc: LDO_REG2 { ++ regulator-name = "vcc_18emmc"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_11: LDO_REG3 { ++ regulator-name = "vdd_11"; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1100000>; ++ }; ++ }; + }; + }; ++}; ++ ++&pinctrl { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&clk_32k_out>; + +- wifi { +- wifi_en: wifi-en { +- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ clk_32k { ++ clk_32k_out: clk-32k-out { ++ rockchip,pins = ++ <1 RK_PD4 1 &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */ + }; ++ }; + +- wifi_host_wake: wifi-host-wake { +- rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>; ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, ++ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>, ++ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, ++ <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; ++ }; + +- bt_rst: bt-rst { +- rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; ++ usb2 { ++ usb20_host_drv: usb20-host-drv { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; ++ }; + +- bt_en: bt-en { +- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ usb3 { ++ usb30_host_drv: usb30-host-drv { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + +-&pmic_int_l { +- rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++&u2phy { ++ status = "okay"; + }; + +-&rk805 { +- interrupt-parent = <&gpio0>; +- interrupts = ; ++&u2phy_host { ++ status = "okay"; + }; + +-&saradc { +- vref-supply = <&vcc_18>; ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++&uart2 { + status = "okay"; + }; + +-&usb20_host_drv { +- rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++&usb20_otg { ++ dr_mode = "host"; ++ status = "okay"; + }; + +-&vcc_host1_5v { +- gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++&usb_host0_ehci { ++ status = "okay"; + }; + +-&vcc_sdio { +- gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&sdio_per_pin>; ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&wdt { ++ status = "okay"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vdd_18>; ++}; ++ ++&tsadc { ++ status = "okay"; ++ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + }; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rock3a-emmc-sfc.patch b/patch/kernel/archive/rockchip64-6.6/board-rock3a-emmc-sfc.patch new file mode 100644 index 000000000..84e0169a4 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rock3a-emmc-sfc.patch @@ -0,0 +1,54 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jianfeng Liu +Date: Wed, 3 Aug 2022 22:22:55 +0200 +Subject: [ARCHEOLOGY] update rockchip64 edge to 5.19 (#4039) + +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 11 ++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index e05ab11981f5..37de541cd4a1 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -753,6 +753,17 @@ &sdmmc2 { + status = "okay"; + }; + ++&sfc { ++ status = "okay"; ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <108000000>; ++ spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <2>; ++ }; ++}; ++ + &tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rock3a-usb3.patch b/patch/kernel/archive/rockchip64-6.6/board-rock3a-usb3.patch new file mode 100644 index 000000000..b5dfe00f7 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rock3a-usb3.patch @@ -0,0 +1,44 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jianfeng Liu +Date: Wed, 3 Aug 2022 22:22:55 +0200 +Subject: [ARCHEOLOGY] update rockchip64 edge to 5.19 (#4039) + +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index 37de541cd4a1..effcb2ee471f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -805,6 +805,7 @@ &usb_host0_ohci { + + &usb_host0_xhci { + extcon = <&usb2phy0>; ++ dr_mode = "host"; + status = "okay"; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rock64-mail-supply.patch b/patch/kernel/archive/rockchip64-6.6/board-rock64-mail-supply.patch new file mode 100644 index 000000000..a108ddef5 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rock64-mail-supply.patch @@ -0,0 +1,29 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: tonymac32 +Date: Sun, 8 Aug 2021 11:49:27 -0400 +Subject: board_rock64_mali-usb-supply + +Signed-off-by: tonymac32 +--- + arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index 0a27fa5271f5..1596ce3368f7 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -135,6 +135,11 @@ &emmc { + status = "okay"; + }; + ++&gpu { ++ status = "okay"; ++ mali-supply = <&vdd_logic>; ++}; ++ + &gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpi3-enable-dmc.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpi3-enable-dmc.patch new file mode 100644 index 000000000..6164405ee --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpi3-enable-dmc.patch @@ -0,0 +1,44 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Wed, 8 Mar 2023 11:12:22 +0100 +Subject: [ARCHEOLOGY] rockchip64: enable dmc on Rock PI E board + +> X-Git-Archeology: - Revision 4ea9330e5185e1c6e248af035cc615d23408316d: https://github.com/armbian/build/commit/4ea9330e5185e1c6e248af035cc615d23408316d +> X-Git-Archeology: Date: Wed, 08 Mar 2023 11:12:22 +0100 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rockchip64: enable dmc on Rock PI E board +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +index 018a3a5075c7..9b3453cece85 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +@@ -15,6 +15,7 @@ + #include + + #include "rk3328.dtsi" ++#include "rk3328-dram-default-timing.dtsi" + + / { + model = "Radxa ROCK Pi E"; +@@ -388,3 +389,9 @@ &usbdrd3 { + &usb_host0_ehci { + status = "okay"; + }; ++ ++&dmc { ++ status = "okay"; ++ center-supply = <&vdd_log>; ++ ddr_timing = <&ddr_timing>; ++}; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpi4-0003-arm64-dts-pcie.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpi4-0003-arm64-dts-pcie.patch new file mode 100644 index 000000000..9ae37ae46 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpi4-0003-arm64-dts-pcie.patch @@ -0,0 +1,130 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Piotr Szczepanik +Date: Mon, 18 Nov 2019 18:23:10 +0100 +Subject: [ARCHEOLOGY] Rock Pi 4 enable PCIe in device tree for "dev" target + (#1624) + +> X-Git-Archeology: > recovered message: > * Rock Pi 4 enabled support for PCIe in device tree +> X-Git-Archeology: > recovered message: > * Rockchip64-dev added possibility to enable PCIe Gen2 speed via overlay +> X-Git-Archeology: - Revision b3bb9345439250d8247f0e24a8e1ef6290b2c279: https://github.com/armbian/build/commit/b3bb9345439250d8247f0e24a8e1ef6290b2c279 +> X-Git-Archeology: Date: Mon, 18 Nov 2019 18:23:10 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Rock Pi 4 enable PCIe in device tree for "dev" target (#1624) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3 +> X-Git-Archeology: Date: Tue, 19 Nov 2019 23:25:39 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Remove K<4, change branches, new features (#1586) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37 +> X-Git-Archeology: Date: Sat, 18 Jul 2020 23:07:01 +0200 +> X-Git-Archeology: From: Werner +> X-Git-Archeology: Subject: Move rockchip/64 current to 5.7.y (#2099) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070 +> X-Git-Archeology: Date: Sun, 13 Dec 2020 22:13:03 -0500 +> X-Git-Archeology: From: tonymac32 +> X-Git-Archeology: Subject: [ rockchip64 ] Clean up patchset +> X-Git-Archeology: +> X-Git-Archeology: - Revision 091d91468e383c3d12a03a465be36b76112ce798: https://github.com/armbian/build/commit/091d91468e383c3d12a03a465be36b76112ce798 +> X-Git-Archeology: Date: Sun, 17 Jan 2021 19:07:59 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switched rockchip64-current to 5.10.y (and synced -dev config/patches) (#2546) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 +> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 +> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 44c4cdf8653104bc395c504d7611d819906ff69b: https://github.com/armbian/build/commit/44c4cdf8653104bc395c504d7611d819906ff69b +> X-Git-Archeology: Date: Fri, 30 Dec 2022 21:17:33 +0100 +> X-Git-Archeology: From: Konstantin Litvinov +> X-Git-Archeology: Subject: Fixed issue with NVMe identification in rk3399-rock-pi-4.dts (#4627) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 44c95b7b0a64486a85f23c5630842ea1b877a695: https://github.com/armbian/build/commit/44c95b7b0a64486a85f23c5630842ea1b877a695 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:01 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: fix unidiff warning from patches of rockchip64-6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +index 980c4534313a..be5c59be0c9d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +@@ -113,6 +113,8 @@ vcc3v3_pcie: vcc3v3-pcie-regulator { + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + +@@ -528,9 +530,11 @@ &pcie0 { + num-lanes = <4>; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + pinctrl-names = "default"; ++ vpcie12v-supply = <&vcc12v_dcin>; + vpcie0v9-supply = <&vcc_0v9>; + vpcie1v8-supply = <&vcc_1v8>; + vpcie3v3-supply = <&vcc3v3_pcie>; ++ bus-scan-delay-ms = <1500>; + status = "okay"; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0001-arm64-dts.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0001-arm64-dts.patch new file mode 100644 index 000000000..611f00912 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0001-arm64-dts.patch @@ -0,0 +1,404 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: brentr +Date: Fri, 23 Dec 2022 21:57:53 +0100 +Subject: [ARCHEOLOGY] Rockpis devtree mainlined (#4603) + +> X-Git-Archeology: > recovered message: > * moved rockpro64 patch out of rockpis patch sequence +> X-Git-Archeology: > recovered message: > It had been misnamed +> X-Git-Archeology: > recovered message: > * patch new mainline devtree for Rock Pi-S instead of overwritting it. +> X-Git-Archeology: > recovered message: > Also restores lost bluetooth compatibility items on UART4 +> X-Git-Archeology: - Revision 588c2ec17e709dec19304fa50522459702ebfadd: https://github.com/armbian/build/commit/588c2ec17e709dec19304fa50522459702ebfadd +> X-Git-Archeology: Date: Fri, 23 Dec 2022 21:57:53 +0100 +> X-Git-Archeology: From: brentr +> X-Git-Archeology: Subject: Rockpis devtree mainlined (#4603) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 240 +++++++--- + 1 file changed, 164 insertions(+), 76 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +index e9810d2f0407..0d917658d24a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -2,6 +2,7 @@ + /* + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Jagan Teki ++ * Revised: 2022 Brent Roman + */ + + /dts-v1/; +@@ -11,12 +12,6 @@ / { + model = "Radxa ROCK Pi S"; + compatible = "radxa,rockpis", "rockchip,rk3308"; + +- aliases { +- ethernet0 = &gmac; +- mmc0 = &emmc; +- mmc1 = &sdmmc; +- }; +- + chosen { + stdout-path = "serial0:1500000n8"; + }; +@@ -27,44 +22,102 @@ leds { + pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>; + + green-led { +- default-state = "on"; +- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "rockpis:green:power"; ++ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; ++ default-state = "on"; + }; + + blue-led { +- default-state = "on"; +- gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "rockpis:blue:user"; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; ++ default-state = "on"; + }; + }; + ++ codec: acodec-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "rockchip,rk3308-acodec"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,codec-hp-det; ++ simple-audio-card,widgets = ++ "Headphone", "Headphones"; ++ simple-audio-card,cpu { ++ sound-dai = <&i2s_8ch_2>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&acodec>; ++ }; ++ }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,name = "i2s_8ch_0"; ++ ++ simple-audio-card,dai-link@1 { ++ format = "i2s"; ++ cpu { ++ sound-dai = <&i2s_8ch_0>; ++ }; ++ ++ codec { ++ sound-dai = <&pcm5102a>; ++ }; ++ }; ++ }; ++ ++ pcm5102a: pcm5102a { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5102a"; ++ pcm510x,format = "i2s"; ++ }; ++ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; ++ /* ++ * On the module itself this is one of these (depending ++ * on the actual card populated): ++ * - SDIO_RESET_L_WL_REG_ON ++ * - PDN (power down when low) ++ */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; + +- vcc_1v8: vcc-1v8 { ++ vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; +- regulator-name = "vcc_1v8"; ++ regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- vin-supply = <&vcc_io>; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; + }; + +- vcc_io: vcc-io { ++ vdd_core: vdd-core { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm0 0 5000 1>; ++ regulator-name = "vdd_core"; ++ regulator-min-microvolt = <827000>; ++ regulator-max-microvolt = <1340000>; ++ regulator-init-microvolt = <1015000>; ++ regulator-settling-time-up-us = <250>; ++ regulator-always-on; ++ regulator-boot-on; ++ pwm-supply = <&vcc5v0_sys>; ++ }; ++ ++ vdd_log: vdd-log { + compatible = "regulator-fixed"; +- regulator-name = "vcc_io"; ++ regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; + vin-supply = <&vcc5v0_sys>; + }; + +@@ -78,49 +131,50 @@ vcc_ddr: vcc-ddr { + vin-supply = <&vcc5v0_sys>; + }; + +- vcc5v0_otg: vcc5v0-otg { ++ vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; +- enable-active-high; +- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&otg_vbus_drv>; +- regulator-name = "vcc5v0_otg"; ++ regulator-name = "vcc_1v8"; + regulator-always-on; +- vin-supply = <&vcc5v0_sys>; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_io>; + }; + +- vcc5v0_sys: vcc5v0-sys { ++ vcc_io: vcc-io { + compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_sys"; ++ regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; + }; + +- vdd_core: vdd-core { +- compatible = "pwm-regulator"; +- pwms = <&pwm0 0 5000 1>; +- pwm-supply = <&vcc5v0_sys>; +- regulator-name = "vdd_core"; +- regulator-min-microvolt = <827000>; +- regulator-max-microvolt = <1340000>; +- regulator-settling-time-up-us = <250>; ++ vcc_phy: vcc-phy-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + +- vdd_log: vdd-log { ++ vcc5v0_otg: vcc5v0-otg { + compatible = "regulator-fixed"; +- regulator-name = "vdd_log"; ++ regulator-name = "vcc5v0_otg"; + regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <1050000>; +- regulator-max-microvolt = <1050000>; ++ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&otg_vbus_drv>; + vin-supply = <&vcc5v0_sys>; + }; + }; + ++&acodec { ++ status = "okay"; ++ #sound-dai-cells = <0>; ++}; ++ + &cpu0 { + cpu-supply = <&vdd_core>; + }; +@@ -128,23 +182,60 @@ &cpu0 { + &emmc { + bus-width = <4>; + cap-mmc-highspeed; +- mmc-hs200-1_8v; + non-removable; +- vmmc-supply = <&vcc_io>; + status = "okay"; + }; + ++&sdmmc { ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; ++ card-detect-delay = <800>; ++ status = "okay"; ++}; ++ ++&sdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ no-mmc; ++ status = "okay"; ++ ++ rtl8723ds: wifi@1 { ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake>; ++ }; ++}; ++ + &gmac { ++ phy-supply = <&vcc_phy>; + clock_in_out = "output"; +- phy-supply = <&vcc_io>; ++ assigned-clocks = <&cru SCLK_MAC>; ++ assigned-clock-parents = <&cru SCLK_MAC_SRC>; + snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "okay"; + }; + +-&i2c1 { ++&i2s_8ch_0 { ++ assigned-clocks = <&cru SCLK_I2S0_8CH_RX>; ++ assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>; ++ rockchip,clk-trcm = <1>; ++ #sound-dai-cells = <0>; ++}; ++ ++&i2s_8ch_2 { + status = "okay"; ++ #sound-dai-cells = <0>; + }; + + &pinctrl { +@@ -171,7 +262,9 @@ sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; ++ }; + ++ wifi { + wifi_host_wake: wifi-host-wake { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; +@@ -188,42 +281,29 @@ &saradc { + status = "okay"; + }; + +-&sdio { +- #address-cells = <1>; +- #size-cells = <0>; +- cap-sd-highspeed; +- cap-sdio-irq; +- keep-power-in-suspend; +- max-frequency = <1000000>; +- mmc-pwrseq = <&sdio_pwrseq>; +- non-removable; +- sd-uhs-sdr104; ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; /* 0:CRU */ ++ rockchip,hw-tshut-polarity = <1>; /* 1:HIGH */ + status = "okay"; + }; + +-&sdmmc { +- cap-sd-highspeed; ++&i2c1 { + status = "okay"; + }; + +-&u2phy { +- status = "okay"; +- +- u2phy_host: host-port { +- phy-supply = <&vcc5v0_otg>; +- status = "okay"; +- }; +- +- u2phy_otg: otg-port { +- phy-supply = <&vcc5v0_otg>; +- status = "okay"; +- }; ++&spi2 { ++// status = "okay"; //conflicts with UART2 ++ max-freq = <10000000>; + }; + + &uart0 { + status = "okay"; + }; + ++&uart2 { ++ status = "okay"; ++}; ++ + &uart4 { + status = "okay"; + +@@ -234,19 +314,27 @@ bluetooth { + }; + }; + +-&usb_host_ehci { ++&u2phy { + status = "okay"; ++ ++ u2phy_host: host-port { ++ phy-supply = <&vcc5v0_otg>; ++ status = "okay"; ++ }; ++ ++ u2phy_otg: otg-port { ++ status = "okay"; ++ }; + }; + +-&usb_host_ohci { ++&usb20_otg { + status = "okay"; + }; + +-&usb20_otg { +- dr_mode = "peripheral"; ++&usb_host_ehci { + status = "okay"; + }; + +-&wdt { ++&usb_host_ohci{ + status = "okay"; + }; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch new file mode 100644 index 000000000..3db2657a8 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch @@ -0,0 +1,24 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: ashthespy +Date: Thu, 16 Jan 2020 21:13:09 +0100 +Subject: arm64: dts: rk3308: Add mac node at dtsi level + +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index 2ae4bb7d5e62..2a6f41e2281f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -24,6 +24,7 @@ aliases { + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; ++ ethernet0 = &gmac; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch new file mode 100644 index 000000000..2d86ad6c3 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch @@ -0,0 +1,87 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: ashthespy +Date: Fri, 17 Jan 2020 15:57:53 +0100 +Subject: arm64: dts: rockchip: add cpu's thermal config for rk3308 + +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 64 ++++++++++ + 1 file changed, 64 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index 2a6f41e2281f..fde32008902a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -552,6 +552,70 @@ saradc: saradc@ff1e0000 { + status = "disabled"; + }; + ++ thermal_zones: thermal-zones { ++ ++ soc_thermal: soc-thermal { ++ polling-delay-passive = <20>; ++ polling-delay = <1000>; ++ sustainable-power = <300>; ++ ++ thermal-sensors = <&tsadc 1>; ++ ++ trips { ++ threshold: trip-point-0 { ++ temperature = <70000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ target: trip-point-1 { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ soc_crit: soc-crit { ++ temperature = <115000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&target>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <4096>; ++ }; ++ }; ++ ++ }; ++ ++ logic_thermal: logic-thermal { ++ polling-delay-passive = <100>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ ++ thermal-sensors = <&tsadc 0>; ++ }; ++ }; ++ ++ tsadc: tsadc@ff1f0000 { ++ compatible = "rockchip,rk3308-tsadc"; ++ reg = <0x0 0xff1f0000 0x0 0x100>; ++ interrupts = ; ++ rockchip,grf = <&grf>; ++ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; ++ clock-names = "tsadc", "apb_pclk"; ++ assigned-clocks = <&cru SCLK_TSADC>; ++ assigned-clock-rates = <50000>; ++ resets = <&cru SRST_TSADC>; ++ reset-names = "tsadc-apb"; ++ pinctrl-names = "gpio", "otpout"; ++ pinctrl-0 = <&tsadc_otp_pin>; ++ pinctrl-1 = <&tsadc_otp_out>; ++ #thermal-sensor-cells = <1>; ++ rockchip,hw-tshut-temp = <120000>; ++ status = "disabled"; ++ }; ++ + dmac0: dma-controller@ff2c0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff2c0000 0x0 0x4000>; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch new file mode 100644 index 000000000..3902d61c8 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch @@ -0,0 +1,71 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Rocky Hao +Date: Fri, 9 Mar 2018 17:36:39 +0800 +Subject: thermal: rockchip: add tsadc support for rk3308 + +Change-Id: Ibf1782ca471c8ad4b14d6fd64eeb123181903adc +Signed-off-by: Rocky Hao +--- + Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 1 + + drivers/thermal/rockchip_thermal.c | 26 ++++++++++ + 2 files changed, 27 insertions(+) + +diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +index 55f8ec0bec01..c822baf04aed 100644 +--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml ++++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +@@ -15,6 +15,7 @@ properties: + - rockchip,px30-tsadc + - rockchip,rk3228-tsadc + - rockchip,rk3288-tsadc ++ - rockchip,rk3308-tsadc + - rockchip,rk3328-tsadc + - rockchip,rk3368-tsadc + - rockchip,rk3399-tsadc +diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c +index 77231a9d28ff..13182e2a3142 100644 +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -1060,6 +1060,28 @@ static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, + writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); + } + ++static const struct rockchip_tsadc_chip rk3308_tsadc_data = { ++ .chn_num = 2, /* 2 channels for tsadc */ ++ ++ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ ++ .tshut_temp = 95000, ++ ++ .initialize = rk_tsadcv4_initialize, ++ .irq_ack = rk_tsadcv3_irq_ack, ++ .control = rk_tsadcv3_control, ++ .get_temp = rk_tsadcv2_get_temp, ++ .set_alarm_temp = rk_tsadcv2_alarm_temp, ++ .set_tshut_temp = rk_tsadcv2_tshut_temp, ++ .set_tshut_mode = rk_tsadcv2_tshut_mode, ++ ++ .table = { ++ .id = rk3328_code_table, ++ .length = ARRAY_SIZE(rk3328_code_table), ++ .data_mask = TSADCV2_DATA_MASK, ++ .mode = ADC_INCREMENT, ++ }, ++}; ++ + static const struct rockchip_tsadc_chip px30_tsadc_data = { + /* cpu, gpu */ + .chn_offset = 0, +@@ -1321,6 +1343,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { + .compatible = "rockchip,rk3288-tsadc", + .data = (void *)&rk3288_tsadc_data, + }, ++ { ++ .compatible = "rockchip,rk3308-tsadc", ++ .data = (void *)&rk3308_tsadc_data, ++ }, + { + .compatible = "rockchip,rk3328-tsadc", + .data = (void *)&rk3328_tsadc_data, +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch new file mode 100644 index 000000000..e4c527331 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch @@ -0,0 +1,126 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: ashthespy +Date: Fri, 17 Jan 2020 16:22:13 +0100 +Subject: arm64: dts: rockchip: add i2s_8ch for rk3308 + +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 103 ++++++++++ + 1 file changed, 103 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index fde32008902a..1567758ca90e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -638,6 +638,109 @@ dmac1: dma-controller@ff2d0000 { + #dma-cells = <1>; + }; + ++ i2s_8ch_0: i2s@ff300000 { ++ compatible = "rockchip,rk3308-i2s-tdm"; ++ reg = <0x0 0xff300000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>, ++ <&cru SCLK_I2S0_8CH_TX_SRC>, ++ <&cru SCLK_I2S0_8CH_RX_SRC>, ++ <&cru PLL_VPLL0>, ++ <&cru PLL_VPLL1>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk", ++ "mclk_tx_src", "mclk_rx_src", ++ "mclk_root0", "mclk_root1"; ++ dmas = <&dmac1 0>, <&dmac1 1>; ++ dma-names = "tx", "rx"; ++ resets = <&cru SRST_I2S0_8CH_TX_M>, <&cru SRST_I2S0_8CH_RX_M>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,cru = <&cru>; ++ rockchip,grf = <&grf>; ++ rockchip,mclk-calibrate; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_8ch_0_sclktx ++ &i2s_8ch_0_sclkrx ++ &i2s_8ch_0_lrcktx ++ &i2s_8ch_0_lrckrx ++ &i2s_8ch_0_sdi0 ++ &i2s_8ch_0_sdi1 ++ &i2s_8ch_0_sdi2 ++ &i2s_8ch_0_sdi3 ++ &i2s_8ch_0_sdo0 ++ &i2s_8ch_0_sdo1 ++ &i2s_8ch_0_sdo2 ++ &i2s_8ch_0_sdo3 ++ &i2s_8ch_0_mclk>; ++ status = "disabled"; ++ }; ++ ++ i2s_8ch_1: i2s@ff310000 { ++ compatible = "rockchip,rk3308-i2s-tdm"; ++ reg = <0x0 0xff310000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>, ++ <&cru SCLK_I2S1_8CH_TX_SRC>, ++ <&cru SCLK_I2S1_8CH_RX_SRC>, ++ <&cru PLL_VPLL0>, ++ <&cru PLL_VPLL1>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk", ++ "mclk_tx_src", "mclk_rx_src", ++ "mclk_root0", "mclk_root1"; ++ dmas = <&dmac1 2>, <&dmac1 3>; ++ dma-names = "tx", "rx"; ++ resets = <&cru SRST_I2S1_8CH_TX_M>, <&cru SRST_I2S1_8CH_RX_M>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,cru = <&cru>; ++ rockchip,grf = <&grf>; ++ rockchip,mclk-calibrate; ++ rockchip,io-multiplex; ++ status = "disabled"; ++ }; ++ ++ i2s_8ch_2: i2s@ff320000 { ++ compatible = "rockchip,rk3308-i2s-tdm"; ++ reg = <0x0 0xff320000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_I2S2_8CH_TX>, <&cru SCLK_I2S2_8CH_RX>, <&cru HCLK_I2S2_8CH>, ++ <&cru SCLK_I2S2_8CH_TX_SRC>, ++ <&cru SCLK_I2S2_8CH_RX_SRC>, ++ <&cru PLL_VPLL0>, ++ <&cru PLL_VPLL1>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk", ++ "mclk_tx_src", "mclk_rx_src", ++ "mclk_root0", "mclk_root1"; ++ dmas = <&dmac1 4>, <&dmac1 5>; ++ dma-names = "tx", "rx"; ++ resets = <&cru SRST_I2S2_8CH_TX_M>, <&cru SRST_I2S2_8CH_RX_M>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,cru = <&cru>; ++ rockchip,grf = <&grf>; ++ rockchip,mclk-calibrate; ++ status = "disabled"; ++ }; ++ ++ i2s_8ch_3: i2s@ff330000 { ++ compatible = "rockchip,rk3308-i2s-tdm"; ++ reg = <0x0 0xff330000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_I2S3_8CH_TX>, <&cru SCLK_I2S3_8CH_RX>, <&cru HCLK_I2S3_8CH>, ++ <&cru SCLK_I2S3_8CH_TX_SRC>, ++ <&cru SCLK_I2S3_8CH_RX_SRC>, ++ <&cru PLL_VPLL0>, ++ <&cru PLL_VPLL1>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk", ++ "mclk_tx_src", "mclk_rx_src", ++ "mclk_root0", "mclk_root1"; ++ dmas = <&dmac1 7>; ++ dma-names = "rx"; ++ resets = <&cru SRST_I2S3_8CH_TX_M>, <&cru SRST_I2S3_8CH_RX_M>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,cru = <&cru>; ++ rockchip,grf = <&grf>; ++ rockchip,mclk-calibrate; ++ status = "disabled"; ++ }; ++ + i2s_2ch_0: i2s@ff350000 { + compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff350000 0x0 0x1000>; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch new file mode 100644 index 000000000..5cd290367 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch @@ -0,0 +1,41 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: ashthespy +Date: Fri, 17 Jan 2020 17:12:51 +0100 +Subject: arm64: dts: rk3308: Add rk-timer-rtc + +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 11 +++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index 1567758ca90e..291f011800b2 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -540,6 +540,15 @@ rktimer: rktimer@ff1a0000 { + clock-names = "pclk", "timer"; + }; + ++ rk_timer_rtc: rk-timer-rtc@ff1a0020 { ++ compatible = "rockchip,rk3308-timer-rtc"; ++ reg = <0x0 0xff1a0020 0x0 0x20>; ++ interrupts = ; ++ clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; ++ clock-names = "pclk", "timer"; ++ status = "disabled"; ++ }; ++ + saradc: saradc@ff1e0000 { + compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xff1e0000 0x0 0x100>; +@@ -740,7 +749,7 @@ i2s_8ch_3: i2s@ff330000 { + rockchip,mclk-calibrate; + status = "disabled"; + }; +- ++ + i2s_2ch_0: i2s@ff350000 { + compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff350000 0x0 0x1000>; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch new file mode 100644 index 000000000..ae402dbe9 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch @@ -0,0 +1,2638 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Xing Zheng +Date: Sun, 11 Mar 2018 11:37:28 +0800 +Subject: ASoC: codecs: Add RK3308 internal codec driver + +This adds support for the RK3308 audio codec. + +Change-Id: Ieccdebaa27f4a46f6de9406046a6e02e20398013 +Signed-off-by: Xing Zheng +--- + sound/soc/codecs/Kconfig | 5 + + sound/soc/codecs/Makefile | 2 + + sound/soc/codecs/rk3308_codec.c | 1604 ++++++++++ + sound/soc/codecs/rk3308_codec.h | 960 ++++++ + 4 files changed, 2571 insertions(+) + +diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig +index 947473d2da7d..35cf63ff5457 100644 +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -174,6 +174,7 @@ config SND_SOC_ALL_CODECS + imply SND_SOC_PCM512x_I2C + imply SND_SOC_PCM512x_SPI + imply SND_SOC_PEB2466 ++ imply SND_SOC_RK3308 + imply SND_SOC_RK3328 + imply SND_SOC_RK817 + imply SND_SOC_RT274 +@@ -1331,6 +1332,10 @@ config SND_SOC_PEB2466 + To compile this driver as a module, choose M here: the module + will be called snd-soc-peb2466. + ++config SND_SOC_RK3308 ++ select REGMAP_MMIO ++ tristate "Rockchip RK3308 CODEC" ++ + config SND_SOC_RK3328 + tristate "Rockchip RK3328 audio CODEC" + select REGMAP_MMIO +diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile +index b48a9a323b84..23a6bf365bd7 100644 +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -196,6 +196,7 @@ snd-soc-pcm512x-objs := pcm512x.o + snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o + snd-soc-pcm512x-spi-objs := pcm512x-spi.o + snd-soc-peb2466-objs := peb2466.o ++snd-soc-rk3308-objs := rk3308_codec.o + snd-soc-rk3328-objs := rk3328_codec.o + snd-soc-rk817-objs := rk817_codec.o + snd-soc-rl6231-objs := rl6231.o +@@ -573,6 +574,7 @@ obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o + obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o + obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o + obj-$(CONFIG_SND_SOC_PEB2466) += snd-soc-peb2466.o ++obj-$(CONFIG_SND_SOC_RK3308) += snd-soc-rk3308.o + obj-$(CONFIG_SND_SOC_RK3328) += snd-soc-rk3328.o + obj-$(CONFIG_SND_SOC_RK817) += snd-soc-rk817.o + obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o +diff --git a/sound/soc/codecs/rk3308_codec.c b/sound/soc/codecs/rk3308_codec.c +new file mode 100644 +index 000000000000..106f09738dd0 +--- /dev/null ++++ b/sound/soc/codecs/rk3308_codec.c +@@ -0,0 +1,1604 @@ ++/* ++ * rk3308_codec.c -- RK3308 ALSA Soc Audio Driver ++ * ++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "rk3308_codec.h" ++ ++struct rk3308_codec_priv { ++ const struct device *plat_dev; ++ struct device dev; ++ struct reset_control *reset; ++ struct regmap *regmap; ++ struct clk *pclk; ++ struct gpio_desc *spk_ctl_gpio; ++ int adc_ch; /* To select ADCs for channel */ ++ int adc_ch0_using_linein; ++}; ++ ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_gain_tlv, ++ -1800, 150, 2850); ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_max_gain_tlv, ++ -1350, 600, 2850); ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_min_gain_tlv, ++ -1800, 600, 2400); ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_mic_gain_tlv, ++ 0, 600, 3000); ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv, ++ -1800, 150, 2850); ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_gain_tlv, ++ 0, 150, 600); ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpout_gain_tlv, ++ -3900, 150, 600); ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpmix_gain_tlv, ++ -600, 600, 0); ++ ++static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = { ++ /* ALC AGC Channel*/ ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Volume", ++ RK3308_ALC_L_DIG_CON03(0), ++ RK3308_ALC_R_DIG_CON03(0), ++ RK3308_AGC_PGA_GAIN_SFT, ++ RK3308_AGC_PGA_GAIN_NDB_18, ++ RK3308_AGC_PGA_GAIN_PDB_28_5, ++ 0, rk3308_codec_alc_agc_ch_gain_tlv), ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Volume", ++ RK3308_ALC_L_DIG_CON03(1), ++ RK3308_ALC_R_DIG_CON03(1), ++ RK3308_AGC_PGA_GAIN_SFT, ++ RK3308_AGC_PGA_GAIN_NDB_18, ++ RK3308_AGC_PGA_GAIN_PDB_28_5, ++ 0, rk3308_codec_alc_agc_ch_gain_tlv), ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Volume", ++ RK3308_ALC_L_DIG_CON03(2), ++ RK3308_ALC_R_DIG_CON03(2), ++ RK3308_AGC_PGA_GAIN_SFT, ++ RK3308_AGC_PGA_GAIN_NDB_18, ++ RK3308_AGC_PGA_GAIN_PDB_28_5, ++ 0, rk3308_codec_alc_agc_ch_gain_tlv), ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Volume", ++ RK3308_ALC_L_DIG_CON03(3), ++ RK3308_ALC_R_DIG_CON03(3), ++ RK3308_AGC_PGA_GAIN_SFT, ++ RK3308_AGC_PGA_GAIN_NDB_18, ++ RK3308_AGC_PGA_GAIN_PDB_28_5, ++ 0, rk3308_codec_alc_agc_ch_gain_tlv), ++ ++ /* ALC AGC MAX */ ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Max Volume", ++ RK3308_ALC_L_DIG_CON09(0), ++ RK3308_ALC_R_DIG_CON09(0), ++ RK3308_AGC_MAX_GAIN_PGA_SFT, ++ RK3308_AGC_MAX_GAIN_PGA_NDB_13_5, ++ RK3308_AGC_MAX_GAIN_PGA_PDB_28_5, ++ 0, rk3308_codec_alc_agc_ch_max_gain_tlv), ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Max Volume", ++ RK3308_ALC_L_DIG_CON09(1), ++ RK3308_ALC_R_DIG_CON09(1), ++ RK3308_AGC_MAX_GAIN_PGA_SFT, ++ RK3308_AGC_MAX_GAIN_PGA_NDB_13_5, ++ RK3308_AGC_MAX_GAIN_PGA_PDB_28_5, ++ 0, rk3308_codec_alc_agc_ch_max_gain_tlv), ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Max Volume", ++ RK3308_ALC_L_DIG_CON09(2), ++ RK3308_ALC_R_DIG_CON09(2), ++ RK3308_AGC_MAX_GAIN_PGA_SFT, ++ RK3308_AGC_MAX_GAIN_PGA_NDB_13_5, ++ RK3308_AGC_MAX_GAIN_PGA_PDB_28_5, ++ 0, rk3308_codec_alc_agc_ch_max_gain_tlv), ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Max Volume", ++ RK3308_ALC_L_DIG_CON09(3), ++ RK3308_ALC_R_DIG_CON09(3), ++ RK3308_AGC_MAX_GAIN_PGA_SFT, ++ RK3308_AGC_MAX_GAIN_PGA_NDB_13_5, ++ RK3308_AGC_MAX_GAIN_PGA_PDB_28_5, ++ 0, rk3308_codec_alc_agc_ch_max_gain_tlv), ++ ++ /* ALC AGC MIN */ ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Min Volume", ++ RK3308_ALC_L_DIG_CON09(0), ++ RK3308_ALC_R_DIG_CON09(0), ++ RK3308_AGC_MIN_GAIN_PGA_SFT, ++ RK3308_AGC_MIN_GAIN_PGA_NDB_18, ++ RK3308_AGC_MIN_GAIN_PGA_PDB_24, ++ 0, rk3308_codec_alc_agc_ch_min_gain_tlv), ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Min Volume", ++ RK3308_ALC_L_DIG_CON09(1), ++ RK3308_ALC_R_DIG_CON09(1), ++ RK3308_AGC_MIN_GAIN_PGA_SFT, ++ RK3308_AGC_MIN_GAIN_PGA_NDB_18, ++ RK3308_AGC_MIN_GAIN_PGA_PDB_24, ++ 0, rk3308_codec_alc_agc_ch_min_gain_tlv), ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Min Volume", ++ RK3308_ALC_L_DIG_CON09(2), ++ RK3308_ALC_R_DIG_CON09(2), ++ RK3308_AGC_MIN_GAIN_PGA_SFT, ++ RK3308_AGC_MIN_GAIN_PGA_NDB_18, ++ RK3308_AGC_MIN_GAIN_PGA_PDB_24, ++ 0, rk3308_codec_alc_agc_ch_min_gain_tlv), ++ SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Min Volume", ++ RK3308_ALC_L_DIG_CON09(3), ++ RK3308_ALC_R_DIG_CON09(3), ++ RK3308_AGC_MIN_GAIN_PGA_SFT, ++ RK3308_AGC_MIN_GAIN_PGA_NDB_18, ++ RK3308_AGC_MIN_GAIN_PGA_PDB_24, ++ 0, rk3308_codec_alc_agc_ch_min_gain_tlv), ++ ++ /* ADC MIC */ ++ SOC_SINGLE_RANGE_TLV("ADC MIC Channel 0 Left Volume", ++ RK3308_ADC_ANA_CON01(0), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_0DB, ++ RK3308_ADC_CH1_MIC_GAIN_30DB, ++ 0, rk3308_codec_adc_mic_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC MIC Channel 0 Right Volume", ++ RK3308_ADC_ANA_CON01(0), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_0DB, ++ RK3308_ADC_CH2_MIC_GAIN_30DB, ++ 0, rk3308_codec_adc_mic_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC MIC Channel 1 Left Volume", ++ RK3308_ADC_ANA_CON01(1), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_0DB, ++ RK3308_ADC_CH1_MIC_GAIN_30DB, ++ 0, rk3308_codec_adc_mic_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC MIC Channel 1 Right Volume", ++ RK3308_ADC_ANA_CON01(1), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_0DB, ++ RK3308_ADC_CH2_MIC_GAIN_30DB, ++ 0, rk3308_codec_adc_mic_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC MIC Channel 2 Left Volume", ++ RK3308_ADC_ANA_CON01(2), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_0DB, ++ RK3308_ADC_CH1_MIC_GAIN_30DB, ++ 0, rk3308_codec_adc_mic_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC MIC Channel 2 Right Volume", ++ RK3308_ADC_ANA_CON01(2), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_0DB, ++ RK3308_ADC_CH2_MIC_GAIN_30DB, ++ 0, rk3308_codec_adc_mic_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC MIC Channel 3 Left Volume", ++ RK3308_ADC_ANA_CON01(3), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_0DB, ++ RK3308_ADC_CH1_MIC_GAIN_30DB, ++ 0, rk3308_codec_adc_mic_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC MIC Channel 3 Right Volume", ++ RK3308_ADC_ANA_CON01(3), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_0DB, ++ RK3308_ADC_CH2_MIC_GAIN_30DB, ++ 0, rk3308_codec_adc_mic_gain_tlv), ++ ++ /* ADC ALC */ ++ SOC_SINGLE_RANGE_TLV("ADC ALC Channel 0 Left Volume", ++ RK3308_ADC_ANA_CON03(0), ++ RK3308_ADC_CH1_ALC_GAIN_SFT, ++ RK3308_ADC_CH1_ALC_GAIN_NDB_18, ++ RK3308_ADC_CH1_ALC_GAIN_PDB_28_5, ++ 0, rk3308_codec_adc_alc_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC ALC Channel 0 Right Volume", ++ RK3308_ADC_ANA_CON04(0), ++ RK3308_ADC_CH2_ALC_GAIN_SFT, ++ RK3308_ADC_CH2_ALC_GAIN_NDB_18, ++ RK3308_ADC_CH2_ALC_GAIN_PDB_28_5, ++ 0, rk3308_codec_adc_alc_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC ALC Channel 1 Left Volume", ++ RK3308_ADC_ANA_CON03(1), ++ RK3308_ADC_CH1_ALC_GAIN_SFT, ++ RK3308_ADC_CH1_ALC_GAIN_NDB_18, ++ RK3308_ADC_CH1_ALC_GAIN_PDB_28_5, ++ 0, rk3308_codec_adc_alc_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC ALC Channel 1 Right Volume", ++ RK3308_ADC_ANA_CON04(1), ++ RK3308_ADC_CH2_ALC_GAIN_SFT, ++ RK3308_ADC_CH2_ALC_GAIN_NDB_18, ++ RK3308_ADC_CH2_ALC_GAIN_PDB_28_5, ++ 0, rk3308_codec_adc_alc_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC ALC Channel 2 Left Volume", ++ RK3308_ADC_ANA_CON03(2), ++ RK3308_ADC_CH1_ALC_GAIN_SFT, ++ RK3308_ADC_CH1_ALC_GAIN_NDB_18, ++ RK3308_ADC_CH1_ALC_GAIN_PDB_28_5, ++ 0, rk3308_codec_adc_alc_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC ALC Channel 2 Right Volume", ++ RK3308_ADC_ANA_CON04(2), ++ RK3308_ADC_CH2_ALC_GAIN_SFT, ++ RK3308_ADC_CH2_ALC_GAIN_NDB_18, ++ RK3308_ADC_CH2_ALC_GAIN_PDB_28_5, ++ 0, rk3308_codec_adc_alc_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC ALC Channel 3 Left Volume", ++ RK3308_ADC_ANA_CON03(3), ++ RK3308_ADC_CH1_ALC_GAIN_SFT, ++ RK3308_ADC_CH1_ALC_GAIN_NDB_18, ++ RK3308_ADC_CH1_ALC_GAIN_PDB_28_5, ++ 0, rk3308_codec_adc_alc_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ADC ALC Channel 3 Right Volume", ++ RK3308_ADC_ANA_CON04(3), ++ RK3308_ADC_CH2_ALC_GAIN_SFT, ++ RK3308_ADC_CH2_ALC_GAIN_NDB_18, ++ RK3308_ADC_CH2_ALC_GAIN_PDB_28_5, ++ 0, rk3308_codec_adc_alc_gain_tlv), ++ ++ /* DAC */ ++ SOC_SINGLE_RANGE_TLV("DAC Left Volume", ++ RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_GAIN_SFT, ++ RK3308_DAC_L_GAIN_0DB, ++ RK3308_DAC_L_GAIN_PDB_6, ++ 0, rk3308_codec_dac_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("DAC Right Volume", ++ RK3308_DAC_ANA_CON04, ++ RK3308_DAC_R_GAIN_SFT, ++ RK3308_DAC_R_GAIN_0DB, ++ RK3308_DAC_R_GAIN_PDB_6, ++ 0, rk3308_codec_dac_gain_tlv), ++ ++ /* DAC HPOUT */ ++ SOC_SINGLE_RANGE_TLV("DAC HPOUT Left Volume", ++ RK3308_DAC_ANA_CON05, ++ RK3308_DAC_L_HPOUT_GAIN_SFT, ++ RK3308_DAC_L_HPOUT_GAIN_NDB_39, ++ RK3308_DAC_L_HPOUT_GAIN_PDB_6, ++ 0, rk3308_codec_dac_hpout_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("DAC HPOUT Right Volume", ++ RK3308_DAC_ANA_CON06, ++ RK3308_DAC_R_HPOUT_GAIN_SFT, ++ RK3308_DAC_R_HPOUT_GAIN_NDB_39, ++ RK3308_DAC_R_HPOUT_GAIN_PDB_6, ++ 0, rk3308_codec_dac_hpout_gain_tlv), ++ ++ /* DAC HPMIX */ ++ SOC_SINGLE_RANGE_TLV("DAC HPMIX Left Volume", ++ RK3308_DAC_ANA_CON05, ++ RK3308_DAC_L_HPMIX_GAIN_SFT, ++ RK3308_DAC_L_HPMIX_GAIN_NDB_6, ++ RK3308_DAC_L_HPMIX_GAIN_0DB, ++ 0, rk3308_codec_dac_hpmix_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("DAC HPMIX Right Volume", ++ RK3308_DAC_ANA_CON05, ++ RK3308_DAC_R_HPMIX_GAIN_SFT, ++ RK3308_DAC_R_HPMIX_GAIN_NDB_6, ++ RK3308_DAC_R_HPMIX_GAIN_0DB, ++ 0, rk3308_codec_dac_hpmix_gain_tlv), ++}; ++ ++static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on) ++{ ++ gpiod_direction_output(rk3308->spk_ctl_gpio, on); ++} ++ ++static int rk3308_codec_reset(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ reset_control_assert(rk3308->reset); ++ usleep_range(200, 300); /* estimated value */ ++ reset_control_deassert(rk3308->reset); ++ ++ regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00); ++ usleep_range(200, 300); /* estimated value */ ++ regmap_write(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_SYS_WORK | ++ RK3308_DAC_DIG_WORK | ++ RK3308_ADC_DIG_WORK); ++ ++ return 0; ++} ++ ++static int rk3308_set_bias_level(struct snd_soc_codec *codec, ++ enum snd_soc_bias_level level) ++{ ++ switch (level) { ++ case SND_SOC_BIAS_ON: ++ break; ++ ++ case SND_SOC_BIAS_PREPARE: ++ break; ++ ++ case SND_SOC_BIAS_STANDBY: ++ case SND_SOC_BIAS_OFF: ++ break; ++ } ++ ++ snd_soc_codec_force_bias_level(codec, level); ++ ++ return 0; ++} ++ ++static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai, ++ unsigned int fmt) ++{ ++ struct snd_soc_codec *codec = codec_dai->codec; ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0; ++ int ch = rk3308->adc_ch; ++ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBS_CFS: ++ adc_aif2 |= RK3308_ADC_IO_MODE_SLAVE; ++ adc_aif2 |= RK3308_ADC_MODE_SLAVE; ++ dac_aif2 |= RK3308_DAC_IO_MODE_SLAVE; ++ dac_aif2 |= RK3308_DAC_MODE_SLAVE; ++ break; ++ case SND_SOC_DAIFMT_CBM_CFM: ++ adc_aif2 |= RK3308_ADC_IO_MODE_MASTER; ++ adc_aif2 |= RK3308_ADC_MODE_MASTER; ++ dac_aif2 |= RK3308_DAC_IO_MODE_MASTER; ++ dac_aif2 |= RK3308_DAC_MODE_MASTER; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_DSP_A: ++ adc_aif1 |= RK3308_ADC_I2S_MODE_PCM; ++ dac_aif1 |= RK3308_DAC_I2S_MODE_PCM; ++ break; ++ case SND_SOC_DAIFMT_I2S: ++ adc_aif1 |= RK3308_ADC_I2S_MODE_I2S; ++ dac_aif1 |= RK3308_DAC_I2S_MODE_I2S; ++ break; ++ case SND_SOC_DAIFMT_RIGHT_J: ++ adc_aif1 |= RK3308_ADC_I2S_MODE_RJ; ++ dac_aif1 |= RK3308_DAC_I2S_MODE_RJ; ++ break; ++ case SND_SOC_DAIFMT_LEFT_J: ++ adc_aif1 |= RK3308_ADC_I2S_MODE_RJ; ++ dac_aif1 |= RK3308_DAC_I2S_MODE_LJ; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL; ++ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL; ++ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL; ++ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; ++ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; ++ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; ++ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; ++ break; ++ case SND_SOC_DAIFMT_IB_NF: ++ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL; ++ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; ++ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL; ++ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; ++ break; ++ case SND_SOC_DAIFMT_NB_IF: ++ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; ++ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL; ++ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; ++ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(ch), ++ RK3308_ADC_I2S_LRC_POL_MSK | ++ RK3308_ADC_I2S_MODE_MSK, ++ adc_aif1); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(ch), ++ RK3308_ADC_IO_MODE_MSK | ++ RK3308_ADC_MODE_MSK | ++ RK3308_ADC_I2S_BIT_CLK_POL_MSK, ++ adc_aif2); ++ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, ++ RK3308_DAC_I2S_LRC_POL_MSK | ++ RK3308_DAC_I2S_MODE_MSK, ++ dac_aif1); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, ++ RK3308_DAC_IO_MODE_MSK | ++ RK3308_DAC_MODE_MSK | ++ RK3308_DAC_I2S_BIT_CLK_POL_MSK, ++ dac_aif2); ++ ++ return 0; ++} ++ ++static int rk3308_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0; ++ int ch = rk3308->adc_ch; ++ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS; ++ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS; ++ break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS; ++ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS; ++ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS; ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: ++ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS; ++ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (params_channels(params)) { ++ case 1: ++ adc_aif1 |= RK3308_ADC_I2S_MONO; ++ break; ++ case 2: ++ adc_aif1 |= RK3308_ADC_I2S_STEREO; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ adc_aif1 |= RK3308_ADC_I2S_LR_NORMAL; ++ adc_aif2 |= RK3308_ADC_I2S_WORK; ++ dac_aif1 |= RK3308_DAC_I2S_LR_NORMAL; ++ dac_aif2 |= RK3308_DAC_I2S_WORK; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(ch), ++ RK3308_ADC_I2S_VALID_LEN_MSK | ++ RK3308_ADC_I2S_LR_MSK | ++ RK3308_ADC_I2S_TYPE_MSK, ++ adc_aif1); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(ch), ++ RK3308_ADC_I2S_MSK, ++ adc_aif2); ++ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, ++ RK3308_DAC_I2S_VALID_LEN_MSK | ++ RK3308_DAC_I2S_LR_MSK, ++ dac_aif1); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, ++ RK3308_DAC_I2S_MSK, ++ dac_aif2); ++ ++ return 0; ++} ++ ++static int rk3308_digital_mute(struct snd_soc_dai *dai, int mute) ++{ ++ return 0; ++} ++ ++static int rk3308_codec_dac_enable(struct rk3308_codec_priv *rk3308) ++{ ++ /* Step 01 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, ++ RK3308_DAC_CURRENT_MSK, ++ RK3308_DAC_CURRENT_EN); ++ ++ /* Step 02 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_BUF_REF_L_MSK | ++ RK3308_DAC_BUF_REF_R_MSK, ++ RK3308_DAC_BUF_REF_L_EN | ++ RK3308_DAC_BUF_REF_R_EN); ++ ++ /* Step 03 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_POP_SOUND_L_MSK | ++ RK3308_DAC_POP_SOUND_R_MSK, ++ RK3308_DAC_POP_SOUND_L_WORK | ++ RK3308_DAC_POP_SOUND_R_WORK); ++ ++ /* Step 04 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN, ++ RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN); ++ ++ /* Step 05 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK, ++ RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK); ++ ++ /* Step 06 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN, ++ RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN); ++ ++ /* Step 07 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN, ++ RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN); ++ ++ /* Step 08 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK, ++ RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK); ++ ++ /* Step 09 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN, ++ RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN); ++ ++ /* Step 10 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN, ++ RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN); ++ ++ /* Step 11 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN, ++ RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN); ++ ++ /* Step 12 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK, ++ RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK); ++ ++ /* Step 13 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, ++ RK3308_DAC_L_HPMIX_SEL_MSK | ++ RK3308_DAC_R_HPMIX_SEL_MSK, ++ RK3308_DAC_L_HPMIX_I2S | ++ RK3308_DAC_R_HPMIX_I2S); ++ ++ /* Step 14 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_UNMUTE | ++ RK3308_DAC_R_HPMIX_UNMUTE, ++ RK3308_DAC_L_HPMIX_UNMUTE | ++ RK3308_DAC_R_HPMIX_UNMUTE); ++ ++ /* Step 15 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, ++ RK3308_DAC_L_HPMIX_GAIN_MSK | ++ RK3308_DAC_R_HPMIX_GAIN_MSK, ++ RK3308_DAC_L_HPMIX_GAIN_0DB | ++ RK3308_DAC_R_HPMIX_GAIN_0DB); ++ ++ /* Step 16 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_UNMUTE | ++ RK3308_DAC_R_HPOUT_UNMUTE, ++ RK3308_DAC_L_HPOUT_UNMUTE | ++ RK3308_DAC_R_HPOUT_UNMUTE); ++ ++ /* Step 17 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_UNMUTE | ++ RK3308_DAC_R_LINEOUT_UNMUTE, ++ RK3308_DAC_L_LINEOUT_UNMUTE | ++ RK3308_DAC_R_LINEOUT_UNMUTE); ++ ++ /* Step 18 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, ++ RK3308_DAC_L_HPOUT_GAIN_MSK, ++ RK3308_DAC_L_HPOUT_GAIN_0DB); ++ ++ /* Step 18 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, ++ RK3308_DAC_R_HPOUT_GAIN_MSK, ++ RK3308_DAC_R_HPOUT_GAIN_0DB); ++ ++ /* Step 19 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_GAIN_MSK | RK3308_DAC_R_GAIN_MSK, ++ RK3308_DAC_L_GAIN_0DB | RK3308_DAC_R_GAIN_0DB); ++ ++ return 0; ++} ++ ++static int rk3308_codec_dac_disable(struct rk3308_codec_priv *rk3308) ++{ ++ /* Step 01 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_GAIN_MSK | RK3308_DAC_R_GAIN_MSK, ++ RK3308_DAC_L_GAIN_0DB | RK3308_DAC_R_GAIN_0DB); ++ ++ /* ++ * Step 02 ++ * ++ * Note1. In the step2, adjusting the register step by step to the ++ * appropriate value and taking 20ms as time step ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, ++ RK3308_DAC_L_HPOUT_GAIN_MSK, ++ RK3308_DAC_L_HPOUT_GAIN_NDB_39); ++ ++ /* Step 02 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, ++ RK3308_DAC_R_HPOUT_GAIN_MSK, ++ RK3308_DAC_R_HPOUT_GAIN_NDB_39); ++ ++ /* Step 03 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_UNMUTE | ++ RK3308_DAC_R_HPMIX_UNMUTE, ++ RK3308_DAC_L_HPMIX_MUTE | ++ RK3308_DAC_R_HPMIX_MUTE); ++ ++ /* Step 04 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, ++ RK3308_DAC_L_HPMIX_SEL_MSK | ++ RK3308_DAC_R_HPMIX_SEL_MSK, ++ RK3308_DAC_L_HPMIX_NONE | ++ RK3308_DAC_R_HPMIX_NONE); ++ ++ /* Step 05 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_UNMUTE | ++ RK3308_DAC_R_HPOUT_UNMUTE, ++ RK3308_DAC_L_HPOUT_MUTE | ++ RK3308_DAC_R_HPOUT_MUTE); ++ ++ /* Step 06 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK, ++ RK3308_DAC_L_DAC_INIT | RK3308_DAC_R_DAC_INIT); ++ ++ /* Step 07 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN, ++ RK3308_DAC_L_HPOUT_DIS | RK3308_DAC_R_HPOUT_DIS); ++ ++ /* Step 08 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_UNMUTE | ++ RK3308_DAC_R_LINEOUT_UNMUTE, ++ RK3308_DAC_L_LINEOUT_MUTE | ++ RK3308_DAC_R_LINEOUT_MUTE); ++ ++ /* Step 09 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN, ++ RK3308_DAC_L_LINEOUT_DIS | RK3308_DAC_R_LINEOUT_DIS); ++ ++ /* Step 10 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN, ++ RK3308_DAC_L_HPMIX_DIS | RK3308_DAC_R_HPMIX_DIS); ++ ++ /* Step 11 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN, ++ RK3308_DAC_L_DAC_DIS | RK3308_DAC_R_DAC_DIS); ++ ++ /* Step 12 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN, ++ RK3308_DAC_L_CLK_DIS | RK3308_DAC_R_CLK_DIS); ++ ++ /* Step 13 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN, ++ RK3308_DAC_L_REF_DIS | RK3308_DAC_R_REF_DIS); ++ ++ /* Step 14 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_POP_SOUND_L_MSK | ++ RK3308_DAC_POP_SOUND_R_MSK, ++ RK3308_DAC_POP_SOUND_L_INIT | ++ RK3308_DAC_POP_SOUND_R_INIT); ++ ++ /* Step 15 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_BUF_REF_L_EN | RK3308_DAC_BUF_REF_R_EN, ++ RK3308_DAC_BUF_REF_L_DIS | RK3308_DAC_BUF_REF_R_DIS); ++ ++ /* Step 16 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, ++ RK3308_DAC_CURRENT_EN, ++ RK3308_DAC_CURRENT_DIS); ++ ++ /* Step 17 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK, ++ RK3308_DAC_L_HPOUT_INIT | RK3308_DAC_R_HPOUT_INIT); ++ ++ /* Step 18 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK, ++ RK3308_DAC_L_HPMIX_INIT | RK3308_DAC_R_HPMIX_INIT); ++ ++ /* Step 19 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, ++ RK3308_DAC_L_HPMIX_GAIN_MSK | ++ RK3308_DAC_R_HPMIX_GAIN_MSK, ++ RK3308_DAC_L_HPMIX_GAIN_NDB_6 | ++ RK3308_DAC_R_HPMIX_GAIN_NDB_6); ++ ++ /* ++ * Note2. If the ACODEC_DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3] ++ * is set to 0x1, add the steps from the section Disable DAC ++ * Configuration Standard Usage Flow after complete the step 19 ++ */ ++ ++ return 0; ++} ++ ++static int rk3308_codec_power_on(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ /* 1. Supply the power of digital part and reset the Audio Codec */ ++ /* Do nothing */ ++ ++ /* ++ * 2. Configure ACODEC_DAC_ANA_CON1[1:0] and ACODEC_DAC_ANA_CON1[5:4] ++ * to 0x1, to setup dc voltage of the DAC channel output ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_POP_SOUND_L_MSK, RK3308_DAC_POP_SOUND_L_INIT); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_POP_SOUND_R_MSK, RK3308_DAC_POP_SOUND_R_INIT); ++ ++ /* ++ * 3. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 0x1 ++ * ++ * Note: Only the reg (ADC_ANA_CON10+0x0)[6:0] represent the control ++ * signal to select current to pre-charge/dis_charge ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, RK3308_ADC_SEL_I_64(1)); ++ ++ /* 4. Supply the power of the analog part(AVDD,AVDDRV) */ ++ ++ /* ++ * 5. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x1 to setup ++ * reference voltage ++ * ++ * Note: Only the reg (ADC_ANA_CON10+0x0)[7] represent the enable ++ * signal of reference voltage module ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_REF_EN, RK3308_ADC_REF_EN); ++ ++ /* ++ * 6. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to ++ * 0x7f step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to ++ * 0x7f directly. The suggestion slot time of the step is 20ms. ++ */ ++ mdelay(20); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, ++ RK3308_ADC_DONT_SEL_ALL); ++ ++ /* 7. Wait until the voltage of VCM keeps stable at the AVDD/2 */ ++ usleep_range(200, 300); /* estimated value */ ++ ++ /* ++ * 8. Configure the register ACODEC_ADC_ANA_CON10[6:0] to the ++ * appropriate value(expect 0x0) for reducing power. ++ */ ++ ++ /* TODO: choose an appropriate charge value */ ++ ++ return 0; ++} ++ ++static int rk3308_codec_power_off(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ /* ++ * 1. Keep the power on and disable the DAC and ADC path according to ++ * the section power on configuration standard usage flow. ++ */ ++ ++ /* 2. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 0x1 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, RK3308_ADC_SEL_I_64(1)); ++ ++ /* 3. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x0 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_REF_EN, RK3308_ADC_REF_DIS); ++ ++ /* ++ * 4.Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to 0x7f ++ * step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to 0x7f ++ * directly. The suggestion slot time of the step is 20ms ++ */ ++ mdelay(20); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, ++ RK3308_ADC_DONT_SEL_ALL); ++ ++ /* 5. Wait until the voltage of VCM keeps stable at the AGND */ ++ usleep_range(200, 300); /* estimated value */ ++ ++ /* 6. Power off the analog power supply */ ++ /* 7. Power off the digital power supply */ ++ ++ /* Do something via hardware */ ++ ++ return 0; ++} ++ ++static int check_micbias(int micbias) ++{ ++ switch (micbias) { ++ case RK3308_ADC_MICBIAS_VOLT_0_85: ++ case RK3308_ADC_MICBIAS_VOLT_0_8: ++ case RK3308_ADC_MICBIAS_VOLT_0_75: ++ case RK3308_ADC_MICBIAS_VOLT_0_7: ++ case RK3308_ADC_MICBIAS_VOLT_0_65: ++ case RK3308_ADC_MICBIAS_VOLT_0_6: ++ case RK3308_ADC_MICBIAS_VOLT_0_55: ++ case RK3308_ADC_MICBIAS_VOLT_0_5: ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308, ++ int micbias) ++{ ++ int ch = rk3308->adc_ch; ++ int ret; ++ ++ if (ch != 1 && ch != 2) { ++ dev_err(rk3308->plat_dev, ++ "%s: currnet ch: %d, only ch1/2 control MICBIAS1/2\n", ++ __func__, ch); ++ return -EINVAL; ++ } ++ ++ /* 1. Power up the ACODEC and keep the AVDDH stable */ ++ ++ /* 2. Configure ACODEC_ADC_ANA_CON7[2:0] to the certain value */ ++ ret = check_micbias(micbias); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, "This is an invalid micbias: %d\n", ++ micbias); ++ return ret; ++ } ++ ++ /* ++ * Note: Only the reg (ADC_ANA_CON7+0x0)[2:0] represent the level range ++ * control signal of MICBIAS voltage ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), ++ RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK, ++ micbias); ++ ++ /* 3. Wait until the VCMH keep stable */ ++ usleep_range(200, 300); /* estimated value */ ++ ++ /* 4. Configure ACODEC_ADC_ANA_CON8[4] to 0x1 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(ch), ++ RK3308_ADC_MICBIAS_CURRENT_MSK, ++ RK3308_ADC_MICBIAS_CURRENT_EN); ++ ++ /* ++ * 5. Configure the (ADC_ANA_CON7+0x40)[3] or (ADC_ANA_CON7+0x80)[3] ++ * to 0x1. ++ * (ADC_ANA_CON7+0x40)[3] used to control the MICBIAS1, and ++ * (ADC_ANA_CON7+0x80)[3] used to control the MICBIAS2 ++ */ ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), ++ RK3308_ADC_MIC_BIAS_BUF_EN, ++ RK3308_ADC_MIC_BIAS_BUF_EN); ++ ++ return 0; ++} ++ ++static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308) ++{ ++ int ch = rk3308->adc_ch; ++ ++ if (ch != 1 && ch != 2) { ++ dev_err(rk3308->plat_dev, ++ "%s: currnet ch: %d, only ch1/2 control MICBIAS1/2\n", ++ __func__, ch); ++ return -EINVAL; ++ } ++ ++ /* 1. Enable the MICBIAS and keep the Audio Codec stable */ ++ /* Do nothing */ ++ ++ /* ++ * 2. Configure the (ADC_ANA_CON7+0x40)[3] or ++ * (ADC_ANA_CON7+0x80)[3] to 0x0 ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), ++ RK3308_ADC_MIC_BIAS_BUF_EN, ++ RK3308_ADC_MIC_BIAS_BUF_DIS); ++ ++ /* 3. Configure ACODEC_ADC_ANA_CON8[4] to 0x0 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(ch), ++ RK3308_ADC_MICBIAS_CURRENT_MSK, ++ RK3308_ADC_MICBIAS_CURRENT_DIS); ++ ++ return 0; ++} ++ ++static int rk3308_codec_alc_enable(struct rk3308_codec_priv *rk3308) ++{ ++ int ch = rk3308->adc_ch; ++ ++ /* ++ * 1. Set he max level and min level of the ALC need to control. ++ * ++ * These values are estimated ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON05(ch), ++ RK3308_AGC_LO_8BITS_AGC_MIN_MSK, ++ 0x16); ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON05(ch), ++ RK3308_AGC_HI_8BITS_AGC_MIN_MSK, ++ 0x40); ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON05(ch), ++ RK3308_AGC_LO_8BITS_AGC_MAX_MSK, ++ 0x26); ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON05(ch), ++ RK3308_AGC_HI_8BITS_AGC_MAX_MSK, ++ 0x40); ++ ++ /* ++ * 2. Set ACODEC_ALC_DIG_CON4[2:0] according to the sample rate ++ * ++ * By default is 44.1KHz for sample. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON04(ch), ++ RK3308_AGC_APPROX_RATE_MSK, ++ RK3308_AGC_APPROX_RATE_44_1K); ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON04(ch), ++ RK3308_AGC_APPROX_RATE_MSK, ++ RK3308_AGC_APPROX_RATE_44_1K); ++ ++ /* 3. Set ACODEC_ALC_DIG_CON9[6] to 0x1, to enable the ALC module */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), ++ RK3308_AGC_FUNC_SEL_MSK, ++ RK3308_AGC_FUNC_SEL_EN); ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(ch), ++ RK3308_AGC_FUNC_SEL_MSK, ++ RK3308_AGC_FUNC_SEL_EN); ++ ++ /* ++ * 4. Set ACODEC_ADC_ANA_CON11[1:0], (ACODEC_ADC_ANA_CON11+0x40)[1:0], ++ * (ACODEC_ADC_ANA_CON11+0x80)[1:0] and (ACODEC_ADC_ANA_CON11+0xc0)[1:0] ++ * to 0x3, to enable the ALC module to control the gain of PGA. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(ch), ++ RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK | ++ RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK, ++ RK3308_ADC_ALCL_CON_GAIN_PGAL_EN | ++ RK3308_ADC_ALCR_CON_GAIN_PGAR_EN); ++ ++ /* ++ * 5.Observe the current ALC output gain by reading ++ * ACODEC_ALC_DIG_CON12[4:0] ++ * ++ * The default GAIN is 0x0c ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON12(ch), ++ RK3308_AGC_GAIN_MSK, ++ 0x0c); ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON12(ch), ++ RK3308_AGC_GAIN_MSK, ++ 0x0c); ++ ++ return 0; ++} ++ ++static int rk3308_codec_alc_disable(struct rk3308_codec_priv *rk3308) ++{ ++ int ch = rk3308->adc_ch; ++ ++ /* ++ * 1. Set ACODEC_ALC_DIG_CON9[6] to 0x0, to disable the ALC module, ++ * then the ALC output gain will keep to the last value ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), ++ RK3308_AGC_FUNC_SEL_MSK, ++ RK3308_AGC_FUNC_SEL_DIS); ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(ch), ++ RK3308_AGC_FUNC_SEL_MSK, ++ RK3308_AGC_FUNC_SEL_DIS); ++ ++ /* ++ * 2. Set ACODEC_ADC_ANA_CON11[1:0], (ACODEC_ADC_ANA_CON11+0x40)[1:0], ++ * (ACODEC_ADC_ANA_CON11+0x80)[1:0] and (ACODEC_ADC_ANA_CON11+0xc0)[1:0] ++ * to 0x0, to disable the ALC module to control the gain of PGA. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(ch), ++ RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK | ++ RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK, ++ RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS | ++ RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS); ++ ++ return 0; ++} ++ ++static int rk3308_codec_adc_ana_enable(struct rk3308_codec_priv *rk3308) ++{ ++ unsigned int adc_aif1 = 0, adc_aif2 = 0; ++ unsigned int agc_func_en; ++ int ch = rk3308->adc_ch; ++ ++ /* ++ * 1. Set the ACODEC_ADC_ANA_CON7[7:6] and ACODEC_ADC_ANA_CON7[5:4], ++ * to select the line-in or microphone as input of ADC ++ * ++ * Note1. Please ignore the step1 for enabling ADC3, ADC4, ADC5, ++ * ADC6, ADC7, and ADC8 ++ */ ++ if (ch == 0) { ++ if (rk3308->adc_ch0_using_linein) { ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), ++ RK3308_ADC_CH1_IN_SEL_MSK, ++ RK3308_ADC_CH1_IN_LINEIN); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), ++ RK3308_ADC_CH2_IN_SEL_MSK, ++ RK3308_ADC_CH2_IN_LINEIN); ++ } else { ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), ++ RK3308_ADC_CH1_IN_SEL_MSK, ++ RK3308_ADC_CH1_IN_MIC); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), ++ RK3308_ADC_CH2_IN_SEL_MSK, ++ RK3308_ADC_CH2_IN_MIC); ++ } ++ } ++ ++ /* ++ * 2. Set ACODEC_ADC_ANA_CON0[7:0] to 0xff, to end the mute station ++ * of ADC, to enable the MIC module, to enable the reference voltage ++ * buffer, and to end the initialization of MIC ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(ch), ++ RK3308_ADC_CH1_CH2_MIC_ALL_MSK, ++ RK3308_ADC_CH1_CH2_MIC_ALL); ++ ++ /* ++ * 3. Set ACODEC_ADC_ANA_CON6[0] to 0x1, to enable the current source ++ * of audio ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(ch), ++ RK3308_ADC_CURRENT_MSK, ++ RK3308_ADC_CURRENT_EN); ++ ++ /* ++ * 4. Set ACODEC_ADC_ANA_CON2[7:0] to 0x77, to enable the ALC module, ++ * to enable the zero-crossing detection function, and to end the ++ * initialization of ALC ++ * ++ * Note2. Please set ACODEC_ADC_ANA_CON2[7:0] to 0x33 in step4 ++ * if the AGC function is closed ++ */ ++ ++ adc_aif1 = RK3308_ADC_CH1_ALC_EN | RK3308_ADC_CH1_ALC_WORK; ++ regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), &agc_func_en); ++ if (agc_func_en & RK3308_AGC_FUNC_SEL_EN) ++ adc_aif1 |= RK3308_ADC_CH1_ZEROCROSS_DET_EN; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch), ++ RK3308_ADC_CH1_ALC_ZC_MSK, ++ adc_aif1); ++ ++ adc_aif2 = RK3308_ADC_CH2_ALC_EN | RK3308_ADC_CH2_ALC_WORK; ++ regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), &agc_func_en); ++ if (agc_func_en & RK3308_AGC_FUNC_SEL_EN) ++ adc_aif2 |= RK3308_ADC_CH2_ZEROCROSS_DET_EN; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch), ++ RK3308_ADC_CH2_ALC_ZC_MSK, ++ adc_aif2); ++ ++ /* ++ * 5. Set ACODEC_ADC_ANA_CON5[7:0] to 0x77, to enable the clock and ++ * ADC module, and to end the initialization of ADC ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), ++ RK3308_ADC_CH1_ADC_CLK_MSK, ++ RK3308_ADC_CH1_CLK_EN | ++ RK3308_ADC_CH1_ADC_EN | ++ RK3308_ADC_CH1_ADC_WORK); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), ++ RK3308_ADC_CH2_ADC_CLK_MSK, ++ RK3308_ADC_CH2_CLK_EN | ++ RK3308_ADC_CH2_ADC_EN | ++ RK3308_ADC_CH2_ADC_WORK); ++ ++ /* ++ * 6. Set ACODEC_ADC_ANA_CON1[5:4] and ACODEC_ADC_ANA_CON1[1:0], ++ * to select the gain of the MIC ++ * ++ * By default is 0db. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), ++ RK3308_ADC_CH1_MIC_GAIN_MSK, ++ RK3308_ADC_CH1_MIC_GAIN_0DB); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), ++ RK3308_ADC_CH2_MIC_GAIN_MSK, ++ RK3308_ADC_CH2_MIC_GAIN_0DB); ++ ++ /* ++ * 7.Set ACODEC_ADC_ANA_CON3[4:0] and ACODEC_ADC_ANA_CON4[3:0] to ++ * select the gain of ALC ++ * ++ * By default is 0db. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON03(ch), ++ RK3308_ADC_CH1_ALC_GAIN_MSK, ++ RK3308_ADC_CH1_ALC_GAIN_0DB); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON04(ch), ++ RK3308_ADC_CH2_ALC_GAIN_MSK, ++ RK3308_ADC_CH2_ALC_GAIN_0DB); ++ ++ /* 8.Begin recording */ ++ ++ return 0; ++} ++ ++static int rk3308_codec_adc_ana_disable(struct rk3308_codec_priv *rk3308) ++{ ++ int ch = rk3308->adc_ch; ++ ++ /* ++ * 1. Set ACODEC_ADC_ANA_CON2[7:0] to 0x0, to disable the ALC module, ++ * to disable the zero-crossing detection function, and to begin the ++ * initialization of ALC ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch), ++ RK3308_ADC_CH1_ALC_ZC_MSK, ++ 0); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch), ++ RK3308_ADC_CH2_ALC_ZC_MSK, ++ 0); ++ ++ /* ++ * 2. Set ACODEC_ADC_ANA_CON5[7:0] to 0x0, to disable the clock and ++ * ADC module, and to begin the initialization of ADC ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), ++ RK3308_ADC_CH1_ADC_CLK_MSK, ++ 0); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), ++ RK3308_ADC_CH2_ADC_CLK_MSK, ++ 0); ++ ++ /* ++ * 3. Set ACODEC_ADC_ANA_CON0[7:0] to 0x88, to disable the MIC module, ++ * to disable the reference voltage buffer, and to begin the ++ * initialization of MIC ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(ch), ++ RK3308_ADC_CH1_CH2_MIC_ALL_MSK, ++ RK3308_ADC_CH1_MIC_UNMUTE | ++ RK3308_ADC_CH2_MIC_UNMUTE); ++ ++ /* ++ * 4. Set ACODEC_ADC_ANA_CON6[0] to 0x0, to disable the current ++ * source of audio ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(ch), ++ RK3308_ADC_CURRENT_MSK, ++ RK3308_ADC_CURRENT_DIS); ++ ++ return 0; ++} ++ ++static int rk3308_codec_open_capture(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ rk3308_codec_alc_enable(rk3308); ++ rk3308_codec_adc_ana_enable(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_codec_close_capture(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ rk3308_codec_alc_disable(rk3308); ++ rk3308_codec_adc_ana_disable(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_codec_open_playback(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ rk3308_codec_dac_enable(rk3308); ++ rk3308_speaker_ctl(rk3308, 1); ++ ++ return 0; ++} ++ ++static int rk3308_codec_close_playback(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ rk3308_speaker_ctl(rk3308, 0); ++ rk3308_codec_dac_disable(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_pcm_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ int ret = 0; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ ret = rk3308_codec_open_playback(codec); ++ else ++ ret = rk3308_codec_open_capture(codec); ++ ++ return ret; ++} ++ ++static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ rk3308_codec_close_playback(codec); ++ else ++ rk3308_codec_close_capture(codec); ++} ++ ++static struct snd_soc_dai_ops rk3308_dai_ops = { ++ .hw_params = rk3308_hw_params, ++ .set_fmt = rk3308_set_dai_fmt, ++ .digital_mute = rk3308_digital_mute, ++ .startup = rk3308_pcm_startup, ++ .shutdown = rk3308_pcm_shutdown, ++}; ++ ++static struct snd_soc_dai_driver rk3308_dai[] = { ++ { ++ .name = "rk3308-hifi", ++ .id = RK3308_HIFI, ++ .playback = { ++ .stream_name = "HiFi Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_96000, ++ .formats = (SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S20_3LE | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S32_LE), ++ }, ++ .capture = { ++ .stream_name = "HiFi Capture", ++ .channels_min = 1, ++ .channels_max = 8, ++ .rates = SNDRV_PCM_RATE_8000_96000, ++ .formats = (SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S20_3LE | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S32_LE), ++ }, ++ .ops = &rk3308_dai_ops, ++ }, ++}; ++ ++static int rk3308_suspend(struct snd_soc_codec *codec) ++{ ++ rk3308_set_bias_level(codec, SND_SOC_BIAS_OFF); ++ ++ return 0; ++} ++ ++static int rk3308_resume(struct snd_soc_codec *codec) ++{ ++ rk3308_set_bias_level(codec, SND_SOC_BIAS_STANDBY); ++ ++ return 0; ++} ++ ++static int rk3308_probe(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ rk3308_codec_reset(codec); ++ rk3308_codec_power_on(codec); ++ ++ rk3308_codec_micbias_enable(rk3308, RK3308_ADC_MICBIAS_VOLT_0_7); ++ ++ return 0; ++} ++ ++static int rk3308_remove(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ rk3308_speaker_ctl(rk3308, 0); ++ rk3308_codec_micbias_disable(rk3308); ++ rk3308_codec_power_off(codec); ++ ++ return 0; ++} ++ ++static struct snd_soc_codec_driver soc_codec_dev_rk3308 = { ++ .probe = rk3308_probe, ++ .remove = rk3308_remove, ++ .suspend = rk3308_suspend, ++ .resume = rk3308_resume, ++ .set_bias_level = rk3308_set_bias_level, ++ .controls = rk3308_codec_dapm_controls, ++ .num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls), ++}; ++ ++static const struct reg_default rk3308_codec_reg_defaults[] = { ++ { RK3308_GLB_CON, 0x07 }, ++}; ++ ++static bool rk3308_codec_write_read_reg(struct device *dev, unsigned int reg) ++{ ++ /* All registers can be read / write */ ++ return true; ++} ++ ++static bool rk3308_codec_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case RK3308_GLB_CON: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static const struct regmap_config rk3308_codec_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = RK3308_DAC_ANA_CON13, ++ .writeable_reg = rk3308_codec_write_read_reg, ++ .readable_reg = rk3308_codec_write_read_reg, ++ .volatile_reg = rk3308_codec_volatile_reg, ++ .reg_defaults = rk3308_codec_reg_defaults, ++ .num_reg_defaults = ARRAY_SIZE(rk3308_codec_reg_defaults), ++ .cache_type = REGCACHE_FLAT, ++}; ++ ++static ssize_t adc_ch_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ ++ return sprintf(buf, "adc_ch: %d\n", rk3308->adc_ch); ++} ++ ++static ssize_t adc_ch_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ unsigned long ch; ++ int ret = kstrtoul(buf, 10, &ch); ++ ++ if (ret < 0 || ch > 4) { ++ dev_err(dev, "Invalid ch: %ld, ret: %d\n", ch, ret); ++ return -EINVAL; ++ } ++ ++ rk3308->adc_ch = ch; ++ ++ dev_info(dev, "Store ch: %d\n", rk3308->adc_ch); ++ ++ return count; ++} ++ ++static const struct device_attribute adc_ch_attrs[] = { ++ __ATTR(adc_ch, 0644, adc_ch_show, adc_ch_store), ++}; ++ ++static void rk3308_codec_device_release(struct device *dev) ++{ ++ /* Do nothing */ ++} ++ ++static int rk3308_codec_sysfs_init(struct platform_device *pdev, ++ struct rk3308_codec_priv *rk3308) ++{ ++ struct device *dev = &rk3308->dev; ++ int i; ++ ++ dev->release = rk3308_codec_device_release; ++ dev->parent = &pdev->dev; ++ set_dev_node(dev, dev_to_node(&pdev->dev)); ++ dev_set_name(dev, "rk3308-acodec-dev"); ++ ++ if (device_register(dev)) { ++ dev_err(&pdev->dev, ++ "Register 'rk3308-acodec-dev' failed\n"); ++ dev->parent = NULL; ++ return -ENOMEM; ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(adc_ch_attrs); i++) { ++ if (device_create_file(dev, &adc_ch_attrs[i])) { ++ dev_err(&pdev->dev, ++ "Create 'rk3308-acodec-dev' attr failed\n"); ++ device_unregister(dev); ++ return -ENOMEM; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rk3308_platform_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct rk3308_codec_priv *rk3308; ++ struct resource *res; ++ void __iomem *base; ++ int ret = 0; ++ struct regmap *grf; ++ ++ grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); ++ if (IS_ERR(grf)) { ++ dev_err(&pdev->dev, ++ "Missing 'rockchip,grf' property\n"); ++ return PTR_ERR(grf); ++ } ++ ++ rk3308 = devm_kzalloc(&pdev->dev, sizeof(*rk3308), GFP_KERNEL); ++ if (!rk3308) ++ return -ENOMEM; ++ ++ ret = rk3308_codec_sysfs_init(pdev, rk3308); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Sysfs init failed\n"); ++ return ret; ++ } ++ ++ rk3308->plat_dev = &pdev->dev; ++ ++ rk3308->reset = devm_reset_control_get(&pdev->dev, "acodec-reset"); ++ if (IS_ERR(rk3308->reset)) { ++ ret = PTR_ERR(rk3308->reset); ++ if (ret != -ENOENT) ++ return ret; ++ ++ dev_dbg(&pdev->dev, "No reset control found\n"); ++ rk3308->reset = NULL; ++ } ++ ++ /* GPIO0_A5 control speaker on RK3308 EVB */ ++ rk3308->spk_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "spk_ctl", ++ GPIOD_OUT_HIGH); ++ if (IS_ERR(rk3308->spk_ctl_gpio)) { ++ ret = PTR_ERR(rk3308->spk_ctl_gpio); ++ dev_err(&pdev->dev, "Unable to claim gpio spk_ctl\n"); ++ return ret; ++ } ++ ++ rk3308->pclk = devm_clk_get(&pdev->dev, "acodec"); ++ if (IS_ERR(rk3308->pclk)) { ++ dev_err(&pdev->dev, "Can't get acodec pclk\n"); ++ return PTR_ERR(rk3308->pclk); ++ } ++ ++ ret = clk_prepare_enable(rk3308->pclk); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to enable acodec pclk: %d\n", ret); ++ return ret; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) { ++ ret = PTR_ERR(base); ++ dev_err(&pdev->dev, "Failed to ioremap resource\n"); ++ goto failed; ++ } ++ ++ rk3308->regmap = devm_regmap_init_mmio(&pdev->dev, base, ++ &rk3308_codec_regmap_config); ++ if (IS_ERR(rk3308->regmap)) { ++ ret = PTR_ERR(rk3308->regmap); ++ dev_err(&pdev->dev, "Failed to regmap mmio\n"); ++ goto failed; ++ } ++ ++ platform_set_drvdata(pdev, rk3308); ++ ++ ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_rk3308, ++ rk3308_dai, ARRAY_SIZE(rk3308_dai)); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to register codec: %d\n", ret); ++ goto failed; ++ } ++ ++ return ret; ++ ++failed: ++ clk_disable_unprepare(rk3308->pclk); ++ ++ return ret; ++} ++ ++static int rk3308_platform_remove(struct platform_device *pdev) ++{ ++ struct rk3308_codec_priv *rk3308 = ++ (struct rk3308_codec_priv *)platform_get_drvdata(pdev); ++ ++ clk_disable_unprepare(rk3308->pclk); ++ snd_soc_unregister_codec(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id rk3308codec_of_match[] = { ++ { .compatible = "rockchip,rk3308-codec", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, rk3308codec_of_match); ++ ++static struct platform_driver rk3308_codec_driver = { ++ .driver = { ++ .name = "rk3308-acodec", ++ .of_match_table = of_match_ptr(rk3308codec_of_match), ++ }, ++ .probe = rk3308_platform_probe, ++ .remove = rk3308_platform_remove, ++}; ++module_platform_driver(rk3308_codec_driver); ++ ++MODULE_AUTHOR("Xing Zheng "); ++MODULE_DESCRIPTION("ASoC RK3308 Codec Driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/sound/soc/codecs/rk3308_codec.h b/sound/soc/codecs/rk3308_codec.h +new file mode 100644 +index 000000000000..6cfa69157785 +--- /dev/null ++++ b/sound/soc/codecs/rk3308_codec.h +@@ -0,0 +1,960 @@ ++/* ++ * rk3308_codec.h -- RK3308 ALSA Soc Audio Driver ++ * ++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++ ++#ifndef __RK3308_CODEC_H__ ++#define __RK3308_CODEC_H__ ++ ++#define ACODEC_RESET_CTL 0x00 /* REG 0x00 */ ++ ++/* ADC DIGITAL REGISTERS */ ++#define ACODEC_ADC_I2S_CTL0 0x04 /* REG 0x01 */ ++#define ACODEC_ADC_I2S_CTL1 0x08 /* REG 0x02 */ ++#define ACODEC_ADC_BIST_MODE_SEL 0x0c /* REG 0x03 */ ++/* Resevred REG 0x04 ~ 0x06 */ ++#define ACODEC_ADC_DATA_PATH 0x1c /* REG 0x07 */ ++/* Resevred REG 0x08 ~ 0x0f */ ++ ++/* REG 0x10 ~ 0x1c are used to configure AGC of Left channel (ALC1) */ ++#define ACODEC_ADC_PGA_AGC_L_CTL0 0x40 /* REG 0x10 */ ++#define ACODEC_ADC_PGA_AGC_L_CTL1 0x44 /* REG 0x11 */ ++#define ACODEC_ADC_PGA_AGC_L_CTL2 0x48 /* REG 0x12 */ ++#define ACODEC_ADC_PGA_AGC_L_CTL3 0x4c /* REG 0x13 */ ++#define ACODEC_ADC_PGA_AGC_L_CTL4 0x50 /* REG 0x14 */ ++#define ACODEC_ADC_PGA_AGC_L_LO_MAX 0x54 /* REG 0x15 */ ++#define ACODEC_ADC_PGA_AGC_L_HI_MAX 0x58 /* REG 0x16 */ ++#define ACODEC_ADC_PGA_AGC_L_LO_MIN 0x5c /* REG 0x17 */ ++#define ACODEC_ADC_PGA_AGC_L_HI_MIN 0x60 /* REG 0x18 */ ++#define ACODEC_ADC_PGA_AGC_L_CTL5 0x64 /* REG 0x19 */ ++/* Resevred REG 0x1a ~ 0x1b */ ++#define ACODEC_ADC_AGC_L_RO_GAIN 0x70 /* REG 0x1c */ ++ ++/* REG 0x20 ~ 0x2c are used to configure AGC of Right channel (ALC2) */ ++#define ACODEC_ADC_PGA_AGC_R_CTL0 0x80 /* REG 0x20 */ ++#define ACODEC_ADC_PGA_AGC_R_CTL1 0x84 /* REG 0x21 */ ++#define ACODEC_ADC_PGA_AGC_R_CTL2 0x88 /* REG 0x22 */ ++#define ACODEC_ADC_PGA_AGC_R_CTL3 0x8c /* REG 0x23 */ ++#define ACODEC_ADC_PGA_AGC_R_CTL4 0x90 /* REG 0x24 */ ++#define ACODEC_ADC_PGA_AGC_R_LO_MAX 0x94 /* REG 0x25 */ ++#define ACODEC_ADC_PGA_AGC_R_HI_MAX 0x98 /* REG 0x26 */ ++#define ACODEC_ADC_PGA_AGC_R_LO_MIN 0x9c /* REG 0x27 */ ++#define ACODEC_ADC_PGA_AGC_R_HI_MIN 0xa0 /* REG 0x28 */ ++#define ACODEC_ADC_PGA_AGC_R_CTL5 0xa4 /* REG 0x29 */ ++/* Resevred REG 0x2a ~ 0x2b */ ++#define ACODEC_ADC_AGC_R_RO_GAIN 0xb0 /* REG 0x2c */ ++ ++/* DAC DIGITAL REGISTERS */ ++#define ACODEC_DAC_I2S_CTL0 0x04 /* REG 0x01 */ ++#define ACODEC_DAC_I2S_CTL1 0x08 /* REG 0x02 */ ++#define ACODEC_DAC_BIST_MODE_SEL 0x0c /* REG 0x03 */ ++/* Resevred REG 0x04 */ ++#define ACODEC_DAC_DATA_SEL 0x14 /* REG 0x05 */ ++/* Resevred REG 0x06 ~ 0x09 */ ++#define ACODEC_DAC_DATA_HI 0x28 /* REG 0x0a */ ++#define ACODEC_DAC_DATA_LO 0x2c /* REG 0x0b */ ++/* Resevred REG 0x0c ~ 0x0f */ ++ ++/* ADC ANALOG REGISTERS */ ++#define ACODEC_ADC_ANA_MIC_CTL 0x00 /* REG 0x00 */ ++#define ACODEC_ADC_ANA_MIC_GAIN 0x04 /* REG 0x01 */ ++#define ACODEC_ADC_ANA_ALC_CTL 0x08 /* REG 0x02 */ ++#define ACODEC_ADC_ANA_ALC_GAIN1 0x0c /* REG 0x03 */ ++#define ACODEC_ADC_ANA_ALC_GAIN2 0x10 /* REG 0x04 */ ++#define ACODEC_ADC_ANA_CTL0 0x14 /* REG 0x05 */ ++#define ACODEC_ADC_ANA_CTL1 0x18 /* REG 0x06 */ ++#define ACODEC_ADC_ANA_CTL2 0x1c /* REG 0x07 */ ++#define ACODEC_ADC_ANA_CTL3 0x20 /* REG 0x08 */ ++/* Resevred REG 0x09 */ ++#define ACODEC_ADC_ANA_CTL4 0x28 /* REG 0x0a */ ++#define ACODEC_ADC_ANA_ALC_PGA 0x2c /* REG 0x0b */ ++/* Resevred REG 0x0c ~ 0x0f */ ++ ++/* DAC ANALOG REGISTERS */ ++#define ACODEC_DAC_ANA_CTL0 0x00 /* REG 0x00 */ ++#define ACODEC_DAC_ANA_POP_VOLT 0x04 /* REG 0x01 */ ++#define ACODEC_DAC_ANA_CTL1 0x08 /* REG 0x02 */ ++#define ACODEC_DAC_ANA_HPOUT 0x0c /* REG 0x03 */ ++#define ACODEC_DAC_ANA_LINEOUT 0x10 /* REG 0x04 */ ++#define ACODEC_DAC_ANA_L_HPOUT_GAIN 0x14 /* REG 0x05 */ ++#define ACODEC_DAC_ANA_R_HPOUT_GAIN 0x18 /* REG 0x06 */ ++/* Resevred REG 0x07 ~ 0x0b */ ++#define ACODEC_DAC_ANA_HPMIX_CTL0 0x30 /* REG 0x0c */ ++#define ACODEC_DAC_ANA_HPMIX_CTL1 0x34 /* REG 0x0d */ ++/* Resevred REG 0x0e ~ 0x0f */ ++ ++/* ++ * These registers are referenced by codec driver ++ */ ++ ++#define RK3308_GLB_CON ACODEC_RESET_CTL ++ ++/* ADC DIGITAL REGISTERS */ ++ ++/* ++ * The ADC chanel are 0 ~ 3, that control: ++ * ++ * CH0: left_0(ADC1) and right_0(ADC2) ++ * CH1: left_1(ADC3) and right_1(ADC4) ++ * CH2: left_2(ADC5) and right_2(ADC6) ++ * CH3: left_3(ADC7) and right_3(ADC8) ++ */ ++#define RK3308_ADC_DIG_OFFSET(ch) ((ch & 0x3) * 0xc0 + 0x0) ++ ++#define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL0) ++#define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1) ++#define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL) ++#define RK3308_ADC_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH) ++ ++#define RK3308_ALC_L_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0) ++#define RK3308_ALC_L_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL1) ++#define RK3308_ALC_L_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL2) ++#define RK3308_ALC_L_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL3) ++#define RK3308_ALC_L_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL4) ++#define RK3308_ALC_L_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MAX) ++#define RK3308_ALC_L_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MAX) ++#define RK3308_ALC_L_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_LO_MIN) ++#define RK3308_ALC_L_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_HI_MIN) ++#define RK3308_ALC_L_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL5) ++#define RK3308_ALC_L_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_L_RO_GAIN) ++ ++#define RK3308_ALC_R_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL0) ++#define RK3308_ALC_R_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL1) ++#define RK3308_ALC_R_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL2) ++#define RK3308_ALC_R_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL3) ++#define RK3308_ALC_R_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL4) ++#define RK3308_ALC_R_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MAX) ++#define RK3308_ALC_R_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MAX) ++#define RK3308_ALC_R_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_LO_MIN) ++#define RK3308_ALC_R_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_HI_MIN) ++#define RK3308_ALC_R_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_R_CTL5) ++#define RK3308_ALC_R_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_AGC_R_RO_GAIN) ++ ++/* DAC DIGITAL REGISTERS */ ++#define RK3308_DAC_DIG_OFFSET 0x300 ++ ++#define RK3308_DAC_DIG_CON01 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL0) ++#define RK3308_DAC_DIG_CON02 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL1) ++#define RK3308_DAC_DIG_CON03 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_BIST_MODE_SEL) ++#define RK3308_DAC_DIG_CON05 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_SEL) ++#define RK3308_DAC_DIG_CON10 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_HI) ++#define RK3308_DAC_DIG_CON11 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_LO) ++ ++/* ADC ANALOG REGISTERS */ ++/* ++ * The ADC chanel are 0 ~ 3, that control: ++ * ++ * CH0: left_0(ADC1) and right_0(ADC2) ++ * CH1: left_1(ADC3) and right_1(ADC4) ++ * CH2: left_2(ADC5) and right_2(ADC6) ++ * CH3: left_3(ADC7) and right_3(ADC8) ++ */ ++#define RK3308_ADC_ANA_OFFSET(ch) ((ch & 0x3) * 0x40 + 0x340) ++ ++#define RK3308_ADC_ANA_CON00(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_CTL) ++#define RK3308_ADC_ANA_CON01(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_MIC_GAIN) ++#define RK3308_ADC_ANA_CON02(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_CTL) ++#define RK3308_ADC_ANA_CON03(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN1) ++#define RK3308_ADC_ANA_CON04(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_GAIN2) ++#define RK3308_ADC_ANA_CON05(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL0) ++#define RK3308_ADC_ANA_CON06(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL1) ++#define RK3308_ADC_ANA_CON07(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL2) ++#define RK3308_ADC_ANA_CON08(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL3) ++#define RK3308_ADC_ANA_CON10(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_CTL4) ++#define RK3308_ADC_ANA_CON11(ch) (RK3308_ADC_ANA_OFFSET(ch) + ACODEC_ADC_ANA_ALC_PGA) ++ ++/* DAC ANALOG REGISTERS */ ++#define RK3308_DAC_ANA_OFFSET 0x440 ++ ++#define RK3308_DAC_ANA_CON00 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL0) ++#define RK3308_DAC_ANA_CON01 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_POP_VOLT) ++#define RK3308_DAC_ANA_CON02 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL1) ++#define RK3308_DAC_ANA_CON03 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPOUT) ++#define RK3308_DAC_ANA_CON04 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT) ++#define RK3308_DAC_ANA_CON05 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_L_HPOUT_GAIN) ++#define RK3308_DAC_ANA_CON06 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_R_HPOUT_GAIN) ++#define RK3308_DAC_ANA_CON12 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL0) ++#define RK3308_DAC_ANA_CON13 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL1) ++ ++/* ++ * These are the bits for registers ++ */ ++ ++/* RK3308_GLB_CON - REG: 0x0000 */ ++#define RK3308_ADC_BIST_WORK (1 << 7) ++#define RK3308_ADC_BIST_RESET (0 << 7) ++#define RK3308_DAC_BIST_WORK (1 << 6) ++#define RK3308_DAC_BIST_RESET (0 << 6) ++#define RK3308_CODEC_RST_MSK (0x7 << 0) ++#define RK3308_ADC_DIG_WORK (1 << 2) ++#define RK3308_ADC_DIG_RESET (0 << 2) ++#define RK3308_DAC_DIG_WORK (1 << 1) ++#define RK3308_DAC_DIG_RESET (0 << 1) ++#define RK3308_SYS_WORK (1 << 0) ++#define RK3308_SYS_RESET (0 << 0) ++ ++/* RK3308_ADC_DIG_CON01 - REG: 0x0004 */ ++#define RK3308_ADC_I2S_LRC_POL_MSK (1 << 0) ++#define RK3308_ADC_I2S_LRC_POL_REVERSAL (1 << 0) ++#define RK3308_ADC_I2S_LRC_POL_NORMAL (0 << 0) ++#define RK3308_ADC_I2S_VALID_LEN_SFT 5 ++#define RK3308_ADC_I2S_VALID_LEN_MSK (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT) ++#define RK3308_ADC_I2S_VALID_LEN_32BITS (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT) ++#define RK3308_ADC_I2S_VALID_LEN_24BITS (0x2 << RK3308_ADC_I2S_VALID_LEN_SFT) ++#define RK3308_ADC_I2S_VALID_LEN_20BITS (0x1 << RK3308_ADC_I2S_VALID_LEN_SFT) ++#define RK3308_ADC_I2S_VALID_LEN_16BITS (0x0 << RK3308_ADC_I2S_VALID_LEN_SFT) ++#define RK3308_ADC_I2S_MODE_SFT 3 ++#define RK3308_ADC_I2S_MODE_MSK (0x3 << RK3308_ADC_I2S_MODE_SFT) ++#define RK3308_ADC_I2S_MODE_PCM (0x3 << RK3308_ADC_I2S_MODE_SFT) ++#define RK3308_ADC_I2S_MODE_I2S (0x2 << RK3308_ADC_I2S_MODE_SFT) ++#define RK3308_ADC_I2S_MODE_LJ (0x1 << RK3308_ADC_I2S_MODE_SFT) ++#define RK3308_ADC_I2S_MODE_RJ (0x0 << RK3308_ADC_I2S_MODE_SFT) ++#define RK3308_ADC_I2S_LR_MSK (1 << 1) ++#define RK3308_ADC_I2S_LR_SWAP (1 << 1) ++#define RK3308_ADC_I2S_LR_NORMAL (0 << 1) ++#define RK3308_ADC_I2S_TYPE_MSK (1 << 0) ++#define RK3308_ADC_I2S_MONO (1 << 0) ++#define RK3308_ADC_I2S_STEREO (0 << 0) ++ ++/* RK3308_ADC_DIG_CON02 - REG: 0x0008 */ ++#define RK3308_ADC_IO_MODE_MSK (1 << 5) ++#define RK3308_ADC_IO_MODE_MASTER (1 << 5) ++#define RK3308_ADC_IO_MODE_SLAVE (0 << 5) ++#define RK3308_ADC_MODE_MSK (1 << 4) ++#define RK3308_ADC_MODE_MASTER (1 << 4) ++#define RK3308_ADC_MODE_SLAVE (0 << 4) ++#define RK3308_ADC_I2S_FRAME_LEN_SFT 2 ++#define RK3308_ADC_I2S_FRAME_LEN_MSK (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT) ++#define RK3308_ADC_I2S_FRAME_32BITS (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT) ++#define RK3308_ADC_I2S_FRAME_24BITS (0x2 << RK3308_ADC_I2S_FRAME_LEN_SFT) ++#define RK3308_ADC_I2S_FRAME_20BITS (0x1 << RK3308_ADC_I2S_FRAME_LEN_SFT) ++#define RK3308_ADC_I2S_FRAME_16BITS (0x0 << RK3308_ADC_I2S_FRAME_LEN_SFT) ++#define RK3308_ADC_I2S_MSK (0x1 << 1) ++#define RK3308_ADC_I2S_WORK (0x1 << 1) ++#define RK3308_ADC_I2S_RESET (0x0 << 1) ++#define RK3308_ADC_I2S_BIT_CLK_POL_MSK (0x1 << 0) ++#define RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL (0x1 << 0) ++#define RK3308_ADC_I2S_BIT_CLK_POL_NORMAL (0x0 << 0) ++ ++/* RK3308_ADC_DIG_CON03 - REG: 0x000c */ ++#define RK3308_ADC_L_CH_BIST_SFT 2 ++#define RK3308_ADC_L_CH_BIST_MSK (0x3 << RK3308_ADC_L_CH_BIST_SFT) ++#define RK3308_ADC_L_CH_BIST_LEFT (0x3 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */ ++#define RK3308_ADC_L_CH_BIST_SINE (0x2 << RK3308_ADC_L_CH_BIST_SFT) ++#define RK3308_ADC_L_CH_BIST_CUBE (0x1 << RK3308_ADC_L_CH_BIST_SFT) ++#define RK3308_ADC_L_CH_BIST_RIGHT (0x0 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */ ++#define RK3308_ADC_R_CH_BIST_SFT 0 ++#define RK3308_ADC_R_CH_BIST_MSK (0x3 << RK3308_ADC_R_CH_BIST_SFT) ++#define RK3308_ADC_R_CH_BIST_LEFT (0x3 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */ ++#define RK3308_ADC_R_CH_BIST_SINE (0x2 << RK3308_ADC_R_CH_BIST_SFT) ++#define RK3308_ADC_R_CH_BIST_CUBE (0x1 << RK3308_ADC_R_CH_BIST_SFT) ++#define RK3308_ADC_R_CH_BIST_RIGHT (0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */ ++ ++/* RK3308_ADC_DIG_CON07 - REG: 0x001c */ ++#define RK3308_ADCL_DATA_SFT 4 ++#define RK3308_ADCL_DATA(x) (x << RK3308_ADCL_DATA_SFT) ++#define RK3308_ADCR_DATA_SFT 2 ++#define RK3308_ADCR_DATA(x) (x << RK3308_ADCR_DATA_SFT) ++#define RK3308_ADCL_DATA_SEL_ADCL (0x1 << 1) ++#define RK3308_ADCL_DATA_SEL_NORMAL (0x0 << 1) ++#define RK3308_ADCR_DATA_SEL_ADCR (0x1 << 0) ++#define RK3308_ADCR_DATA_SEL_NORMAL (0x0 << 0) ++ ++/* ++ * RK3308_ALC_L_DIG_CON00 - REG: 0x0040 + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON00 - REG: 0x0080 + ch * 0xc0 ++ */ ++#define RK3308_GAIN_ATTACK_JACK (0x1 << 6) ++#define RK3308_GAIN_ATTACK_NORMAL (0x0 << 6) ++#define RK3308_CTRL_GEN_SFT 4 ++#define RK3308_CTRL_GEN_MSK (0x3 << RK3308_ALC_CTRL_GEN_SFT) ++#define RK3308_CTRL_GEN_JACK3 (0x3 << RK3308_ALC_CTRL_GEN_SFT) ++#define RK3308_CTRL_GEN_JACK2 (0x2 << RK3308_ALC_CTRL_GEN_SFT) ++#define RK3308_CTRL_GEN_JACK1 (0x1 << RK3308_ALC_CTRL_GEN_SFT) ++#define RK3308_CTRL_GEN_NORMAL (0x0 << RK3308_ALC_CTRL_GEN_SFT) ++#define RK3308_AGC_HOLD_TIME_SFT 0 ++#define RK3308_AGC_HOLD_TIME_MSK (0xf << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_1S (0xa << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_512MS (0x9 << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_256MS (0x8 << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_128MS (0x7 << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_64MS (0x6 << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_32MS (0x5 << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_16MS (0x4 << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_8MS (0x3 << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_4MS (0x2 << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_2MS (0x1 << RK3308_AGC_HOLD_TIME_SFT) ++#define RK3308_AGC_HOLD_TIME_0MS (0x0 << RK3308_AGC_HOLD_TIME_SFT) ++ ++/* ++ * RK3308_ALC_L_DIG_CON01 - REG: 0x0044 + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON01 - REG: 0x0084 + ch * 0xc0 ++ */ ++#define RK3308_AGC_DECAY_TIME_SFT 4 ++/* Normal mode (reg_agc_mode = 0) */ ++#define RK3308_AGC_DECAY_NORMAL_MSK (0xf << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_512MS (0xa << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_256MS (0x9 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_128MS (0x8 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_64MS (0x7 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_32MS (0x6 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_16MS (0x5 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_8MS (0x4 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_4MS (0x3 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_2MS (0x2 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_1MS (0x1 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_NORMAL_0MS (0x0 << RK3308_AGC_DECAY_TIME_SFT) ++/* Limiter mode (reg_agc_mode = 1) */ ++#define RK3308_AGC_DECAY_LIMITER_MSK (0xf << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_128MS (0xa << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_64MS (0x9 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_32MS (0x8 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_16MS (0x7 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_8MS (0x6 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_4MS (0x5 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_2MS (0x4 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_1MS (0x3 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_500US (0x2 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_250US (0x1 << RK3308_AGC_DECAY_TIME_SFT) ++#define RK3308_AGC_DECAY_LIMITER_125US (0x0 << RK3308_AGC_DECAY_TIME_SFT) ++ ++#define RK3308_AGC_ATTACK_TIME_SFT 0 ++/* Normal mode (reg_agc_mode = 0) */ ++#define RK3308_AGC_ATTACK_NORMAL_MSK (0xf << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_128MS (0xa << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_64MS (0x9 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_32MS (0x8 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_16MS (0x7 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_8MS (0x6 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_4MS (0x5 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_2MS (0x4 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_1MS (0x3 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_500US (0x2 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_250US (0x1 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_NORMAL_125US (0x0 << RK3308_AGC_ATTACK_TIME_SFT) ++/* Limiter mode (reg_agc_mode = 1) */ ++#define RK3308_AGC_ATTACK_LIMITER_MSK (0xf << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_32MS (0xa << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_16MS (0x9 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_8MS (0x8 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_4MS (0x7 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_2MS (0x6 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_1MS (0x5 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_500US (0x4 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_250US (0x3 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_125US (0x2 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_64US (0x1 << RK3308_AGC_ATTACK_TIME_SFT) ++#define RK3308_AGC_ATTACK_LIMITER_32US (0x0 << RK3308_AGC_ATTACK_TIME_SFT) ++ ++/* ++ * RK3308_ALC_L_DIG_CON02 - REG: 0x0048 + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON02 - REG: 0x0088 + ch * 0xc0 ++ */ ++#define RK3308_AGC_MODE_LIMITER (0x1 << 7) ++#define RK3308_AGC_MODE_NORMAL (0x0 << 7) ++#define RK3308_AGC_ZERO_CRO_EN (0x1 << 6) ++#define RK3308_AGC_ZERO_CRO_DIS (0x0 << 6) ++#define RK3308_AGC_AMP_RECOVER_GAIN (0x1 << 5) ++#define RK3308_AGC_AMP_RECOVER_LVOL (0x0 << 5) ++#define RK3308_AGC_FAST_DEC_EN (0x1 << 4) ++#define RK3308_AGC_FAST_DEC_DIS (0x0 << 4) ++#define RK3308_AGC_NOISE_GATE_EN (0x1 << 3) ++#define RK3308_AGC_NOISE_GATE_DIS (0x0 << 3) ++#define RK3308_AGC_NOISE_GATE_THRESH_SFT 0 ++#define RK3308_AGC_NOISE_GATE_THRESH_MSK (0x7 << RK3308_AGC_NOISE_GATE_THRESH_SFT) ++#define RK3308_AGC_NOISE_GATE_THRESH_N81DB (0x7 << RK3308_AGC_NOISE_GATE_THRESH_SFT) ++#define RK3308_AGC_NOISE_GATE_THRESH_N75DB (0x6 << RK3308_AGC_NOISE_GATE_THRESH_SFT) ++#define RK3308_AGC_NOISE_GATE_THRESH_N69DB (0x5 << RK3308_AGC_NOISE_GATE_THRESH_SFT) ++#define RK3308_AGC_NOISE_GATE_THRESH_N63DB (0x4 << RK3308_AGC_NOISE_GATE_THRESH_SFT) ++#define RK3308_AGC_NOISE_GATE_THRESH_N57DB (0x3 << RK3308_AGC_NOISE_GATE_THRESH_SFT) ++#define RK3308_AGC_NOISE_GATE_THRESH_N51DB (0x2 << RK3308_AGC_NOISE_GATE_THRESH_SFT) ++#define RK3308_AGC_NOISE_GATE_THRESH_N45DB (0x1 << RK3308_AGC_NOISE_GATE_THRESH_SFT) ++#define RK3308_AGC_NOISE_GATE_THRESH_N39DB (0x0 << RK3308_AGC_NOISE_GATE_THRESH_SFT) ++ ++/* ++ * RK3308_ALC_L_DIG_CON03 - REG: 0x004c + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON03 - REG: 0x008c + ch * 0xc0 ++ */ ++#define RK3308_AGC_PGA_ZERO_CRO_EN (0x1 << 5) ++#define RK3308_AGC_PGA_ZERO_CRO_DIS (0x0 << 5) ++#define RK3308_AGC_PGA_GAIN_SFT 0 ++#define RK3308_AGC_PGA_GAIN_MSK (0x1f << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_28_5 (0x1f << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_27 (0x1e << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_25_5 (0x1d << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_24 (0x1c << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_22_5 (0x1b << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_21 (0x1a << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_19_5 (0x19 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_18 (0x18 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_16_5 (0x17 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_15 (0x16 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_13_5 (0x15 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_12 (0x14 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_10_5 (0x13 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_9 (0x12 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_7_5 (0x11 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_6 (0x10 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_4_5 (0x0f << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_3 (0x0e << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_PDB_1_5 (0x0d << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_0DB (0x0c << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_1_5 (0x0b << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_3 (0x0a << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_4_5 (0x09 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_6 (0x08 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_7_5 (0x07 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_9 (0x06 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_10_5 (0x05 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_12 (0x04 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_13_5 (0x03 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_15 (0x02 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_16_5 (0x01 << RK3308_AGC_PGA_GAIN_SFT) ++#define RK3308_AGC_PGA_GAIN_NDB_18 (0x00 << RK3308_AGC_PGA_GAIN_SFT) ++ ++/* ++ * RK3308_ALC_L_DIG_CON04 - REG: 0x0050 + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON04 - REG: 0x0090 + ch * 0xc0 ++ */ ++#define RK3308_AGC_SLOW_CLK_EN (0x1 << 3) ++#define RK3308_AGC_SLOW_CLK_DIS (0x0 << 3) ++#define RK3308_AGC_APPROX_RATE_SFT 0 ++#define RK3308_AGC_APPROX_RATE_MSK (0x7 << RK3308_AGC_APPROX_RATE_SFT) ++#define RK3308_AGC_APPROX_RATE_8K (0x7 << RK3308_AGC_APPROX_RATE_SFT) ++#define RK3308_AGC_APPROX_RATE_12K (0x6 << RK3308_AGC_APPROX_RATE_SFT) ++#define RK3308_AGC_APPROX_RATE_16K (0x5 << RK3308_AGC_APPROX_RATE_SFT) ++#define RK3308_AGC_APPROX_RATE_24K (0x4 << RK3308_AGC_APPROX_RATE_SFT) ++#define RK3308_AGC_APPROX_RATE_32K (0x3 << RK3308_AGC_APPROX_RATE_SFT) ++#define RK3308_AGC_APPROX_RATE_44_1K (0x2 << RK3308_AGC_APPROX_RATE_SFT) ++#define RK3308_AGC_APPROX_RATE_48K (0x1 << RK3308_AGC_APPROX_RATE_SFT) ++#define RK3308_AGC_APPROX_RATE_96K (0x0 << RK3308_AGC_APPROX_RATE_SFT) ++ ++/* ++ * RK3308_ALC_L_DIG_CON05 - REG: 0x0054 + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON05 - REG: 0x0094 + ch * 0xc0 ++ */ ++#define RK3308_AGC_LO_8BITS_AGC_MAX_MSK 0xff ++ ++/* ++ * RK3308_ALC_L_DIG_CON06 - REG: 0x0058 + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON06 - REG: 0x0098 + ch * 0xc0 ++ */ ++#define RK3308_AGC_HI_8BITS_AGC_MAX_MSK 0xff ++ ++/* ++ * RK3308_ALC_L_DIG_CON07 - REG: 0x005c + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON07 - REG: 0x009c + ch * 0xc0 ++ */ ++#define RK3308_AGC_LO_8BITS_AGC_MIN_MSK 0xff ++ ++/* ++ * RK3308_ALC_L_DIG_CON08 - REG: 0x0060 + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON08 - REG: 0x00a0 + ch * 0xc0 ++ */ ++#define RK3308_AGC_HI_8BITS_AGC_MIN_MSK 0xff ++ ++/* ++ * RK3308_ALC_L_DIG_CON09 - REG: 0x0064 + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON09 - REG: 0x00a4 + ch * 0xc0 ++ */ ++#define RK3308_AGC_FUNC_SEL_MSK (0x1 << 6) ++#define RK3308_AGC_FUNC_SEL_EN (0x1 << 6) ++#define RK3308_AGC_FUNC_SEL_DIS (0x0 << 6) ++#define RK3308_AGC_MAX_GAIN_PGA_SFT 3 ++#define RK3308_AGC_MAX_GAIN_PGA_MSK (0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MAX_GAIN_PGA_PDB_28_5 (0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MAX_GAIN_PGA_PDB_22_5 (0x6 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MAX_GAIN_PGA_PDB_16_5 (0x5 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MAX_GAIN_PGA_PDB_10_5 (0x4 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MAX_GAIN_PGA_PDB_4_5 (0x3 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MAX_GAIN_PGA_NDB_1_5 (0x2 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MAX_GAIN_PGA_NDB_7_5 (0x1 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MAX_GAIN_PGA_NDB_13_5 (0x0 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_SFT 0 ++#define RK3308_AGC_MIN_GAIN_PGA_MSK (0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_PDB_24 (0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_PDB_18 (0x6 << RK3308_AGC_MIN_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_PDB_12 (0x5 << RK3308_AGC_MIN_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_PDB_6 (0x4 << RK3308_AGC_MIN_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_0DB (0x3 << RK3308_AGC_MIN_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_NDB_6 (0x2 << RK3308_AGC_MIN_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_NDB_12 (0x1 << RK3308_AGC_MIN_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_NDB_18 (0x0 << RK3308_AGC_MIN_GAIN_PGA_SFT) ++ ++/* ++ * RK3308_ALC_L_DIG_CON12 - REG: 0x0068 + ch * 0xc0 ++ * RK3308_ALC_R_DIG_CON12 - REG: 0x00a8 + ch * 0xc0 ++ */ ++#define RK3308_AGC_GAIN_MSK 0x1f ++ ++/* RK3308_DAC_DIG_CON01 - REG: 0x0304 */ ++#define RK3308_DAC_I2S_LRC_POL_MSK (0x1 << 7) ++#define RK3308_DAC_I2S_LRC_POL_REVERSAL (0x1 << 7) ++#define RK3308_DAC_I2S_LRC_POL_NORMAL (0x0 << 7) ++#define RK3308_DAC_I2S_VALID_LEN_SFT 5 ++#define RK3308_DAC_I2S_VALID_LEN_MSK (0x3 << RK3308_DAC_I2S_VALID_LEN_SFT) ++#define RK3308_DAC_I2S_VALID_LEN_32BITS (0x3 << RK3308_DAC_I2S_VALID_LEN_SFT) ++#define RK3308_DAC_I2S_VALID_LEN_24BITS (0x2 << RK3308_DAC_I2S_VALID_LEN_SFT) ++#define RK3308_DAC_I2S_VALID_LEN_20BITS (0x1 << RK3308_DAC_I2S_VALID_LEN_SFT) ++#define RK3308_DAC_I2S_VALID_LEN_16BITS (0x0 << RK3308_DAC_I2S_VALID_LEN_SFT) ++#define RK3308_DAC_I2S_MODE_SFT 3 ++#define RK3308_DAC_I2S_MODE_MSK (0x3 << RK3308_DAC_I2S_MODE_SFT) ++#define RK3308_DAC_I2S_MODE_PCM (0x3 << RK3308_DAC_I2S_MODE_SFT) ++#define RK3308_DAC_I2S_MODE_I2S (0x2 << RK3308_DAC_I2S_MODE_SFT) ++#define RK3308_DAC_I2S_MODE_LJ (0x1 << RK3308_DAC_I2S_MODE_SFT) ++#define RK3308_DAC_I2S_MODE_RJ (0x0 << RK3308_DAC_I2S_MODE_SFT) ++#define RK3308_DAC_I2S_LR_MSK (0x1 << 2) ++#define RK3308_DAC_I2S_LR_SWAP (0x1 << 2) ++#define RK3308_DAC_I2S_LR_NORMAL (0x0 << 2) ++ ++/* RK3308_DAC_DIG_CON02 - REG: 0x0308 */ ++#define RK3308_DAC_IO_MODE_MSK (0x1 << 5) ++#define RK3308_DAC_IO_MODE_MASTER (0x1 << 5) ++#define RK3308_DAC_IO_MODE_SLAVE (0x0 << 5) ++#define RK3308_DAC_MODE_MSK (0x1 << 4) ++#define RK3308_DAC_MODE_MASTER (0x1 << 4) ++#define RK3308_DAC_MODE_SLAVE (0x0 << 4) ++#define RK3308_DAC_I2S_FRAME_LEN_SFT 2 ++#define RK3308_DAC_I2S_FRAME_LEN_MSK (0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT) ++#define RK3308_DAC_I2S_FRAME_32BITS (0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT) ++#define RK3308_DAC_I2S_FRAME_24BITS (0x2 << RK3308_DAC_I2S_FRAME_LEN_SFT) ++#define RK3308_DAC_I2S_FRAME_20BITS (0x1 << RK3308_DAC_I2S_FRAME_LEN_SFT) ++#define RK3308_DAC_I2S_FRAME_16BITS (0x0 << RK3308_DAC_I2S_FRAME_LEN_SFT) ++#define RK3308_DAC_I2S_MSK (0x1 << 1) ++#define RK3308_DAC_I2S_WORK (0x1 << 1) ++#define RK3308_DAC_I2S_RESET (0x0 << 1) ++#define RK3308_DAC_I2S_BIT_CLK_POL_MSK (0x1 << 0) ++#define RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL (0x1 << 0) ++#define RK3308_DAC_I2S_BIT_CLK_POL_NORMAL (0x0 << 0) ++ ++/* RK3308_DAC_DIG_CON03 - REG: 0x030C */ ++#define RK3308_DAC_L_CH_BIST_SFT 2 ++#define RK3308_DAC_L_CH_BIST_MSK (0x3 << RK3308_DAC_L_CH_BIST_SFT) ++#define RK3308_DAC_L_CH_BIST_LEFT (0x3 << RK3308_DAC_L_CH_BIST_SFT) /* normal mode */ ++#define RK3308_DAC_L_CH_BIST_CUBE (0x2 << RK3308_DAC_L_CH_BIST_SFT) ++#define RK3308_DAC_L_CH_BIST_SINE (0x1 << RK3308_DAC_L_CH_BIST_SFT) ++#define RK3308_DAC_L_CH_BIST_RIGHT (0x0 << RK3308_DAC_L_CH_BIST_SFT) /* normal mode */ ++#define RK3308_DAC_R_CH_BIST_SFT 0 ++#define RK3308_DAC_R_CH_BIST_MSK (0x3 << RK3308_DAC_R_CH_BIST_SFT) ++#define RK3308_DAC_R_CH_BIST_LEFT (0x3 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */ ++#define RK3308_DAC_R_CH_BIST_CUBE (0x2 << RK3308_DAC_R_CH_BIST_SFT) ++#define RK3308_DAC_R_CH_BIST_SINE (0x1 << RK3308_DAC_R_CH_BIST_SFT) ++#define RK3308_DAC_R_CH_BIST_RIGHT (0x0 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */ ++ ++/* RK3308_DAC_DIG_CON05 - REG: 0x0314 */ ++#define RK3308_DAC_L_REG_CTL_INDATA (0x1 << 2) ++#define RK3308_DAC_L_NORMAL_DATA (0x0 << 2) ++#define RK3308_DAC_R_REG_CTL_INDATA (0x1 << 1) ++#define RK3308_DAC_R_NORMAL_DATA (0x0 << 1) ++ ++/* RK3308_DAC_DIG_CON10 - REG: 0x0328 */ ++#define RK3308_DAC_DATA_HI4(x) (x & 0xf) /* Need to RK3308_DAC_x_REG_CTL_INDATA */ ++ ++/* RK3308_DAC_DIG_CON11 - REG: 0x032c */ ++#define RK3308_DAC_DATA_LO8(x) (x & 0xff) /* Need to RK3308_DAC_x_REG_CTL_INDATA */ ++ ++/* RK3308_ADC_ANA_CON00 - REG: 0x0340 */ ++#define RK3308_ADC_CH1_CH2_MIC_ALL_MSK (0xff << 0) ++#define RK3308_ADC_CH1_CH2_MIC_ALL 0xff ++#define RK3308_ADC_CH2_MIC_UNMUTE (0x1 << 7) ++#define RK3308_ADC_CH2_MIC_MUTE (0x0 << 7) ++#define RK3308_ADC_CH2_MIC_WORK (0x1 << 6) ++#define RK3308_ADC_CH2_MIC_INIT (0x0 << 6) ++#define RK3308_ADC_CH2_MIC_EN (0x1 << 5) ++#define RK3308_ADC_CH2_MIC_DIS (0x0 << 5) ++#define RK3308_ADC_CH2_BUF_REF_EN (0x1 << 4) ++#define RK3308_ADC_CH2_BUF_REF_DIS (0x0 << 4) ++#define RK3308_ADC_CH1_MIC_UNMUTE (0x1 << 3) ++#define RK3308_ADC_CH1_MIC_MUTE (0x0 << 3) ++#define RK3308_ADC_CH1_MIC_WORK (0x1 << 2) ++#define RK3308_ADC_CH1_MIC_INIT (0x0 << 2) ++#define RK3308_ADC_CH1_MIC_EN (0x1 << 1) ++#define RK3308_ADC_CH1_MIC_DIS (0x0 << 1) ++#define RK3308_ADC_CH1_BUF_REF_EN (0x1 << 0) ++#define RK3308_ADC_CH1_BUF_REF_DIS (0x0 << 0) ++ ++/* RK3308_ADC_ANA_CON01 - REG: 0x0344 */ ++#define RK3308_ADC_CH2_MIC_GAIN_SFT 4 ++#define RK3308_ADC_CH2_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT) ++#define RK3308_ADC_CH2_MIC_GAIN_30DB (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT) ++#define RK3308_ADC_CH2_MIC_GAIN_20DB (0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT) ++#define RK3308_ADC_CH2_MIC_GAIN_6DB (0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT) ++#define RK3308_ADC_CH2_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH2_MIC_GAIN_SFT) ++#define RK3308_ADC_CH1_MIC_GAIN_SFT 0 ++#define RK3308_ADC_CH1_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT) ++#define RK3308_ADC_CH1_MIC_GAIN_30DB (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT) ++#define RK3308_ADC_CH1_MIC_GAIN_20DB (0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT) ++#define RK3308_ADC_CH1_MIC_GAIN_6DB (0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT) ++#define RK3308_ADC_CH1_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH1_MIC_GAIN_SFT) ++ ++/* RK3308_ADC_ANA_CON02 - REG: 0x0348 */ ++#define RK3308_ADC_CH2_ALC_ZC_MSK (0x7 << 4) ++#define RK3308_ADC_CH2_ZEROCROSS_DET_EN (0x1 << 6) ++#define RK3308_ADC_CH2_ZEROCROSS_DET_DIS (0x0 << 6) ++#define RK3308_ADC_CH2_ALC_WORK (0x1 << 5) ++#define RK3308_ADC_CH2_ALC_INIT (0x0 << 5) ++#define RK3308_ADC_CH2_ALC_EN (0x1 << 4) ++#define RK3308_ADC_CH2_ALC_DIS (0x0 << 4) ++ ++#define RK3308_ADC_CH1_ALC_ZC_MSK (0x7 << 0) ++#define RK3308_ADC_CH1_ZEROCROSS_DET_EN (0x1 << 2) ++#define RK3308_ADC_CH1_ZEROCROSS_DET_DIS (0x0 << 2) ++#define RK3308_ADC_CH1_ALC_WORK (0x1 << 1) ++#define RK3308_ADC_CH1_ALC_INIT (0x0 << 1) ++#define RK3308_ADC_CH1_ALC_EN (0x1 << 0) ++#define RK3308_ADC_CH1_ALC_DIS (0x0 << 0) ++ ++/* RK3308_ADC_ANA_CON03 - REG: 0x034c */ ++#define RK3308_ADC_CH1_ALC_GAIN_SFT 0 ++#define RK3308_ADC_CH1_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_28_5 (0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_27 (0x1e << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_25_5 (0x1d << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_24 (0x1c << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_22_5 (0x1b << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_21 (0x1a << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_19_5 (0x19 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_18 (0x18 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_16_5 (0x17 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_15 (0x16 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_13_5 (0x15 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_12 (0x14 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_10_5 (0x13 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_9 (0x12 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_7_5 (0x11 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_6 (0x10 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_4_5 (0x0f << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_3 (0x0e << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_PDB_1_5 (0x0d << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_0DB (0x0c << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_1_5 (0x0b << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_3 (0x0a << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_4_5 (0x09 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_6 (0x08 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_7_5 (0x07 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_9 (0x06 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_10_5 (0x05 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_12 (0x04 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_13_5 (0x03 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_15 (0x02 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_16_5 (0x01 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++#define RK3308_ADC_CH1_ALC_GAIN_NDB_18 (0x00 << RK3308_ADC_CH1_ALC_GAIN_SFT) ++ ++/* RK3308_ADC_ANA_CON04 - REG: 0x0350 */ ++#define RK3308_ADC_CH2_ALC_GAIN_SFT 0 ++#define RK3308_ADC_CH2_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_28_5 (0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_27 (0x1e << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_25_5 (0x1d << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_24 (0x1c << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_22_5 (0x1b << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_21 (0x1a << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_19_5 (0x19 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_18 (0x18 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_16_5 (0x17 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_15 (0x16 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_13_5 (0x15 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_12 (0x14 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_10_5 (0x13 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_9 (0x12 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_7_5 (0x11 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_6 (0x10 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_4_5 (0x0f << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_3 (0x0e << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_PDB_1_5 (0x0d << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_0DB (0x0c << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_1_5 (0x0b << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_3 (0x0a << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_4_5 (0x09 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_6 (0x08 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_7_5 (0x07 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_9 (0x06 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_10_5 (0x05 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_12 (0x04 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_13_5 (0x03 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_15 (0x02 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_16_5 (0x01 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++#define RK3308_ADC_CH2_ALC_GAIN_NDB_18 (0x00 << RK3308_ADC_CH2_ALC_GAIN_SFT) ++ ++/* RK3308_ADC_ANA_CON05 - REG: 0x0354 */ ++#define RK3308_ADC_CH2_ADC_CLK_MSK (0x7 << 4) ++#define RK3308_ADC_CH2_ADC_WORK (0x1 << 6) ++#define RK3308_ADC_CH2_ADC_INIT (0x0 << 6) ++#define RK3308_ADC_CH2_ADC_EN (0x1 << 5) ++#define RK3308_ADC_CH2_ADC_DIS (0x0 << 5) ++#define RK3308_ADC_CH2_CLK_EN (0x1 << 4) ++#define RK3308_ADC_CH2_CLK_DIS (0x0 << 4) ++ ++#define RK3308_ADC_CH1_ADC_CLK_MSK (0x7 << 0) ++#define RK3308_ADC_CH1_ADC_WORK (0x1 << 2) ++#define RK3308_ADC_CH1_ADC_INIT (0x0 << 2) ++#define RK3308_ADC_CH1_ADC_EN (0x1 << 1) ++#define RK3308_ADC_CH1_ADC_DIS (0x0 << 1) ++#define RK3308_ADC_CH1_CLK_EN (0x1 << 0) ++#define RK3308_ADC_CH1_CLK_DIS (0x0 << 0) ++ ++/* RK3308_ADC_ANA_CON06 - REG: 0x0358 */ ++#define RK3308_ADC_CURRENT_MSK (0x1 << 0) ++#define RK3308_ADC_CURRENT_EN (0x1 << 0) ++#define RK3308_ADC_CURRENT_DIS (0x0 << 0) ++ ++/* RK3308_ADC_ANA_CON07 - REG: 0x035c */ ++/* Note: The register configuration is only valid for ADC2 */ ++#define RK3308_ADC_CH2_IN_SEL_SFT 6 ++#define RK3308_ADC_CH2_IN_SEL_MSK (0x3 << RK3308_ADC_CH2_IN_SEL_SFT) ++#define RK3308_ADC_CH2_IN_LINEIN_MIC (0x3 << RK3308_ADC_CH2_IN_SEL_SFT) ++#define RK3308_ADC_CH2_IN_LINEIN (0x2 << RK3308_ADC_CH2_IN_SEL_SFT) ++#define RK3308_ADC_CH2_IN_MIC (0x1 << RK3308_ADC_CH2_IN_SEL_SFT) ++#define RK3308_ADC_CH2_IN_NONE (0x0 << RK3308_ADC_CH2_IN_SEL_SFT) ++/* Note: The register configuration is only valid for ADC1 */ ++#define RK3308_ADC_CH1_IN_SEL_SFT 4 ++#define RK3308_ADC_CH1_IN_SEL_MSK (0x3 << RK3308_ADC_CH1_IN_SEL_SFT) ++#define RK3308_ADC_CH1_IN_LINEIN_MIC (0x3 << RK3308_ADC_CH1_IN_SEL_SFT) ++#define RK3308_ADC_CH1_IN_LINEIN (0x2 << RK3308_ADC_CH1_IN_SEL_SFT) ++#define RK3308_ADC_CH1_IN_MIC (0x1 << RK3308_ADC_CH1_IN_SEL_SFT) ++#define RK3308_ADC_CH1_IN_NONE (0x0 << RK3308_ADC_CH1_IN_SEL_SFT) ++ ++#define RK3308_ADC_MIC_BIAS_BUF_EN (0x1 << 3) ++#define RK3308_ADC_MIC_BIAS_BUF_DIS (0x0 << 3) ++#define RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT 0 ++#define RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK (0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++#define RK3308_ADC_MICBIAS_VOLT_0_85 (0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++#define RK3308_ADC_MICBIAS_VOLT_0_8 (0x6 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++#define RK3308_ADC_MICBIAS_VOLT_0_75 (0x5 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++#define RK3308_ADC_MICBIAS_VOLT_0_7 (0x4 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++#define RK3308_ADC_MICBIAS_VOLT_0_65 (0x3 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++#define RK3308_ADC_MICBIAS_VOLT_0_6 (0x2 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++#define RK3308_ADC_MICBIAS_VOLT_0_55 (0x1 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++#define RK3308_ADC_MICBIAS_VOLT_0_5 (0x0 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++ ++/* RK3308_ADC_ANA_CON08 - REG: 0x0360 */ ++#define RK3308_ADC_MICBIAS_CURRENT_MSK (0x1 << 4) ++#define RK3308_ADC_MICBIAS_CURRENT_EN (0x1 << 4) ++#define RK3308_ADC_MICBIAS_CURRENT_DIS (0x0 << 4) ++ ++/* RK3308_ADC_ANA_CON10 - REG: 0x0368 */ ++#define RK3308_ADC_REF_EN (0x1 << 7) ++#define RK3308_ADC_REF_DIS (0x0 << 7) ++#define RK3308_ADC_CURRENT_CHARGE_SFT 0 ++#define RK3308_ADC_CURRENT_CHARGE_MSK (0x7f << RK3308_ADC_CURRENT_CHARGE_SFT) ++#define RK3308_ADC_DONT_SEL_ALL (0x7f << RK3308_ADC_CURRENT_CHARGE_SFT) ++/* ++ * 0: Choose the current I ++ * 1: Don't choose the current I ++ */ ++#define RK3308_ADC_SEL_I_1(x) ((x & 0x1) << 6) ++#define RK3308_ADC_SEL_I_2(x) ((x & 0x1) << 5) ++#define RK3308_ADC_SEL_I_4(x) ((x & 0x1) << 4) ++#define RK3308_ADC_SEL_I_8(x) ((x & 0x1) << 3) ++#define RK3308_ADC_SEL_I_16(x) ((x & 0x1) << 2) ++#define RK3308_ADC_SEL_I_32(x) ((x & 0x1) << 1) ++#define RK3308_ADC_SEL_I_64(x) ((x & 0x1) << 0) ++ ++/* RK3308_ADC_ANA_CON11 - REG: 0x036c */ ++#define RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK (0x1 << 1) ++#define RK3308_ADC_ALCR_CON_GAIN_PGAR_EN (0x1 << 1) ++#define RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS (0x0 << 1) ++#define RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK (0x1 << 0) ++#define RK3308_ADC_ALCL_CON_GAIN_PGAL_EN (0x1 << 0) ++#define RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS (0x0 << 0) ++ ++/* RK3308_DAC_ANA_CON00 - REG: 0x0440 */ ++#define RK3308_DAC_HEADPHONE_DET_EN (0x1 << 1) ++#define RK3308_DAC_HEADPHONE_DET_DIS (0x0 << 1) ++#define RK3308_DAC_CURRENT_MSK (0x1 << 0) ++#define RK3308_DAC_CURRENT_EN (0x1 << 0) ++#define RK3308_DAC_CURRENT_DIS (0x0 << 0) ++ ++/* RK3308_DAC_ANA_CON01 - REG: 0x0444 */ ++#define RK3308_DAC_BUF_REF_R_MSK (0x1 << 6) ++#define RK3308_DAC_BUF_REF_R_EN (0x1 << 6) ++#define RK3308_DAC_BUF_REF_R_DIS (0x0 << 6) ++#define RK3308_DAC_POP_SOUND_R_SFT 4 ++#define RK3308_DAC_POP_SOUND_R_MSK (0x3 << RK3308_DAC_POP_SOUND_R_SFT) ++#define RK3308_DAC_POP_SOUND_R_WORK (0x2 << RK3308_DAC_POP_SOUND_R_SFT) ++#define RK3308_DAC_POP_SOUND_R_INIT (0x1 << RK3308_DAC_POP_SOUND_R_SFT) ++#define RK3308_DAC_BUF_REF_L_MSK (0x1 << 2) ++#define RK3308_DAC_BUF_REF_L_EN (0x1 << 2) ++#define RK3308_DAC_BUF_REF_L_DIS (0x0 << 2) ++#define RK3308_DAC_POP_SOUND_L_SFT 0 ++#define RK3308_DAC_POP_SOUND_L_MSK (0x3 << RK3308_DAC_POP_SOUND_L_SFT) ++#define RK3308_DAC_POP_SOUND_L_WORK (0x2 << RK3308_DAC_POP_SOUND_L_SFT) ++#define RK3308_DAC_POP_SOUND_L_INIT (0x1 << RK3308_DAC_POP_SOUND_L_SFT) ++ ++/* RK3308_DAC_ANA_CON02 - REG: 0x0448 */ ++#define RK3308_DAC_R_DAC_WORK (0x1 << 7) ++#define RK3308_DAC_R_DAC_INIT (0x0 << 7) ++#define RK3308_DAC_R_DAC_EN (0x1 << 6) ++#define RK3308_DAC_R_DAC_DIS (0x0 << 6) ++#define RK3308_DAC_R_CLK_EN (0x1 << 5) ++#define RK3308_DAC_R_CLK_DIS (0x0 << 5) ++#define RK3308_DAC_R_REF_EN (0x1 << 4) ++#define RK3308_DAC_R_REF_DIS (0x0 << 4) ++#define RK3308_DAC_L_DAC_WORK (0x1 << 3) ++#define RK3308_DAC_L_DAC_INIT (0x0 << 3) ++#define RK3308_DAC_L_DAC_EN (0x1 << 2) ++#define RK3308_DAC_L_DAC_DIS (0x0 << 2) ++#define RK3308_DAC_L_CLK_EN (0x1 << 1) ++#define RK3308_DAC_L_CLK_DIS (0x0 << 1) ++#define RK3308_DAC_L_REF_EN (0x1 << 0) ++#define RK3308_DAC_L_REF_DIS (0x0 << 0) ++ ++/* RK3308_DAC_ANA_CON03 - REG: 0x044c */ ++#define RK3308_DAC_R_HPOUT_WORK (0x1 << 6) ++#define RK3308_DAC_R_HPOUT_INIT (0x0 << 6) ++#define RK3308_DAC_R_HPOUT_EN (0x1 << 5) ++#define RK3308_DAC_R_HPOUT_DIS (0x0 << 5) ++#define RK3308_DAC_R_HPOUT_UNMUTE (0x1 << 4) ++#define RK3308_DAC_R_HPOUT_MUTE (0x0 << 4) ++#define RK3308_DAC_L_HPOUT_WORK (0x1 << 2) ++#define RK3308_DAC_L_HPOUT_INIT (0x0 << 2) ++#define RK3308_DAC_L_HPOUT_EN (0x1 << 1) ++#define RK3308_DAC_L_HPOUT_DIS (0x0 << 1) ++#define RK3308_DAC_L_HPOUT_UNMUTE (0x1 << 0) ++#define RK3308_DAC_L_HPOUT_MUTE (0x0 << 0) ++ ++/* RK3308_DAC_ANA_CON04 - REG: 0x0450 */ ++#define RK3308_DAC_R_GAIN_SFT 6 ++#define RK3308_DAC_R_GAIN_MSK (0x3 << RK3308_DAC_R_GAIN_SFT) ++#define RK3308_DAC_R_GAIN_0DB (0x3 << RK3308_DAC_R_GAIN_SFT) ++#define RK3308_DAC_R_GAIN_PDB_1_5 (0x2 << RK3308_DAC_R_GAIN_SFT) ++#define RK3308_DAC_R_GAIN_PDB_3 (0x1 << RK3308_DAC_R_GAIN_SFT) ++#define RK3308_DAC_R_GAIN_PDB_6 (0x0 << RK3308_DAC_R_GAIN_SFT) ++#define RK3308_DAC_R_LINEOUT_UNMUTE (0x1 << 5) ++#define RK3308_DAC_R_LINEOUT_MUTE (0x0 << 5) ++#define RK3308_DAC_R_LINEOUT_EN (0x1 << 4) ++#define RK3308_DAC_R_LINEOUT_DIS (0x0 << 4) ++#define RK3308_DAC_L_GAIN_SFT 2 ++#define RK3308_DAC_L_GAIN_MSK (0x3 << RK3308_DAC_L_GAIN_SFT) ++#define RK3308_DAC_L_GAIN_0DB (0x3 << RK3308_DAC_L_GAIN_SFT) ++#define RK3308_DAC_L_GAIN_PDB_1_5 (0x2 << RK3308_DAC_L_GAIN_SFT) ++#define RK3308_DAC_L_GAIN_PDB_3 (0x1 << RK3308_DAC_L_GAIN_SFT) ++#define RK3308_DAC_L_GAIN_PDB_6 (0x0 << RK3308_DAC_L_GAIN_SFT) ++#define RK3308_DAC_L_LINEOUT_UNMUTE (0x1 << 1) ++#define RK3308_DAC_L_LINEOUT_MUTE (0x0 << 1) ++#define RK3308_DAC_L_LINEOUT_EN (0x1 << 0) ++#define RK3308_DAC_L_LINEOUT_DIS (0x0 << 0) ++ ++/* RK3308_DAC_ANA_CON05 - REG: 0x0454, step is 1.5db */ ++#define RK3308_DAC_L_HPOUT_GAIN_SFT 0 ++#define RK3308_DAC_L_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_PDB_6 (0x1e << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_PDB_4_5 (0x1d << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_PDB_3 (0x1c << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_PDB_1_5 (0x1b << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_0DB (0x1a << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_1_5 (0x19 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_3 (0x18 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_4_5 (0x17 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_6 (0x16 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_7_5 (0x15 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_9 (0x14 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_10_5 (0x13 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_12 (0x12 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_13_5 (0x11 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_15 (0x10 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_16_5 (0x0f << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_18 (0x0e << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_19_5 (0x0d << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_21 (0x0c << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_22_5 (0x0b << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_24 (0x0a << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_25_5 (0x09 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_27 (0x08 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_28_5 (0x07 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_30 (0x06 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_31_5 (0x05 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_33 (0x04 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_34_5 (0x03 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_36 (0x02 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_37_5 (0x01 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++#define RK3308_DAC_L_HPOUT_GAIN_NDB_39 (0x00 << RK3308_DAC_L_HPOUT_GAIN_SFT) ++ ++/* RK3308_DAC_ANA_CON06 - REG: 0x0458, step is 1.5db */ ++#define RK3308_DAC_R_HPOUT_GAIN_SFT 0 ++#define RK3308_DAC_R_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_PDB_6 (0x1e << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_PDB_4_5 (0x1d << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_PDB_3 (0x1c << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_PDB_1_5 (0x1b << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_0DB (0x1a << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_1_5 (0x19 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_3 (0x18 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_4_5 (0x17 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_6 (0x16 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_7_5 (0x15 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_9 (0x14 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_10_5 (0x13 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_12 (0x12 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_13_5 (0x11 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_15 (0x10 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_16_5 (0x0f << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_18 (0x0e << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_19_5 (0x0d << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_21 (0x0c << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_22_5 (0x0b << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_24 (0x0a << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_25_5 (0x09 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_27 (0x08 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_28_5 (0x07 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_30 (0x06 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_31_5 (0x05 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_33 (0x04 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_34_5 (0x03 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_36 (0x02 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_37_5 (0x01 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++#define RK3308_DAC_R_HPOUT_GAIN_NDB_39 (0x00 << RK3308_DAC_R_HPOUT_GAIN_SFT) ++ ++/* RK3308_DAC_ANA_CON12 - REG: 0x0470 */ ++#define RK3308_DAC_R_HPMIX_SEL_SFT 6 ++#define RK3308_DAC_R_HPMIX_SEL_MSK (0x3 << RK3308_DAC_R_HPMIX_SEL_SFT) ++#define RK3308_DAC_R_HPMIX_LINEIN_I2S (0x3 << RK3308_DAC_R_HPMIX_SEL_SFT) ++#define RK3308_DAC_R_HPMIX_LINEIN (0x2 << RK3308_DAC_R_HPMIX_SEL_SFT) ++#define RK3308_DAC_R_HPMIX_I2S (0x1 << RK3308_DAC_R_HPMIX_SEL_SFT) ++#define RK3308_DAC_R_HPMIX_NONE (0x0 << RK3308_DAC_R_HPMIX_SEL_SFT) ++#define RK3308_DAC_R_HPMIX_GAIN_SFT 4 ++#define RK3308_DAC_R_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_R_HPMIX_GAIN_SFT) ++#define RK3308_DAC_R_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_R_HPMIX_GAIN_SFT) ++#define RK3308_DAC_R_HPMIX_GAIN_NDB_6 (0x1 << RK3308_DAC_R_HPMIX_GAIN_SFT) ++#define RK3308_DAC_L_HPMIX_SEL_SFT 2 ++#define RK3308_DAC_L_HPMIX_SEL_MSK (0x3 << RK3308_DAC_L_HPMIX_SEL_SFT) ++#define RK3308_DAC_L_HPMIX_LINEIN_I2S (0x3 << RK3308_DAC_L_HPMIX_SEL_SFT) ++#define RK3308_DAC_L_HPMIX_LINEIN (0x2 << RK3308_DAC_L_HPMIX_SEL_SFT) ++#define RK3308_DAC_L_HPMIX_I2S (0x1 << RK3308_DAC_L_HPMIX_SEL_SFT) ++#define RK3308_DAC_L_HPMIX_NONE (0x0 << RK3308_DAC_L_HPMIX_SEL_SFT) ++#define RK3308_DAC_L_HPMIX_GAIN_SFT 0 ++#define RK3308_DAC_L_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_L_HPMIX_GAIN_SFT) ++#define RK3308_DAC_L_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_L_HPMIX_GAIN_SFT) ++#define RK3308_DAC_L_HPMIX_GAIN_NDB_6 (0x1 << RK3308_DAC_L_HPMIX_GAIN_SFT) ++ ++/* RK3308_DAC_ANA_CON13 - REG: 0x0474 */ ++#define RK3308_DAC_R_HPMIX_UNMUTE (0x1 << 6) ++#define RK3308_DAC_R_HPMIX_MUTE (0x0 << 6) ++#define RK3308_DAC_R_HPMIX_WORK (0x1 << 5) ++#define RK3308_DAC_R_HPMIX_INIT (0x0 << 5) ++#define RK3308_DAC_R_HPMIX_EN (0x1 << 4) ++#define RK3308_DAC_R_HPMIX_DIS (0x0 << 4) ++#define RK3308_DAC_L_HPMIX_UNMUTE (0x1 << 2) ++#define RK3308_DAC_L_HPMIX_MUTE (0x0 << 2) ++#define RK3308_DAC_L_HPMIX_WORK (0x1 << 1) ++#define RK3308_DAC_L_HPMIX_INIT (0x0 << 1) ++#define RK3308_DAC_L_HPMIX_EN (0x1 << 0) ++#define RK3308_DAC_L_HPMIX_DIS (0x0 << 0) ++ ++#define RK3308_HIFI 0x0 ++ ++#endif /* __RK3308_CODEC_H__ */ +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch new file mode 100644 index 000000000..8c83b14e0 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch @@ -0,0 +1,6738 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: ashthespy +Date: Mon, 3 Feb 2020 17:13:59 +0100 +Subject: Sync `rk3308_codec` to BSP tree + +--- + Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.txt | 78 + + sound/soc/codecs/rk3308_codec.c | 5687 ++++++++-- + sound/soc/codecs/rk3308_codec.h | 217 +- + sound/soc/codecs/rk3308_codec_provider.h | 28 + + 4 files changed, 4894 insertions(+), 1116 deletions(-) + +diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.txt +new file mode 100644 +index 000000000000..e20bbd73e37e +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.txt +@@ -0,0 +1,78 @@ ++* Rockchip RK3308 Internal Codec ++ ++Required properties: ++ ++- compatible: "rockchip,rk3308-codec" ++- reg: The physical base address of the controller and length of memory ++ mapped region. ++- rockchip,grf: The phandle of the syscon node for GRF register. ++- clocks: A list of phandle + clock-specifer pairs, one for each entry in ++ clock-names. ++- clock-names: It should be "acodec". ++- resets : Must contain an entry for each entry in reset-names. ++- reset-names : Must include the following entries: "acodec-reset". ++ ++Optional properties: ++- rockchip,enable-all-adcs: This is a boolean type property, that shows whether ++ force enable all of ADCs. The following shows the relationship between grps ++ and ADC: ++ * grp 0 -- select ADC1 / ADC2 ++ * grp 1 -- select ADC3 / ADC4 ++ * grp 2 -- select ADC5 / ADC6 ++ * grp 3 -- select ADC7 / ADC8 ++ If the property is not used, the enabled ADC groups refer to needed channels ++ via configure hw_params. ++ ++- rockchip,adc-grps-route: This is a variable length array, that shows the ++ mapping route of ACODEC sdo to I2S sdi. By default, they are one-to-one ++ mapping: ++ * sdi_0 <-- sdo_0 ++ * sdi_1 <-- sdo_1 ++ * sdi_2 <-- sdo_2 ++ * sdi_3 <-- sdo_3 ++ If you would like to change the route mapping like this: ++ * sdi_0 <-- sdo_3 ++ * sdi_1 <-- sdo_0 ++ * sdi_2 <-- sdo_2 ++ * sdi_3 <-- sdo_1 ++ You need to add the property on dts: ++ - rockchip,adc-grps-route = <3 0 2 1>; ++ ++- rockchip,delay-loopback-handle-ms: This property points out that the delay for ++ handling ADC after enable PAs during loopback. ++- rockchip,delay-start-play-ms: This property points out the delay ms of start ++ playback according to different amplifier performance. ++- rockchip,en-always-grps: This property will keep the needed ADCs enabled ++ always after enabling once. ++- rockchip,loopback-grp: It points out the ADC group which is the loopback used. ++- rockchip,no-deep-low-power: The codec will not enter deep low power mode ++ during suspend. ++- rockchip,no-hp-det: If there is no headphone on boards, we don't need to ++ enable headphone detection. ++- rockchip,micbias1: Using internal micbias1 supply which are from codec. ++- rockchip,micbias2: Using internal micbias2 supply which are from codec. ++- rockchip,hp-jack-reversed;: To detect headphone via the reversed jack. ++- hp-ctl-gpios: The gpio of head phone controller. ++- pa-drv-gpios: The gpio of poweramplifier controller ++- rockchip,delay-pa-drv-ms: This property points out that the delay for ++ power on amplifier ++- spk-ctl-gpios: The gpio of speak controller. ++- micbias-en-gpios: The GPIO to enable external micbias. ++- vmicbias-supply: The phandle to the regulator to handle external micbias. ++ ++Example for rk3308 internal codec: ++ ++acodec: acodec@ff560000 { ++ compatible = "rockchip,rk3308-codec"; ++ reg = <0x0 0xff560000 0x0 0x10000>; ++ rockchip,grf = <&grf>; ++ clocks = <&cru PCLK_ACODEC>; ++ clock-names = "acodec"; ++ resets = <&cru SRST_ACODEC_P>; ++ reset-names = "acodec-reset"; ++ rockchip,loopback-grp = <0>; ++ hp-ctl-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; ++ pa-drv-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; ++ spk-ctl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; +diff --git a/sound/soc/codecs/rk3308_codec.c b/sound/soc/codecs/rk3308_codec.c +index 106f09738dd0..815e22fc346c 100644 +--- a/sound/soc/codecs/rk3308_codec.c ++++ b/sound/soc/codecs/rk3308_codec.c +@@ -29,1420 +29,4699 @@ + #include + #include + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + #include + #include ++#include + #include + #include + + #include "rk3308_codec.h" ++#include "rk3308_codec_provider.h" ++ ++#if defined(CONFIG_DEBUG_FS) ++#include ++#include ++#include ++#endif ++ ++#define CODEC_DRV_NAME "rk3308-acodec" ++ ++#define ADC_GRP_SKIP_MAGIC 0x1001 ++#define ADC_LR_GROUP_MAX 4 ++#define ADC_STABLE_MS 200 ++#define DEBUG_POP_ALWAYS 0 ++#define HPDET_POLL_MS 2000 ++#define NOT_USED 255 ++#define LOOPBACK_HANDLE_MS 100 ++#define PA_DRV_MS 5 ++ ++#define GRF_SOC_CON1 0x304 ++#define GRF_CHIP_ID 0x800 ++#define GRF_I2S2_8CH_SDI_SFT 0 ++#define GRF_I2S3_4CH_SDI_SFT 8 ++#define GRF_I2S1_2CH_SDI_SFT 12 ++ ++#define GRF_I2S2_8CH_SDI_R_MSK(i, v) ((v >> (i * 2 + GRF_I2S2_8CH_SDI_SFT)) & 0x3) ++#define GRF_I2S2_8CH_SDI_W_MSK(i) (0x3 << (i * 2 + GRF_I2S2_8CH_SDI_SFT + 16)) ++#define GRF_I2S2_8CH_SDI(i, v) (((v & 0x3) << (i * 2 + GRF_I2S2_8CH_SDI_SFT)) |\ ++ GRF_I2S2_8CH_SDI_W_MSK(i)) ++ ++#define GRF_I2S3_4CH_SDI_W_MSK(i) (0x3 << (i * 2 + GRF_I2S3_4CH_SDI_SFT + 16)) ++#define GRF_I2S3_4CH_SDI(i, v) (((v & 0x3) << (i * 2 + GRF_I2S3_4CH_SDI_SFT)) |\ ++ GRF_I2S3_4CH_SDI_W_MSK(i)) ++ ++#define GRF_I2S1_2CH_SDI_W_MSK (0x3 << (GRF_I2S1_2CH_SDI_SFT + 16)) ++#define GRF_I2S1_2CH_SDI(v) (((v & 0x3) << GRF_I2S1_2CH_SDI_SFT) |\ ++ GRF_I2S1_2CH_SDI_W_MSK) ++ ++#define DETECT_GRF_ACODEC_HPDET_COUNTER 0x0030 ++#define DETECT_GRF_ACODEC_HPDET_CON 0x0034 ++#define DETECT_GRF_ACODEC_HPDET_STATUS 0x0038 ++#define DETECT_GRF_ACODEC_HPDET_STATUS_CLR 0x003c ++ ++/* 200ms based on pclk is 100MHz */ ++#define DEFAULT_HPDET_COUNT 20000000 ++#define HPDET_NEG_IRQ_SFT 1 ++#define HPDET_POS_IRQ_SFT 0 ++#define HPDET_BOTH_NEG_POS ((1 << HPDET_NEG_IRQ_SFT) |\ ++ (1 << HPDET_POS_IRQ_SFT)) ++ ++#define ACODEC_VERSION_A 0xa ++#define ACODEC_VERSION_B 0xb ++ ++enum { ++ ACODEC_TO_I2S2_8CH = 0, ++ ACODEC_TO_I2S3_4CH, ++ ACODEC_TO_I2S1_2CH, ++}; ++ ++enum { ++ ADC_GRP0_MICIN = 0, ++ ADC_GRP0_LINEIN ++}; ++ ++enum { ++ ADC_TYPE_NORMAL = 0, ++ ADC_TYPE_LOOPBACK, ++ ADC_TYPE_DBG, ++ ADC_TYPE_ALL, ++}; ++ ++enum { ++ DAC_LINEOUT = 0, ++ DAC_HPOUT = 1, ++ DAC_LINEOUT_HPOUT = 11, ++}; ++ ++enum { ++ EXT_MICBIAS_NONE = 0, ++ EXT_MICBIAS_FUNC1, /* enable external micbias via GPIO */ ++ EXT_MICBIAS_FUNC2, /* enable external micbias via regulator */ ++}; ++ ++enum { ++ PATH_IDLE = 0, ++ PATH_BUSY, ++}; ++ ++enum { ++ PM_NORMAL = 0, ++ PM_LLP_DOWN, /* light low power down */ ++ PM_LLP_UP, ++ PM_DLP_DOWN, /* deep low power down */ ++ PM_DLP_UP, ++ PM_DLP_DOWN2, ++ PM_DLP_UP2, ++}; + + struct rk3308_codec_priv { + const struct device *plat_dev; + struct device dev; + struct reset_control *reset; + struct regmap *regmap; ++ struct regmap *grf; ++ struct regmap *detect_grf; + struct clk *pclk; ++ struct clk *mclk_rx; ++ struct clk *mclk_tx; ++ struct gpio_desc *micbias_en_gpio; ++ struct gpio_desc *hp_ctl_gpio; + struct gpio_desc *spk_ctl_gpio; +- int adc_ch; /* To select ADCs for channel */ +- int adc_ch0_using_linein; ++ struct gpio_desc *pa_drv_gpio; ++ struct snd_soc_codec *codec; ++ struct snd_soc_jack *hpdet_jack; ++ struct regulator *vcc_micbias; ++ u32 codec_ver; ++ ++ /* ++ * To select ADCs for groups: ++ * ++ * grp 0 -- select ADC1 / ADC2 ++ * grp 1 -- select ADC3 / ADC4 ++ * grp 2 -- select ADC5 / ADC6 ++ * grp 3 -- select ADC7 / ADC8 ++ */ ++ u32 used_adc_grps; ++ /* The ADC group which is used for loop back */ ++ u32 loopback_grp; ++ u32 cur_dbg_grp; ++ u32 en_always_grps[ADC_LR_GROUP_MAX]; ++ u32 en_always_grps_num; ++ u32 skip_grps[ADC_LR_GROUP_MAX]; ++ u32 i2s_sdis[ADC_LR_GROUP_MAX]; ++ u32 to_i2s_grps; ++ u32 delay_loopback_handle_ms; ++ u32 delay_start_play_ms; ++ u32 delay_pa_drv_ms; ++ u32 micbias_num; ++ u32 micbias_volt; ++ int which_i2s; ++ int irq; ++ int adc_grp0_using_linein; ++ int adc_zerocross; ++ /* 0: line out, 1: hp out, 11: lineout and hpout */ ++ int dac_output; ++ int dac_path_state; ++ ++ int ext_micbias; ++ int pm_state; ++ ++ /* AGC L/R Off/on */ ++ unsigned int agc_l[ADC_LR_GROUP_MAX]; ++ unsigned int agc_r[ADC_LR_GROUP_MAX]; ++ ++ /* AGC L/R Approximate Sample Rate */ ++ unsigned int agc_asr_l[ADC_LR_GROUP_MAX]; ++ unsigned int agc_asr_r[ADC_LR_GROUP_MAX]; ++ ++ /* ADC MIC Mute/Work */ ++ unsigned int mic_mute_l[ADC_LR_GROUP_MAX]; ++ unsigned int mic_mute_r[ADC_LR_GROUP_MAX]; ++ ++ /* For the high pass filter */ ++ unsigned int hpf_cutoff[ADC_LR_GROUP_MAX]; ++ ++ /* Only hpout do fade-in and fade-out */ ++ unsigned int hpout_l_dgain; ++ unsigned int hpout_r_dgain; ++ ++ bool adc_grps_endisable[ADC_LR_GROUP_MAX]; ++ bool dac_endisable; ++ bool enable_all_adcs; ++ bool enable_micbias; ++ bool micbias1; ++ bool micbias2; ++ bool hp_jack_reversed; ++ bool hp_plugged; ++ bool loopback_dacs_enabled; ++ bool no_deep_low_power; ++ bool no_hp_det; ++ struct delayed_work hpdet_work; ++ struct delayed_work loopback_work; ++ ++#if defined(CONFIG_DEBUG_FS) ++ struct dentry *dbg_codec; ++#endif + }; + +-static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_gain_tlv, ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_gain_tlv, + -1800, 150, 2850); +-static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_max_gain_tlv, ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_max_gain_tlv, + -1350, 600, 2850); +-static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_ch_min_gain_tlv, ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_min_gain_tlv, + -1800, 600, 2400); +-static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_mic_gain_tlv, +- 0, 600, 3000); + static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv, + -1800, 150, 2850); +-static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_gain_tlv, +- 0, 150, 600); ++static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_lineout_gain_tlv, ++ -600, 150, 0); + static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpout_gain_tlv, + -3900, 150, 600); + static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpmix_gain_tlv, + -600, 600, 0); + ++static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_mic_gain_tlv_a, ++ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), ++ 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0), ++); ++ ++static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_mic_gain_tlv_b, ++ 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), ++ 1, 1, TLV_DB_SCALE_ITEM(660, 0, 0), ++ 2, 2, TLV_DB_SCALE_ITEM(1300, 0, 0), ++ 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0), ++); ++ ++static bool handle_loopback(struct rk3308_codec_priv *rk3308); ++ ++static int check_micbias(int micbias); ++ ++static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308, ++ int micbias); ++static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308); ++ ++static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol); ++ ++static const char *offon_text[2] = { ++ [0] = "Off", ++ [1] = "On", ++}; ++ ++static const char *mute_text[2] = { ++ [0] = "Work", ++ [1] = "Mute", ++}; ++ ++/* ADC MICBIAS Volt */ ++#define MICBIAS_VOLT_NUM 8 ++ ++#define MICBIAS_VREFx0_5 0 ++#define MICBIAS_VREFx0_55 1 ++#define MICBIAS_VREFx0_6 2 ++#define MICBIAS_VREFx0_65 3 ++#define MICBIAS_VREFx0_7 4 ++#define MICBIAS_VREFx0_75 5 ++#define MICBIAS_VREFx0_8 6 ++#define MICBIAS_VREFx0_85 7 ++ ++static const char *micbias_volts_enum_array[MICBIAS_VOLT_NUM] = { ++ [MICBIAS_VREFx0_5] = "VREFx0_5", ++ [MICBIAS_VREFx0_55] = "VREFx0_55", ++ [MICBIAS_VREFx0_6] = "VREFx0_6", ++ [MICBIAS_VREFx0_65] = "VREFx0_65", ++ [MICBIAS_VREFx0_7] = "VREFx0_7", ++ [MICBIAS_VREFx0_75] = "VREFx0_75", ++ [MICBIAS_VREFx0_8] = "VREFx0_8", ++ [MICBIAS_VREFx0_85] = "VREFx0_85", ++}; ++ ++static const struct soc_enum rk3308_micbias_volts_enum_array[] = { ++ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(micbias_volts_enum_array), micbias_volts_enum_array), ++}; ++ ++/* ADC MICBIAS1 and MICBIAS2 Main Switch */ ++static const struct soc_enum rk3308_main_micbias_enum_array[] = { ++ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text), ++}; ++ ++static const struct soc_enum rk3308_hpf_enum_array[] = { ++ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(offon_text), offon_text), ++}; ++ ++/* ALC AGC Switch */ ++static const struct soc_enum rk3308_agc_enum_array[] = { ++ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(offon_text), offon_text), ++ SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(offon_text), offon_text), ++}; ++ ++/* ADC MIC Mute/Work Switch */ ++static const struct soc_enum rk3308_mic_mute_enum_array[] = { ++ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(mute_text), mute_text), ++ SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(mute_text), mute_text), ++ SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(mute_text), mute_text), ++ SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(mute_text), mute_text), ++ SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(mute_text), mute_text), ++ SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(mute_text), mute_text), ++ SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(mute_text), mute_text), ++ SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(mute_text), mute_text), ++}; ++ ++/* ALC AGC Approximate Sample Rate */ ++#define AGC_ASR_NUM 8 ++ ++#define AGC_ASR_96KHZ 0 ++#define AGC_ASR_48KHZ 1 ++#define AGC_ASR_44_1KHZ 2 ++#define AGC_ASR_32KHZ 3 ++#define AGC_ASR_24KHZ 4 ++#define AGC_ASR_16KHZ 5 ++#define AGC_ASR_12KHZ 6 ++#define AGC_ASR_8KHZ 7 ++ ++static const char *agc_asr_text[AGC_ASR_NUM] = { ++ [AGC_ASR_96KHZ] = "96KHz", ++ [AGC_ASR_48KHZ] = "48KHz", ++ [AGC_ASR_44_1KHZ] = "44.1KHz", ++ [AGC_ASR_32KHZ] = "32KHz", ++ [AGC_ASR_24KHZ] = "24KHz", ++ [AGC_ASR_16KHZ] = "16KHz", ++ [AGC_ASR_12KHZ] = "12KHz", ++ [AGC_ASR_8KHZ] = "8KHz", ++}; ++ ++static const struct soc_enum rk3308_agc_asr_enum_array[] = { ++ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text), ++ SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text), ++ SOC_ENUM_SINGLE(1, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text), ++ SOC_ENUM_SINGLE(1, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text), ++ SOC_ENUM_SINGLE(2, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text), ++ SOC_ENUM_SINGLE(2, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text), ++ SOC_ENUM_SINGLE(3, 0, ARRAY_SIZE(agc_asr_text), agc_asr_text), ++ SOC_ENUM_SINGLE(3, 1, ARRAY_SIZE(agc_asr_text), agc_asr_text), ++}; ++ ++static const struct snd_kcontrol_new mic_gains_a[] = { ++ /* ADC MIC */ ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Left Volume", ++ RK3308_ADC_ANA_CON01(0), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_a), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Right Volume", ++ RK3308_ADC_ANA_CON01(0), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_a), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Left Volume", ++ RK3308_ADC_ANA_CON01(1), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_a), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Right Volume", ++ RK3308_ADC_ANA_CON01(1), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_a), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Left Volume", ++ RK3308_ADC_ANA_CON01(2), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_a), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Right Volume", ++ RK3308_ADC_ANA_CON01(2), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_a), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Left Volume", ++ RK3308_ADC_ANA_CON01(3), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_a), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Right Volume", ++ RK3308_ADC_ANA_CON01(3), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_a), ++}; ++ ++static const struct snd_kcontrol_new mic_gains_b[] = { ++ /* ADC MIC */ ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Left Volume", ++ RK3308_ADC_ANA_CON01(0), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_b), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 0 Right Volume", ++ RK3308_ADC_ANA_CON01(0), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_b), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Left Volume", ++ RK3308_ADC_ANA_CON01(1), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_b), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 1 Right Volume", ++ RK3308_ADC_ANA_CON01(1), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_b), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Left Volume", ++ RK3308_ADC_ANA_CON01(2), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_b), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 2 Right Volume", ++ RK3308_ADC_ANA_CON01(2), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_b), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Left Volume", ++ RK3308_ADC_ANA_CON01(3), ++ RK3308_ADC_CH1_MIC_GAIN_SFT, ++ RK3308_ADC_CH1_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_b), ++ SOC_SINGLE_EXT_TLV("ADC MIC Group 3 Right Volume", ++ RK3308_ADC_ANA_CON01(3), ++ RK3308_ADC_CH2_MIC_GAIN_SFT, ++ RK3308_ADC_CH2_MIC_GAIN_MAX, ++ 0, ++ rk3308_codec_mic_gain_get, ++ rk3308_codec_mic_gain_put, ++ rk3308_codec_adc_mic_gain_tlv_b), ++}; ++ + static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = { +- /* ALC AGC Channel*/ +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Volume", ++ /* ALC AGC Group */ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Volume", + RK3308_ALC_L_DIG_CON03(0), ++ RK3308_AGC_PGA_GAIN_SFT, ++ RK3308_AGC_PGA_GAIN_MIN, ++ RK3308_AGC_PGA_GAIN_MAX, ++ 0, rk3308_codec_alc_agc_grp_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Volume", + RK3308_ALC_R_DIG_CON03(0), + RK3308_AGC_PGA_GAIN_SFT, +- RK3308_AGC_PGA_GAIN_NDB_18, +- RK3308_AGC_PGA_GAIN_PDB_28_5, +- 0, rk3308_codec_alc_agc_ch_gain_tlv), +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Volume", ++ RK3308_AGC_PGA_GAIN_MIN, ++ RK3308_AGC_PGA_GAIN_MAX, ++ 0, rk3308_codec_alc_agc_grp_gain_tlv), ++ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Volume", + RK3308_ALC_L_DIG_CON03(1), ++ RK3308_AGC_PGA_GAIN_SFT, ++ RK3308_AGC_PGA_GAIN_MIN, ++ RK3308_AGC_PGA_GAIN_MAX, ++ 0, rk3308_codec_alc_agc_grp_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Volume", + RK3308_ALC_R_DIG_CON03(1), + RK3308_AGC_PGA_GAIN_SFT, +- RK3308_AGC_PGA_GAIN_NDB_18, +- RK3308_AGC_PGA_GAIN_PDB_28_5, +- 0, rk3308_codec_alc_agc_ch_gain_tlv), +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Volume", ++ RK3308_AGC_PGA_GAIN_MIN, ++ RK3308_AGC_PGA_GAIN_MAX, ++ 0, rk3308_codec_alc_agc_grp_gain_tlv), ++ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Volume", + RK3308_ALC_L_DIG_CON03(2), ++ RK3308_AGC_PGA_GAIN_SFT, ++ RK3308_AGC_PGA_GAIN_MIN, ++ RK3308_AGC_PGA_GAIN_MAX, ++ 0, rk3308_codec_alc_agc_grp_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Volume", + RK3308_ALC_R_DIG_CON03(2), + RK3308_AGC_PGA_GAIN_SFT, +- RK3308_AGC_PGA_GAIN_NDB_18, +- RK3308_AGC_PGA_GAIN_PDB_28_5, +- 0, rk3308_codec_alc_agc_ch_gain_tlv), +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Volume", ++ RK3308_AGC_PGA_GAIN_MIN, ++ RK3308_AGC_PGA_GAIN_MAX, ++ 0, rk3308_codec_alc_agc_grp_gain_tlv), ++ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Volume", + RK3308_ALC_L_DIG_CON03(3), ++ RK3308_AGC_PGA_GAIN_SFT, ++ RK3308_AGC_PGA_GAIN_MIN, ++ RK3308_AGC_PGA_GAIN_MAX, ++ 0, rk3308_codec_alc_agc_grp_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Volume", + RK3308_ALC_R_DIG_CON03(3), + RK3308_AGC_PGA_GAIN_SFT, +- RK3308_AGC_PGA_GAIN_NDB_18, +- RK3308_AGC_PGA_GAIN_PDB_28_5, +- 0, rk3308_codec_alc_agc_ch_gain_tlv), ++ RK3308_AGC_PGA_GAIN_MIN, ++ RK3308_AGC_PGA_GAIN_MAX, ++ 0, rk3308_codec_alc_agc_grp_gain_tlv), + + /* ALC AGC MAX */ +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Max Volume", ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Max Volume", + RK3308_ALC_L_DIG_CON09(0), ++ RK3308_AGC_MAX_GAIN_PGA_SFT, ++ RK3308_AGC_MAX_GAIN_PGA_MIN, ++ RK3308_AGC_MAX_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Max Volume", + RK3308_ALC_R_DIG_CON09(0), + RK3308_AGC_MAX_GAIN_PGA_SFT, +- RK3308_AGC_MAX_GAIN_PGA_NDB_13_5, +- RK3308_AGC_MAX_GAIN_PGA_PDB_28_5, +- 0, rk3308_codec_alc_agc_ch_max_gain_tlv), +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Max Volume", ++ RK3308_AGC_MAX_GAIN_PGA_MIN, ++ RK3308_AGC_MAX_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), ++ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Max Volume", + RK3308_ALC_L_DIG_CON09(1), ++ RK3308_AGC_MAX_GAIN_PGA_SFT, ++ RK3308_AGC_MAX_GAIN_PGA_MIN, ++ RK3308_AGC_MAX_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Max Volume", + RK3308_ALC_R_DIG_CON09(1), + RK3308_AGC_MAX_GAIN_PGA_SFT, +- RK3308_AGC_MAX_GAIN_PGA_NDB_13_5, +- RK3308_AGC_MAX_GAIN_PGA_PDB_28_5, +- 0, rk3308_codec_alc_agc_ch_max_gain_tlv), +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Max Volume", ++ RK3308_AGC_MAX_GAIN_PGA_MIN, ++ RK3308_AGC_MAX_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), ++ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Max Volume", + RK3308_ALC_L_DIG_CON09(2), ++ RK3308_AGC_MAX_GAIN_PGA_SFT, ++ RK3308_AGC_MAX_GAIN_PGA_MIN, ++ RK3308_AGC_MAX_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Max Volume", + RK3308_ALC_R_DIG_CON09(2), + RK3308_AGC_MAX_GAIN_PGA_SFT, +- RK3308_AGC_MAX_GAIN_PGA_NDB_13_5, +- RK3308_AGC_MAX_GAIN_PGA_PDB_28_5, +- 0, rk3308_codec_alc_agc_ch_max_gain_tlv), +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Max Volume", ++ RK3308_AGC_MAX_GAIN_PGA_MIN, ++ RK3308_AGC_MAX_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), ++ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Max Volume", + RK3308_ALC_L_DIG_CON09(3), ++ RK3308_AGC_MAX_GAIN_PGA_SFT, ++ RK3308_AGC_MAX_GAIN_PGA_MIN, ++ RK3308_AGC_MAX_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Max Volume", + RK3308_ALC_R_DIG_CON09(3), + RK3308_AGC_MAX_GAIN_PGA_SFT, +- RK3308_AGC_MAX_GAIN_PGA_NDB_13_5, +- RK3308_AGC_MAX_GAIN_PGA_PDB_28_5, +- 0, rk3308_codec_alc_agc_ch_max_gain_tlv), ++ RK3308_AGC_MAX_GAIN_PGA_MIN, ++ RK3308_AGC_MAX_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_max_gain_tlv), + + /* ALC AGC MIN */ +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 0 Min Volume", ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Left Min Volume", + RK3308_ALC_L_DIG_CON09(0), ++ RK3308_AGC_MIN_GAIN_PGA_SFT, ++ RK3308_AGC_MIN_GAIN_PGA_MIN, ++ RK3308_AGC_MIN_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 0 Right Min Volume", + RK3308_ALC_R_DIG_CON09(0), + RK3308_AGC_MIN_GAIN_PGA_SFT, +- RK3308_AGC_MIN_GAIN_PGA_NDB_18, +- RK3308_AGC_MIN_GAIN_PGA_PDB_24, +- 0, rk3308_codec_alc_agc_ch_min_gain_tlv), +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 1 Min Volume", ++ RK3308_AGC_MIN_GAIN_PGA_MIN, ++ RK3308_AGC_MIN_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), ++ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Left Min Volume", + RK3308_ALC_L_DIG_CON09(1), ++ RK3308_AGC_MIN_GAIN_PGA_SFT, ++ RK3308_AGC_MIN_GAIN_PGA_MIN, ++ RK3308_AGC_MIN_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 1 Right Min Volume", + RK3308_ALC_R_DIG_CON09(1), + RK3308_AGC_MIN_GAIN_PGA_SFT, +- RK3308_AGC_MIN_GAIN_PGA_NDB_18, +- RK3308_AGC_MIN_GAIN_PGA_PDB_24, +- 0, rk3308_codec_alc_agc_ch_min_gain_tlv), +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 2 Min Volume", ++ RK3308_AGC_MIN_GAIN_PGA_MIN, ++ RK3308_AGC_MIN_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), ++ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Left Min Volume", + RK3308_ALC_L_DIG_CON09(2), ++ RK3308_AGC_MIN_GAIN_PGA_SFT, ++ RK3308_AGC_MIN_GAIN_PGA_MIN, ++ RK3308_AGC_MIN_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 2 Right Min Volume", + RK3308_ALC_R_DIG_CON09(2), + RK3308_AGC_MIN_GAIN_PGA_SFT, +- RK3308_AGC_MIN_GAIN_PGA_NDB_18, +- RK3308_AGC_MIN_GAIN_PGA_PDB_24, +- 0, rk3308_codec_alc_agc_ch_min_gain_tlv), +- SOC_DOUBLE_R_RANGE_TLV("ALC AGC Channel 3 Min Volume", ++ RK3308_AGC_MIN_GAIN_PGA_MIN, ++ RK3308_AGC_MIN_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), ++ ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Left Min Volume", + RK3308_ALC_L_DIG_CON09(3), ++ RK3308_AGC_MIN_GAIN_PGA_SFT, ++ RK3308_AGC_MIN_GAIN_PGA_MIN, ++ RK3308_AGC_MIN_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), ++ SOC_SINGLE_RANGE_TLV("ALC AGC Group 3 Right Min Volume", + RK3308_ALC_R_DIG_CON09(3), + RK3308_AGC_MIN_GAIN_PGA_SFT, +- RK3308_AGC_MIN_GAIN_PGA_NDB_18, +- RK3308_AGC_MIN_GAIN_PGA_PDB_24, +- 0, rk3308_codec_alc_agc_ch_min_gain_tlv), +- +- /* ADC MIC */ +- SOC_SINGLE_RANGE_TLV("ADC MIC Channel 0 Left Volume", +- RK3308_ADC_ANA_CON01(0), +- RK3308_ADC_CH1_MIC_GAIN_SFT, +- RK3308_ADC_CH1_MIC_GAIN_0DB, +- RK3308_ADC_CH1_MIC_GAIN_30DB, +- 0, rk3308_codec_adc_mic_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC MIC Channel 0 Right Volume", +- RK3308_ADC_ANA_CON01(0), +- RK3308_ADC_CH2_MIC_GAIN_SFT, +- RK3308_ADC_CH2_MIC_GAIN_0DB, +- RK3308_ADC_CH2_MIC_GAIN_30DB, +- 0, rk3308_codec_adc_mic_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC MIC Channel 1 Left Volume", +- RK3308_ADC_ANA_CON01(1), +- RK3308_ADC_CH1_MIC_GAIN_SFT, +- RK3308_ADC_CH1_MIC_GAIN_0DB, +- RK3308_ADC_CH1_MIC_GAIN_30DB, +- 0, rk3308_codec_adc_mic_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC MIC Channel 1 Right Volume", +- RK3308_ADC_ANA_CON01(1), +- RK3308_ADC_CH2_MIC_GAIN_SFT, +- RK3308_ADC_CH2_MIC_GAIN_0DB, +- RK3308_ADC_CH2_MIC_GAIN_30DB, +- 0, rk3308_codec_adc_mic_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC MIC Channel 2 Left Volume", +- RK3308_ADC_ANA_CON01(2), +- RK3308_ADC_CH1_MIC_GAIN_SFT, +- RK3308_ADC_CH1_MIC_GAIN_0DB, +- RK3308_ADC_CH1_MIC_GAIN_30DB, +- 0, rk3308_codec_adc_mic_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC MIC Channel 2 Right Volume", +- RK3308_ADC_ANA_CON01(2), +- RK3308_ADC_CH2_MIC_GAIN_SFT, +- RK3308_ADC_CH2_MIC_GAIN_0DB, +- RK3308_ADC_CH2_MIC_GAIN_30DB, +- 0, rk3308_codec_adc_mic_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC MIC Channel 3 Left Volume", +- RK3308_ADC_ANA_CON01(3), +- RK3308_ADC_CH1_MIC_GAIN_SFT, +- RK3308_ADC_CH1_MIC_GAIN_0DB, +- RK3308_ADC_CH1_MIC_GAIN_30DB, +- 0, rk3308_codec_adc_mic_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC MIC Channel 3 Right Volume", +- RK3308_ADC_ANA_CON01(3), +- RK3308_ADC_CH2_MIC_GAIN_SFT, +- RK3308_ADC_CH2_MIC_GAIN_0DB, +- RK3308_ADC_CH2_MIC_GAIN_30DB, +- 0, rk3308_codec_adc_mic_gain_tlv), ++ RK3308_AGC_MIN_GAIN_PGA_MIN, ++ RK3308_AGC_MIN_GAIN_PGA_MAX, ++ 0, rk3308_codec_alc_agc_grp_min_gain_tlv), ++ ++ /* ALC AGC Switch */ ++ SOC_ENUM_EXT("ALC AGC Group 0 Left Switch", rk3308_agc_enum_array[0], ++ rk3308_codec_agc_get, rk3308_codec_agc_put), ++ SOC_ENUM_EXT("ALC AGC Group 0 Right Switch", rk3308_agc_enum_array[1], ++ rk3308_codec_agc_get, rk3308_codec_agc_put), ++ SOC_ENUM_EXT("ALC AGC Group 1 Left Switch", rk3308_agc_enum_array[2], ++ rk3308_codec_agc_get, rk3308_codec_agc_put), ++ SOC_ENUM_EXT("ALC AGC Group 1 Right Switch", rk3308_agc_enum_array[3], ++ rk3308_codec_agc_get, rk3308_codec_agc_put), ++ SOC_ENUM_EXT("ALC AGC Group 2 Left Switch", rk3308_agc_enum_array[4], ++ rk3308_codec_agc_get, rk3308_codec_agc_put), ++ SOC_ENUM_EXT("ALC AGC Group 2 Right Switch", rk3308_agc_enum_array[5], ++ rk3308_codec_agc_get, rk3308_codec_agc_put), ++ SOC_ENUM_EXT("ALC AGC Group 3 Left Switch", rk3308_agc_enum_array[6], ++ rk3308_codec_agc_get, rk3308_codec_agc_put), ++ SOC_ENUM_EXT("ALC AGC Group 3 Right Switch", rk3308_agc_enum_array[7], ++ rk3308_codec_agc_get, rk3308_codec_agc_put), ++ ++ /* ALC AGC Approximate Sample Rate */ ++ SOC_ENUM_EXT("AGC Group 0 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[0], ++ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), ++ SOC_ENUM_EXT("AGC Group 0 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[1], ++ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), ++ SOC_ENUM_EXT("AGC Group 1 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[2], ++ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), ++ SOC_ENUM_EXT("AGC Group 1 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[3], ++ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), ++ SOC_ENUM_EXT("AGC Group 2 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[4], ++ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), ++ SOC_ENUM_EXT("AGC Group 2 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[5], ++ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), ++ SOC_ENUM_EXT("AGC Group 3 Left Approximate Sample Rate", rk3308_agc_asr_enum_array[6], ++ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), ++ SOC_ENUM_EXT("AGC Group 3 Right Approximate Sample Rate", rk3308_agc_asr_enum_array[7], ++ rk3308_codec_agc_asr_get, rk3308_codec_agc_asr_put), ++ ++ /* ADC MICBIAS Voltage */ ++ SOC_ENUM_EXT("ADC MICBIAS Voltage", rk3308_micbias_volts_enum_array[0], ++ rk3308_codec_micbias_volts_get, rk3308_codec_micbias_volts_put), ++ ++ /* ADC Main MICBIAS Switch */ ++ SOC_ENUM_EXT("ADC Main MICBIAS", rk3308_main_micbias_enum_array[0], ++ rk3308_codec_main_micbias_get, rk3308_codec_main_micbias_put), ++ ++ /* ADC MICBIAS1 and MICBIAS2 Switch */ ++ SOC_SINGLE("ADC MICBIAS1", RK3308_ADC_ANA_CON07(1), ++ RK3308_ADC_MIC_BIAS_BUF_SFT, 1, 0), ++ SOC_SINGLE("ADC MICBIAS2", RK3308_ADC_ANA_CON07(2), ++ RK3308_ADC_MIC_BIAS_BUF_SFT, 1, 0), ++ ++ /* ADC MIC Mute/Work Switch */ ++ SOC_ENUM_EXT("ADC MIC Group 0 Left Switch", rk3308_mic_mute_enum_array[0], ++ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), ++ SOC_ENUM_EXT("ADC MIC Group 0 Right Switch", rk3308_mic_mute_enum_array[1], ++ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), ++ SOC_ENUM_EXT("ADC MIC Group 1 Left Switch", rk3308_mic_mute_enum_array[2], ++ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), ++ SOC_ENUM_EXT("ADC MIC Group 1 Right Switch", rk3308_mic_mute_enum_array[3], ++ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), ++ SOC_ENUM_EXT("ADC MIC Group 2 Left Switch", rk3308_mic_mute_enum_array[4], ++ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), ++ SOC_ENUM_EXT("ADC MIC Group 2 Right Switch", rk3308_mic_mute_enum_array[5], ++ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), ++ SOC_ENUM_EXT("ADC MIC Group 3 Left Switch", rk3308_mic_mute_enum_array[6], ++ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), ++ SOC_ENUM_EXT("ADC MIC Group 3 Right Switch", rk3308_mic_mute_enum_array[7], ++ rk3308_codec_mic_mute_get, rk3308_codec_mic_mute_put), + + /* ADC ALC */ +- SOC_SINGLE_RANGE_TLV("ADC ALC Channel 0 Left Volume", ++ SOC_SINGLE_RANGE_TLV("ADC ALC Group 0 Left Volume", + RK3308_ADC_ANA_CON03(0), + RK3308_ADC_CH1_ALC_GAIN_SFT, +- RK3308_ADC_CH1_ALC_GAIN_NDB_18, +- RK3308_ADC_CH1_ALC_GAIN_PDB_28_5, ++ RK3308_ADC_CH1_ALC_GAIN_MIN, ++ RK3308_ADC_CH1_ALC_GAIN_MAX, + 0, rk3308_codec_adc_alc_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC ALC Channel 0 Right Volume", ++ SOC_SINGLE_RANGE_TLV("ADC ALC Group 0 Right Volume", + RK3308_ADC_ANA_CON04(0), + RK3308_ADC_CH2_ALC_GAIN_SFT, +- RK3308_ADC_CH2_ALC_GAIN_NDB_18, +- RK3308_ADC_CH2_ALC_GAIN_PDB_28_5, ++ RK3308_ADC_CH2_ALC_GAIN_MIN, ++ RK3308_ADC_CH2_ALC_GAIN_MAX, + 0, rk3308_codec_adc_alc_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC ALC Channel 1 Left Volume", ++ SOC_SINGLE_RANGE_TLV("ADC ALC Group 1 Left Volume", + RK3308_ADC_ANA_CON03(1), + RK3308_ADC_CH1_ALC_GAIN_SFT, +- RK3308_ADC_CH1_ALC_GAIN_NDB_18, +- RK3308_ADC_CH1_ALC_GAIN_PDB_28_5, ++ RK3308_ADC_CH1_ALC_GAIN_MIN, ++ RK3308_ADC_CH1_ALC_GAIN_MAX, + 0, rk3308_codec_adc_alc_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC ALC Channel 1 Right Volume", ++ SOC_SINGLE_RANGE_TLV("ADC ALC Group 1 Right Volume", + RK3308_ADC_ANA_CON04(1), + RK3308_ADC_CH2_ALC_GAIN_SFT, +- RK3308_ADC_CH2_ALC_GAIN_NDB_18, +- RK3308_ADC_CH2_ALC_GAIN_PDB_28_5, ++ RK3308_ADC_CH2_ALC_GAIN_MIN, ++ RK3308_ADC_CH2_ALC_GAIN_MAX, + 0, rk3308_codec_adc_alc_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC ALC Channel 2 Left Volume", ++ SOC_SINGLE_RANGE_TLV("ADC ALC Group 2 Left Volume", + RK3308_ADC_ANA_CON03(2), + RK3308_ADC_CH1_ALC_GAIN_SFT, +- RK3308_ADC_CH1_ALC_GAIN_NDB_18, +- RK3308_ADC_CH1_ALC_GAIN_PDB_28_5, ++ RK3308_ADC_CH1_ALC_GAIN_MIN, ++ RK3308_ADC_CH1_ALC_GAIN_MAX, + 0, rk3308_codec_adc_alc_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC ALC Channel 2 Right Volume", ++ SOC_SINGLE_RANGE_TLV("ADC ALC Group 2 Right Volume", + RK3308_ADC_ANA_CON04(2), + RK3308_ADC_CH2_ALC_GAIN_SFT, +- RK3308_ADC_CH2_ALC_GAIN_NDB_18, +- RK3308_ADC_CH2_ALC_GAIN_PDB_28_5, ++ RK3308_ADC_CH2_ALC_GAIN_MIN, ++ RK3308_ADC_CH2_ALC_GAIN_MAX, + 0, rk3308_codec_adc_alc_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC ALC Channel 3 Left Volume", ++ SOC_SINGLE_RANGE_TLV("ADC ALC Group 3 Left Volume", + RK3308_ADC_ANA_CON03(3), + RK3308_ADC_CH1_ALC_GAIN_SFT, +- RK3308_ADC_CH1_ALC_GAIN_NDB_18, +- RK3308_ADC_CH1_ALC_GAIN_PDB_28_5, ++ RK3308_ADC_CH1_ALC_GAIN_MIN, ++ RK3308_ADC_CH1_ALC_GAIN_MAX, + 0, rk3308_codec_adc_alc_gain_tlv), +- SOC_SINGLE_RANGE_TLV("ADC ALC Channel 3 Right Volume", ++ SOC_SINGLE_RANGE_TLV("ADC ALC Group 3 Right Volume", + RK3308_ADC_ANA_CON04(3), + RK3308_ADC_CH2_ALC_GAIN_SFT, +- RK3308_ADC_CH2_ALC_GAIN_NDB_18, +- RK3308_ADC_CH2_ALC_GAIN_PDB_28_5, ++ RK3308_ADC_CH2_ALC_GAIN_MIN, ++ RK3308_ADC_CH2_ALC_GAIN_MAX, + 0, rk3308_codec_adc_alc_gain_tlv), + +- /* DAC */ +- SOC_SINGLE_RANGE_TLV("DAC Left Volume", +- RK3308_DAC_ANA_CON04, +- RK3308_DAC_L_GAIN_SFT, +- RK3308_DAC_L_GAIN_0DB, +- RK3308_DAC_L_GAIN_PDB_6, +- 0, rk3308_codec_dac_gain_tlv), +- SOC_SINGLE_RANGE_TLV("DAC Right Volume", +- RK3308_DAC_ANA_CON04, +- RK3308_DAC_R_GAIN_SFT, +- RK3308_DAC_R_GAIN_0DB, +- RK3308_DAC_R_GAIN_PDB_6, +- 0, rk3308_codec_dac_gain_tlv), ++ /* ADC High Pass Filter */ ++ SOC_ENUM_EXT("ADC Group 0 HPF Cut-off", rk3308_hpf_enum_array[0], ++ rk3308_codec_hpf_get, rk3308_codec_hpf_put), ++ SOC_ENUM_EXT("ADC Group 1 HPF Cut-off", rk3308_hpf_enum_array[1], ++ rk3308_codec_hpf_get, rk3308_codec_hpf_put), ++ SOC_ENUM_EXT("ADC Group 2 HPF Cut-off", rk3308_hpf_enum_array[2], ++ rk3308_codec_hpf_get, rk3308_codec_hpf_put), ++ SOC_ENUM_EXT("ADC Group 3 HPF Cut-off", rk3308_hpf_enum_array[3], ++ rk3308_codec_hpf_get, rk3308_codec_hpf_put), ++ ++ /* DAC LINEOUT */ ++ SOC_SINGLE_TLV("DAC LINEOUT Left Volume", ++ RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_GAIN_SFT, ++ RK3308_DAC_L_LINEOUT_GAIN_MAX, ++ 0, rk3308_codec_dac_lineout_gain_tlv), ++ SOC_SINGLE_TLV("DAC LINEOUT Right Volume", ++ RK3308_DAC_ANA_CON04, ++ RK3308_DAC_R_LINEOUT_GAIN_SFT, ++ RK3308_DAC_R_LINEOUT_GAIN_MAX, ++ 0, rk3308_codec_dac_lineout_gain_tlv), + + /* DAC HPOUT */ +- SOC_SINGLE_RANGE_TLV("DAC HPOUT Left Volume", +- RK3308_DAC_ANA_CON05, +- RK3308_DAC_L_HPOUT_GAIN_SFT, +- RK3308_DAC_L_HPOUT_GAIN_NDB_39, +- RK3308_DAC_L_HPOUT_GAIN_PDB_6, +- 0, rk3308_codec_dac_hpout_gain_tlv), +- SOC_SINGLE_RANGE_TLV("DAC HPOUT Right Volume", +- RK3308_DAC_ANA_CON06, +- RK3308_DAC_R_HPOUT_GAIN_SFT, +- RK3308_DAC_R_HPOUT_GAIN_NDB_39, +- RK3308_DAC_R_HPOUT_GAIN_PDB_6, +- 0, rk3308_codec_dac_hpout_gain_tlv), ++ SOC_SINGLE_EXT_TLV("DAC HPOUT Left Volume", ++ RK3308_DAC_ANA_CON05, ++ RK3308_DAC_L_HPOUT_GAIN_SFT, ++ RK3308_DAC_L_HPOUT_GAIN_MAX, ++ 0, ++ rk3308_codec_hpout_l_get_tlv, ++ rk3308_codec_hpout_l_put_tlv, ++ rk3308_codec_dac_hpout_gain_tlv), ++ SOC_SINGLE_EXT_TLV("DAC HPOUT Right Volume", ++ RK3308_DAC_ANA_CON06, ++ RK3308_DAC_R_HPOUT_GAIN_SFT, ++ RK3308_DAC_R_HPOUT_GAIN_MAX, ++ 0, ++ rk3308_codec_hpout_r_get_tlv, ++ rk3308_codec_hpout_r_put_tlv, ++ rk3308_codec_dac_hpout_gain_tlv), + + /* DAC HPMIX */ + SOC_SINGLE_RANGE_TLV("DAC HPMIX Left Volume", +- RK3308_DAC_ANA_CON05, ++ RK3308_DAC_ANA_CON12, + RK3308_DAC_L_HPMIX_GAIN_SFT, +- RK3308_DAC_L_HPMIX_GAIN_NDB_6, +- RK3308_DAC_L_HPMIX_GAIN_0DB, ++ RK3308_DAC_L_HPMIX_GAIN_MIN, ++ RK3308_DAC_L_HPMIX_GAIN_MAX, + 0, rk3308_codec_dac_hpmix_gain_tlv), + SOC_SINGLE_RANGE_TLV("DAC HPMIX Right Volume", +- RK3308_DAC_ANA_CON05, ++ RK3308_DAC_ANA_CON12, + RK3308_DAC_R_HPMIX_GAIN_SFT, +- RK3308_DAC_R_HPMIX_GAIN_NDB_6, +- RK3308_DAC_R_HPMIX_GAIN_0DB, ++ RK3308_DAC_R_HPMIX_GAIN_MIN, ++ RK3308_DAC_R_HPMIX_GAIN_MAX, + 0, rk3308_codec_dac_hpmix_gain_tlv), + }; + +-static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on) ++static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { +- gpiod_direction_output(rk3308->spk_ctl_gpio, on); ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; ++ ++ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { ++ dev_err(rk3308->plat_dev, ++ "%s: Invalid ADC grp: %d\n", __func__, e->reg); ++ return -EINVAL; ++ } ++ ++ if (e->shift_l) ++ ucontrol->value.integer.value[0] = rk3308->agc_r[e->reg]; ++ else ++ ucontrol->value.integer.value[0] = rk3308->agc_l[e->reg]; ++ ++ return 0; + } + +-static int rk3308_codec_reset(struct snd_soc_codec *codec) ++static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; ++ unsigned int value = ucontrol->value.integer.value[0]; ++ int grp = e->reg; + +- reset_control_assert(rk3308->reset); +- usleep_range(200, 300); /* estimated value */ +- reset_control_deassert(rk3308->reset); ++ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { ++ dev_err(rk3308->plat_dev, ++ "%s: Invalid ADC grp: %d\n", __func__, e->reg); ++ return -EINVAL; ++ } + +- regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00); +- usleep_range(200, 300); /* estimated value */ +- regmap_write(rk3308->regmap, RK3308_GLB_CON, +- RK3308_SYS_WORK | +- RK3308_DAC_DIG_WORK | +- RK3308_ADC_DIG_WORK); ++ if (value) { ++ /* ALC AGC On */ ++ if (e->shift_l) { ++ /* ALC AGC Right On */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp), ++ RK3308_AGC_FUNC_SEL_MSK, ++ RK3308_AGC_FUNC_SEL_EN); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp), ++ RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK, ++ RK3308_ADC_ALCR_CON_GAIN_PGAR_EN); ++ ++ rk3308->agc_r[e->reg] = 1; ++ } else { ++ /* ALC AGC Left On */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp), ++ RK3308_AGC_FUNC_SEL_MSK, ++ RK3308_AGC_FUNC_SEL_EN); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp), ++ RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK, ++ RK3308_ADC_ALCL_CON_GAIN_PGAL_EN); ++ ++ rk3308->agc_l[e->reg] = 1; ++ } ++ } else { ++ /* ALC AGC Off */ ++ if (e->shift_l) { ++ /* ALC AGC Right Off */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp), ++ RK3308_AGC_FUNC_SEL_MSK, ++ RK3308_AGC_FUNC_SEL_DIS); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp), ++ RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK, ++ RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS); ++ ++ rk3308->agc_r[e->reg] = 0; ++ } else { ++ /* ALC AGC Left Off */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp), ++ RK3308_AGC_FUNC_SEL_MSK, ++ RK3308_AGC_FUNC_SEL_DIS); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(grp), ++ RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK, ++ RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS); ++ ++ rk3308->agc_l[e->reg] = 0; ++ } ++ } + + return 0; + } + +-static int rk3308_set_bias_level(struct snd_soc_codec *codec, +- enum snd_soc_bias_level level) ++static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { +- switch (level) { +- case SND_SOC_BIAS_ON: +- break; +- +- case SND_SOC_BIAS_PREPARE: +- break; ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; ++ unsigned int value; ++ int grp = e->reg; + +- case SND_SOC_BIAS_STANDBY: +- case SND_SOC_BIAS_OFF: +- break; ++ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { ++ dev_err(rk3308->plat_dev, ++ "%s: Invalid ADC grp: %d\n", __func__, e->reg); ++ return -EINVAL; + } + +- snd_soc_codec_force_bias_level(codec, level); ++ if (e->shift_l) { ++ regmap_read(rk3308->regmap, RK3308_ALC_R_DIG_CON04(grp), &value); ++ rk3308->agc_asr_r[e->reg] = value >> RK3308_AGC_APPROX_RATE_SFT; ++ ucontrol->value.integer.value[0] = rk3308->agc_asr_r[e->reg]; ++ } else { ++ regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON04(grp), &value); ++ rk3308->agc_asr_l[e->reg] = value >> RK3308_AGC_APPROX_RATE_SFT; ++ ucontrol->value.integer.value[0] = rk3308->agc_asr_l[e->reg]; ++ } + + return 0; + } + +-static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai, +- unsigned int fmt) ++static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = codec_dai->codec; ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); +- unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0; +- int ch = rk3308->adc_ch; ++ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; ++ unsigned int value; ++ int grp = e->reg; + +- switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { +- case SND_SOC_DAIFMT_CBS_CFS: +- adc_aif2 |= RK3308_ADC_IO_MODE_SLAVE; +- adc_aif2 |= RK3308_ADC_MODE_SLAVE; +- dac_aif2 |= RK3308_DAC_IO_MODE_SLAVE; +- dac_aif2 |= RK3308_DAC_MODE_SLAVE; +- break; +- case SND_SOC_DAIFMT_CBM_CFM: +- adc_aif2 |= RK3308_ADC_IO_MODE_MASTER; +- adc_aif2 |= RK3308_ADC_MODE_MASTER; +- dac_aif2 |= RK3308_DAC_IO_MODE_MASTER; +- dac_aif2 |= RK3308_DAC_MODE_MASTER; +- break; +- default: ++ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { ++ dev_err(rk3308->plat_dev, ++ "%s: Invalid ADC grp: %d\n", __func__, e->reg); + return -EINVAL; + } + +- switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { +- case SND_SOC_DAIFMT_DSP_A: +- adc_aif1 |= RK3308_ADC_I2S_MODE_PCM; +- dac_aif1 |= RK3308_DAC_I2S_MODE_PCM; +- break; +- case SND_SOC_DAIFMT_I2S: +- adc_aif1 |= RK3308_ADC_I2S_MODE_I2S; +- dac_aif1 |= RK3308_DAC_I2S_MODE_I2S; +- break; +- case SND_SOC_DAIFMT_RIGHT_J: +- adc_aif1 |= RK3308_ADC_I2S_MODE_RJ; +- dac_aif1 |= RK3308_DAC_I2S_MODE_RJ; +- break; +- case SND_SOC_DAIFMT_LEFT_J: +- adc_aif1 |= RK3308_ADC_I2S_MODE_RJ; +- dac_aif1 |= RK3308_DAC_I2S_MODE_LJ; +- break; +- default: +- return -EINVAL; ++ value = ucontrol->value.integer.value[0] << RK3308_AGC_APPROX_RATE_SFT; ++ ++ if (e->shift_l) { ++ /* ALC AGC Right Approximate Sample Rate */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON04(grp), ++ RK3308_AGC_APPROX_RATE_MSK, ++ value); ++ rk3308->agc_asr_r[e->reg] = ucontrol->value.integer.value[0]; ++ } else { ++ /* ALC AGC Left Approximate Sample Rate */ ++ regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON04(grp), ++ RK3308_AGC_APPROX_RATE_MSK, ++ value); ++ rk3308->agc_asr_l[e->reg] = ucontrol->value.integer.value[0]; + } + +- switch (fmt & SND_SOC_DAIFMT_INV_MASK) { +- case SND_SOC_DAIFMT_NB_NF: +- adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL; +- adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL; +- dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL; +- dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL; +- break; +- case SND_SOC_DAIFMT_IB_IF: +- adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; +- adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; +- dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; +- dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; +- break; +- case SND_SOC_DAIFMT_IB_NF: +- adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL; +- adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; +- dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL; +- dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; +- break; +- case SND_SOC_DAIFMT_NB_IF: +- adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; +- adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL; +- dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; +- dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL; +- break; +- default: ++ return 0; ++} ++ ++static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; ++ unsigned int value; ++ int grp = e->reg; ++ ++ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { ++ dev_err(rk3308->plat_dev, ++ "%s: Invalid ADC grp: %d\n", __func__, e->reg); + return -EINVAL; + } + +- regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(ch), +- RK3308_ADC_I2S_LRC_POL_MSK | +- RK3308_ADC_I2S_MODE_MSK, +- adc_aif1); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(ch), +- RK3308_ADC_IO_MODE_MSK | +- RK3308_ADC_MODE_MSK | +- RK3308_ADC_I2S_BIT_CLK_POL_MSK, +- adc_aif2); +- +- regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, +- RK3308_DAC_I2S_LRC_POL_MSK | +- RK3308_DAC_I2S_MODE_MSK, +- dac_aif1); +- regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, +- RK3308_DAC_IO_MODE_MSK | +- RK3308_DAC_MODE_MSK | +- RK3308_DAC_I2S_BIT_CLK_POL_MSK, +- dac_aif2); ++ if (e->shift_l) { ++ /* ADC MIC Right Mute/Work Infos */ ++ regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), &value); ++ rk3308->mic_mute_r[e->reg] = (value & RK3308_ADC_R_CH_BIST_SINE) >> ++ RK3308_ADC_R_CH_BIST_SFT; ++ ucontrol->value.integer.value[0] = rk3308->mic_mute_r[e->reg]; ++ } else { ++ /* ADC MIC Left Mute/Work Infos */ ++ regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), &value); ++ rk3308->mic_mute_l[e->reg] = (value & RK3308_ADC_L_CH_BIST_SINE) >> ++ RK3308_ADC_L_CH_BIST_SFT; ++ ucontrol->value.integer.value[0] = rk3308->mic_mute_l[e->reg]; ++ } + + return 0; + } + +-static int rk3308_hw_params(struct snd_pcm_substream *substream, +- struct snd_pcm_hw_params *params, +- struct snd_soc_dai *dai) ++static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = dai->codec; ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); +- unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0; +- int ch = rk3308->adc_ch; ++ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; ++ unsigned int value; ++ int grp = e->reg; + +- switch (params_format(params)) { +- case SNDRV_PCM_FORMAT_S16_LE: +- adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS; +- dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS; +- break; +- case SNDRV_PCM_FORMAT_S20_3LE: +- adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS; +- dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS; +- break; +- case SNDRV_PCM_FORMAT_S24_LE: +- adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS; +- dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS; +- break; +- case SNDRV_PCM_FORMAT_S32_LE: +- adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS; +- dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS; +- break; +- default: ++ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { ++ dev_err(rk3308->plat_dev, ++ "%s: Invalid ADC grp: %d\n", __func__, e->reg); + return -EINVAL; + } + +- switch (params_channels(params)) { +- case 1: +- adc_aif1 |= RK3308_ADC_I2S_MONO; +- break; +- case 2: +- adc_aif1 |= RK3308_ADC_I2S_STEREO; +- break; +- default: +- return -EINVAL; ++ if (e->shift_l) { ++ /* ADC MIC Right Mute/Work Configuration */ ++ value = ucontrol->value.integer.value[0] << RK3308_ADC_R_CH_BIST_SFT; ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_R_CH_BIST_SINE, ++ value); ++ rk3308->mic_mute_r[e->reg] = ucontrol->value.integer.value[0]; ++ } else { ++ /* ADC MIC Left Mute/Work Configuration */ ++ value = ucontrol->value.integer.value[0] << RK3308_ADC_L_CH_BIST_SFT; ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_L_CH_BIST_SINE, ++ value); ++ rk3308->mic_mute_l[e->reg] = ucontrol->value.integer.value[0]; + } + +- adc_aif1 |= RK3308_ADC_I2S_LR_NORMAL; +- adc_aif2 |= RK3308_ADC_I2S_WORK; +- dac_aif1 |= RK3308_DAC_I2S_LR_NORMAL; +- dac_aif2 |= RK3308_DAC_I2S_WORK; ++ return 0; ++} + +- regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(ch), +- RK3308_ADC_I2S_VALID_LEN_MSK | +- RK3308_ADC_I2S_LR_MSK | +- RK3308_ADC_I2S_TYPE_MSK, +- adc_aif1); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(ch), +- RK3308_ADC_I2S_MSK, +- adc_aif2); ++static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); + +- regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, +- RK3308_DAC_I2S_VALID_LEN_MSK | +- RK3308_DAC_I2S_LR_MSK, +- dac_aif1); +- regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, +- RK3308_DAC_I2S_MSK, +- dac_aif2); ++ ucontrol->value.integer.value[0] = rk3308->micbias_volt; + + return 0; + } + +-static int rk3308_digital_mute(struct snd_soc_dai *dai, int mute) ++static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ unsigned int volt = ucontrol->value.integer.value[0]; ++ int ret; ++ ++ ret = check_micbias(volt); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, "The invalid micbias volt: %d\n", ++ volt); ++ return ret; ++ } ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), ++ RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK, ++ volt); ++ ++ rk3308->micbias_volt = volt; ++ + return 0; + } + +-static int rk3308_codec_dac_enable(struct rk3308_codec_priv *rk3308) ++static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { +- /* Step 01 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, +- RK3308_DAC_CURRENT_MSK, +- RK3308_DAC_CURRENT_EN); +- +- /* Step 02 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, +- RK3308_DAC_BUF_REF_L_MSK | +- RK3308_DAC_BUF_REF_R_MSK, +- RK3308_DAC_BUF_REF_L_EN | +- RK3308_DAC_BUF_REF_R_EN); ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); + +- /* Step 03 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, +- RK3308_DAC_POP_SOUND_L_MSK | +- RK3308_DAC_POP_SOUND_R_MSK, +- RK3308_DAC_POP_SOUND_L_WORK | +- RK3308_DAC_POP_SOUND_R_WORK); ++ ucontrol->value.integer.value[0] = rk3308->enable_micbias; + +- /* Step 04 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, +- RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN, +- RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN); ++ return 0; ++} + +- /* Step 05 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, +- RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK, +- RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK); ++static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ unsigned int on = ucontrol->value.integer.value[0]; ++ ++ if (on) { ++ if (!rk3308->enable_micbias) ++ rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt); ++ } else { ++ if (rk3308->enable_micbias) ++ rk3308_codec_micbias_disable(rk3308); ++ } + +- /* Step 06 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, +- RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN, +- RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN); ++ return 0; ++} + +- /* Step 07 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, +- RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN, +- RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN); ++static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return snd_soc_get_volsw_range(kcontrol, ucontrol); ++} + +- /* Step 08 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, +- RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK, +- RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK); ++static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ unsigned int gain = ucontrol->value.integer.value[0]; + +- /* Step 09 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, +- RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN, +- RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN); ++ if (gain > RK3308_ADC_CH1_MIC_GAIN_MAX) { ++ dev_err(rk3308->plat_dev, "%s: invalid mic gain: %d\n", ++ __func__, gain); ++ return -EINVAL; ++ } + +- /* Step 10 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, +- RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN, +- RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN); ++ if (rk3308->codec_ver == ACODEC_VERSION_A) { ++ /* ++ * From the TRM, there are only suupport 0dB(gain==0) and ++ * 20dB(gain==3) on the codec version A. ++ */ ++ if (!(gain == 0 || gain == RK3308_ADC_CH1_MIC_GAIN_MAX)) { ++ dev_err(rk3308->plat_dev, ++ "version A doesn't supported: %d, expect: 0,%d\n", ++ gain, RK3308_ADC_CH1_MIC_GAIN_MAX); ++ return 0; ++ } ++ } + +- /* Step 11 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, +- RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN, +- RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN); ++ return snd_soc_put_volsw_range(kcontrol, ucontrol); ++} + +- /* Step 12 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, +- RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK, +- RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK); ++static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; ++ unsigned int value; + +- /* Step 13 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, +- RK3308_DAC_L_HPMIX_SEL_MSK | +- RK3308_DAC_R_HPMIX_SEL_MSK, +- RK3308_DAC_L_HPMIX_I2S | +- RK3308_DAC_R_HPMIX_I2S); ++ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { ++ dev_err(rk3308->plat_dev, ++ "%s: Invalid ADC grp: %d\n", __func__, e->reg); ++ return -EINVAL; ++ } + +- /* Step 14 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, +- RK3308_DAC_L_HPMIX_UNMUTE | +- RK3308_DAC_R_HPMIX_UNMUTE, +- RK3308_DAC_L_HPMIX_UNMUTE | +- RK3308_DAC_R_HPMIX_UNMUTE); ++ regmap_read(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg), &value); ++ if (value & RK3308_ADC_HPF_PATH_MSK) ++ rk3308->hpf_cutoff[e->reg] = 0; ++ else ++ rk3308->hpf_cutoff[e->reg] = 1; + +- /* Step 15 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, +- RK3308_DAC_L_HPMIX_GAIN_MSK | +- RK3308_DAC_R_HPMIX_GAIN_MSK, +- RK3308_DAC_L_HPMIX_GAIN_0DB | +- RK3308_DAC_R_HPMIX_GAIN_0DB); ++ ucontrol->value.integer.value[0] = rk3308->hpf_cutoff[e->reg]; + +- /* Step 16 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, +- RK3308_DAC_L_HPOUT_UNMUTE | +- RK3308_DAC_R_HPOUT_UNMUTE, +- RK3308_DAC_L_HPOUT_UNMUTE | +- RK3308_DAC_R_HPOUT_UNMUTE); ++ return 0; ++} + +- /* Step 17 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, +- RK3308_DAC_L_LINEOUT_UNMUTE | +- RK3308_DAC_R_LINEOUT_UNMUTE, +- RK3308_DAC_L_LINEOUT_UNMUTE | +- RK3308_DAC_R_LINEOUT_UNMUTE); ++static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; ++ unsigned int value = ucontrol->value.integer.value[0]; + +- /* Step 18 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, +- RK3308_DAC_L_HPOUT_GAIN_MSK, +- RK3308_DAC_L_HPOUT_GAIN_0DB); ++ if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { ++ dev_err(rk3308->plat_dev, ++ "%s: Invalid ADC grp: %d\n", __func__, e->reg); ++ return -EINVAL; ++ } + +- /* Step 18 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, +- RK3308_DAC_R_HPOUT_GAIN_MSK, +- RK3308_DAC_R_HPOUT_GAIN_0DB); ++ if (value) { ++ /* Enable high pass filter for ADCs */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg), ++ RK3308_ADC_HPF_PATH_MSK, ++ RK3308_ADC_HPF_PATH_EN); ++ } else { ++ /* Disable high pass filter for ADCs. */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON04(e->reg), ++ RK3308_ADC_HPF_PATH_MSK, ++ RK3308_ADC_HPF_PATH_DIS); ++ } + +- /* Step 19 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, +- RK3308_DAC_L_GAIN_MSK | RK3308_DAC_R_GAIN_MSK, +- RK3308_DAC_L_GAIN_0DB | RK3308_DAC_R_GAIN_0DB); ++ rk3308->hpf_cutoff[e->reg] = value; + + return 0; + } + +-static int rk3308_codec_dac_disable(struct rk3308_codec_priv *rk3308) ++static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { +- /* Step 01 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, +- RK3308_DAC_L_GAIN_MSK | RK3308_DAC_R_GAIN_MSK, +- RK3308_DAC_L_GAIN_0DB | RK3308_DAC_R_GAIN_0DB); +- +- /* +- * Step 02 +- * +- * Note1. In the step2, adjusting the register step by step to the +- * appropriate value and taking 20ms as time step +- */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, +- RK3308_DAC_L_HPOUT_GAIN_MSK, +- RK3308_DAC_L_HPOUT_GAIN_NDB_39); +- +- /* Step 02 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, +- RK3308_DAC_R_HPOUT_GAIN_MSK, +- RK3308_DAC_R_HPOUT_GAIN_NDB_39); ++ return snd_soc_get_volsw_range(kcontrol, ucontrol); ++} + +- /* Step 03 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, +- RK3308_DAC_L_HPMIX_UNMUTE | +- RK3308_DAC_R_HPMIX_UNMUTE, +- RK3308_DAC_L_HPMIX_MUTE | +- RK3308_DAC_R_HPMIX_MUTE); ++static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ unsigned int dgain = ucontrol->value.integer.value[0]; + +- /* Step 04 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, +- RK3308_DAC_L_HPMIX_SEL_MSK | +- RK3308_DAC_R_HPMIX_SEL_MSK, +- RK3308_DAC_L_HPMIX_NONE | +- RK3308_DAC_R_HPMIX_NONE); ++ if (dgain > RK3308_DAC_L_HPOUT_GAIN_MAX) { ++ dev_err(rk3308->plat_dev, "%s: invalid l_dgain: %d\n", ++ __func__, dgain); ++ return -EINVAL; ++ } + +- /* Step 05 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, +- RK3308_DAC_L_HPOUT_UNMUTE | +- RK3308_DAC_R_HPOUT_UNMUTE, +- RK3308_DAC_L_HPOUT_MUTE | +- RK3308_DAC_R_HPOUT_MUTE); ++ rk3308->hpout_l_dgain = dgain; + +- /* Step 06 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, +- RK3308_DAC_L_DAC_WORK | RK3308_DAC_R_DAC_WORK, +- RK3308_DAC_L_DAC_INIT | RK3308_DAC_R_DAC_INIT); ++ return snd_soc_put_volsw_range(kcontrol, ucontrol); ++} + +- /* Step 07 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, +- RK3308_DAC_L_HPOUT_EN | RK3308_DAC_R_HPOUT_EN, +- RK3308_DAC_L_HPOUT_DIS | RK3308_DAC_R_HPOUT_DIS); ++static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return snd_soc_get_volsw_range(kcontrol, ucontrol); ++} + +- /* Step 08 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, +- RK3308_DAC_L_LINEOUT_UNMUTE | +- RK3308_DAC_R_LINEOUT_UNMUTE, +- RK3308_DAC_L_LINEOUT_MUTE | +- RK3308_DAC_R_LINEOUT_MUTE); ++static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ unsigned int dgain = ucontrol->value.integer.value[0]; + +- /* Step 09 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, +- RK3308_DAC_L_LINEOUT_EN | RK3308_DAC_R_LINEOUT_EN, +- RK3308_DAC_L_LINEOUT_DIS | RK3308_DAC_R_LINEOUT_DIS); ++ if (dgain > RK3308_DAC_R_HPOUT_GAIN_MAX) { ++ dev_err(rk3308->plat_dev, "%s: invalid r_dgain: %d\n", ++ __func__, dgain); ++ return -EINVAL; ++ } + +- /* Step 10 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, +- RK3308_DAC_L_HPMIX_EN | RK3308_DAC_R_HPMIX_EN, +- RK3308_DAC_L_HPMIX_DIS | RK3308_DAC_R_HPMIX_DIS); ++ rk3308->hpout_r_dgain = dgain; + +- /* Step 11 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, +- RK3308_DAC_L_DAC_EN | RK3308_DAC_R_DAC_EN, +- RK3308_DAC_L_DAC_DIS | RK3308_DAC_R_DAC_DIS); ++ return snd_soc_put_volsw_range(kcontrol, ucontrol); ++} + +- /* Step 12 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, +- RK3308_DAC_L_CLK_EN | RK3308_DAC_R_CLK_EN, +- RK3308_DAC_L_CLK_DIS | RK3308_DAC_R_CLK_DIS); ++static u32 to_mapped_grp(struct rk3308_codec_priv *rk3308, int idx) ++{ ++ return rk3308->i2s_sdis[idx]; ++} + +- /* Step 13 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, +- RK3308_DAC_L_REF_EN | RK3308_DAC_R_REF_EN, +- RK3308_DAC_L_REF_DIS | RK3308_DAC_R_REF_DIS); ++static bool adc_for_each_grp(struct rk3308_codec_priv *rk3308, ++ int type, int idx, u32 *grp) ++{ ++ if (type == ADC_TYPE_NORMAL) { ++ u32 mapped_grp = to_mapped_grp(rk3308, idx); ++ int max_grps; ++ ++ if (rk3308->enable_all_adcs) ++ max_grps = ADC_LR_GROUP_MAX; ++ else ++ max_grps = rk3308->used_adc_grps; ++ ++ if (idx >= max_grps) ++ return false; ++ ++ if ((!rk3308->loopback_dacs_enabled) && ++ handle_loopback(rk3308) && ++ rk3308->loopback_grp == mapped_grp) { ++ /* ++ * Ths loopback DACs are closed, and specify the ++ * loopback ADCs. ++ */ ++ *grp = ADC_GRP_SKIP_MAGIC; ++ } else if (rk3308->en_always_grps_num && ++ rk3308->skip_grps[mapped_grp]) { ++ /* To set the skip flag if the ADC GRP is enabled. */ ++ *grp = ADC_GRP_SKIP_MAGIC; ++ } else { ++ *grp = mapped_grp; ++ } + +- /* Step 14 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, +- RK3308_DAC_POP_SOUND_L_MSK | +- RK3308_DAC_POP_SOUND_R_MSK, +- RK3308_DAC_POP_SOUND_L_INIT | +- RK3308_DAC_POP_SOUND_R_INIT); ++ dev_dbg(rk3308->plat_dev, ++ "ADC_TYPE_NORMAL, idx: %d, mapped_grp: %d, get grp: %d,\n", ++ idx, mapped_grp, *grp); ++ } else if (type == ADC_TYPE_ALL) { ++ if (idx >= ADC_LR_GROUP_MAX) ++ return false; ++ ++ *grp = idx; ++ dev_dbg(rk3308->plat_dev, ++ "ADC_TYPE_ALL, idx: %d, get grp: %d\n", ++ idx, *grp); ++ } else if (type == ADC_TYPE_DBG) { ++ if (idx >= ADC_LR_GROUP_MAX) ++ return false; ++ ++ if (idx == (int)rk3308->cur_dbg_grp) ++ *grp = idx; ++ else ++ *grp = ADC_GRP_SKIP_MAGIC; ++ ++ dev_dbg(rk3308->plat_dev, ++ "ADC_TYPE_DBG, idx: %d, get grp: %d\n", ++ idx, *grp); ++ } else { ++ if (idx >= 1) ++ return false; ++ ++ *grp = rk3308->loopback_grp; ++ dev_dbg(rk3308->plat_dev, ++ "ADC_TYPE_LOOPBACK, idx: %d, get grp: %d\n", ++ idx, *grp); ++ } + +- /* Step 15 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, +- RK3308_DAC_BUF_REF_L_EN | RK3308_DAC_BUF_REF_R_EN, +- RK3308_DAC_BUF_REF_L_DIS | RK3308_DAC_BUF_REF_R_DIS); ++ return true; ++} + +- /* Step 16 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, +- RK3308_DAC_CURRENT_EN, +- RK3308_DAC_CURRENT_DIS); ++static int rk3308_codec_get_dac_path_state(struct rk3308_codec_priv *rk3308) ++{ ++ return rk3308->dac_path_state; ++} + +- /* Step 17 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, +- RK3308_DAC_L_HPOUT_WORK | RK3308_DAC_R_HPOUT_WORK, +- RK3308_DAC_L_HPOUT_INIT | RK3308_DAC_R_HPOUT_INIT); ++static void rk3308_codec_set_dac_path_state(struct rk3308_codec_priv *rk3308, ++ int state) ++{ ++ rk3308->dac_path_state = state; ++} + +- /* Step 18 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, +- RK3308_DAC_L_HPMIX_WORK | RK3308_DAC_R_HPMIX_WORK, +- RK3308_DAC_L_HPMIX_INIT | RK3308_DAC_R_HPMIX_INIT); ++static void rk3308_headphone_ctl(struct rk3308_codec_priv *rk3308, int on) ++{ ++ if (rk3308->hp_ctl_gpio) ++ gpiod_direction_output(rk3308->hp_ctl_gpio, on); ++} + +- /* Step 19 */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, +- RK3308_DAC_L_HPMIX_GAIN_MSK | +- RK3308_DAC_R_HPMIX_GAIN_MSK, +- RK3308_DAC_L_HPMIX_GAIN_NDB_6 | +- RK3308_DAC_R_HPMIX_GAIN_NDB_6); ++static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on) ++{ ++ if (on) { ++ if (rk3308->pa_drv_gpio) { ++ gpiod_direction_output(rk3308->pa_drv_gpio, on); ++ msleep(rk3308->delay_pa_drv_ms); ++ } + +- /* +- * Note2. If the ACODEC_DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3] +- * is set to 0x1, add the steps from the section Disable DAC +- * Configuration Standard Usage Flow after complete the step 19 +- */ ++ if (rk3308->spk_ctl_gpio) ++ gpiod_direction_output(rk3308->spk_ctl_gpio, on); ++ } else { ++ if (rk3308->spk_ctl_gpio) ++ gpiod_direction_output(rk3308->spk_ctl_gpio, on); + +- return 0; ++ if (rk3308->pa_drv_gpio) { ++ msleep(rk3308->delay_pa_drv_ms); ++ gpiod_direction_output(rk3308->pa_drv_gpio, on); ++ } ++ } + } + +-static int rk3308_codec_power_on(struct snd_soc_codec *codec) ++static int rk3308_codec_reset(struct snd_soc_codec *codec) + { + struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); + +- /* 1. Supply the power of digital part and reset the Audio Codec */ +- /* Do nothing */ ++ reset_control_assert(rk3308->reset); ++ usleep_range(2000, 2500); /* estimated value */ ++ reset_control_deassert(rk3308->reset); + +- /* +- * 2. Configure ACODEC_DAC_ANA_CON1[1:0] and ACODEC_DAC_ANA_CON1[5:4] +- * to 0x1, to setup dc voltage of the DAC channel output +- */ +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, +- RK3308_DAC_POP_SOUND_L_MSK, RK3308_DAC_POP_SOUND_L_INIT); +- regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, +- RK3308_DAC_POP_SOUND_R_MSK, RK3308_DAC_POP_SOUND_R_INIT); ++ regmap_write(rk3308->regmap, RK3308_GLB_CON, 0x00); ++ usleep_range(200, 300); /* estimated value */ ++ regmap_write(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_SYS_WORK | ++ RK3308_DAC_DIG_WORK | ++ RK3308_ADC_DIG_WORK); + +- /* +- * 3. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 0x1 +- * +- * Note: Only the reg (ADC_ANA_CON10+0x0)[6:0] represent the control +- * signal to select current to pre-charge/dis_charge +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), +- RK3308_ADC_CURRENT_CHARGE_MSK, RK3308_ADC_SEL_I_64(1)); ++ return 0; ++} + +- /* 4. Supply the power of the analog part(AVDD,AVDDRV) */ ++static int rk3308_codec_adc_dig_reset(struct rk3308_codec_priv *rk3308) ++{ ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_ADC_DIG_WORK, ++ RK3308_ADC_DIG_RESET); ++ udelay(50); ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_ADC_DIG_WORK, ++ RK3308_ADC_DIG_WORK); + +- /* +- * 5. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x1 to setup +- * reference voltage +- * +- * Note: Only the reg (ADC_ANA_CON10+0x0)[7] represent the enable +- * signal of reference voltage module +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), +- RK3308_ADC_REF_EN, RK3308_ADC_REF_EN); ++ return 0; ++} + +- /* +- * 6. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to +- * 0x7f step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to +- * 0x7f directly. The suggestion slot time of the step is 20ms. +- */ +- mdelay(20); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), +- RK3308_ADC_CURRENT_CHARGE_MSK, +- RK3308_ADC_DONT_SEL_ALL); ++static int rk3308_codec_dac_dig_reset(struct rk3308_codec_priv *rk3308) ++{ ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_DAC_DIG_WORK, ++ RK3308_DAC_DIG_RESET); ++ udelay(50); ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_DAC_DIG_WORK, ++ RK3308_DAC_DIG_WORK); + +- /* 7. Wait until the voltage of VCM keeps stable at the AVDD/2 */ +- usleep_range(200, 300); /* estimated value */ ++ return 0; ++} + +- /* +- * 8. Configure the register ACODEC_ADC_ANA_CON10[6:0] to the +- * appropriate value(expect 0x0) for reducing power. +- */ ++static int rk3308_set_bias_level(struct snd_soc_codec *codec, ++ enum snd_soc_bias_level level) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); + +- /* TODO: choose an appropriate charge value */ ++ switch (level) { ++ case SND_SOC_BIAS_ON: ++ break; ++ case SND_SOC_BIAS_PREPARE: ++ break; ++ case SND_SOC_BIAS_STANDBY: ++ regcache_cache_only(rk3308->regmap, false); ++ regcache_sync(rk3308->regmap); ++ break; ++ case SND_SOC_BIAS_OFF: ++ break; ++ } + + return 0; + } + +-static int rk3308_codec_power_off(struct snd_soc_codec *codec) ++static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai, ++ unsigned int fmt) + { ++ struct snd_soc_codec *codec = codec_dai->codec; + struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0; ++ int idx, grp, is_master; ++ int type = ADC_TYPE_ALL; ++ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBS_CFS: ++ adc_aif2 |= RK3308_ADC_IO_MODE_SLAVE; ++ adc_aif2 |= RK3308_ADC_MODE_SLAVE; ++ dac_aif2 |= RK3308_DAC_IO_MODE_SLAVE; ++ dac_aif2 |= RK3308_DAC_MODE_SLAVE; ++ is_master = 0; ++ break; ++ case SND_SOC_DAIFMT_CBM_CFM: ++ adc_aif2 |= RK3308_ADC_IO_MODE_MASTER; ++ adc_aif2 |= RK3308_ADC_MODE_MASTER; ++ dac_aif2 |= RK3308_DAC_IO_MODE_MASTER; ++ dac_aif2 |= RK3308_DAC_MODE_MASTER; ++ is_master = 1; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_DSP_A: ++ adc_aif1 |= RK3308_ADC_I2S_MODE_PCM; ++ dac_aif1 |= RK3308_DAC_I2S_MODE_PCM; ++ break; ++ case SND_SOC_DAIFMT_I2S: ++ adc_aif1 |= RK3308_ADC_I2S_MODE_I2S; ++ dac_aif1 |= RK3308_DAC_I2S_MODE_I2S; ++ break; ++ case SND_SOC_DAIFMT_RIGHT_J: ++ adc_aif1 |= RK3308_ADC_I2S_MODE_RJ; ++ dac_aif1 |= RK3308_DAC_I2S_MODE_RJ; ++ break; ++ case SND_SOC_DAIFMT_LEFT_J: ++ adc_aif1 |= RK3308_ADC_I2S_MODE_LJ; ++ dac_aif1 |= RK3308_DAC_I2S_MODE_LJ; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL; ++ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL; ++ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL; ++ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; ++ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; ++ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; ++ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; ++ break; ++ case SND_SOC_DAIFMT_IB_NF: ++ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_NORMAL; ++ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL; ++ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_NORMAL; ++ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL; ++ break; ++ case SND_SOC_DAIFMT_NB_IF: ++ adc_aif1 |= RK3308_ADC_I2S_LRC_POL_REVERSAL; ++ adc_aif2 |= RK3308_ADC_I2S_BIT_CLK_POL_NORMAL; ++ dac_aif1 |= RK3308_DAC_I2S_LRC_POL_REVERSAL; ++ dac_aif2 |= RK3308_DAC_I2S_BIT_CLK_POL_NORMAL; ++ break; ++ default: ++ return -EINVAL; ++ } + + /* +- * 1. Keep the power on and disable the DAC and ADC path according to +- * the section power on configuration standard usage flow. ++ * Hold ADC Digital registers start at master mode ++ * ++ * There are 8 ADCs and use the same SCLK and LRCK internal for master ++ * mode, We need to make sure that they are in effect at the same time, ++ * otherwise they will cause the abnormal clocks. + */ ++ if (is_master) ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_ADC_DIG_WORK, ++ RK3308_ADC_DIG_RESET); ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp), ++ RK3308_ADC_I2S_LRC_POL_MSK | ++ RK3308_ADC_I2S_MODE_MSK, ++ adc_aif1); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp), ++ RK3308_ADC_IO_MODE_MSK | ++ RK3308_ADC_MODE_MSK | ++ RK3308_ADC_I2S_BIT_CLK_POL_MSK, ++ adc_aif2); ++ } + +- /* 2. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 0x1 */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), +- RK3308_ADC_CURRENT_CHARGE_MSK, RK3308_ADC_SEL_I_64(1)); ++ /* Hold ADC Digital registers end at master mode */ ++ if (is_master) ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_ADC_DIG_WORK, ++ RK3308_ADC_DIG_WORK); + +- /* 3. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x0 */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), +- RK3308_ADC_REF_EN, RK3308_ADC_REF_DIS); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, ++ RK3308_DAC_I2S_LRC_POL_MSK | ++ RK3308_DAC_I2S_MODE_MSK, ++ dac_aif1); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, ++ RK3308_DAC_IO_MODE_MSK | ++ RK3308_DAC_MODE_MSK | ++ RK3308_DAC_I2S_BIT_CLK_POL_MSK, ++ dac_aif2); ++ ++ return 0; ++} ++ ++static int rk3308_codec_dac_dig_config(struct rk3308_codec_priv *rk3308, ++ struct snd_pcm_hw_params *params) ++{ ++ unsigned int dac_aif1 = 0, dac_aif2 = 0; ++ ++ /* Clear the status of DAC DIG Digital reigisters */ ++ rk3308_codec_dac_dig_reset(rk3308); ++ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_16BITS; ++ break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_20BITS; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_24BITS; ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: ++ dac_aif1 |= RK3308_DAC_I2S_VALID_LEN_32BITS; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ dac_aif1 |= RK3308_DAC_I2S_LR_NORMAL; ++ dac_aif2 |= RK3308_DAC_I2S_WORK; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON01, ++ RK3308_DAC_I2S_VALID_LEN_MSK | ++ RK3308_DAC_I2S_LR_MSK, ++ dac_aif1); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_DIG_CON02, ++ RK3308_DAC_I2S_MSK, ++ dac_aif2); ++ ++ return 0; ++} ++ ++static int rk3308_codec_adc_dig_config(struct rk3308_codec_priv *rk3308, ++ struct snd_pcm_hw_params *params) ++{ ++ unsigned int adc_aif1 = 0, adc_aif2 = 0; ++ int type = ADC_TYPE_NORMAL; ++ int idx, grp; ++ ++ /* Clear the status of ADC DIG Digital reigisters */ ++ rk3308_codec_adc_dig_reset(rk3308); ++ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_16BITS; ++ break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_20BITS; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_24BITS; ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: ++ adc_aif1 |= RK3308_ADC_I2S_VALID_LEN_32BITS; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (params_channels(params)) { ++ case 1: ++ adc_aif1 |= RK3308_ADC_I2S_MONO; ++ break; ++ case 2: ++ case 4: ++ case 6: ++ case 8: ++ adc_aif1 |= RK3308_ADC_I2S_STEREO; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ adc_aif1 |= RK3308_ADC_I2S_LR_NORMAL; ++ adc_aif2 |= RK3308_ADC_I2S_WORK; ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON01(grp), ++ RK3308_ADC_I2S_VALID_LEN_MSK | ++ RK3308_ADC_I2S_LR_MSK | ++ RK3308_ADC_I2S_TYPE_MSK, ++ adc_aif1); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON02(grp), ++ RK3308_ADC_I2S_MSK, ++ adc_aif2); ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_update_adc_grps(struct rk3308_codec_priv *rk3308, ++ struct snd_pcm_hw_params *params) ++{ ++ switch (params_channels(params)) { ++ case 1: ++ rk3308->used_adc_grps = 1; ++ break; ++ case 2: ++ case 4: ++ case 6: ++ case 8: ++ rk3308->used_adc_grps = params_channels(params) / 2; ++ break; ++ default: ++ dev_err(rk3308->plat_dev, "Invalid channels: %d\n", ++ params_channels(params)); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rk3308_mute_stream(struct snd_soc_dai *dai, int mute, int stream) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ if (stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ int dgain; ++ ++ if (mute) { ++ for (dgain = 0x2; dgain <= 0x7; dgain++) { ++ /* ++ * Keep the max -> min digital CIC interpolation ++ * filter gain step by step. ++ * ++ * loud: 0x2; whisper: 0x7 ++ */ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_DAC_DIG_CON04, ++ RK3308_DAC_CIC_IF_GAIN_MSK, ++ dgain); ++ usleep_range(200, 300); /* estimated value */ ++ } ++ ++#if !DEBUG_POP_ALWAYS ++ rk3308_headphone_ctl(rk3308, 0); ++ rk3308_speaker_ctl(rk3308, 0); ++#endif ++ } else { ++#if !DEBUG_POP_ALWAYS ++ if (rk3308->dac_output == DAC_LINEOUT) ++ rk3308_speaker_ctl(rk3308, 1); ++ else if (rk3308->dac_output == DAC_HPOUT) ++ rk3308_headphone_ctl(rk3308, 1); ++ ++ if (rk3308->delay_start_play_ms) ++ msleep(rk3308->delay_start_play_ms); ++#endif ++ for (dgain = 0x7; dgain >= 0x2; dgain--) { ++ /* ++ * Keep the min -> max digital CIC interpolation ++ * filter gain step by step ++ * ++ * loud: 0x2; whisper: 0x7 ++ */ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_DAC_DIG_CON04, ++ RK3308_DAC_CIC_IF_GAIN_MSK, ++ dgain); ++ usleep_range(200, 300); /* estimated value */ ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_digital_fadein(struct rk3308_codec_priv *rk3308) ++{ ++ unsigned int dgain, dgain_ref; ++ ++ if (rk3308->hpout_l_dgain != rk3308->hpout_r_dgain) { ++ pr_warn("HPOUT l_dgain: 0x%x != r_dgain: 0x%x\n", ++ rk3308->hpout_l_dgain, rk3308->hpout_r_dgain); ++ dgain_ref = min(rk3308->hpout_l_dgain, rk3308->hpout_r_dgain); ++ } else { ++ dgain_ref = rk3308->hpout_l_dgain; ++ } + + /* +- * 4.Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to 0x7f +- * step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to 0x7f +- * directly. The suggestion slot time of the step is 20ms ++ * We'd better change the gain of the left and right channels ++ * at the same time to avoid different listening + */ +- mdelay(20); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), +- RK3308_ADC_CURRENT_CHARGE_MSK, +- RK3308_ADC_DONT_SEL_ALL); ++ for (dgain = RK3308_DAC_L_HPOUT_GAIN_NDB_39; ++ dgain <= dgain_ref; dgain++) { ++ /* Step 02 decrease dgains for de-pop */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, ++ RK3308_DAC_L_HPOUT_GAIN_MSK, ++ dgain); ++ ++ /* Step 02 decrease dgains for de-pop */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, ++ RK3308_DAC_R_HPOUT_GAIN_MSK, ++ dgain); ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_digital_fadeout(struct rk3308_codec_priv *rk3308) ++{ ++ unsigned int l_dgain, r_dgain; ++ ++ /* ++ * Note. In the step2, adjusting the register step by step to ++ * the appropriate value and taking 20ms as time step ++ */ ++ regmap_read(rk3308->regmap, RK3308_DAC_ANA_CON05, &l_dgain); ++ l_dgain &= RK3308_DAC_L_HPOUT_GAIN_MSK; ++ ++ regmap_read(rk3308->regmap, RK3308_DAC_ANA_CON06, &r_dgain); ++ r_dgain &= RK3308_DAC_R_HPOUT_GAIN_MSK; ++ ++ if (l_dgain != r_dgain) { ++ pr_warn("HPOUT l_dgain: 0x%x != r_dgain: 0x%x\n", ++ l_dgain, r_dgain); ++ l_dgain = min(l_dgain, r_dgain); ++ } ++ ++ /* ++ * We'd better change the gain of the left and right channels ++ * at the same time to avoid different listening ++ */ ++ while (l_dgain >= RK3308_DAC_L_HPOUT_GAIN_NDB_39) { ++ /* Step 02 decrease dgains for de-pop */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, ++ RK3308_DAC_L_HPOUT_GAIN_MSK, ++ l_dgain); ++ ++ /* Step 02 decrease dgains for de-pop */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, ++ RK3308_DAC_R_HPOUT_GAIN_MSK, ++ l_dgain); ++ ++ usleep_range(200, 300); /* estimated value */ ++ ++ if (l_dgain == RK3308_DAC_L_HPOUT_GAIN_NDB_39) ++ break; ++ ++ l_dgain--; ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_dac_lineout_enable(struct rk3308_codec_priv *rk3308) ++{ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* Step 04 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, ++ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | ++ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_L_SEL_DC_FROM_INTERNAL | ++ RK3308_DAC_R_SEL_DC_FROM_INTERNAL); ++ } ++ ++ /* Step 07 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_EN | ++ RK3308_DAC_R_LINEOUT_EN, ++ RK3308_DAC_L_LINEOUT_EN | ++ RK3308_DAC_R_LINEOUT_EN); ++ ++ udelay(20); ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* Step 10 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, ++ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | ++ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL | ++ RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL); ++ ++ udelay(20); ++ } ++ ++ /* Step 19 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_UNMUTE | ++ RK3308_DAC_R_LINEOUT_UNMUTE, ++ RK3308_DAC_L_LINEOUT_UNMUTE | ++ RK3308_DAC_R_LINEOUT_UNMUTE); ++ udelay(20); ++ ++ return 0; ++} ++ ++static int rk3308_codec_dac_lineout_disable(struct rk3308_codec_priv *rk3308) ++{ ++ /* Step 08 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_UNMUTE | ++ RK3308_DAC_R_LINEOUT_UNMUTE, ++ RK3308_DAC_L_LINEOUT_MUTE | ++ RK3308_DAC_R_LINEOUT_MUTE); ++ ++ /* Step 09 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_EN | ++ RK3308_DAC_R_LINEOUT_EN, ++ RK3308_DAC_L_LINEOUT_DIS | ++ RK3308_DAC_R_LINEOUT_DIS); ++ ++ return 0; ++} ++ ++static int rk3308_codec_dac_hpout_enable(struct rk3308_codec_priv *rk3308) ++{ ++ /* Step 03 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_HPOUT_POP_SOUND_L_MSK | ++ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_HPOUT_POP_SOUND_L_WORK | ++ RK3308_DAC_HPOUT_POP_SOUND_R_WORK); ++ ++ udelay(20); ++ ++ /* Step 07 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_EN | ++ RK3308_DAC_R_HPOUT_EN, ++ RK3308_DAC_L_HPOUT_EN | ++ RK3308_DAC_R_HPOUT_EN); ++ ++ udelay(20); ++ ++ /* Step 08 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_WORK | ++ RK3308_DAC_R_HPOUT_WORK, ++ RK3308_DAC_L_HPOUT_WORK | ++ RK3308_DAC_R_HPOUT_WORK); ++ ++ udelay(20); ++ ++ /* Step 16 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_UNMUTE | ++ RK3308_DAC_R_HPOUT_UNMUTE, ++ RK3308_DAC_L_HPOUT_UNMUTE | ++ RK3308_DAC_R_HPOUT_UNMUTE); ++ ++ udelay(20); ++ ++ return 0; ++} ++ ++static int rk3308_codec_dac_hpout_disable(struct rk3308_codec_priv *rk3308) ++{ ++ /* Step 03 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_HPOUT_POP_SOUND_L_MSK | ++ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_HPOUT_POP_SOUND_L_INIT | ++ RK3308_DAC_HPOUT_POP_SOUND_R_INIT); ++ ++ /* Step 07 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_EN | ++ RK3308_DAC_R_HPOUT_EN, ++ RK3308_DAC_L_HPOUT_DIS | ++ RK3308_DAC_R_HPOUT_DIS); ++ ++ /* Step 08 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_WORK | ++ RK3308_DAC_R_HPOUT_WORK, ++ RK3308_DAC_L_HPOUT_INIT | ++ RK3308_DAC_R_HPOUT_INIT); ++ ++ /* Step 16 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_UNMUTE | ++ RK3308_DAC_R_HPOUT_UNMUTE, ++ RK3308_DAC_L_HPOUT_MUTE | ++ RK3308_DAC_R_HPOUT_MUTE); ++ ++ return 0; ++} ++ ++static int rk3308_codec_dac_switch(struct rk3308_codec_priv *rk3308, ++ int dac_output) ++{ int ret = 0; ++ ++ if (rk3308->dac_output == dac_output) { ++ dev_info(rk3308->plat_dev, ++ "Don't need to change dac_output: %d\n", dac_output); ++ goto out; ++ } ++ ++ switch (dac_output) { ++ case DAC_LINEOUT: ++ case DAC_HPOUT: ++ case DAC_LINEOUT_HPOUT: ++ break; ++ default: ++ dev_err(rk3308->plat_dev, "Unknown value: %d\n", dac_output); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (rk3308_codec_get_dac_path_state(rk3308) == PATH_BUSY) { ++ /* ++ * We can only switch the audio path to LINEOUT or HPOUT on ++ * codec during playbacking, otherwise, just update the ++ * dac_output flag. ++ */ ++ switch (dac_output) { ++ case DAC_LINEOUT: ++ rk3308_headphone_ctl(rk3308, 0); ++ rk3308_speaker_ctl(rk3308, 1); ++ rk3308_codec_dac_hpout_disable(rk3308); ++ rk3308_codec_dac_lineout_enable(rk3308); ++ break; ++ case DAC_HPOUT: ++ rk3308_speaker_ctl(rk3308, 0); ++ rk3308_headphone_ctl(rk3308, 1); ++ rk3308_codec_dac_lineout_disable(rk3308); ++ rk3308_codec_dac_hpout_enable(rk3308); ++ break; ++ case DAC_LINEOUT_HPOUT: ++ rk3308_speaker_ctl(rk3308, 1); ++ rk3308_headphone_ctl(rk3308, 1); ++ rk3308_codec_dac_lineout_enable(rk3308); ++ rk3308_codec_dac_hpout_enable(rk3308); ++ break; ++ default: ++ break; ++ } ++ } ++ ++ rk3308->dac_output = dac_output; ++out: ++ dev_dbg(rk3308->plat_dev, "switch dac_output to: %d\n", ++ rk3308->dac_output); ++ ++ return ret; ++} ++ ++static int rk3308_codec_dac_enable(struct rk3308_codec_priv *rk3308) ++{ ++ /* ++ * Note1. If the ACODEC_DAC_ANA_CON12[6] or ACODEC_DAC_ANA_CON12[2] ++ * is set to 0x1, ignoring the step9~12. ++ */ ++ ++ /* ++ * Note2. If the ACODEC_ DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3] ++ * is set to 0x1, the ADC0 or ADC1 should be enabled firstly, and ++ * please refer to Enable ADC Configuration Standard Usage Flow(expect ++ * step7~step9,step14). ++ */ ++ ++ /* ++ * Note3. If no opening the line out, ignoring the step6, step17 and ++ * step19. ++ */ ++ ++ /* ++ * Note4. If no opening the headphone out, ignoring the step3,step7~8, ++ * step16 and step18. ++ */ ++ ++ /* ++ * Note5. In the step18, adjust the register step by step to the ++ * appropriate value and taking 10ms as one time step ++ */ ++ ++ /* ++ * 1. Set the ACODEC_DAC_ANA_CON0[0] to 0x1, to enable the current ++ * source of DAC ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, ++ RK3308_DAC_CURRENT_MSK, ++ RK3308_DAC_CURRENT_EN); ++ ++ udelay(20); ++ ++ /* ++ * 2. Set the ACODEC_DAC_ANA_CON1[6] and ACODEC_DAC_ANA_CON1[2] to 0x1, ++ * to enable the reference voltage buffer ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_BUF_REF_L_MSK | ++ RK3308_DAC_BUF_REF_R_MSK, ++ RK3308_DAC_BUF_REF_L_EN | ++ RK3308_DAC_BUF_REF_R_EN); ++ ++ /* Waiting the stable reference voltage */ ++ mdelay(1); ++ ++ if (rk3308->dac_output == DAC_HPOUT || ++ rk3308->dac_output == DAC_LINEOUT_HPOUT) { ++ /* Step 03 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_HPOUT_POP_SOUND_L_MSK | ++ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_HPOUT_POP_SOUND_L_WORK | ++ RK3308_DAC_HPOUT_POP_SOUND_R_WORK); ++ ++ udelay(20); ++ } ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B && ++ (rk3308->dac_output == DAC_LINEOUT || ++ rk3308->dac_output == DAC_LINEOUT_HPOUT)) { ++ /* Step 04 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, ++ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | ++ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_L_SEL_DC_FROM_INTERNAL | ++ RK3308_DAC_R_SEL_DC_FROM_INTERNAL); ++ ++ udelay(20); ++ } ++ ++ /* Step 05 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_EN | ++ RK3308_DAC_R_HPMIX_EN, ++ RK3308_DAC_L_HPMIX_EN | ++ RK3308_DAC_R_HPMIX_EN); ++ ++ /* Waiting the stable HPMIX */ ++ mdelay(1); ++ ++ /* Step 06. Reset HPMIX and recover HPMIX gains */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_WORK | ++ RK3308_DAC_R_HPMIX_WORK, ++ RK3308_DAC_L_HPMIX_INIT | ++ RK3308_DAC_R_HPMIX_INIT); ++ udelay(50); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_WORK | ++ RK3308_DAC_R_HPMIX_WORK, ++ RK3308_DAC_L_HPMIX_WORK | ++ RK3308_DAC_R_HPMIX_WORK); ++ ++ udelay(20); ++ ++ if (rk3308->dac_output == DAC_LINEOUT || ++ rk3308->dac_output == DAC_LINEOUT_HPOUT) { ++ /* Step 07 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_EN | ++ RK3308_DAC_R_LINEOUT_EN, ++ RK3308_DAC_L_LINEOUT_EN | ++ RK3308_DAC_R_LINEOUT_EN); ++ ++ udelay(20); ++ } ++ ++ if (rk3308->dac_output == DAC_HPOUT || ++ rk3308->dac_output == DAC_LINEOUT_HPOUT) { ++ /* Step 08 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_EN | ++ RK3308_DAC_R_HPOUT_EN, ++ RK3308_DAC_L_HPOUT_EN | ++ RK3308_DAC_R_HPOUT_EN); ++ ++ udelay(20); ++ ++ /* Step 09 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_WORK | ++ RK3308_DAC_R_HPOUT_WORK, ++ RK3308_DAC_L_HPOUT_WORK | ++ RK3308_DAC_R_HPOUT_WORK); ++ ++ udelay(20); ++ } ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* Step 10 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, ++ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | ++ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL | ++ RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL); ++ ++ udelay(20); ++ } ++ ++ /* Step 11 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_REF_EN | ++ RK3308_DAC_R_REF_EN, ++ RK3308_DAC_L_REF_EN | ++ RK3308_DAC_R_REF_EN); ++ ++ udelay(20); ++ ++ /* Step 12 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_CLK_EN | ++ RK3308_DAC_R_CLK_EN, ++ RK3308_DAC_L_CLK_EN | ++ RK3308_DAC_R_CLK_EN); ++ ++ udelay(20); ++ ++ /* Step 13 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_DAC_EN | ++ RK3308_DAC_R_DAC_EN, ++ RK3308_DAC_L_DAC_EN | ++ RK3308_DAC_R_DAC_EN); ++ ++ udelay(20); ++ ++ /* Step 14 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_DAC_WORK | ++ RK3308_DAC_R_DAC_WORK, ++ RK3308_DAC_L_DAC_WORK | ++ RK3308_DAC_R_DAC_WORK); ++ ++ udelay(20); ++ ++ /* Step 15 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, ++ RK3308_DAC_L_HPMIX_SEL_MSK | ++ RK3308_DAC_R_HPMIX_SEL_MSK, ++ RK3308_DAC_L_HPMIX_I2S | ++ RK3308_DAC_R_HPMIX_I2S); ++ ++ udelay(20); ++ ++ /* Step 16 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_UNMUTE | ++ RK3308_DAC_R_HPMIX_UNMUTE, ++ RK3308_DAC_L_HPMIX_UNMUTE | ++ RK3308_DAC_R_HPMIX_UNMUTE); ++ ++ udelay(20); ++ ++ /* Step 17: Put configuration HPMIX Gain to DAPM */ ++ ++ if (rk3308->dac_output == DAC_HPOUT || ++ rk3308->dac_output == DAC_LINEOUT_HPOUT) { ++ /* Step 18 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_UNMUTE | ++ RK3308_DAC_R_HPOUT_UNMUTE, ++ RK3308_DAC_L_HPOUT_UNMUTE | ++ RK3308_DAC_R_HPOUT_UNMUTE); ++ ++ udelay(20); ++ } ++ ++ if (rk3308->dac_output == DAC_LINEOUT || ++ rk3308->dac_output == DAC_LINEOUT_HPOUT) { ++ /* Step 19 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_UNMUTE | ++ RK3308_DAC_R_LINEOUT_UNMUTE, ++ RK3308_DAC_L_LINEOUT_UNMUTE | ++ RK3308_DAC_R_LINEOUT_UNMUTE); ++ udelay(20); ++ } ++ ++ /* Step 20, put configuration HPOUT gain to DAPM control */ ++ /* Step 21, put configuration LINEOUT gain to DAPM control */ ++ ++ if (rk3308->dac_output == DAC_HPOUT || ++ rk3308->dac_output == DAC_LINEOUT_HPOUT) { ++ /* Just for HPOUT */ ++ rk3308_codec_digital_fadein(rk3308); ++ } ++ ++ rk3308->dac_endisable = true; ++ ++ /* TODO: TRY TO TEST DRIVE STRENGTH */ ++ ++ return 0; ++} ++ ++static int rk3308_codec_dac_disable(struct rk3308_codec_priv *rk3308) ++{ ++ /* ++ * Step 00 skipped. Keep the DAC channel work and input the mute signal. ++ */ ++ ++ /* Step 01 skipped. May set the min gain for LINEOUT. */ ++ ++ /* Step 02 skipped. May set the min gain for HPOUT. */ ++ ++ if (rk3308->dac_output == DAC_HPOUT || ++ rk3308->dac_output == DAC_LINEOUT_HPOUT) { ++ /* Just for HPOUT */ ++ rk3308_codec_digital_fadeout(rk3308); ++ } ++ ++ /* Step 03 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_UNMUTE | ++ RK3308_DAC_R_HPMIX_UNMUTE, ++ RK3308_DAC_L_HPMIX_UNMUTE | ++ RK3308_DAC_R_HPMIX_UNMUTE); ++ ++ /* Step 04 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, ++ RK3308_DAC_L_HPMIX_SEL_MSK | ++ RK3308_DAC_R_HPMIX_SEL_MSK, ++ RK3308_DAC_L_HPMIX_NONE | ++ RK3308_DAC_R_HPMIX_NONE); ++ /* Step 05 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_UNMUTE | ++ RK3308_DAC_R_HPOUT_UNMUTE, ++ RK3308_DAC_L_HPOUT_MUTE | ++ RK3308_DAC_R_HPOUT_MUTE); ++ ++ /* Step 06 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_DAC_WORK | ++ RK3308_DAC_R_DAC_WORK, ++ RK3308_DAC_L_DAC_INIT | ++ RK3308_DAC_R_DAC_INIT); ++ ++ /* Step 07 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_EN | ++ RK3308_DAC_R_HPOUT_EN, ++ RK3308_DAC_L_HPOUT_DIS | ++ RK3308_DAC_R_HPOUT_DIS); ++ ++ /* Step 08 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_UNMUTE | ++ RK3308_DAC_R_LINEOUT_UNMUTE, ++ RK3308_DAC_L_LINEOUT_MUTE | ++ RK3308_DAC_R_LINEOUT_MUTE); ++ ++ /* Step 09 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_EN | ++ RK3308_DAC_R_LINEOUT_EN, ++ RK3308_DAC_L_LINEOUT_DIS | ++ RK3308_DAC_R_LINEOUT_DIS); ++ ++ /* Step 10 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_EN | ++ RK3308_DAC_R_HPMIX_EN, ++ RK3308_DAC_L_HPMIX_DIS | ++ RK3308_DAC_R_HPMIX_DIS); ++ ++ /* Step 11 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_DAC_EN | ++ RK3308_DAC_R_DAC_EN, ++ RK3308_DAC_L_DAC_DIS | ++ RK3308_DAC_R_DAC_DIS); ++ ++ /* Step 12 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_CLK_EN | ++ RK3308_DAC_R_CLK_EN, ++ RK3308_DAC_L_CLK_DIS | ++ RK3308_DAC_R_CLK_DIS); ++ ++ /* Step 13 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON02, ++ RK3308_DAC_L_REF_EN | ++ RK3308_DAC_R_REF_EN, ++ RK3308_DAC_L_REF_DIS | ++ RK3308_DAC_R_REF_DIS); ++ ++ /* Step 14 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_HPOUT_POP_SOUND_L_MSK | ++ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_HPOUT_POP_SOUND_L_INIT | ++ RK3308_DAC_HPOUT_POP_SOUND_R_INIT); ++ ++ /* Step 15 */ ++ if (rk3308->codec_ver == ACODEC_VERSION_B && ++ (rk3308->dac_output == DAC_LINEOUT || ++ rk3308->dac_output == DAC_LINEOUT_HPOUT)) { ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, ++ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK | ++ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_L_SEL_DC_FROM_VCM | ++ RK3308_DAC_R_SEL_DC_FROM_VCM); ++ } ++ ++ /* Step 16 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_BUF_REF_L_EN | ++ RK3308_DAC_BUF_REF_R_EN, ++ RK3308_DAC_BUF_REF_L_DIS | ++ RK3308_DAC_BUF_REF_R_DIS); ++ ++ /* Step 17 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, ++ RK3308_DAC_CURRENT_EN, ++ RK3308_DAC_CURRENT_DIS); ++ ++ /* Step 18 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON03, ++ RK3308_DAC_L_HPOUT_WORK | ++ RK3308_DAC_R_HPOUT_WORK, ++ RK3308_DAC_L_HPOUT_INIT | ++ RK3308_DAC_R_HPOUT_INIT); ++ ++ /* Step 19 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON13, ++ RK3308_DAC_L_HPMIX_WORK | ++ RK3308_DAC_R_HPMIX_WORK, ++ RK3308_DAC_L_HPMIX_WORK | ++ RK3308_DAC_R_HPMIX_WORK); ++ ++ /* Step 20 skipped, may set the min gain for HPOUT. */ ++ ++ /* ++ * Note2. If the ACODEC_DAC_ANA_CON12[7] or ACODEC_DAC_ANA_CON12[3] ++ * is set to 0x1, add the steps from the section Disable ADC ++ * Configuration Standard Usage Flow after complete the step 19 ++ * ++ * IF USING LINE-IN ++ * rk3308_codec_adc_ana_disable(rk3308, type); ++ */ ++ ++ rk3308->dac_endisable = false; ++ ++ return 0; ++} ++ ++static int rk3308_codec_power_on(struct rk3308_codec_priv *rk3308) ++{ ++ unsigned int v; ++ ++ /* 0. Supply the power of digital part and reset the Audio Codec */ ++ /* Do nothing */ ++ ++ /* ++ * 1. Configure ACODEC_DAC_ANA_CON1[1:0] and ACODEC_DAC_ANA_CON1[5:4] ++ * to 0x1, to setup dc voltage of the DAC channel output. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_HPOUT_POP_SOUND_L_MSK, ++ RK3308_DAC_HPOUT_POP_SOUND_L_INIT); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON01, ++ RK3308_DAC_HPOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_HPOUT_POP_SOUND_R_INIT); ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* ++ * 2. Configure ACODEC_DAC_ANA_CON15[1:0] and ++ * ACODEC_DAC_ANA_CON15[5:4] to 0x1, to setup dc voltage of ++ * the DAC channel output. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, ++ RK3308_DAC_LINEOUT_POP_SOUND_L_MSK, ++ RK3308_DAC_L_SEL_DC_FROM_VCM); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON15, ++ RK3308_DAC_LINEOUT_POP_SOUND_R_MSK, ++ RK3308_DAC_R_SEL_DC_FROM_VCM); ++ } ++ ++ /* ++ * 3. Configure the register ACODEC_ADC_ANA_CON10[3:0] to 7’b000_0001. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, ++ RK3308_ADC_SEL_I(0x1)); ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* ++ * 4. Configure the register ACODEC_ADC_ANA_CON14[3:0] to ++ * 4’b0001. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, ++ RK3308_DAC_CURRENT_CHARGE_MSK, ++ RK3308_DAC_SEL_I(0x1)); ++ } ++ ++ /* 5. Supply the power of the analog part(AVDD,AVDDRV) */ ++ ++ /* ++ * 6. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x1 to setup ++ * reference voltage ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_REF_EN, RK3308_ADC_REF_EN); ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* ++ * 7. Configure the register ACODEC_ADC_ANA_CON14[4] to 0x1 to ++ * setup reference voltage ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, ++ RK3308_DAC_VCM_LINEOUT_EN, ++ RK3308_DAC_VCM_LINEOUT_EN); ++ } ++ ++ /* ++ * 8. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to ++ * 0x7f step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to ++ * 0x7f directly. Here the slot time of the step is 200us. ++ */ ++ for (v = 0x1; v <= 0x7f; v++) { ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, ++ v); ++ udelay(200); ++ } ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* ++ * 9. Change the register ACODEC_ADC_ANA_CON14[3:0] from the 0x1 ++ * to 0xf step by step or configure the ++ * ACODEC_ADC_ANA_CON14[3:0] to 0xf directly. Here the slot ++ * time of the step is 200us. ++ */ ++ for (v = 0x1; v <= 0xf; v++) { ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, ++ RK3308_DAC_CURRENT_CHARGE_MSK, ++ v); ++ udelay(200); ++ } ++ } ++ ++ /* 10. Wait until the voltage of VCM keeps stable at the AVDD/2 */ ++ msleep(20); /* estimated value */ ++ ++ /* ++ * 11. Configure the register ACODEC_ADC_ANA_CON10[6:0] to the ++ * appropriate value(expect 0x0) for reducing power. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, 0x7c); ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* ++ * 12. Configure the register ACODEC_DAC_ANA_CON14[6:0] to the ++ * appropriate value(expect 0x0) for reducing power. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, ++ RK3308_DAC_CURRENT_CHARGE_MSK, 0xf); ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_power_off(struct rk3308_codec_priv *rk3308) ++{ ++ unsigned int v; ++ ++ /* ++ * 0. Keep the power on and disable the DAC and ADC path according to ++ * the section power on configuration standard usage flow. ++ */ ++ ++ /* ++ * 1. Configure the register ACODEC_ADC_ANA_CON10[6:0] to 7’b000_0001. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, ++ RK3308_ADC_SEL_I(0x1)); ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* ++ * 2. Configure the register ACODEC_DAC_ANA_CON14[3:0] to ++ * 4’b0001. ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, ++ RK3308_DAC_CURRENT_CHARGE_MSK, ++ RK3308_DAC_SEL_I(0x1)); ++ } ++ ++ /* 3. Configure the register ACODEC_ADC_ANA_CON10[7] to 0x0 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_REF_EN, ++ RK3308_ADC_REF_DIS); ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* 4. Configure the register ACODEC_DAC_ANA_CON14[7] to 0x0 */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON14, ++ RK3308_DAC_VCM_LINEOUT_EN, ++ RK3308_DAC_VCM_LINEOUT_DIS); ++ } ++ ++ /* ++ * 5. Change the register ACODEC_ADC_ANA_CON10[6:0] from the 0x1 to 0x7f ++ * step by step or configure the ACODEC_ADC_ANA_CON10[6:0] to 0x7f ++ * directly. Here the slot time of the step is 200us. ++ */ ++ for (v = 0x1; v <= 0x7f; v++) { ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, ++ v); ++ udelay(200); ++ } ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* ++ * 6. Change the register ACODEC_DAC_ANA_CON14[3:0] from the 0x1 ++ * to 0xf step by step or configure the ++ * ACODEC_DAC_ANA_CON14[3:0] to 0xf directly. Here the slot ++ * time of the step is 200us. ++ */ ++ for (v = 0x1; v <= 0x7f; v++) { ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_ANA_CON10(0), ++ RK3308_ADC_CURRENT_CHARGE_MSK, ++ v); ++ udelay(200); ++ } ++ } ++ ++ /* 7. Wait until the voltage of VCM keeps stable at the AGND */ ++ msleep(20); /* estimated value */ ++ ++ /* 8. Power off the analog power supply */ ++ /* 9. Power off the digital power supply */ ++ ++ /* Do something via hardware */ ++ ++ return 0; ++} ++ ++static int rk3308_codec_headset_detect_enable(struct rk3308_codec_priv *rk3308) ++{ ++ /* ++ * Set ACODEC_DAC_ANA_CON0[1] to 0x1, to enable the headset insert ++ * detection ++ * ++ * Note. When the voltage of PAD HPDET> 8*AVDD/9, the output value of ++ * the pin_hpdet will be set to 0x1 and assert a interrupt ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, ++ RK3308_DAC_HEADPHONE_DET_MSK, ++ RK3308_DAC_HEADPHONE_DET_EN); ++ ++ return 0; ++} ++ ++static int rk3308_codec_headset_detect_disable(struct rk3308_codec_priv *rk3308) ++{ ++ /* ++ * Set ACODEC_DAC_ANA_CON0[1] to 0x0, to disable the headset insert ++ * detection ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON00, ++ RK3308_DAC_HEADPHONE_DET_MSK, ++ RK3308_DAC_HEADPHONE_DET_DIS); ++ ++ return 0; ++} ++ ++static int rk3308_codec_check_i2s_sdis(struct rk3308_codec_priv *rk3308, ++ int num) ++{ ++ int i, j, ret = 0; ++ ++ switch (num) { ++ case 1: ++ rk3308->which_i2s = ACODEC_TO_I2S1_2CH; ++ break; ++ case 2: ++ rk3308->which_i2s = ACODEC_TO_I2S3_4CH; ++ break; ++ case 4: ++ rk3308->which_i2s = ACODEC_TO_I2S2_8CH; ++ break; ++ default: ++ dev_err(rk3308->plat_dev, "Invalid i2s sdis num: %d\n", num); ++ ret = -EINVAL; ++ goto err; ++ } ++ ++ for (i = 0; i < num; i++) { ++ if (rk3308->i2s_sdis[i] > ADC_LR_GROUP_MAX - 1) { ++ dev_err(rk3308->plat_dev, ++ "i2s_sdis[%d]: %d is overflow\n", ++ i, rk3308->i2s_sdis[i]); ++ ret = -EINVAL; ++ goto err; ++ } ++ ++ for (j = 0; j < num; j++) { ++ if (i == j) ++ continue; ++ ++ if (rk3308->i2s_sdis[i] == rk3308->i2s_sdis[j]) { ++ dev_err(rk3308->plat_dev, ++ "Invalid i2s_sdis: [%d]%d == [%d]%d\n", ++ i, rk3308->i2s_sdis[i], ++ j, rk3308->i2s_sdis[j]); ++ ret = -EINVAL; ++ goto err; ++ } ++ } ++ } ++ ++err: ++ return ret; ++} ++ ++static int rk3308_codec_adc_grps_route_config(struct rk3308_codec_priv *rk3308) ++{ ++ int idx = 0; ++ ++ if (rk3308->which_i2s == ACODEC_TO_I2S2_8CH) { ++ for (idx = 0; idx < rk3308->to_i2s_grps; idx++) { ++ regmap_write(rk3308->grf, GRF_SOC_CON1, ++ GRF_I2S2_8CH_SDI(idx, rk3308->i2s_sdis[idx])); ++ } ++ } else if (rk3308->which_i2s == ACODEC_TO_I2S3_4CH) { ++ for (idx = 0; idx < rk3308->to_i2s_grps; idx++) { ++ regmap_write(rk3308->grf, GRF_SOC_CON1, ++ GRF_I2S3_4CH_SDI(idx, rk3308->i2s_sdis[idx])); ++ } ++ } else if (rk3308->which_i2s == ACODEC_TO_I2S1_2CH) { ++ regmap_write(rk3308->grf, GRF_SOC_CON1, ++ GRF_I2S1_2CH_SDI(rk3308->i2s_sdis[idx])); ++ } ++ ++ return 0; ++} ++ ++/* Put default one-to-one mapping */ ++static int rk3308_codec_adc_grps_route_default(struct rk3308_codec_priv *rk3308) ++{ ++ unsigned int idx; ++ ++ /* ++ * The GRF values may be kept the previous status after hot reboot, ++ * if the property 'rockchip,adc-grps-route' is not set, we need to ++ * recover default the order of sdi/sdo for i2s2_8ch/i2s3_8ch/i2s1_2ch. ++ */ ++ regmap_write(rk3308->grf, GRF_SOC_CON1, ++ GRF_I2S1_2CH_SDI(0)); ++ ++ for (idx = 0; idx < 2; idx++) { ++ regmap_write(rk3308->grf, GRF_SOC_CON1, ++ GRF_I2S3_4CH_SDI(idx, idx)); ++ } ++ ++ /* Using i2s2_8ch by default. */ ++ rk3308->which_i2s = ACODEC_TO_I2S2_8CH; ++ rk3308->to_i2s_grps = ADC_LR_GROUP_MAX; ++ ++ for (idx = 0; idx < ADC_LR_GROUP_MAX; idx++) { ++ rk3308->i2s_sdis[idx] = idx; ++ regmap_write(rk3308->grf, GRF_SOC_CON1, ++ GRF_I2S2_8CH_SDI(idx, idx)); ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_adc_grps_route(struct rk3308_codec_priv *rk3308, ++ struct device_node *np) ++{ ++ int num, ret; ++ ++ num = of_count_phandle_with_args(np, "rockchip,adc-grps-route", NULL); ++ if (num < 0) { ++ if (num == -ENOENT) { ++ /* Not use 'rockchip,adc-grps-route' property here */ ++ rk3308_codec_adc_grps_route_default(rk3308); ++ ret = 0; ++ } else { ++ dev_err(rk3308->plat_dev, ++ "Failed to read 'rockchip,adc-grps-route' num: %d\n", ++ num); ++ ret = num; ++ } ++ return ret; ++ } ++ ++ ret = of_property_read_u32_array(np, "rockchip,adc-grps-route", ++ rk3308->i2s_sdis, num); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, ++ "Failed to read 'rockchip,adc-grps-route': %d\n", ++ ret); ++ return ret; ++ } ++ ++ ret = rk3308_codec_check_i2s_sdis(rk3308, num); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, ++ "Failed to check i2s_sdis: %d\n", ret); ++ return ret; ++ } ++ ++ rk3308->to_i2s_grps = num; ++ ++ rk3308_codec_adc_grps_route_config(rk3308); ++ ++ return 0; ++} ++ ++static int check_micbias(int micbias) ++{ ++ switch (micbias) { ++ case RK3308_ADC_MICBIAS_VOLT_0_85: ++ case RK3308_ADC_MICBIAS_VOLT_0_8: ++ case RK3308_ADC_MICBIAS_VOLT_0_75: ++ case RK3308_ADC_MICBIAS_VOLT_0_7: ++ case RK3308_ADC_MICBIAS_VOLT_0_65: ++ case RK3308_ADC_MICBIAS_VOLT_0_6: ++ case RK3308_ADC_MICBIAS_VOLT_0_55: ++ case RK3308_ADC_MICBIAS_VOLT_0_5: ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static bool handle_loopback(struct rk3308_codec_priv *rk3308) ++{ ++ /* The version B doesn't need to handle loopback. */ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) ++ return false; ++ ++ switch (rk3308->loopback_grp) { ++ case 0: ++ case 1: ++ case 2: ++ case 3: ++ return true; ++ } ++ ++ return false; ++} ++ ++static bool has_en_always_grps(struct rk3308_codec_priv *rk3308) ++{ ++ int idx; ++ ++ if (rk3308->en_always_grps_num) { ++ for (idx = 0; idx < ADC_LR_GROUP_MAX; idx++) { ++ if (rk3308->en_always_grps[idx] >= 0 && ++ rk3308->en_always_grps[idx] <= ADC_LR_GROUP_MAX - 1) ++ return true; ++ } ++ } ++ ++ return false; ++} ++ ++static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308, ++ int micbias) ++{ ++ int ret; ++ ++ if (rk3308->ext_micbias != EXT_MICBIAS_NONE) ++ return 0; ++ ++ /* 0. Power up the ACODEC and keep the AVDDH stable */ ++ ++ /* Step 1. Configure ACODEC_ADC_ANA_CON7[2:0] to the certain value */ ++ ret = check_micbias(micbias); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, "This is an invalid micbias: %d\n", ++ micbias); ++ return ret; ++ } ++ ++ /* ++ * Note: Only the reg (ADC_ANA_CON7+0x0)[2:0] represent the level range ++ * control signal of MICBIAS voltage ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), ++ RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK, ++ micbias); ++ ++ /* Step 2. Wait until the VCMH keep stable */ ++ msleep(20); /* estimated value */ ++ ++ /* ++ * Step 3. Configure ACODEC_ADC_ANA_CON8[4] to 0x1 ++ * ++ * Note: Only the reg (ADC_ANA_CON8+0x0)[4] represent the enable ++ * signal of current source for MICBIAS ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(0), ++ RK3308_ADC_MICBIAS_CURRENT_MSK, ++ RK3308_ADC_MICBIAS_CURRENT_EN); ++ ++ /* ++ * Step 4. Configure the (ADC_ANA_CON7+0x40)[3] or ++ * (ADC_ANA_CON7+0x80)[3] to 0x1. ++ * ++ * (ADC_ANA_CON7+0x40)[3] used to control the MICBIAS1, and ++ * (ADC_ANA_CON7+0x80)[3] used to control the MICBIAS2 ++ */ ++ if (rk3308->micbias1) ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(1), ++ RK3308_ADC_MIC_BIAS_BUF_EN, ++ RK3308_ADC_MIC_BIAS_BUF_EN); ++ ++ if (rk3308->micbias2) ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(2), ++ RK3308_ADC_MIC_BIAS_BUF_EN, ++ RK3308_ADC_MIC_BIAS_BUF_EN); ++ ++ /* waiting micbias stabled*/ ++ mdelay(50); ++ ++ rk3308->enable_micbias = true; ++ ++ return 0; ++} ++ ++static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308) ++{ ++ if (rk3308->ext_micbias != EXT_MICBIAS_NONE) ++ return 0; ++ ++ /* Step 0. Enable the MICBIAS and keep the Audio Codec stable */ ++ /* Do nothing */ ++ ++ /* ++ * Step 1. Configure the (ADC_ANA_CON7+0x40)[3] or ++ * (ADC_ANA_CON7+0x80)[3] to 0x0 ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(1), ++ RK3308_ADC_MIC_BIAS_BUF_EN, ++ RK3308_ADC_MIC_BIAS_BUF_DIS); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(2), ++ RK3308_ADC_MIC_BIAS_BUF_EN, ++ RK3308_ADC_MIC_BIAS_BUF_DIS); ++ ++ /* ++ * Step 2. Configure ACODEC_ADC_ANA_CON8[4] to 0x0 ++ * ++ * Note: Only the reg (ADC_ANA_CON8+0x0)[4] represent the enable ++ * signal of current source for MICBIAS ++ */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(0), ++ RK3308_ADC_MICBIAS_CURRENT_MSK, ++ RK3308_ADC_MICBIAS_CURRENT_DIS); ++ ++ rk3308->enable_micbias = false; ++ ++ return 0; ++} ++ ++static int rk3308_codec_adc_reinit_mics(struct rk3308_codec_priv *rk3308, ++ int type) ++{ ++ int idx, grp; ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 1 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), ++ RK3308_ADC_CH1_ADC_WORK | ++ RK3308_ADC_CH2_ADC_WORK, ++ RK3308_ADC_CH1_ADC_INIT | ++ RK3308_ADC_CH2_ADC_INIT); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 2 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), ++ RK3308_ADC_CH1_ALC_WORK | ++ RK3308_ADC_CH2_ALC_WORK, ++ RK3308_ADC_CH1_ALC_INIT | ++ RK3308_ADC_CH2_ALC_INIT); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 3 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), ++ RK3308_ADC_CH1_MIC_WORK | ++ RK3308_ADC_CH2_MIC_WORK, ++ RK3308_ADC_CH1_MIC_INIT | ++ RK3308_ADC_CH2_MIC_INIT); ++ } ++ ++ usleep_range(200, 250); /* estimated value */ ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 1 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), ++ RK3308_ADC_CH1_ADC_WORK | ++ RK3308_ADC_CH2_ADC_WORK, ++ RK3308_ADC_CH1_ADC_WORK | ++ RK3308_ADC_CH2_ADC_WORK); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 2 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), ++ RK3308_ADC_CH1_ALC_WORK | ++ RK3308_ADC_CH2_ALC_WORK, ++ RK3308_ADC_CH1_ALC_WORK | ++ RK3308_ADC_CH2_ALC_WORK); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 3 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), ++ RK3308_ADC_CH1_MIC_WORK | ++ RK3308_ADC_CH2_MIC_WORK, ++ RK3308_ADC_CH1_MIC_WORK | ++ RK3308_ADC_CH2_MIC_WORK); ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_adc_ana_enable(struct rk3308_codec_priv *rk3308, ++ int type) ++{ ++ unsigned int agc_func_en; ++ int idx, grp; ++ ++ /* ++ * 1. Set the ACODEC_ADC_ANA_CON7[7:6] and ACODEC_ADC_ANA_CON7[5:4], ++ * to select the line-in or microphone as input of ADC ++ * ++ * Note1. Please ignore the step1 for enabling ADC3, ADC4, ADC5, ++ * ADC6, ADC7, and ADC8 ++ */ ++ if (rk3308->adc_grp0_using_linein) { ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), ++ RK3308_ADC_CH1_IN_SEL_MSK | ++ RK3308_ADC_CH2_IN_SEL_MSK, ++ RK3308_ADC_CH1_IN_LINEIN | ++ RK3308_ADC_CH2_IN_LINEIN); ++ ++ /* Keep other ADCs as MIC-IN */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ /* The groups without line-in are >= 1 */ ++ if (grp < 1 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_ANA_CON07(grp), ++ RK3308_ADC_CH1_IN_SEL_MSK | ++ RK3308_ADC_CH2_IN_SEL_MSK, ++ RK3308_ADC_CH1_IN_MIC | ++ RK3308_ADC_CH2_IN_MIC); ++ } ++ } else { ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_ANA_CON07(grp), ++ RK3308_ADC_CH1_IN_SEL_MSK | ++ RK3308_ADC_CH2_IN_SEL_MSK, ++ RK3308_ADC_CH1_IN_MIC | ++ RK3308_ADC_CH2_IN_MIC); ++ } ++ } ++ ++ /* ++ * 2. Set ACODEC_ADC_ANA_CON0[7] and [3] to 0x1, to end the mute station ++ * of ADC, to enable the MIC module, to enable the reference voltage ++ * buffer, and to end the initialization of MIC ++ */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), ++ RK3308_ADC_CH1_MIC_UNMUTE | ++ RK3308_ADC_CH2_MIC_UNMUTE, ++ RK3308_ADC_CH1_MIC_UNMUTE | ++ RK3308_ADC_CH2_MIC_UNMUTE); ++ } ++ ++ /* ++ * 3. Set ACODEC_ADC_ANA_CON6[0] to 0x1, to enable the current source ++ * of audio ++ */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(grp), ++ RK3308_ADC_CURRENT_MSK, ++ RK3308_ADC_CURRENT_EN); ++ } ++ ++ /* ++ * This is mainly used for BIST mode that wait ADCs are stable. ++ * ++ * By tested results, the type delay is >40us, but we need to leave ++ * enough delay margin. ++ */ ++ usleep_range(400, 500); ++ ++ /* vendor step 4*/ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), ++ RK3308_ADC_CH1_BUF_REF_EN | ++ RK3308_ADC_CH2_BUF_REF_EN, ++ RK3308_ADC_CH1_BUF_REF_EN | ++ RK3308_ADC_CH2_BUF_REF_EN); ++ } ++ ++ /* vendor step 5 */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), ++ RK3308_ADC_CH1_MIC_EN | ++ RK3308_ADC_CH2_MIC_EN, ++ RK3308_ADC_CH1_MIC_EN | ++ RK3308_ADC_CH2_MIC_EN); ++ } ++ ++ /* vendor step 6 */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), ++ RK3308_ADC_CH1_ALC_EN | ++ RK3308_ADC_CH2_ALC_EN, ++ RK3308_ADC_CH1_ALC_EN | ++ RK3308_ADC_CH2_ALC_EN); ++ } ++ ++ /* vendor step 7 */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), ++ RK3308_ADC_CH1_CLK_EN | ++ RK3308_ADC_CH2_CLK_EN, ++ RK3308_ADC_CH1_CLK_EN | ++ RK3308_ADC_CH2_CLK_EN); ++ } ++ ++ /* vendor step 8 */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), ++ RK3308_ADC_CH1_ADC_EN | ++ RK3308_ADC_CH2_ADC_EN, ++ RK3308_ADC_CH1_ADC_EN | ++ RK3308_ADC_CH2_ADC_EN); ++ } ++ ++ /* vendor step 9 */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), ++ RK3308_ADC_CH1_ADC_WORK | ++ RK3308_ADC_CH2_ADC_WORK, ++ RK3308_ADC_CH1_ADC_WORK | ++ RK3308_ADC_CH2_ADC_WORK); ++ } ++ ++ /* vendor step 10 */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), ++ RK3308_ADC_CH1_ALC_WORK | ++ RK3308_ADC_CH2_ALC_WORK, ++ RK3308_ADC_CH1_ALC_WORK | ++ RK3308_ADC_CH2_ALC_WORK); ++ } ++ ++ /* vendor step 11 */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), ++ RK3308_ADC_CH1_MIC_WORK | ++ RK3308_ADC_CH2_MIC_WORK, ++ RK3308_ADC_CH1_MIC_WORK | ++ RK3308_ADC_CH2_MIC_WORK); ++ } ++ ++ /* vendor step 12 */ ++ ++ /* vendor step 13 */ ++ ++ /* vendor step 14 */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(grp), ++ &agc_func_en); ++ if (rk3308->adc_zerocross || ++ agc_func_en & RK3308_AGC_FUNC_SEL_EN) { ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_ANA_CON02(grp), ++ RK3308_ADC_CH1_ZEROCROSS_DET_EN, ++ RK3308_ADC_CH1_ZEROCROSS_DET_EN); ++ } ++ regmap_read(rk3308->regmap, RK3308_ALC_R_DIG_CON09(grp), ++ &agc_func_en); ++ if (rk3308->adc_zerocross || ++ agc_func_en & RK3308_AGC_FUNC_SEL_EN) { ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_ANA_CON02(grp), ++ RK3308_ADC_CH2_ZEROCROSS_DET_EN, ++ RK3308_ADC_CH2_ZEROCROSS_DET_EN); ++ } ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ rk3308->adc_grps_endisable[grp] = true; ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_adc_ana_disable(struct rk3308_codec_priv *rk3308, ++ int type) ++{ ++ int idx, grp; ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 1 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), ++ RK3308_ADC_CH1_ZEROCROSS_DET_EN | ++ RK3308_ADC_CH2_ZEROCROSS_DET_EN, ++ RK3308_ADC_CH1_ZEROCROSS_DET_DIS | ++ RK3308_ADC_CH2_ZEROCROSS_DET_DIS); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 2 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), ++ RK3308_ADC_CH1_ADC_EN | ++ RK3308_ADC_CH2_ADC_EN, ++ RK3308_ADC_CH1_ADC_DIS | ++ RK3308_ADC_CH2_ADC_DIS); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 3 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), ++ RK3308_ADC_CH1_CLK_EN | ++ RK3308_ADC_CH2_CLK_EN, ++ RK3308_ADC_CH1_CLK_DIS | ++ RK3308_ADC_CH2_CLK_DIS); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 4 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), ++ RK3308_ADC_CH1_ALC_EN | ++ RK3308_ADC_CH2_ALC_EN, ++ RK3308_ADC_CH1_ALC_DIS | ++ RK3308_ADC_CH2_ALC_DIS); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 5 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), ++ RK3308_ADC_CH1_MIC_EN | ++ RK3308_ADC_CH2_MIC_EN, ++ RK3308_ADC_CH1_MIC_DIS | ++ RK3308_ADC_CH2_MIC_DIS); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 6 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), ++ RK3308_ADC_CH1_BUF_REF_EN | ++ RK3308_ADC_CH2_BUF_REF_EN, ++ RK3308_ADC_CH1_BUF_REF_DIS | ++ RK3308_ADC_CH2_BUF_REF_DIS); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 7 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(grp), ++ RK3308_ADC_CURRENT_MSK, ++ RK3308_ADC_CURRENT_DIS); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 8 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(grp), ++ RK3308_ADC_CH1_ADC_WORK | ++ RK3308_ADC_CH2_ADC_WORK, ++ RK3308_ADC_CH1_ADC_INIT | ++ RK3308_ADC_CH2_ADC_INIT); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 9 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(grp), ++ RK3308_ADC_CH1_ALC_WORK | ++ RK3308_ADC_CH2_ALC_WORK, ++ RK3308_ADC_CH1_ALC_INIT | ++ RK3308_ADC_CH2_ALC_INIT); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ /* vendor step 10 */ ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(grp), ++ RK3308_ADC_CH1_MIC_WORK | ++ RK3308_ADC_CH2_MIC_WORK, ++ RK3308_ADC_CH1_MIC_INIT | ++ RK3308_ADC_CH2_MIC_INIT); ++ } ++ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ rk3308->adc_grps_endisable[grp] = false; ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_open_capture(struct rk3308_codec_priv *rk3308) ++{ ++ int idx, grp = 0; ++ int type = ADC_TYPE_NORMAL; ++ ++ rk3308_codec_adc_ana_enable(rk3308, type); ++ rk3308_codec_adc_reinit_mics(rk3308, type); ++ ++ if (rk3308->adc_grp0_using_linein) { ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(0), ++ RK3308_ADC_L_CH_BIST_MSK, ++ RK3308_ADC_L_CH_NORMAL_RIGHT); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_DIG_CON03(0), ++ RK3308_ADC_R_CH_BIST_MSK, ++ RK3308_ADC_R_CH_NORMAL_LEFT); ++ } else { ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (handle_loopback(rk3308) && ++ idx == rk3308->loopback_grp && ++ grp == ADC_GRP_SKIP_MAGIC) { ++ /* ++ * Switch to dummy BIST mode (BIST keep reset ++ * now) to keep the zero input data in I2S bus. ++ * ++ * It may cause the glitch if we hold the ADC ++ * digtital i2s module in codec. ++ * ++ * Then, the grp which is set from loopback_grp. ++ */ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(rk3308->loopback_grp), ++ RK3308_ADC_L_CH_BIST_MSK, ++ RK3308_ADC_L_CH_BIST_SINE); ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(rk3308->loopback_grp), ++ RK3308_ADC_R_CH_BIST_MSK, ++ RK3308_ADC_R_CH_BIST_SINE); ++ } else { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_L_CH_BIST_MSK, ++ RK3308_ADC_L_CH_NORMAL_LEFT); ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_R_CH_BIST_MSK, ++ RK3308_ADC_R_CH_NORMAL_RIGHT); ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static void rk3308_codec_adc_mclk_disable(struct rk3308_codec_priv *rk3308) ++{ ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_ADC_MCLK_MSK, ++ RK3308_ADC_MCLK_DIS); ++} ++ ++static void rk3308_codec_adc_mclk_enable(struct rk3308_codec_priv *rk3308) ++{ ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_ADC_MCLK_MSK, ++ RK3308_ADC_MCLK_EN); ++ udelay(20); ++} ++ ++static void rk3308_codec_dac_mclk_disable(struct rk3308_codec_priv *rk3308) ++{ ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_DAC_MCLK_MSK, ++ RK3308_DAC_MCLK_DIS); ++} ++ ++static void rk3308_codec_dac_mclk_enable(struct rk3308_codec_priv *rk3308) ++{ ++ regmap_update_bits(rk3308->regmap, RK3308_GLB_CON, ++ RK3308_DAC_MCLK_MSK, ++ RK3308_DAC_MCLK_EN); ++ udelay(20); ++} ++ ++static int rk3308_codec_open_dbg_capture(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_adc_ana_enable(rk3308, ADC_TYPE_DBG); ++ ++ return 0; ++} ++ ++static int rk3308_codec_close_dbg_capture(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_DBG); ++ ++ return 0; ++} ++ ++static int rk3308_codec_close_all_capture(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_ALL); ++ ++ return 0; ++} ++ ++static int rk3308_codec_close_capture(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_NORMAL); ++ ++ return 0; ++} ++ ++static int rk3308_codec_open_playback(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_dac_enable(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_codec_close_playback(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_dac_disable(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_codec_llp_down(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_adc_mclk_disable(rk3308); ++ rk3308_codec_dac_mclk_disable(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_codec_llp_up(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_adc_mclk_enable(rk3308); ++ rk3308_codec_dac_mclk_enable(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_codec_dlp_down(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_micbias_disable(rk3308); ++ rk3308_codec_power_off(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_codec_dlp_up(struct rk3308_codec_priv *rk3308) ++{ ++ rk3308_codec_power_on(rk3308); ++ rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt); ++ ++ return 0; ++} ++ ++/* Just used for debug and trace power state */ ++static void rk3308_codec_set_pm_state(struct rk3308_codec_priv *rk3308, ++ int pm_state) ++{ ++ int ret; ++ ++ switch (pm_state) { ++ case PM_LLP_DOWN: ++ rk3308_codec_llp_down(rk3308); ++ break; ++ case PM_LLP_UP: ++ rk3308_codec_llp_up(rk3308); ++ break; ++ case PM_DLP_DOWN: ++ rk3308_codec_dlp_down(rk3308); ++ break; ++ case PM_DLP_UP: ++ rk3308_codec_dlp_up(rk3308); ++ break; ++ case PM_DLP_DOWN2: ++ clk_disable_unprepare(rk3308->mclk_rx); ++ clk_disable_unprepare(rk3308->mclk_tx); ++ clk_disable_unprepare(rk3308->pclk); ++ break; ++ case PM_DLP_UP2: ++ ret = clk_prepare_enable(rk3308->pclk); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, ++ "Failed to enable acodec pclk: %d\n", ret); ++ goto err; ++ } ++ ++ ret = clk_prepare_enable(rk3308->mclk_rx); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, ++ "Failed to enable i2s mclk_rx: %d\n", ret); ++ goto err; ++ } ++ ++ ret = clk_prepare_enable(rk3308->mclk_tx); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, ++ "Failed to enable i2s mclk_tx: %d\n", ret); ++ goto err; ++ } ++ break; ++ default: ++ dev_err(rk3308->plat_dev, "Invalid pm_state: %d\n", pm_state); ++ goto err; ++ } ++ ++ rk3308->pm_state = pm_state; ++ ++err: ++ return; ++} ++ ++static void rk3308_codec_update_adcs_status(struct rk3308_codec_priv *rk3308, ++ int state) ++{ ++ int idx, grp; ++ ++ /* Update skip_grps flags if the ADCs need to be enabled always. */ ++ if (state == PATH_BUSY) { ++ for (idx = 0; idx < rk3308->used_adc_grps; idx++) { ++ u32 mapped_grp = to_mapped_grp(rk3308, idx); ++ ++ for (grp = 0; grp < rk3308->en_always_grps_num; grp++) { ++ u32 en_always_grp = rk3308->en_always_grps[grp]; ++ ++ if (mapped_grp == en_always_grp) ++ rk3308->skip_grps[en_always_grp] = 1; ++ } ++ } ++ } ++} ++ ++static int rk3308_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_pcm_str *playback_str = ++ &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK]; ++ int type = ADC_TYPE_LOOPBACK; ++ int idx, grp; ++ int ret; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ /* DAC only supports 2 channels */ ++ rk3308_codec_dac_mclk_enable(rk3308); ++ rk3308_codec_open_playback(rk3308); ++ rk3308_codec_dac_dig_config(rk3308, params); ++ rk3308_codec_set_dac_path_state(rk3308, PATH_BUSY); ++ } else { ++ if (rk3308->micbias_num && ++ !rk3308->enable_micbias) ++ rk3308_codec_micbias_enable(rk3308, rk3308->micbias_volt); ++ ++ rk3308_codec_adc_mclk_enable(rk3308); ++ ret = rk3308_codec_update_adc_grps(rk3308, params); ++ if (ret < 0) ++ return ret; ++ ++ if (handle_loopback(rk3308)) { ++ if (rk3308->micbias_num && ++ (params_channels(params) == 2) && ++ to_mapped_grp(rk3308, 0) == rk3308->loopback_grp) ++ rk3308_codec_micbias_disable(rk3308); ++ ++ /* Check the DACs are opened */ ++ if (playback_str->substream_opened) { ++ rk3308->loopback_dacs_enabled = true; ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_L_CH_BIST_MSK, ++ RK3308_ADC_L_CH_NORMAL_LEFT); ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_R_CH_BIST_MSK, ++ RK3308_ADC_R_CH_NORMAL_RIGHT); ++ } ++ } else { ++ rk3308->loopback_dacs_enabled = false; ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_L_CH_BIST_MSK, ++ RK3308_ADC_L_CH_BIST_SINE); ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_R_CH_BIST_MSK, ++ RK3308_ADC_R_CH_BIST_SINE); ++ } ++ } ++ } ++ ++ rk3308_codec_open_capture(rk3308); ++ rk3308_codec_adc_dig_config(rk3308, params); ++ rk3308_codec_update_adcs_status(rk3308, PATH_BUSY); ++ } ++ ++ return 0; ++} ++ ++static int rk3308_pcm_trigger(struct snd_pcm_substream *substream, ++ int cmd, struct snd_soc_dai *dai) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ int type = ADC_TYPE_LOOPBACK; ++ int idx, grp; ++ ++ if (handle_loopback(rk3308) && ++ rk3308->dac_output == DAC_LINEOUT && ++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ if (cmd == SNDRV_PCM_TRIGGER_START) { ++ struct snd_pcm_str *capture_str = ++ &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE]; ++ ++ if (capture_str->substream_opened) ++ queue_delayed_work(system_power_efficient_wq, ++ &rk3308->loopback_work, ++ msecs_to_jiffies(rk3308->delay_loopback_handle_ms)); ++ } else if (cmd == SNDRV_PCM_TRIGGER_STOP) { ++ /* ++ * Switch to dummy bist mode to kick the glitch during disable ++ * ADCs and keep zero input data ++ */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_L_CH_BIST_MSK, ++ RK3308_ADC_L_CH_BIST_SINE); ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_R_CH_BIST_MSK, ++ RK3308_ADC_R_CH_BIST_SINE); ++ } ++ rk3308_codec_adc_ana_disable(rk3308, ADC_TYPE_LOOPBACK); ++ } ++ } ++ ++ return 0; ++} ++ ++static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ rk3308_codec_close_playback(rk3308); ++ rk3308_codec_dac_mclk_disable(rk3308); ++ regcache_cache_only(rk3308->regmap, false); ++ regcache_sync(rk3308->regmap); ++ rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE); ++ } else { ++ rk3308_codec_close_capture(rk3308); ++ if (!has_en_always_grps(rk3308)) { ++ rk3308_codec_adc_mclk_disable(rk3308); ++ rk3308_codec_update_adcs_status(rk3308, PATH_IDLE); ++ if (rk3308->micbias_num && ++ rk3308->enable_micbias) ++ rk3308_codec_micbias_disable(rk3308); ++ } ++ ++ regcache_cache_only(rk3308->regmap, false); ++ regcache_sync(rk3308->regmap); ++ } ++} ++ ++static struct snd_soc_dai_ops rk3308_dai_ops = { ++ .hw_params = rk3308_hw_params, ++ .set_fmt = rk3308_set_dai_fmt, ++ .mute_stream = rk3308_mute_stream, ++ .trigger = rk3308_pcm_trigger, ++ .shutdown = rk3308_pcm_shutdown, ++}; ++ ++static struct snd_soc_dai_driver rk3308_dai[] = { ++ { ++ .name = "rk3308-hifi", ++ .id = RK3308_HIFI, ++ .playback = { ++ .stream_name = "HiFi Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = (SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S20_3LE | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S32_LE), ++ }, ++ .capture = { ++ .stream_name = "HiFi Capture", ++ .channels_min = 1, ++ .channels_max = 8, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = (SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S20_3LE | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S32_LE), ++ }, ++ .ops = &rk3308_dai_ops, ++ }, ++}; ++ ++static int rk3308_suspend(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ if (rk3308->no_deep_low_power) ++ goto out; ++ ++ rk3308_codec_dlp_down(rk3308); ++ clk_disable_unprepare(rk3308->mclk_rx); ++ clk_disable_unprepare(rk3308->mclk_tx); ++ clk_disable_unprepare(rk3308->pclk); ++ ++out: ++ rk3308_set_bias_level(codec, SND_SOC_BIAS_OFF); ++ return 0; ++} ++ ++static int rk3308_resume(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ int ret = 0; ++ ++ if (rk3308->no_deep_low_power) ++ goto out; ++ ++ ret = clk_prepare_enable(rk3308->pclk); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, ++ "Failed to enable acodec pclk: %d\n", ret); ++ goto out; ++ } ++ ++ ret = clk_prepare_enable(rk3308->mclk_rx); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, ++ "Failed to enable i2s mclk_rx: %d\n", ret); ++ goto out; ++ } ++ ++ ret = clk_prepare_enable(rk3308->mclk_tx); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, ++ "Failed to enable i2s mclk_tx: %d\n", ret); ++ goto out; ++ } ++ ++ rk3308_codec_dlp_up(rk3308); ++out: ++ rk3308_set_bias_level(codec, SND_SOC_BIAS_STANDBY); ++ return ret; ++} ++ ++static int rk3308_codec_default_gains(struct rk3308_codec_priv *rk3308) ++{ ++ int grp; ++ ++ /* Prepare ADC gains */ ++ /* vendor step 12, set MIC PGA default gains */ ++ for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON01(grp), ++ RK3308_ADC_CH1_MIC_GAIN_MSK | ++ RK3308_ADC_CH2_MIC_GAIN_MSK, ++ RK3308_ADC_CH1_MIC_GAIN_0DB | ++ RK3308_ADC_CH2_MIC_GAIN_0DB); ++ } ++ ++ /* vendor step 13, set ALC default gains */ ++ for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON03(grp), ++ RK3308_ADC_CH1_ALC_GAIN_MSK, ++ RK3308_ADC_CH1_ALC_GAIN_0DB); ++ regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON04(grp), ++ RK3308_ADC_CH2_ALC_GAIN_MSK, ++ RK3308_ADC_CH2_ALC_GAIN_0DB); ++ } ++ ++ /* Prepare DAC gains */ ++ /* Step 15, set HPMIX default gains */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON12, ++ RK3308_DAC_L_HPMIX_GAIN_MSK | ++ RK3308_DAC_R_HPMIX_GAIN_MSK, ++ RK3308_DAC_L_HPMIX_GAIN_NDB_6 | ++ RK3308_DAC_R_HPMIX_GAIN_NDB_6); ++ ++ /* Step 18, set HPOUT default gains */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON05, ++ RK3308_DAC_L_HPOUT_GAIN_MSK, ++ RK3308_DAC_L_HPOUT_GAIN_NDB_39); ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON06, ++ RK3308_DAC_R_HPOUT_GAIN_MSK, ++ RK3308_DAC_R_HPOUT_GAIN_NDB_39); ++ ++ /* Using the same gain to HPOUT LR channels */ ++ rk3308->hpout_l_dgain = RK3308_DAC_L_HPOUT_GAIN_NDB_39; ++ ++ /* Step 19, set LINEOUT default gains */ ++ regmap_update_bits(rk3308->regmap, RK3308_DAC_ANA_CON04, ++ RK3308_DAC_L_LINEOUT_GAIN_MSK | ++ RK3308_DAC_R_LINEOUT_GAIN_MSK, ++ RK3308_DAC_L_LINEOUT_GAIN_NDB_6 | ++ RK3308_DAC_R_LINEOUT_GAIN_NDB_6); ++ ++ return 0; ++} ++ ++static int rk3308_codec_setup_en_always_adcs(struct rk3308_codec_priv *rk3308, ++ struct device_node *np) ++{ ++ int num, ret; ++ ++ num = of_count_phandle_with_args(np, "rockchip,en-always-grps", NULL); ++ if (num < 0) { ++ if (num == -ENOENT) { ++ /* ++ * If there is note use 'rockchip,en-always-grps' ++ * property, return 0 is also right. ++ */ ++ ret = 0; ++ } else { ++ dev_err(rk3308->plat_dev, ++ "Failed to read 'rockchip,adc-grps-route' num: %d\n", ++ num); ++ ret = num; ++ } ++ ++ rk3308->en_always_grps_num = 0; ++ return ret; ++ } ++ ++ rk3308->en_always_grps_num = num; ++ ++ ret = of_property_read_u32_array(np, "rockchip,en-always-grps", ++ rk3308->en_always_grps, num); ++ if (ret < 0) { ++ dev_err(rk3308->plat_dev, ++ "Failed to read 'rockchip,en-always-grps': %d\n", ++ ret); ++ return ret; ++ } ++ ++ /* Clear all of skip_grps flags. */ ++ for (num = 0; num < ADC_LR_GROUP_MAX; num++) ++ rk3308->skip_grps[num] = 0; ++ ++ /* The loopback grp should not be enabled always. */ ++ for (num = 0; num < rk3308->en_always_grps_num; num++) { ++ if (rk3308->en_always_grps[num] == rk3308->loopback_grp) { ++ dev_err(rk3308->plat_dev, ++ "loopback_grp: %d should not be enabled always!\n", ++ rk3308->loopback_grp); ++ ret = -EINVAL; ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_dapm_mic_gains(struct rk3308_codec_priv *rk3308) ++{ ++ int ret; ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ ret = snd_soc_add_codec_controls(rk3308->codec, ++ mic_gains_b, ++ ARRAY_SIZE(mic_gains_b)); ++ if (ret) { ++ dev_err(rk3308->plat_dev, ++ "%s: add mic_gains_b failed: %d\n", ++ __func__, ret); ++ return ret; ++ } ++ } else { ++ ret = snd_soc_add_codec_controls(rk3308->codec, ++ mic_gains_a, ++ ARRAY_SIZE(mic_gains_a)); ++ if (ret) { ++ dev_err(rk3308->plat_dev, ++ "%s: add mic_gains_a failed: %d\n", ++ __func__, ret); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rk3308_codec_check_micbias(struct rk3308_codec_priv *rk3308, ++ struct device_node *np) ++{ ++ struct device *dev = (struct device *)rk3308->plat_dev; ++ int num = 0, ret; ++ ++ /* Check internal micbias */ ++ rk3308->micbias1 = ++ of_property_read_bool(np, "rockchip,micbias1"); ++ if (rk3308->micbias1) ++ num++; ++ ++ rk3308->micbias2 = ++ of_property_read_bool(np, "rockchip,micbias2"); ++ if (rk3308->micbias2) ++ num++; ++ ++ rk3308->micbias_volt = RK3308_ADC_MICBIAS_VOLT_0_85; /* by default */ ++ rk3308->micbias_num = num; ++ ++ /* Check external micbias */ ++ rk3308->ext_micbias = EXT_MICBIAS_NONE; ++ ++ rk3308->micbias_en_gpio = devm_gpiod_get_optional(dev, ++ "micbias-en", ++ GPIOD_IN); ++ if (!rk3308->micbias_en_gpio) { ++ dev_info(dev, "Don't need micbias-en gpio\n"); ++ } else if (IS_ERR(rk3308->micbias_en_gpio)) { ++ ret = PTR_ERR(rk3308->micbias_en_gpio); ++ dev_err(dev, "Unable to claim gpio micbias-en\n"); ++ return ret; ++ } else if (gpiod_get_value(rk3308->micbias_en_gpio)) { ++ rk3308->ext_micbias = EXT_MICBIAS_FUNC1; ++ } ++ ++ rk3308->vcc_micbias = devm_regulator_get_optional(dev, ++ "vmicbias"); ++ if (IS_ERR(rk3308->vcc_micbias)) { ++ if (PTR_ERR(rk3308->vcc_micbias) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; ++ dev_info(dev, "no vmicbias regulator found\n"); ++ } else { ++ ret = regulator_enable(rk3308->vcc_micbias); ++ if (ret) { ++ dev_err(dev, "Can't enable vmicbias: %d\n", ret); ++ return ret; ++ } ++ rk3308->ext_micbias = EXT_MICBIAS_FUNC2; ++ } ++ ++ dev_info(dev, "Check ext_micbias: %d\n", rk3308->ext_micbias); ++ ++ return 0; ++} ++ ++static int rk3308_codec_dapm_controls_prepare(struct rk3308_codec_priv *rk3308) ++{ ++ int grp; ++ ++ for (grp = 0; grp < ADC_LR_GROUP_MAX; grp++) { ++ rk3308->hpf_cutoff[grp] = 0; ++ rk3308->agc_l[grp] = 0; ++ rk3308->agc_r[grp] = 0; ++ rk3308->agc_asr_l[grp] = AGC_ASR_96KHZ; ++ rk3308->agc_asr_r[grp] = AGC_ASR_96KHZ; ++ } ++ ++ rk3308_codec_dapm_mic_gains(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_codec_prepare(struct rk3308_codec_priv *rk3308) ++{ ++ /* Clear registers for ADC and DAC */ ++ rk3308_codec_close_playback(rk3308); ++ rk3308_codec_close_all_capture(rk3308); ++ rk3308_codec_default_gains(rk3308); ++ rk3308_codec_llp_down(rk3308); ++ rk3308_codec_dapm_controls_prepare(rk3308); ++ ++ return 0; ++} ++ ++static int rk3308_probe(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ int ext_micbias; ++ ++ rk3308->codec = codec; ++ rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE); ++ ++ rk3308_codec_reset(codec); ++ rk3308_codec_power_on(rk3308); ++ ++ /* From vendor recommend, disable micbias at first. */ ++ ext_micbias = rk3308->ext_micbias; ++ rk3308->ext_micbias = EXT_MICBIAS_NONE; ++ rk3308_codec_micbias_disable(rk3308); ++ rk3308->ext_micbias = ext_micbias; ++ ++ rk3308_codec_prepare(rk3308); ++ if (!rk3308->no_hp_det) ++ rk3308_codec_headset_detect_enable(rk3308); ++ ++ regcache_cache_only(rk3308->regmap, false); ++ regcache_sync(rk3308->regmap); ++ ++ return 0; ++} + +- /* 5. Wait until the voltage of VCM keeps stable at the AGND */ +- usleep_range(200, 300); /* estimated value */ ++static int rk3308_remove(struct snd_soc_codec *codec) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ ++ rk3308_headphone_ctl(rk3308, 0); ++ rk3308_speaker_ctl(rk3308, 0); ++ if (!rk3308->no_hp_det) ++ rk3308_codec_headset_detect_disable(rk3308); ++ rk3308_codec_micbias_disable(rk3308); ++ rk3308_codec_power_off(rk3308); + +- /* 6. Power off the analog power supply */ +- /* 7. Power off the digital power supply */ ++ rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE); + +- /* Do something via hardware */ ++ regcache_cache_only(rk3308->regmap, false); ++ regcache_sync(rk3308->regmap); + + return 0; + } + +-static int check_micbias(int micbias) ++static struct snd_soc_codec_driver soc_codec_dev_rk3308 = { ++ .probe = rk3308_probe, ++ .remove = rk3308_remove, ++ .suspend = rk3308_suspend, ++ .resume = rk3308_resume, ++ .set_bias_level = rk3308_set_bias_level, ++ .controls = rk3308_codec_dapm_controls, ++ .num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls), ++}; ++ ++static const struct reg_default rk3308_codec_reg_defaults[] = { ++ { RK3308_GLB_CON, 0x07 }, ++}; ++ ++static bool rk3308_codec_write_read_reg(struct device *dev, unsigned int reg) + { +- switch (micbias) { +- case RK3308_ADC_MICBIAS_VOLT_0_85: +- case RK3308_ADC_MICBIAS_VOLT_0_8: +- case RK3308_ADC_MICBIAS_VOLT_0_75: +- case RK3308_ADC_MICBIAS_VOLT_0_7: +- case RK3308_ADC_MICBIAS_VOLT_0_65: +- case RK3308_ADC_MICBIAS_VOLT_0_6: +- case RK3308_ADC_MICBIAS_VOLT_0_55: +- case RK3308_ADC_MICBIAS_VOLT_0_5: +- return 0; +- } ++ /* All registers can be read / write */ ++ return true; ++} + +- return -EINVAL; ++static bool rk3308_codec_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ return true; + } + +-static int rk3308_codec_micbias_enable(struct rk3308_codec_priv *rk3308, +- int micbias) ++static void rk3308_codec_hpdetect_work(struct work_struct *work) + { +- int ch = rk3308->adc_ch; +- int ret; ++ struct rk3308_codec_priv *rk3308 = ++ container_of(work, struct rk3308_codec_priv, hpdet_work.work); ++ unsigned int val; ++ int need_poll = 0, need_irq = 0; ++ int need_report = 0, report_type = 0; ++ int dac_output = DAC_LINEOUT; ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ /* Check headphone plugged/unplugged directly. */ ++ regmap_read(rk3308->detect_grf, ++ DETECT_GRF_ACODEC_HPDET_STATUS, &val); ++ regmap_write(rk3308->detect_grf, ++ DETECT_GRF_ACODEC_HPDET_STATUS_CLR, val); ++ ++ if (rk3308->hp_jack_reversed) { ++ switch (val) { ++ case 0x0: ++ case 0x2: ++ dac_output = DAC_HPOUT; ++ report_type = SND_JACK_HEADPHONE; ++ break; ++ default: ++ break; ++ } ++ } else { ++ switch (val) { ++ case 0x1: ++ dac_output = DAC_HPOUT; ++ report_type = SND_JACK_HEADPHONE; ++ break; ++ default: ++ /* Includes val == 2 or others. */ ++ break; ++ } ++ } + +- if (ch != 1 && ch != 2) { +- dev_err(rk3308->plat_dev, +- "%s: currnet ch: %d, only ch1/2 control MICBIAS1/2\n", +- __func__, ch); +- return -EINVAL; +- } ++ rk3308_codec_dac_switch(rk3308, dac_output); ++ if (rk3308->hpdet_jack) ++ snd_soc_jack_report(rk3308->hpdet_jack, ++ report_type, ++ SND_JACK_HEADPHONE); + +- /* 1. Power up the ACODEC and keep the AVDDH stable */ ++ enable_irq(rk3308->irq); + +- /* 2. Configure ACODEC_ADC_ANA_CON7[2:0] to the certain value */ +- ret = check_micbias(micbias); +- if (ret < 0) { +- dev_err(rk3308->plat_dev, "This is an invalid micbias: %d\n", +- micbias); +- return ret; ++ return; + } + +- /* +- * Note: Only the reg (ADC_ANA_CON7+0x0)[2:0] represent the level range +- * control signal of MICBIAS voltage +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(0), +- RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK, +- micbias); ++ /* Check headphone unplugged via poll. */ ++ regmap_read(rk3308->regmap, RK3308_DAC_DIG_CON14, &val); + +- /* 3. Wait until the VCMH keep stable */ +- usleep_range(200, 300); /* estimated value */ ++ if (rk3308->hp_jack_reversed) { ++ if (!val) { ++ rk3308->hp_plugged = true; ++ report_type = SND_JACK_HEADPHONE; + +- /* 4. Configure ACODEC_ADC_ANA_CON8[4] to 0x1 */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(ch), +- RK3308_ADC_MICBIAS_CURRENT_MSK, +- RK3308_ADC_MICBIAS_CURRENT_EN); ++ need_report = 1; ++ need_irq = 1; ++ } else { ++ if (rk3308->hp_plugged) { ++ rk3308->hp_plugged = false; ++ need_report = 1; ++ } ++ need_poll = 1; ++ } ++ } else { ++ if (!val) { ++ rk3308->hp_plugged = false; + +- /* +- * 5. Configure the (ADC_ANA_CON7+0x40)[3] or (ADC_ANA_CON7+0x80)[3] +- * to 0x1. +- * (ADC_ANA_CON7+0x40)[3] used to control the MICBIAS1, and +- * (ADC_ANA_CON7+0x80)[3] used to control the MICBIAS2 +- */ ++ need_report = 1; ++ need_irq = 1; ++ } else { ++ if (!rk3308->hp_plugged) { ++ rk3308->hp_plugged = true; ++ report_type = SND_JACK_HEADPHONE; ++ need_report = 1; ++ } ++ need_poll = 1; ++ } ++ } + +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), +- RK3308_ADC_MIC_BIAS_BUF_EN, +- RK3308_ADC_MIC_BIAS_BUF_EN); ++ if (need_poll) ++ queue_delayed_work(system_power_efficient_wq, ++ &rk3308->hpdet_work, ++ msecs_to_jiffies(HPDET_POLL_MS)); + +- return 0; +-} ++ if (need_report) { ++ if (report_type) ++ dac_output = DAC_HPOUT; + +-static int rk3308_codec_micbias_disable(struct rk3308_codec_priv *rk3308) +-{ +- int ch = rk3308->adc_ch; ++ rk3308_codec_dac_switch(rk3308, dac_output); + +- if (ch != 1 && ch != 2) { +- dev_err(rk3308->plat_dev, +- "%s: currnet ch: %d, only ch1/2 control MICBIAS1/2\n", +- __func__, ch); +- return -EINVAL; ++ if (rk3308->hpdet_jack) ++ snd_soc_jack_report(rk3308->hpdet_jack, ++ report_type, ++ SND_JACK_HEADPHONE); + } + +- /* 1. Enable the MICBIAS and keep the Audio Codec stable */ +- /* Do nothing */ +- +- /* +- * 2. Configure the (ADC_ANA_CON7+0x40)[3] or +- * (ADC_ANA_CON7+0x80)[3] to 0x0 +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), +- RK3308_ADC_MIC_BIAS_BUF_EN, +- RK3308_ADC_MIC_BIAS_BUF_DIS); +- +- /* 3. Configure ACODEC_ADC_ANA_CON8[4] to 0x0 */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON08(ch), +- RK3308_ADC_MICBIAS_CURRENT_MSK, +- RK3308_ADC_MICBIAS_CURRENT_DIS); ++ if (need_irq) ++ enable_irq(rk3308->irq); ++} + +- return 0; ++static void rk3308_codec_loopback_work(struct work_struct *work) ++{ ++ struct rk3308_codec_priv *rk3308 = ++ container_of(work, struct rk3308_codec_priv, loopback_work.work); ++ int type = ADC_TYPE_LOOPBACK; ++ int idx, grp; ++ ++ /* Prepare loopback ADCs */ ++ rk3308_codec_adc_ana_enable(rk3308, type); ++ ++ /* Waiting ADCs are stable */ ++ msleep(ADC_STABLE_MS); ++ ++ /* Recover normal mode after enable ADCs */ ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) { ++ if (grp < 0 || grp > ADC_LR_GROUP_MAX - 1) ++ continue; ++ ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_L_CH_BIST_MSK, ++ RK3308_ADC_L_CH_NORMAL_LEFT); ++ regmap_update_bits(rk3308->regmap, ++ RK3308_ADC_DIG_CON03(grp), ++ RK3308_ADC_R_CH_BIST_MSK, ++ RK3308_ADC_R_CH_NORMAL_RIGHT); ++ } + } + +-static int rk3308_codec_alc_enable(struct rk3308_codec_priv *rk3308) ++static irqreturn_t rk3308_codec_hpdet_isr(int irq, void *data) + { +- int ch = rk3308->adc_ch; ++ struct rk3308_codec_priv *rk3308 = data; + + /* +- * 1. Set he max level and min level of the ALC need to control. +- * +- * These values are estimated ++ * For the high level irq trigger, disable irq and avoid a lot of ++ * repeated irq handlers entry. + */ +- regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON05(ch), +- RK3308_AGC_LO_8BITS_AGC_MIN_MSK, +- 0x16); +- regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON05(ch), +- RK3308_AGC_HI_8BITS_AGC_MIN_MSK, +- 0x40); +- +- regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON05(ch), +- RK3308_AGC_LO_8BITS_AGC_MAX_MSK, +- 0x26); +- regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON05(ch), +- RK3308_AGC_HI_8BITS_AGC_MAX_MSK, +- 0x40); ++ disable_irq_nosync(rk3308->irq); ++ queue_delayed_work(system_power_efficient_wq, ++ &rk3308->hpdet_work, msecs_to_jiffies(10)); + +- /* +- * 2. Set ACODEC_ALC_DIG_CON4[2:0] according to the sample rate +- * +- * By default is 44.1KHz for sample. +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON04(ch), +- RK3308_AGC_APPROX_RATE_MSK, +- RK3308_AGC_APPROX_RATE_44_1K); +- regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON04(ch), +- RK3308_AGC_APPROX_RATE_MSK, +- RK3308_AGC_APPROX_RATE_44_1K); +- +- /* 3. Set ACODEC_ALC_DIG_CON9[6] to 0x1, to enable the ALC module */ +- regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), +- RK3308_AGC_FUNC_SEL_MSK, +- RK3308_AGC_FUNC_SEL_EN); +- regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(ch), +- RK3308_AGC_FUNC_SEL_MSK, +- RK3308_AGC_FUNC_SEL_EN); ++ return IRQ_HANDLED; ++} + +- /* +- * 4. Set ACODEC_ADC_ANA_CON11[1:0], (ACODEC_ADC_ANA_CON11+0x40)[1:0], +- * (ACODEC_ADC_ANA_CON11+0x80)[1:0] and (ACODEC_ADC_ANA_CON11+0xc0)[1:0] +- * to 0x3, to enable the ALC module to control the gain of PGA. +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(ch), +- RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK | +- RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK, +- RK3308_ADC_ALCL_CON_GAIN_PGAL_EN | +- RK3308_ADC_ALCR_CON_GAIN_PGAR_EN); ++void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_codec *codec, ++ struct snd_soc_jack *hpdet_jack); ++EXPORT_SYMBOL_GPL(rk3308_codec_set_jack_detect_cb); + +- /* +- * 5.Observe the current ALC output gain by reading +- * ACODEC_ALC_DIG_CON12[4:0] +- * +- * The default GAIN is 0x0c +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON12(ch), +- RK3308_AGC_GAIN_MSK, +- 0x0c); +- regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON12(ch), +- RK3308_AGC_GAIN_MSK, +- 0x0c); ++static void rk3308_codec_set_jack_detect(struct snd_soc_codec *codec, ++ struct snd_soc_jack *hpdet_jack) ++{ ++ struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); + +- return 0; +-} ++ rk3308->hpdet_jack = hpdet_jack; + +-static int rk3308_codec_alc_disable(struct rk3308_codec_priv *rk3308) +-{ +- int ch = rk3308->adc_ch; ++ /* To detect jack once during startup */ ++ disable_irq_nosync(rk3308->irq); ++ queue_delayed_work(system_power_efficient_wq, ++ &rk3308->hpdet_work, msecs_to_jiffies(10)); + +- /* +- * 1. Set ACODEC_ALC_DIG_CON9[6] to 0x0, to disable the ALC module, +- * then the ALC output gain will keep to the last value +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), +- RK3308_AGC_FUNC_SEL_MSK, +- RK3308_AGC_FUNC_SEL_DIS); +- regmap_update_bits(rk3308->regmap, RK3308_ALC_R_DIG_CON09(ch), +- RK3308_AGC_FUNC_SEL_MSK, +- RK3308_AGC_FUNC_SEL_DIS); ++ dev_info(rk3308->plat_dev, "%s: Request detect hp jack once\n", ++ __func__); ++} + +- /* +- * 2. Set ACODEC_ADC_ANA_CON11[1:0], (ACODEC_ADC_ANA_CON11+0x40)[1:0], +- * (ACODEC_ADC_ANA_CON11+0x80)[1:0] and (ACODEC_ADC_ANA_CON11+0xc0)[1:0] +- * to 0x0, to disable the ALC module to control the gain of PGA. +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON11(ch), +- RK3308_ADC_ALCL_CON_GAIN_PGAL_MSK | +- RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK, +- RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS | +- RK3308_ADC_ALCR_CON_GAIN_PGAR_DIS); ++static const struct regmap_config rk3308_codec_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = RK3308_DAC_ANA_CON15, ++ .writeable_reg = rk3308_codec_write_read_reg, ++ .readable_reg = rk3308_codec_write_read_reg, ++ .volatile_reg = rk3308_codec_volatile_reg, ++ .reg_defaults = rk3308_codec_reg_defaults, ++ .num_reg_defaults = ARRAY_SIZE(rk3308_codec_reg_defaults), ++ .cache_type = REGCACHE_FLAT, ++}; + +- return 0; ++static ssize_t pm_state_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ ++ return sprintf(buf, "pm_state: %d\n", rk3308->pm_state); + } + +-static int rk3308_codec_adc_ana_enable(struct rk3308_codec_priv *rk3308) ++static ssize_t pm_state_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) + { +- unsigned int adc_aif1 = 0, adc_aif2 = 0; +- unsigned int agc_func_en; +- int ch = rk3308->adc_ch; ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ unsigned long pm_state; ++ int ret = kstrtoul(buf, 10, &pm_state); + +- /* +- * 1. Set the ACODEC_ADC_ANA_CON7[7:6] and ACODEC_ADC_ANA_CON7[5:4], +- * to select the line-in or microphone as input of ADC +- * +- * Note1. Please ignore the step1 for enabling ADC3, ADC4, ADC5, +- * ADC6, ADC7, and ADC8 +- */ +- if (ch == 0) { +- if (rk3308->adc_ch0_using_linein) { +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), +- RK3308_ADC_CH1_IN_SEL_MSK, +- RK3308_ADC_CH1_IN_LINEIN); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), +- RK3308_ADC_CH2_IN_SEL_MSK, +- RK3308_ADC_CH2_IN_LINEIN); +- } else { +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), +- RK3308_ADC_CH1_IN_SEL_MSK, +- RK3308_ADC_CH1_IN_MIC); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON07(ch), +- RK3308_ADC_CH2_IN_SEL_MSK, +- RK3308_ADC_CH2_IN_MIC); +- } ++ if (ret < 0) { ++ dev_err(dev, "Invalid pm_state: %ld, ret: %d\n", ++ pm_state, ret); ++ return -EINVAL; + } + +- /* +- * 2. Set ACODEC_ADC_ANA_CON0[7:0] to 0xff, to end the mute station +- * of ADC, to enable the MIC module, to enable the reference voltage +- * buffer, and to end the initialization of MIC +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(ch), +- RK3308_ADC_CH1_CH2_MIC_ALL_MSK, +- RK3308_ADC_CH1_CH2_MIC_ALL); ++ rk3308_codec_set_pm_state(rk3308, pm_state); + +- /* +- * 3. Set ACODEC_ADC_ANA_CON6[0] to 0x1, to enable the current source +- * of audio +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(ch), +- RK3308_ADC_CURRENT_MSK, +- RK3308_ADC_CURRENT_EN); ++ dev_info(dev, "Store pm_state: %d\n", rk3308->pm_state); + +- /* +- * 4. Set ACODEC_ADC_ANA_CON2[7:0] to 0x77, to enable the ALC module, +- * to enable the zero-crossing detection function, and to end the +- * initialization of ALC +- * +- * Note2. Please set ACODEC_ADC_ANA_CON2[7:0] to 0x33 in step4 +- * if the AGC function is closed +- */ ++ return count; ++} + +- adc_aif1 = RK3308_ADC_CH1_ALC_EN | RK3308_ADC_CH1_ALC_WORK; +- regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), &agc_func_en); +- if (agc_func_en & RK3308_AGC_FUNC_SEL_EN) +- adc_aif1 |= RK3308_ADC_CH1_ZEROCROSS_DET_EN; ++static ssize_t adc_grps_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ u32 grp; ++ int type = ADC_TYPE_NORMAL, count = 0; ++ int idx; ++ ++ count += sprintf(buf + count, "current used adc_grps:\n"); ++ count += sprintf(buf + count, "- normal:"); ++ for (idx = 0; adc_for_each_grp(rk3308, type, idx, &grp); idx++) ++ count += sprintf(buf + count, " %d", grp); ++ count += sprintf(buf + count, "\n"); ++ count += sprintf(buf + count, "- loopback: %d\n", ++ rk3308->loopback_grp); + +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch), +- RK3308_ADC_CH1_ALC_ZC_MSK, +- adc_aif1); ++ return count; ++} + +- adc_aif2 = RK3308_ADC_CH2_ALC_EN | RK3308_ADC_CH2_ALC_WORK; +- regmap_read(rk3308->regmap, RK3308_ALC_L_DIG_CON09(ch), &agc_func_en); +- if (agc_func_en & RK3308_AGC_FUNC_SEL_EN) +- adc_aif2 |= RK3308_ADC_CH2_ZEROCROSS_DET_EN; ++static ssize_t adc_grps_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ char adc_type; ++ int grps, ret; ++ ++ ret = sscanf(buf, "%c,%d", &adc_type, &grps); ++ if (ret != 2) { ++ dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n", ++ __func__, ret); ++ return -EFAULT; ++ } + +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch), +- RK3308_ADC_CH2_ALC_ZC_MSK, +- adc_aif2); ++ if (adc_type == 'n') ++ rk3308->used_adc_grps = grps; ++ else if (adc_type == 'l') ++ rk3308->loopback_grp = grps; + +- /* +- * 5. Set ACODEC_ADC_ANA_CON5[7:0] to 0x77, to enable the clock and +- * ADC module, and to end the initialization of ADC +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), +- RK3308_ADC_CH1_ADC_CLK_MSK, +- RK3308_ADC_CH1_CLK_EN | +- RK3308_ADC_CH1_ADC_EN | +- RK3308_ADC_CH1_ADC_WORK); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), +- RK3308_ADC_CH2_ADC_CLK_MSK, +- RK3308_ADC_CH2_CLK_EN | +- RK3308_ADC_CH2_ADC_EN | +- RK3308_ADC_CH2_ADC_WORK); ++ return count; ++} + +- /* +- * 6. Set ACODEC_ADC_ANA_CON1[5:4] and ACODEC_ADC_ANA_CON1[1:0], +- * to select the gain of the MIC +- * +- * By default is 0db. +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), +- RK3308_ADC_CH1_MIC_GAIN_MSK, +- RK3308_ADC_CH1_MIC_GAIN_0DB); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), +- RK3308_ADC_CH2_MIC_GAIN_MSK, +- RK3308_ADC_CH2_MIC_GAIN_0DB); ++static ssize_t adc_grps_route_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ char which_i2s[32] = {0}; ++ int count = 0; ++ u32 grp; + +- /* +- * 7.Set ACODEC_ADC_ANA_CON3[4:0] and ACODEC_ADC_ANA_CON4[3:0] to +- * select the gain of ALC +- * +- * By default is 0db. +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON03(ch), +- RK3308_ADC_CH1_ALC_GAIN_MSK, +- RK3308_ADC_CH1_ALC_GAIN_0DB); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON04(ch), +- RK3308_ADC_CH2_ALC_GAIN_MSK, +- RK3308_ADC_CH2_ALC_GAIN_0DB); ++ switch (rk3308->which_i2s) { ++ case ACODEC_TO_I2S1_2CH: ++ strcpy(which_i2s, "i2s1_2ch"); ++ break; ++ case ACODEC_TO_I2S3_4CH: ++ strcpy(which_i2s, "i2s3_4ch"); ++ break; ++ default: ++ strcpy(which_i2s, "i2s2_8ch"); ++ break; ++ } + +- /* 8.Begin recording */ ++ count += sprintf(buf + count, "%s from acodec route mapping:\n", ++ which_i2s); ++ for (grp = 0; grp < rk3308->to_i2s_grps; grp++) { ++ count += sprintf(buf + count, "* sdi_%d <-- sdo_%d\n", ++ grp, rk3308->i2s_sdis[grp]); ++ } + +- return 0; ++ return count; + } + +-static int rk3308_codec_adc_ana_disable(struct rk3308_codec_priv *rk3308) ++static ssize_t adc_grps_route_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) + { +- int ch = rk3308->adc_ch; ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ int which_i2s, idx, i2s_sdis[ADC_LR_GROUP_MAX]; ++ int ret; + +- /* +- * 1. Set ACODEC_ADC_ANA_CON2[7:0] to 0x0, to disable the ALC module, +- * to disable the zero-crossing detection function, and to begin the +- * initialization of ALC +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch), +- RK3308_ADC_CH1_ALC_ZC_MSK, +- 0); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON02(ch), +- RK3308_ADC_CH2_ALC_ZC_MSK, +- 0); ++ ret = sscanf(buf, "%d,%d,%d,%d,%d", &which_i2s, ++ &i2s_sdis[0], &i2s_sdis[1], &i2s_sdis[2], &i2s_sdis[3]); ++ if (ret != 5) { ++ dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n", ++ __func__, ret); ++ goto err; ++ } + +- /* +- * 2. Set ACODEC_ADC_ANA_CON5[7:0] to 0x0, to disable the clock and +- * ADC module, and to begin the initialization of ADC +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), +- RK3308_ADC_CH1_ADC_CLK_MSK, +- 0); +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON05(ch), +- RK3308_ADC_CH2_ADC_CLK_MSK, +- 0); ++ if (which_i2s < ACODEC_TO_I2S2_8CH || ++ which_i2s > ACODEC_TO_I2S1_2CH) { ++ dev_err(rk3308->plat_dev, "Invalid i2s type: %d\n", which_i2s); ++ goto err; ++ } + +- /* +- * 3. Set ACODEC_ADC_ANA_CON0[7:0] to 0x88, to disable the MIC module, +- * to disable the reference voltage buffer, and to begin the +- * initialization of MIC +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON00(ch), +- RK3308_ADC_CH1_CH2_MIC_ALL_MSK, +- RK3308_ADC_CH1_MIC_UNMUTE | +- RK3308_ADC_CH2_MIC_UNMUTE); ++ rk3308->which_i2s = which_i2s; + +- /* +- * 4. Set ACODEC_ADC_ANA_CON6[0] to 0x0, to disable the current +- * source of audio +- */ +- regmap_update_bits(rk3308->regmap, RK3308_ADC_ANA_CON06(ch), +- RK3308_ADC_CURRENT_MSK, +- RK3308_ADC_CURRENT_DIS); ++ switch (rk3308->which_i2s) { ++ case ACODEC_TO_I2S1_2CH: ++ rk3308->to_i2s_grps = 1; ++ break; ++ case ACODEC_TO_I2S3_4CH: ++ rk3308->to_i2s_grps = 2; ++ break; ++ default: ++ rk3308->to_i2s_grps = 4; ++ break; ++ } + +- return 0; ++ for (idx = 0; idx < rk3308->to_i2s_grps; idx++) ++ rk3308->i2s_sdis[idx] = i2s_sdis[idx]; ++ ++ rk3308_codec_adc_grps_route_config(rk3308); ++ ++err: ++ return count; + } + +-static int rk3308_codec_open_capture(struct snd_soc_codec *codec) ++static ssize_t adc_grp0_in_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); +- +- rk3308_codec_alc_enable(rk3308); +- rk3308_codec_adc_ana_enable(rk3308); ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); + +- return 0; ++ return sprintf(buf, "adc ch0 using: %s\n", ++ rk3308->adc_grp0_using_linein ? "line in" : "mic in"); + } + +-static int rk3308_codec_close_capture(struct snd_soc_codec *codec) ++static ssize_t adc_grp0_in_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ unsigned long using_linein; ++ int ret = kstrtoul(buf, 10, &using_linein); ++ ++ if (ret < 0 || using_linein > 1) { ++ dev_err(dev, "Invalid input status: %ld, ret: %d\n", ++ using_linein, ret); ++ return -EINVAL; ++ } + +- rk3308_codec_alc_disable(rk3308); +- rk3308_codec_adc_ana_disable(rk3308); ++ rk3308->adc_grp0_using_linein = using_linein; + +- return 0; ++ dev_info(dev, "store using_linein: %d\n", ++ rk3308->adc_grp0_using_linein); ++ ++ return count; + } + +-static int rk3308_codec_open_playback(struct snd_soc_codec *codec) ++static ssize_t adc_zerocross_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); +- +- rk3308_codec_dac_enable(rk3308); +- rk3308_speaker_ctl(rk3308, 1); ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); + +- return 0; ++ return sprintf(buf, "adc zerocross: %s\n", ++ rk3308->adc_zerocross ? "enabled" : "disabled"); + } + +-static int rk3308_codec_close_playback(struct snd_soc_codec *codec) ++static ssize_t adc_zerocross_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ unsigned long zerocross; ++ int ret = kstrtoul(buf, 10, &zerocross); + +- rk3308_speaker_ctl(rk3308, 0); +- rk3308_codec_dac_disable(rk3308); ++ if (ret < 0 || zerocross > 1) { ++ dev_err(dev, "Invalid zerocross: %ld, ret: %d\n", ++ zerocross, ret); ++ return -EINVAL; ++ } + +- return 0; ++ rk3308->adc_zerocross = zerocross; ++ ++ dev_info(dev, "store adc zerocross: %d\n", rk3308->adc_zerocross); ++ ++ return count; + } + +-static int rk3308_pcm_startup(struct snd_pcm_substream *substream, +- struct snd_soc_dai *dai) ++static ssize_t adc_grps_endisable_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) + { +- struct snd_soc_codec *codec = dai->codec; +- int ret = 0; ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ int count = 0, i; + +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) +- ret = rk3308_codec_open_playback(codec); +- else +- ret = rk3308_codec_open_capture(codec); ++ count += sprintf(buf + count, "enabled adc grps:"); ++ for (i = 0; i < ADC_LR_GROUP_MAX; i++) ++ count += sprintf(buf + count, "%d ", ++ rk3308->adc_grps_endisable[i]); + +- return ret; ++ count += sprintf(buf + count, "\n"); ++ return count; + } + +-static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream, +- struct snd_soc_dai *dai) ++static ssize_t adc_grps_endisable_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) + { +- struct snd_soc_codec *codec = dai->codec; ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ int grp, endisable, ret; + +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) +- rk3308_codec_close_playback(codec); +- else +- rk3308_codec_close_capture(codec); +-} ++ ret = sscanf(buf, "%d,%d", &grp, &endisable); ++ if (ret != 2) { ++ dev_err(rk3308->plat_dev, "%s sscanf failed: %d\n", ++ __func__, ret); ++ return -EFAULT; ++ } + +-static struct snd_soc_dai_ops rk3308_dai_ops = { +- .hw_params = rk3308_hw_params, +- .set_fmt = rk3308_set_dai_fmt, +- .digital_mute = rk3308_digital_mute, +- .startup = rk3308_pcm_startup, +- .shutdown = rk3308_pcm_shutdown, +-}; ++ rk3308->cur_dbg_grp = grp; + +-static struct snd_soc_dai_driver rk3308_dai[] = { +- { +- .name = "rk3308-hifi", +- .id = RK3308_HIFI, +- .playback = { +- .stream_name = "HiFi Playback", +- .channels_min = 2, +- .channels_max = 2, +- .rates = SNDRV_PCM_RATE_8000_96000, +- .formats = (SNDRV_PCM_FMTBIT_S16_LE | +- SNDRV_PCM_FMTBIT_S20_3LE | +- SNDRV_PCM_FMTBIT_S24_LE | +- SNDRV_PCM_FMTBIT_S32_LE), +- }, +- .capture = { +- .stream_name = "HiFi Capture", +- .channels_min = 1, +- .channels_max = 8, +- .rates = SNDRV_PCM_RATE_8000_96000, +- .formats = (SNDRV_PCM_FMTBIT_S16_LE | +- SNDRV_PCM_FMTBIT_S20_3LE | +- SNDRV_PCM_FMTBIT_S24_LE | +- SNDRV_PCM_FMTBIT_S32_LE), +- }, +- .ops = &rk3308_dai_ops, +- }, +-}; ++ if (endisable) ++ rk3308_codec_open_dbg_capture(rk3308); ++ else ++ rk3308_codec_close_dbg_capture(rk3308); + +-static int rk3308_suspend(struct snd_soc_codec *codec) +-{ +- rk3308_set_bias_level(codec, SND_SOC_BIAS_OFF); ++ dev_info(dev, "ADC grp %d endisable: %d\n", grp, endisable); + +- return 0; ++ return count; + } + +-static int rk3308_resume(struct snd_soc_codec *codec) ++static ssize_t dac_endisable_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) + { +- rk3308_set_bias_level(codec, SND_SOC_BIAS_STANDBY); ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); + +- return 0; ++ return sprintf(buf, "%d\n", rk3308->dac_endisable); + } + +-static int rk3308_probe(struct snd_soc_codec *codec) ++static ssize_t dac_endisable_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ unsigned long endisable; ++ int ret = kstrtoul(buf, 10, &endisable); + +- rk3308_codec_reset(codec); +- rk3308_codec_power_on(codec); ++ if (ret < 0) { ++ dev_err(dev, "Invalid endisable: %ld, ret: %d\n", ++ endisable, ret); ++ return -EINVAL; ++ } ++ ++ if (endisable) ++ rk3308_codec_open_playback(rk3308); ++ else ++ rk3308_codec_close_playback(rk3308); + +- rk3308_codec_micbias_enable(rk3308, RK3308_ADC_MICBIAS_VOLT_0_7); ++ dev_info(dev, "DAC endisable: %ld\n", endisable); + +- return 0; ++ return count; + } + +-static int rk3308_remove(struct snd_soc_codec *codec) ++static ssize_t dac_output_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ ssize_t ret = 0; + +- rk3308_speaker_ctl(rk3308, 0); +- rk3308_codec_micbias_disable(rk3308); +- rk3308_codec_power_off(codec); ++ switch (rk3308->dac_output) { ++ case DAC_LINEOUT: ++ ret = sprintf(buf, "dac path: %s\n", "line out"); ++ break; ++ case DAC_HPOUT: ++ ret = sprintf(buf, "dac path: %s\n", "hp out"); ++ break; ++ case DAC_LINEOUT_HPOUT: ++ ret = sprintf(buf, "dac path: %s\n", ++ "both line out and hp out"); ++ break; ++ default: ++ pr_err("Invalid dac path: %d ?\n", rk3308->dac_output); ++ break; ++ } + +- return 0; ++ return ret; + } + +-static struct snd_soc_codec_driver soc_codec_dev_rk3308 = { +- .probe = rk3308_probe, +- .remove = rk3308_remove, +- .suspend = rk3308_suspend, +- .resume = rk3308_resume, +- .set_bias_level = rk3308_set_bias_level, +- .controls = rk3308_codec_dapm_controls, +- .num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls), +-}; +- +-static const struct reg_default rk3308_codec_reg_defaults[] = { +- { RK3308_GLB_CON, 0x07 }, +-}; +- +-static bool rk3308_codec_write_read_reg(struct device *dev, unsigned int reg) ++static ssize_t dac_output_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) + { +- /* All registers can be read / write */ +- return true; +-} ++ struct rk3308_codec_priv *rk3308 = ++ container_of(dev, struct rk3308_codec_priv, dev); ++ unsigned long dac_output; ++ int ret = kstrtoul(buf, 10, &dac_output); + +-static bool rk3308_codec_volatile_reg(struct device *dev, unsigned int reg) +-{ +- switch (reg) { +- case RK3308_GLB_CON: +- return true; +- default: +- return false; ++ if (ret < 0) { ++ dev_err(dev, "Invalid input status: %ld, ret: %d\n", ++ dac_output, ret); ++ return -EINVAL; + } +-} + +-static const struct regmap_config rk3308_codec_regmap_config = { +- .reg_bits = 32, +- .reg_stride = 4, +- .val_bits = 32, +- .max_register = RK3308_DAC_ANA_CON13, +- .writeable_reg = rk3308_codec_write_read_reg, +- .readable_reg = rk3308_codec_write_read_reg, +- .volatile_reg = rk3308_codec_volatile_reg, +- .reg_defaults = rk3308_codec_reg_defaults, +- .num_reg_defaults = ARRAY_SIZE(rk3308_codec_reg_defaults), +- .cache_type = REGCACHE_FLAT, +-}; ++ rk3308_codec_dac_switch(rk3308, dac_output); + +-static ssize_t adc_ch_show(struct device *dev, +- struct device_attribute *attr, +- char *buf) ++ dev_info(dev, "Store dac_output: %d\n", rk3308->dac_output); ++ ++ return count; ++} ++ ++static ssize_t enable_all_adcs_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) + { + struct rk3308_codec_priv *rk3308 = + container_of(dev, struct rk3308_codec_priv, dev); + +- return sprintf(buf, "adc_ch: %d\n", rk3308->adc_ch); ++ return sprintf(buf, "%d\n", rk3308->enable_all_adcs); + } + +-static ssize_t adc_ch_store(struct device *dev, +- struct device_attribute *attr, +- const char *buf, size_t count) ++static ssize_t enable_all_adcs_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) + { + struct rk3308_codec_priv *rk3308 = + container_of(dev, struct rk3308_codec_priv, dev); +- unsigned long ch; +- int ret = kstrtoul(buf, 10, &ch); ++ unsigned long enable; ++ int ret = kstrtoul(buf, 10, &enable); + +- if (ret < 0 || ch > 4) { +- dev_err(dev, "Invalid ch: %ld, ret: %d\n", ch, ret); ++ if (ret < 0) { ++ dev_err(dev, "Invalid enable value: %ld, ret: %d\n", ++ enable, ret); + return -EINVAL; + } + +- rk3308->adc_ch = ch; +- +- dev_info(dev, "Store ch: %d\n", rk3308->adc_ch); ++ rk3308->enable_all_adcs = enable; + + return count; + } + +-static const struct device_attribute adc_ch_attrs[] = { +- __ATTR(adc_ch, 0644, adc_ch_show, adc_ch_store), ++static const struct device_attribute acodec_attrs[] = { ++ __ATTR_RW(adc_grps), ++ __ATTR_RW(adc_grps_endisable), ++ __ATTR_RW(adc_grps_route), ++ __ATTR_RW(adc_grp0_in), ++ __ATTR_RW(adc_zerocross), ++ __ATTR_RW(dac_endisable), ++ __ATTR_RW(dac_output), ++ __ATTR_RW(enable_all_adcs), ++ __ATTR_RW(pm_state), + }; + + static void rk3308_codec_device_release(struct device *dev) +@@ -1468,8 +4747,8 @@ static int rk3308_codec_sysfs_init(struct platform_device *pdev, + return -ENOMEM; + } + +- for (i = 0; i < ARRAY_SIZE(adc_ch_attrs); i++) { +- if (device_create_file(dev, &adc_ch_attrs[i])) { ++ for (i = 0; i < ARRAY_SIZE(acodec_attrs); i++) { ++ if (device_create_file(dev, &acodec_attrs[i])) { + dev_err(&pdev->dev, + "Create 'rk3308-acodec-dev' attr failed\n"); + device_unregister(dev); +@@ -1480,32 +4759,136 @@ static int rk3308_codec_sysfs_init(struct platform_device *pdev, + return 0; + } + ++#if defined(CONFIG_DEBUG_FS) ++static int rk3308_codec_debugfs_reg_show(struct seq_file *s, void *v) ++{ ++ struct rk3308_codec_priv *rk3308 = s->private; ++ unsigned int i; ++ unsigned int val; ++ ++ for (i = RK3308_GLB_CON; i <= RK3308_DAC_ANA_CON13; i += 4) { ++ regmap_read(rk3308->regmap, i, &val); ++ if (!(i % 16)) ++ seq_printf(s, "\nR:%04x: ", i); ++ seq_printf(s, "%08x ", val); ++ } ++ ++ seq_puts(s, "\n"); ++ ++ return 0; ++} ++ ++static ssize_t rk3308_codec_debugfs_reg_operate(struct file *file, ++ const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct rk3308_codec_priv *rk3308 = ++ ((struct seq_file *)file->private_data)->private; ++ unsigned int reg, val; ++ char op; ++ char kbuf[32]; ++ int ret; ++ ++ if (count >= sizeof(kbuf)) ++ return -EINVAL; ++ ++ if (copy_from_user(kbuf, buf, count)) ++ return -EFAULT; ++ kbuf[count] = '\0'; ++ ++ ret = sscanf(kbuf, "%c,%x,%x", &op, ®, &val); ++ if (ret != 3) { ++ pr_err("sscanf failed: %d\n", ret); ++ return -EFAULT; ++ } ++ ++ if (op == 'w') { ++ pr_info("Write reg: 0x%04x with val: 0x%08x\n", reg, val); ++ regmap_write(rk3308->regmap, reg, val); ++ regcache_cache_only(rk3308->regmap, false); ++ regcache_sync(rk3308->regmap); ++ pr_info("Read back reg: 0x%04x with val: 0x%08x\n", reg, val); ++ } else if (op == 'r') { ++ regmap_read(rk3308->regmap, reg, &val); ++ pr_info("Read reg: 0x%04x with val: 0x%08x\n", reg, val); ++ } else { ++ pr_err("This is an invalid operation: %c\n", op); ++ } ++ ++ return count; ++} ++ ++static int rk3308_codec_debugfs_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ++ rk3308_codec_debugfs_reg_show, inode->i_private); ++} ++ ++static const struct file_operations rk3308_codec_reg_debugfs_fops = { ++ .owner = THIS_MODULE, ++ .open = rk3308_codec_debugfs_open, ++ .read = seq_read, ++ .write = rk3308_codec_debugfs_reg_operate, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++#endif /* CONFIG_DEBUG_FS */ ++ ++static int rk3308_codec_get_version(struct rk3308_codec_priv *rk3308) ++{ ++ unsigned int chip_id; ++ ++ regmap_read(rk3308->grf, GRF_CHIP_ID, &chip_id); ++ switch (chip_id) { ++ case 3306: ++ rk3308->codec_ver = ACODEC_VERSION_A; ++ break; ++ case 0x3308: ++ rk3308->codec_ver = ACODEC_VERSION_B; ++ break; ++ default: ++ pr_err("Unknown chip_id: %d / 0x%x\n", chip_id, chip_id); ++ return -EFAULT; ++ } ++ ++ pr_info("The acodec version is: %x\n", rk3308->codec_ver); ++ return 0; ++} ++ + static int rk3308_platform_probe(struct platform_device *pdev) + { + struct device_node *np = pdev->dev.of_node; + struct rk3308_codec_priv *rk3308; + struct resource *res; + void __iomem *base; +- int ret = 0; +- struct regmap *grf; +- +- grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); +- if (IS_ERR(grf)) { +- dev_err(&pdev->dev, +- "Missing 'rockchip,grf' property\n"); +- return PTR_ERR(grf); +- } ++ int ret; + + rk3308 = devm_kzalloc(&pdev->dev, sizeof(*rk3308), GFP_KERNEL); + if (!rk3308) + return -ENOMEM; + ++ rk3308->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); ++ if (IS_ERR(rk3308->grf)) { ++ dev_err(&pdev->dev, ++ "Missing 'rockchip,grf' property\n"); ++ return PTR_ERR(rk3308->grf); ++ } ++ + ret = rk3308_codec_sysfs_init(pdev, rk3308); + if (ret < 0) { + dev_err(&pdev->dev, "Sysfs init failed\n"); + return ret; + } + ++#if defined(CONFIG_DEBUG_FS) ++ rk3308->dbg_codec = debugfs_create_dir(CODEC_DRV_NAME, NULL); ++ if (IS_ERR(rk3308->dbg_codec)) ++ dev_err(&pdev->dev, ++ "Failed to create debugfs dir for rk3308!\n"); ++ else ++ debugfs_create_file("reg", 0644, rk3308->dbg_codec, ++ rk3308, &rk3308_codec_reg_debugfs_fops); ++#endif + rk3308->plat_dev = &pdev->dev; + + rk3308->reset = devm_reset_control_get(&pdev->dev, "acodec-reset"); +@@ -1518,27 +4901,146 @@ static int rk3308_platform_probe(struct platform_device *pdev) + rk3308->reset = NULL; + } + +- /* GPIO0_A5 control speaker on RK3308 EVB */ +- rk3308->spk_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "spk_ctl", +- GPIOD_OUT_HIGH); +- if (IS_ERR(rk3308->spk_ctl_gpio)) { ++ rk3308->hp_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "hp-ctl", ++ GPIOD_OUT_LOW); ++ if (!rk3308->hp_ctl_gpio) { ++ dev_info(&pdev->dev, "Don't need hp-ctl gpio\n"); ++ } else if (IS_ERR(rk3308->hp_ctl_gpio)) { ++ ret = PTR_ERR(rk3308->hp_ctl_gpio); ++ dev_err(&pdev->dev, "Unable to claim gpio hp-ctl\n"); ++ return ret; ++ } ++ ++ rk3308->spk_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "spk-ctl", ++ GPIOD_OUT_LOW); ++ ++ if (!rk3308->spk_ctl_gpio) { ++ dev_info(&pdev->dev, "Don't need spk-ctl gpio\n"); ++ } else if (IS_ERR(rk3308->spk_ctl_gpio)) { + ret = PTR_ERR(rk3308->spk_ctl_gpio); +- dev_err(&pdev->dev, "Unable to claim gpio spk_ctl\n"); ++ dev_err(&pdev->dev, "Unable to claim gpio spk-ctl\n"); ++ return ret; ++ } ++ ++ rk3308->pa_drv_gpio = devm_gpiod_get_optional(&pdev->dev, "pa-drv", ++ GPIOD_OUT_LOW); ++ ++ if (!rk3308->pa_drv_gpio) { ++ dev_info(&pdev->dev, "Don't need pa-drv gpio\n"); ++ } else if (IS_ERR(rk3308->pa_drv_gpio)) { ++ ret = PTR_ERR(rk3308->pa_drv_gpio); ++ dev_err(&pdev->dev, "Unable to claim gpio pa-drv\n"); + return ret; + } + ++ if (rk3308->pa_drv_gpio) { ++ rk3308->delay_pa_drv_ms = PA_DRV_MS; ++ ret = of_property_read_u32(np, "rockchip,delay-pa-drv-ms", ++ &rk3308->delay_pa_drv_ms); ++ } ++ ++#if DEBUG_POP_ALWAYS ++ dev_info(&pdev->dev, "Enable all ctl gpios always for debugging pop\n"); ++ rk3308_headphone_ctl(rk3308, 1); ++ rk3308_speaker_ctl(rk3308, 1); ++#else ++ dev_info(&pdev->dev, "De-pop as much as possible\n"); ++ rk3308_headphone_ctl(rk3308, 0); ++ rk3308_speaker_ctl(rk3308, 0); ++#endif ++ + rk3308->pclk = devm_clk_get(&pdev->dev, "acodec"); + if (IS_ERR(rk3308->pclk)) { + dev_err(&pdev->dev, "Can't get acodec pclk\n"); + return PTR_ERR(rk3308->pclk); + } + ++ rk3308->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx"); ++ if (IS_ERR(rk3308->mclk_rx)) { ++ dev_err(&pdev->dev, "Can't get acodec mclk_rx\n"); ++ return PTR_ERR(rk3308->mclk_rx); ++ } ++ ++ rk3308->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx"); ++ if (IS_ERR(rk3308->mclk_tx)) { ++ dev_err(&pdev->dev, "Can't get acodec mclk_tx\n"); ++ return PTR_ERR(rk3308->mclk_tx); ++ } ++ + ret = clk_prepare_enable(rk3308->pclk); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to enable acodec pclk: %d\n", ret); + return ret; + } + ++ ret = clk_prepare_enable(rk3308->mclk_rx); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to enable i2s mclk_rx: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(rk3308->mclk_tx); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to enable i2s mclk_tx: %d\n", ret); ++ return ret; ++ } ++ ++ rk3308_codec_check_micbias(rk3308, np); ++ ++ rk3308->enable_all_adcs = ++ of_property_read_bool(np, "rockchip,enable-all-adcs"); ++ ++ rk3308->hp_jack_reversed = ++ of_property_read_bool(np, "rockchip,hp-jack-reversed"); ++ ++ rk3308->no_deep_low_power = ++ of_property_read_bool(np, "rockchip,no-deep-low-power"); ++ ++ rk3308->no_hp_det = ++ of_property_read_bool(np, "rockchip,no-hp-det"); ++ ++ rk3308->delay_loopback_handle_ms = LOOPBACK_HANDLE_MS; ++ ret = of_property_read_u32(np, "rockchip,delay-loopback-handle-ms", ++ &rk3308->delay_loopback_handle_ms); ++ ++ rk3308->delay_start_play_ms = 0; ++ ret = of_property_read_u32(np, "rockchip,delay-start-play-ms", ++ &rk3308->delay_start_play_ms); ++ ++ rk3308->loopback_grp = NOT_USED; ++ ret = of_property_read_u32(np, "rockchip,loopback-grp", ++ &rk3308->loopback_grp); ++ /* ++ * If there is no loopback on some board, the -EINVAL indicates that ++ * we don't need add the node, and it is not an error. ++ */ ++ if (ret < 0 && ret != -EINVAL) { ++ dev_err(&pdev->dev, "Failed to read loopback property: %d\n", ++ ret); ++ return ret; ++ } ++ ++ ret = rk3308_codec_adc_grps_route(rk3308, np); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to route ADC groups: %d\n", ++ ret); ++ return ret; ++ } ++ ++ ret = rk3308_codec_setup_en_always_adcs(rk3308, np); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to setup enabled always ADCs: %d\n", ++ ret); ++ return ret; ++ } ++ ++ ret = rk3308_codec_get_version(rk3308); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to get acodec version: %d\n", ++ ret); ++ return ret; ++ } ++ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { +@@ -1555,10 +5057,65 @@ static int rk3308_platform_probe(struct platform_device *pdev) + goto failed; + } + ++ if (!rk3308->no_hp_det) { ++ int index = 0; ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) ++ index = 1; ++ ++ rk3308->irq = platform_get_irq(pdev, index); ++ if (rk3308->irq < 0) { ++ dev_err(&pdev->dev, "Can not get codec irq\n"); ++ goto failed; ++ } ++ ++ INIT_DELAYED_WORK(&rk3308->hpdet_work, rk3308_codec_hpdetect_work); ++ ++ ret = devm_request_irq(&pdev->dev, rk3308->irq, ++ rk3308_codec_hpdet_isr, ++ 0, ++ "acodec-hpdet", ++ rk3308); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to request IRQ: %d\n", ret); ++ goto failed; ++ } ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_B) { ++ rk3308->detect_grf = ++ syscon_regmap_lookup_by_phandle(np, "rockchip,detect-grf"); ++ if (IS_ERR(rk3308->detect_grf)) { ++ dev_err(&pdev->dev, ++ "Missing 'rockchip,detect-grf' property\n"); ++ return PTR_ERR(rk3308->detect_grf); ++ } ++ ++ /* Configure filter count and enable hpdet irq. */ ++ regmap_write(rk3308->detect_grf, ++ DETECT_GRF_ACODEC_HPDET_COUNTER, ++ DEFAULT_HPDET_COUNT); ++ regmap_write(rk3308->detect_grf, ++ DETECT_GRF_ACODEC_HPDET_CON, ++ (HPDET_BOTH_NEG_POS << 16) | ++ HPDET_BOTH_NEG_POS); ++ } ++ ++ rk3308_codec_set_jack_detect_cb = rk3308_codec_set_jack_detect; ++ } ++ ++ if (rk3308->codec_ver == ACODEC_VERSION_A) ++ INIT_DELAYED_WORK(&rk3308->loopback_work, ++ rk3308_codec_loopback_work); ++ ++ rk3308->adc_grp0_using_linein = ADC_GRP0_MICIN; ++ rk3308->dac_output = DAC_LINEOUT; ++ rk3308->adc_zerocross = 1; ++ rk3308->pm_state = PM_NORMAL; ++ + platform_set_drvdata(pdev, rk3308); + + ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_rk3308, +- rk3308_dai, ARRAY_SIZE(rk3308_dai)); ++ rk3308_dai, ARRAY_SIZE(rk3308_dai)); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register codec: %d\n", ret); + goto failed; +@@ -1567,7 +5124,10 @@ static int rk3308_platform_probe(struct platform_device *pdev) + return ret; + + failed: ++ clk_disable_unprepare(rk3308->mclk_rx); ++ clk_disable_unprepare(rk3308->mclk_tx); + clk_disable_unprepare(rk3308->pclk); ++ device_unregister(&rk3308->dev); + + return ret; + } +@@ -1577,8 +5137,11 @@ static int rk3308_platform_remove(struct platform_device *pdev) + struct rk3308_codec_priv *rk3308 = + (struct rk3308_codec_priv *)platform_get_drvdata(pdev); + ++ clk_disable_unprepare(rk3308->mclk_rx); ++ clk_disable_unprepare(rk3308->mclk_tx); + clk_disable_unprepare(rk3308->pclk); + snd_soc_unregister_codec(&pdev->dev); ++ device_unregister(&rk3308->dev); + + return 0; + } +@@ -1591,7 +5154,7 @@ MODULE_DEVICE_TABLE(of, rk3308codec_of_match); + + static struct platform_driver rk3308_codec_driver = { + .driver = { +- .name = "rk3308-acodec", ++ .name = CODEC_DRV_NAME, + .of_match_table = of_match_ptr(rk3308codec_of_match), + }, + .probe = rk3308_platform_probe, +diff --git a/sound/soc/codecs/rk3308_codec.h b/sound/soc/codecs/rk3308_codec.h +index 6cfa69157785..93e089dae081 100644 +--- a/sound/soc/codecs/rk3308_codec.h ++++ b/sound/soc/codecs/rk3308_codec.h +@@ -26,7 +26,8 @@ + #define ACODEC_ADC_I2S_CTL0 0x04 /* REG 0x01 */ + #define ACODEC_ADC_I2S_CTL1 0x08 /* REG 0x02 */ + #define ACODEC_ADC_BIST_MODE_SEL 0x0c /* REG 0x03 */ +-/* Resevred REG 0x04 ~ 0x06 */ ++#define ACODEC_ADC_HPF_PATH 0x10 /* REG 0x04 */ ++/* Resevred REG 0x05 ~ 0x06 */ + #define ACODEC_ADC_DATA_PATH 0x1c /* REG 0x07 */ + /* Resevred REG 0x08 ~ 0x0f */ + +@@ -62,12 +63,15 @@ + #define ACODEC_DAC_I2S_CTL0 0x04 /* REG 0x01 */ + #define ACODEC_DAC_I2S_CTL1 0x08 /* REG 0x02 */ + #define ACODEC_DAC_BIST_MODE_SEL 0x0c /* REG 0x03 */ +-/* Resevred REG 0x04 */ ++#define ACODEC_DAC_DIGITAL_GAIN 0x10 /* REG 0x04 */ + #define ACODEC_DAC_DATA_SEL 0x14 /* REG 0x05 */ + /* Resevred REG 0x06 ~ 0x09 */ + #define ACODEC_DAC_DATA_HI 0x28 /* REG 0x0a */ + #define ACODEC_DAC_DATA_LO 0x2c /* REG 0x0b */ +-/* Resevred REG 0x0c ~ 0x0f */ ++/* Resevred REG 0x0c */ ++#define ACODEC_DAC_HPDET_DELAYTIME 0x34 /* REG 0x0d */ ++#define ACODEC_DAC_HPDET_STATUS 0x38 /* REG 0x0e, Read-only */ ++/* Resevred REG 0x0f */ + + /* ADC ANALOG REGISTERS */ + #define ACODEC_ADC_ANA_MIC_CTL 0x00 /* REG 0x00 */ +@@ -92,10 +96,13 @@ + #define ACODEC_DAC_ANA_LINEOUT 0x10 /* REG 0x04 */ + #define ACODEC_DAC_ANA_L_HPOUT_GAIN 0x14 /* REG 0x05 */ + #define ACODEC_DAC_ANA_R_HPOUT_GAIN 0x18 /* REG 0x06 */ ++#define ACODEC_DAC_ANA_DRV_HPOUT 0x1c /* REG 0x07 */ ++#define ACODEC_DAC_ANA_DRV_LINEOUT 0x20 /* REG 0x08 */ + /* Resevred REG 0x07 ~ 0x0b */ + #define ACODEC_DAC_ANA_HPMIX_CTL0 0x30 /* REG 0x0c */ + #define ACODEC_DAC_ANA_HPMIX_CTL1 0x34 /* REG 0x0d */ +-/* Resevred REG 0x0e ~ 0x0f */ ++#define ACODEC_DAC_ANA_LINEOUT_CTL0 0x38 /* REG 0x0e */ ++#define ACODEC_DAC_ANA_LINEOUT_CTL1 0x3c /* REG 0x0f */ + + /* + * These registers are referenced by codec driver +@@ -106,7 +113,7 @@ + /* ADC DIGITAL REGISTERS */ + + /* +- * The ADC chanel are 0 ~ 3, that control: ++ * The ADC group are 0 ~ 3, that control: + * + * CH0: left_0(ADC1) and right_0(ADC2) + * CH1: left_1(ADC3) and right_1(ADC4) +@@ -118,6 +125,7 @@ + #define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL0) + #define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_I2S_CTL1) + #define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_BIST_MODE_SEL) ++#define RK3308_ADC_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_HPF_PATH) + #define RK3308_ADC_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_DATA_PATH) + + #define RK3308_ALC_L_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET(ch) + ACODEC_ADC_PGA_AGC_L_CTL0) +@@ -150,13 +158,16 @@ + #define RK3308_DAC_DIG_CON01 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL0) + #define RK3308_DAC_DIG_CON02 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_I2S_CTL1) + #define RK3308_DAC_DIG_CON03 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_BIST_MODE_SEL) ++#define RK3308_DAC_DIG_CON04 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DIGITAL_GAIN) + #define RK3308_DAC_DIG_CON05 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_SEL) + #define RK3308_DAC_DIG_CON10 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_HI) + #define RK3308_DAC_DIG_CON11 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_DATA_LO) ++#define RK3308_DAC_DIG_CON13 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_DELAYTIME) ++#define RK3308_DAC_DIG_CON14 (RK3308_DAC_DIG_OFFSET + ACODEC_DAC_HPDET_STATUS) + + /* ADC ANALOG REGISTERS */ + /* +- * The ADC chanel are 0 ~ 3, that control: ++ * The ADC group are 0 ~ 3, that control: + * + * CH0: left_0(ADC1) and right_0(ADC2) + * CH1: left_1(ADC3) and right_1(ADC4) +@@ -179,7 +190,6 @@ + + /* DAC ANALOG REGISTERS */ + #define RK3308_DAC_ANA_OFFSET 0x440 +- + #define RK3308_DAC_ANA_CON00 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL0) + #define RK3308_DAC_ANA_CON01 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_POP_VOLT) + #define RK3308_DAC_ANA_CON02 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_CTL1) +@@ -187,8 +197,12 @@ + #define RK3308_DAC_ANA_CON04 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT) + #define RK3308_DAC_ANA_CON05 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_L_HPOUT_GAIN) + #define RK3308_DAC_ANA_CON06 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_R_HPOUT_GAIN) ++#define RK3308_DAC_ANA_CON07 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_DRV_HPOUT) ++#define RK3308_DAC_ANA_CON08 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_DRV_LINEOUT) + #define RK3308_DAC_ANA_CON12 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL0) + #define RK3308_DAC_ANA_CON13 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_HPMIX_CTL1) ++#define RK3308_DAC_ANA_CON14 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT_CTL0) ++#define RK3308_DAC_ANA_CON15 (RK3308_DAC_ANA_OFFSET + ACODEC_DAC_ANA_LINEOUT_CTL1) + + /* + * These are the bits for registers +@@ -199,6 +213,12 @@ + #define RK3308_ADC_BIST_RESET (0 << 7) + #define RK3308_DAC_BIST_WORK (1 << 6) + #define RK3308_DAC_BIST_RESET (0 << 6) ++#define RK3308_ADC_MCLK_MSK (1 << 5) ++#define RK3308_ADC_MCLK_DIS (1 << 5) ++#define RK3308_ADC_MCLK_EN (0 << 5) ++#define RK3308_DAC_MCLK_MSK (1 << 4) ++#define RK3308_DAC_MCLK_DIS (1 << 4) ++#define RK3308_DAC_MCLK_EN (0 << 4) + #define RK3308_CODEC_RST_MSK (0x7 << 0) + #define RK3308_ADC_DIG_WORK (1 << 2) + #define RK3308_ADC_DIG_RESET (0 << 2) +@@ -253,16 +273,27 @@ + /* RK3308_ADC_DIG_CON03 - REG: 0x000c */ + #define RK3308_ADC_L_CH_BIST_SFT 2 + #define RK3308_ADC_L_CH_BIST_MSK (0x3 << RK3308_ADC_L_CH_BIST_SFT) +-#define RK3308_ADC_L_CH_BIST_LEFT (0x3 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */ +-#define RK3308_ADC_L_CH_BIST_SINE (0x2 << RK3308_ADC_L_CH_BIST_SFT) +-#define RK3308_ADC_L_CH_BIST_CUBE (0x1 << RK3308_ADC_L_CH_BIST_SFT) +-#define RK3308_ADC_L_CH_BIST_RIGHT (0x0 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */ ++#define RK3308_ADC_L_CH_NORMAL_RIGHT (0x3 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */ ++#define RK3308_ADC_L_CH_BIST_CUBE (0x2 << RK3308_ADC_L_CH_BIST_SFT) ++#define RK3308_ADC_L_CH_BIST_SINE (0x1 << RK3308_ADC_L_CH_BIST_SFT) ++#define RK3308_ADC_L_CH_NORMAL_LEFT (0x0 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */ + #define RK3308_ADC_R_CH_BIST_SFT 0 + #define RK3308_ADC_R_CH_BIST_MSK (0x3 << RK3308_ADC_R_CH_BIST_SFT) +-#define RK3308_ADC_R_CH_BIST_LEFT (0x3 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */ +-#define RK3308_ADC_R_CH_BIST_SINE (0x2 << RK3308_ADC_R_CH_BIST_SFT) +-#define RK3308_ADC_R_CH_BIST_CUBE (0x1 << RK3308_ADC_R_CH_BIST_SFT) +-#define RK3308_ADC_R_CH_BIST_RIGHT (0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */ ++#define RK3308_ADC_R_CH_NORMAL_LEFT (0x3 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */ ++#define RK3308_ADC_R_CH_BIST_CUBE (0x2 << RK3308_ADC_R_CH_BIST_SFT) ++#define RK3308_ADC_R_CH_BIST_SINE (0x1 << RK3308_ADC_R_CH_BIST_SFT) ++#define RK3308_ADC_R_CH_NORMAL_RIGHT (0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */ ++ ++/* RK3308_ADC_DIG_CON04 - REG: 0x0010 */ ++#define RK3308_ADC_HPF_PATH_SFT 2 ++#define RK3308_ADC_HPF_PATH_MSK (1 << RK3308_ADC_HPF_PATH_SFT) ++#define RK3308_ADC_HPF_PATH_DIS (1 << RK3308_ADC_HPF_PATH_SFT) ++#define RK3308_ADC_HPF_PATH_EN (0 << RK3308_ADC_HPF_PATH_SFT) ++#define RK3308_ADC_HPF_CUTOFF_SFT 0 ++#define RK3308_ADC_HPF_CUTOFF_MSK (0x3 << RK3308_ADC_HPF_CUTOFF_SFT) ++#define RK3308_ADC_HPF_CUTOFF_612HZ (0x2 << RK3308_ADC_HPF_CUTOFF_SFT) ++#define RK3308_ADC_HPF_CUTOFF_245HZ (0x1 << RK3308_ADC_HPF_CUTOFF_SFT) ++#define RK3308_ADC_HPF_CUTOFF_20HZ (0x0 << RK3308_ADC_HPF_CUTOFF_SFT) + + /* RK3308_ADC_DIG_CON07 - REG: 0x001c */ + #define RK3308_ADCL_DATA_SFT 4 +@@ -391,6 +422,8 @@ + */ + #define RK3308_AGC_PGA_ZERO_CRO_EN (0x1 << 5) + #define RK3308_AGC_PGA_ZERO_CRO_DIS (0x0 << 5) ++#define RK3308_AGC_PGA_GAIN_MAX 0x1f ++#define RK3308_AGC_PGA_GAIN_MIN 0 + #define RK3308_AGC_PGA_GAIN_SFT 0 + #define RK3308_AGC_PGA_GAIN_MSK (0x1f << RK3308_AGC_PGA_GAIN_SFT) + #define RK3308_AGC_PGA_GAIN_PDB_28_5 (0x1f << RK3308_AGC_PGA_GAIN_SFT) +@@ -474,6 +507,8 @@ + #define RK3308_AGC_FUNC_SEL_MSK (0x1 << 6) + #define RK3308_AGC_FUNC_SEL_EN (0x1 << 6) + #define RK3308_AGC_FUNC_SEL_DIS (0x0 << 6) ++#define RK3308_AGC_MAX_GAIN_PGA_MAX 0x7 ++#define RK3308_AGC_MAX_GAIN_PGA_MIN 0 + #define RK3308_AGC_MAX_GAIN_PGA_SFT 3 + #define RK3308_AGC_MAX_GAIN_PGA_MSK (0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT) + #define RK3308_AGC_MAX_GAIN_PGA_PDB_28_5 (0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT) +@@ -484,6 +519,8 @@ + #define RK3308_AGC_MAX_GAIN_PGA_NDB_1_5 (0x2 << RK3308_AGC_MAX_GAIN_PGA_SFT) + #define RK3308_AGC_MAX_GAIN_PGA_NDB_7_5 (0x1 << RK3308_AGC_MAX_GAIN_PGA_SFT) + #define RK3308_AGC_MAX_GAIN_PGA_NDB_13_5 (0x0 << RK3308_AGC_MAX_GAIN_PGA_SFT) ++#define RK3308_AGC_MIN_GAIN_PGA_MAX 0x7 ++#define RK3308_AGC_MIN_GAIN_PGA_MIN 0 + #define RK3308_AGC_MIN_GAIN_PGA_SFT 0 + #define RK3308_AGC_MIN_GAIN_PGA_MSK (0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT) + #define RK3308_AGC_MIN_GAIN_PGA_PDB_24 (0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT) +@@ -555,6 +592,18 @@ + #define RK3308_DAC_R_CH_BIST_SINE (0x1 << RK3308_DAC_R_CH_BIST_SFT) + #define RK3308_DAC_R_CH_BIST_RIGHT (0x0 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */ + ++/* RK3308_DAC_DIG_CON04 - REG: 0x0310 */ ++#define RK3308_DAC_MODULATOR_GAIN_SFT 4 ++#define RK3308_DAC_MODULATOR_GAIN_MSK (0x7 << RK3308_DAC_MODULATOR_GAIN_SFT) ++#define RK3308_DAC_MODULATOR_GAIN_4_8DB (0x5 << RK3308_DAC_MODULATOR_GAIN_SFT) ++#define RK3308_DAC_MODULATOR_GAIN_4_2DB (0x4 << RK3308_DAC_MODULATOR_GAIN_SFT) ++#define RK3308_DAC_MODULATOR_GAIN_3_5DB (0x3 << RK3308_DAC_MODULATOR_GAIN_SFT) ++#define RK3308_DAC_MODULATOR_GAIN_2_8DB (0x2 << RK3308_DAC_MODULATOR_GAIN_SFT) ++#define RK3308_DAC_MODULATOR_GAIN_2DB (0x1 << RK3308_DAC_MODULATOR_GAIN_SFT) ++#define RK3308_DAC_MODULATOR_GAIN_0DB (0x0 << RK3308_DAC_MODULATOR_GAIN_SFT) ++#define RK3308_DAC_CIC_IF_GAIN_SFT 0 ++#define RK3308_DAC_CIC_IF_GAIN_MSK (0x7 << RK3308_DAC_CIC_IF_GAIN_SFT) ++ + /* RK3308_DAC_DIG_CON05 - REG: 0x0314 */ + #define RK3308_DAC_L_REG_CTL_INDATA (0x1 << 2) + #define RK3308_DAC_L_NORMAL_DATA (0x0 << 2) +@@ -587,18 +636,30 @@ + #define RK3308_ADC_CH1_BUF_REF_EN (0x1 << 0) + #define RK3308_ADC_CH1_BUF_REF_DIS (0x0 << 0) + +-/* RK3308_ADC_ANA_CON01 - REG: 0x0344 */ ++/* RK3308_ADC_ANA_CON01 - REG: 0x0344 ++ * ++ * The PGA of MIC-INs: ++ * 0x0 - MIC1~MIC8 0dB ++ * 0x1 - MIC1~MIC8 6.6dB ++ * 0x2 - MIC1~MIC8 13dB ++ * 0x3 - MIC1~MIC8 20dB ++ */ ++#define RK3308_ADC_CH2_MIC_GAIN_MAX 0x3 ++#define RK3308_ADC_CH2_MIC_GAIN_MIN 0 + #define RK3308_ADC_CH2_MIC_GAIN_SFT 4 + #define RK3308_ADC_CH2_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT) +-#define RK3308_ADC_CH2_MIC_GAIN_30DB (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT) +-#define RK3308_ADC_CH2_MIC_GAIN_20DB (0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT) +-#define RK3308_ADC_CH2_MIC_GAIN_6DB (0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT) ++#define RK3308_ADC_CH2_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT) ++#define RK3308_ADC_CH2_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT) /* TRM: only used for version B */ ++#define RK3308_ADC_CH2_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT) /* TRM: only used for version B */ + #define RK3308_ADC_CH2_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH2_MIC_GAIN_SFT) ++ ++#define RK3308_ADC_CH1_MIC_GAIN_MAX 0x3 ++#define RK3308_ADC_CH1_MIC_GAIN_MIN 0 + #define RK3308_ADC_CH1_MIC_GAIN_SFT 0 + #define RK3308_ADC_CH1_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT) +-#define RK3308_ADC_CH1_MIC_GAIN_30DB (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT) +-#define RK3308_ADC_CH1_MIC_GAIN_20DB (0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT) +-#define RK3308_ADC_CH1_MIC_GAIN_6DB (0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT) ++#define RK3308_ADC_CH1_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT) ++#define RK3308_ADC_CH1_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT) /* TRM: only used for version B */ ++#define RK3308_ADC_CH1_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT) /* TRM: only used for version B */ + #define RK3308_ADC_CH1_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH1_MIC_GAIN_SFT) + + /* RK3308_ADC_ANA_CON02 - REG: 0x0348 */ +@@ -619,6 +680,8 @@ + #define RK3308_ADC_CH1_ALC_DIS (0x0 << 0) + + /* RK3308_ADC_ANA_CON03 - REG: 0x034c */ ++#define RK3308_ADC_CH1_ALC_GAIN_MAX 0x1f ++#define RK3308_ADC_CH1_ALC_GAIN_MIN 0 + #define RK3308_ADC_CH1_ALC_GAIN_SFT 0 + #define RK3308_ADC_CH1_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT) + #define RK3308_ADC_CH1_ALC_GAIN_PDB_28_5 (0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT) +@@ -655,6 +718,8 @@ + #define RK3308_ADC_CH1_ALC_GAIN_NDB_18 (0x00 << RK3308_ADC_CH1_ALC_GAIN_SFT) + + /* RK3308_ADC_ANA_CON04 - REG: 0x0350 */ ++#define RK3308_ADC_CH2_ALC_GAIN_MAX 0x1f ++#define RK3308_ADC_CH2_ALC_GAIN_MIN 0 + #define RK3308_ADC_CH2_ALC_GAIN_SFT 0 + #define RK3308_ADC_CH2_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT) + #define RK3308_ADC_CH2_ALC_GAIN_PDB_28_5 (0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT) +@@ -728,10 +793,16 @@ + #define RK3308_ADC_CH1_IN_MIC (0x1 << RK3308_ADC_CH1_IN_SEL_SFT) + #define RK3308_ADC_CH1_IN_NONE (0x0 << RK3308_ADC_CH1_IN_SEL_SFT) + +-#define RK3308_ADC_MIC_BIAS_BUF_EN (0x1 << 3) +-#define RK3308_ADC_MIC_BIAS_BUF_DIS (0x0 << 3) ++#define RK3308_ADC_MIC_BIAS_BUF_SFT 3 ++#define RK3308_ADC_MIC_BIAS_BUF_EN (0x1 << RK3308_ADC_MIC_BIAS_BUF_SFT) ++#define RK3308_ADC_MIC_BIAS_BUF_DIS (0x0 << RK3308_ADC_MIC_BIAS_BUF_SFT) + #define RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT 0 + #define RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK (0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) ++/* ++ * The follow MICBIAS_VOLTs are based on the external reference voltage(Vref). ++ * For example, the Vref == 3.3V, the MICBIAS_VOLT_0_85 is equal: ++ * 3.3V * 0.85 = 2.805V. ++ */ + #define RK3308_ADC_MICBIAS_VOLT_0_85 (0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) + #define RK3308_ADC_MICBIAS_VOLT_0_8 (0x6 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) + #define RK3308_ADC_MICBIAS_VOLT_0_75 (0x5 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT) +@@ -751,18 +822,11 @@ + #define RK3308_ADC_REF_DIS (0x0 << 7) + #define RK3308_ADC_CURRENT_CHARGE_SFT 0 + #define RK3308_ADC_CURRENT_CHARGE_MSK (0x7f << RK3308_ADC_CURRENT_CHARGE_SFT) +-#define RK3308_ADC_DONT_SEL_ALL (0x7f << RK3308_ADC_CURRENT_CHARGE_SFT) + /* +- * 0: Choose the current I +- * 1: Don't choose the current I ++ * 1: Choose the current I ++ * 0: Don't choose the current I + */ +-#define RK3308_ADC_SEL_I_1(x) ((x & 0x1) << 6) +-#define RK3308_ADC_SEL_I_2(x) ((x & 0x1) << 5) +-#define RK3308_ADC_SEL_I_4(x) ((x & 0x1) << 4) +-#define RK3308_ADC_SEL_I_8(x) ((x & 0x1) << 3) +-#define RK3308_ADC_SEL_I_16(x) ((x & 0x1) << 2) +-#define RK3308_ADC_SEL_I_32(x) ((x & 0x1) << 1) +-#define RK3308_ADC_SEL_I_64(x) ((x & 0x1) << 0) ++#define RK3308_ADC_SEL_I(x) (x & 0x7f) + + /* RK3308_ADC_ANA_CON11 - REG: 0x036c */ + #define RK3308_ADC_ALCR_CON_GAIN_PGAR_MSK (0x1 << 1) +@@ -773,6 +837,7 @@ + #define RK3308_ADC_ALCL_CON_GAIN_PGAL_DIS (0x0 << 0) + + /* RK3308_DAC_ANA_CON00 - REG: 0x0440 */ ++#define RK3308_DAC_HEADPHONE_DET_MSK (0x1 << 1) + #define RK3308_DAC_HEADPHONE_DET_EN (0x1 << 1) + #define RK3308_DAC_HEADPHONE_DET_DIS (0x0 << 1) + #define RK3308_DAC_CURRENT_MSK (0x1 << 0) +@@ -783,17 +848,17 @@ + #define RK3308_DAC_BUF_REF_R_MSK (0x1 << 6) + #define RK3308_DAC_BUF_REF_R_EN (0x1 << 6) + #define RK3308_DAC_BUF_REF_R_DIS (0x0 << 6) +-#define RK3308_DAC_POP_SOUND_R_SFT 4 +-#define RK3308_DAC_POP_SOUND_R_MSK (0x3 << RK3308_DAC_POP_SOUND_R_SFT) +-#define RK3308_DAC_POP_SOUND_R_WORK (0x2 << RK3308_DAC_POP_SOUND_R_SFT) +-#define RK3308_DAC_POP_SOUND_R_INIT (0x1 << RK3308_DAC_POP_SOUND_R_SFT) ++#define RK3308_DAC_HPOUT_POP_SOUND_R_SFT 4 ++#define RK3308_DAC_HPOUT_POP_SOUND_R_MSK (0x3 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) ++#define RK3308_DAC_HPOUT_POP_SOUND_R_WORK (0x2 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) ++#define RK3308_DAC_HPOUT_POP_SOUND_R_INIT (0x1 << RK3308_DAC_HPOUT_POP_SOUND_R_SFT) + #define RK3308_DAC_BUF_REF_L_MSK (0x1 << 2) + #define RK3308_DAC_BUF_REF_L_EN (0x1 << 2) + #define RK3308_DAC_BUF_REF_L_DIS (0x0 << 2) +-#define RK3308_DAC_POP_SOUND_L_SFT 0 +-#define RK3308_DAC_POP_SOUND_L_MSK (0x3 << RK3308_DAC_POP_SOUND_L_SFT) +-#define RK3308_DAC_POP_SOUND_L_WORK (0x2 << RK3308_DAC_POP_SOUND_L_SFT) +-#define RK3308_DAC_POP_SOUND_L_INIT (0x1 << RK3308_DAC_POP_SOUND_L_SFT) ++#define RK3308_DAC_HPOUT_POP_SOUND_L_SFT 0 ++#define RK3308_DAC_HPOUT_POP_SOUND_L_MSK (0x3 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) ++#define RK3308_DAC_HPOUT_POP_SOUND_L_WORK (0x2 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) ++#define RK3308_DAC_HPOUT_POP_SOUND_L_INIT (0x1 << RK3308_DAC_HPOUT_POP_SOUND_L_SFT) + + /* RK3308_DAC_ANA_CON02 - REG: 0x0448 */ + #define RK3308_DAC_R_DAC_WORK (0x1 << 7) +@@ -828,28 +893,31 @@ + #define RK3308_DAC_L_HPOUT_MUTE (0x0 << 0) + + /* RK3308_DAC_ANA_CON04 - REG: 0x0450 */ +-#define RK3308_DAC_R_GAIN_SFT 6 +-#define RK3308_DAC_R_GAIN_MSK (0x3 << RK3308_DAC_R_GAIN_SFT) +-#define RK3308_DAC_R_GAIN_0DB (0x3 << RK3308_DAC_R_GAIN_SFT) +-#define RK3308_DAC_R_GAIN_PDB_1_5 (0x2 << RK3308_DAC_R_GAIN_SFT) +-#define RK3308_DAC_R_GAIN_PDB_3 (0x1 << RK3308_DAC_R_GAIN_SFT) +-#define RK3308_DAC_R_GAIN_PDB_6 (0x0 << RK3308_DAC_R_GAIN_SFT) ++#define RK3308_DAC_R_LINEOUT_GAIN_MAX 0x3 ++#define RK3308_DAC_R_LINEOUT_GAIN_SFT 6 ++#define RK3308_DAC_R_LINEOUT_GAIN_MSK (0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT) ++#define RK3308_DAC_R_LINEOUT_GAIN_0DB (0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT) ++#define RK3308_DAC_R_LINEOUT_GAIN_NDB_1_5 (0x2 << RK3308_DAC_R_LINEOUT_GAIN_SFT) ++#define RK3308_DAC_R_LINEOUT_GAIN_NDB_3 (0x1 << RK3308_DAC_R_LINEOUT_GAIN_SFT) ++#define RK3308_DAC_R_LINEOUT_GAIN_NDB_6 (0x0 << RK3308_DAC_R_LINEOUT_GAIN_SFT) + #define RK3308_DAC_R_LINEOUT_UNMUTE (0x1 << 5) + #define RK3308_DAC_R_LINEOUT_MUTE (0x0 << 5) + #define RK3308_DAC_R_LINEOUT_EN (0x1 << 4) + #define RK3308_DAC_R_LINEOUT_DIS (0x0 << 4) +-#define RK3308_DAC_L_GAIN_SFT 2 +-#define RK3308_DAC_L_GAIN_MSK (0x3 << RK3308_DAC_L_GAIN_SFT) +-#define RK3308_DAC_L_GAIN_0DB (0x3 << RK3308_DAC_L_GAIN_SFT) +-#define RK3308_DAC_L_GAIN_PDB_1_5 (0x2 << RK3308_DAC_L_GAIN_SFT) +-#define RK3308_DAC_L_GAIN_PDB_3 (0x1 << RK3308_DAC_L_GAIN_SFT) +-#define RK3308_DAC_L_GAIN_PDB_6 (0x0 << RK3308_DAC_L_GAIN_SFT) ++#define RK3308_DAC_L_LINEOUT_GAIN_MAX 0x3 ++#define RK3308_DAC_L_LINEOUT_GAIN_SFT 2 ++#define RK3308_DAC_L_LINEOUT_GAIN_MSK (0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT) ++#define RK3308_DAC_L_LINEOUT_GAIN_0DB (0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT) ++#define RK3308_DAC_L_LINEOUT_GAIN_NDB_1_5 (0x2 << RK3308_DAC_L_LINEOUT_GAIN_SFT) ++#define RK3308_DAC_L_LINEOUT_GAIN_NDB_3 (0x1 << RK3308_DAC_L_LINEOUT_GAIN_SFT) ++#define RK3308_DAC_L_LINEOUT_GAIN_NDB_6 (0x0 << RK3308_DAC_L_LINEOUT_GAIN_SFT) + #define RK3308_DAC_L_LINEOUT_UNMUTE (0x1 << 1) + #define RK3308_DAC_L_LINEOUT_MUTE (0x0 << 1) + #define RK3308_DAC_L_LINEOUT_EN (0x1 << 0) + #define RK3308_DAC_L_LINEOUT_DIS (0x0 << 0) + + /* RK3308_DAC_ANA_CON05 - REG: 0x0454, step is 1.5db */ ++#define RK3308_DAC_L_HPOUT_GAIN_MAX 0x1e + #define RK3308_DAC_L_HPOUT_GAIN_SFT 0 + #define RK3308_DAC_L_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_L_HPOUT_GAIN_SFT) + #define RK3308_DAC_L_HPOUT_GAIN_PDB_6 (0x1e << RK3308_DAC_L_HPOUT_GAIN_SFT) +@@ -885,6 +953,7 @@ + #define RK3308_DAC_L_HPOUT_GAIN_NDB_39 (0x00 << RK3308_DAC_L_HPOUT_GAIN_SFT) + + /* RK3308_DAC_ANA_CON06 - REG: 0x0458, step is 1.5db */ ++#define RK3308_DAC_R_HPOUT_GAIN_MAX 0x1e + #define RK3308_DAC_R_HPOUT_GAIN_SFT 0 + #define RK3308_DAC_R_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_R_HPOUT_GAIN_SFT) + #define RK3308_DAC_R_HPOUT_GAIN_PDB_6 (0x1e << RK3308_DAC_R_HPOUT_GAIN_SFT) +@@ -919,6 +988,18 @@ + #define RK3308_DAC_R_HPOUT_GAIN_NDB_37_5 (0x01 << RK3308_DAC_R_HPOUT_GAIN_SFT) + #define RK3308_DAC_R_HPOUT_GAIN_NDB_39 (0x00 << RK3308_DAC_R_HPOUT_GAIN_SFT) + ++/* RK3308_DAC_ANA_CON07 - REG: 0x045c */ ++#define RK3308_DAC_R_HPOUT_DRV_SFT 4 ++#define RK3308_DAC_R_HPOUT_DRV_MSK (0xf << RK3308_DAC_R_HPOUT_DRV_SFT) ++#define RK3308_DAC_L_HPOUT_DRV_SFT 0 ++#define RK3308_DAC_L_HPOUT_DRV_MSK (0xf << RK3308_DAC_L_HPOUT_DRV_SFT) ++ ++/* RK3308_DAC_ANA_CON08 - REG: 0x0460 */ ++#define RK3308_DAC_R_LINEOUT_DRV_SFT 4 ++#define RK3308_DAC_R_LINEOUT_DRV_MSK (0xf << RK3308_DAC_R_LINEOUT_DRV_SFT) ++#define RK3308_DAC_L_LINEOUT_DRV_SFT 0 ++#define RK3308_DAC_L_LINEOUT_DRV_MSK (0xf << RK3308_DAC_L_LINEOUT_DRV_SFT) ++ + /* RK3308_DAC_ANA_CON12 - REG: 0x0470 */ + #define RK3308_DAC_R_HPMIX_SEL_SFT 6 + #define RK3308_DAC_R_HPMIX_SEL_MSK (0x3 << RK3308_DAC_R_HPMIX_SEL_SFT) +@@ -926,6 +1007,8 @@ + #define RK3308_DAC_R_HPMIX_LINEIN (0x2 << RK3308_DAC_R_HPMIX_SEL_SFT) + #define RK3308_DAC_R_HPMIX_I2S (0x1 << RK3308_DAC_R_HPMIX_SEL_SFT) + #define RK3308_DAC_R_HPMIX_NONE (0x0 << RK3308_DAC_R_HPMIX_SEL_SFT) ++#define RK3308_DAC_R_HPMIX_GAIN_MIN 0x1 ++#define RK3308_DAC_R_HPMIX_GAIN_MAX 0x2 + #define RK3308_DAC_R_HPMIX_GAIN_SFT 4 + #define RK3308_DAC_R_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_R_HPMIX_GAIN_SFT) + #define RK3308_DAC_R_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_R_HPMIX_GAIN_SFT) +@@ -936,6 +1019,8 @@ + #define RK3308_DAC_L_HPMIX_LINEIN (0x2 << RK3308_DAC_L_HPMIX_SEL_SFT) + #define RK3308_DAC_L_HPMIX_I2S (0x1 << RK3308_DAC_L_HPMIX_SEL_SFT) + #define RK3308_DAC_L_HPMIX_NONE (0x0 << RK3308_DAC_L_HPMIX_SEL_SFT) ++#define RK3308_DAC_L_HPMIX_GAIN_MIN 0x1 ++#define RK3308_DAC_L_HPMIX_GAIN_MAX 0x2 + #define RK3308_DAC_L_HPMIX_GAIN_SFT 0 + #define RK3308_DAC_L_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_L_HPMIX_GAIN_SFT) + #define RK3308_DAC_L_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_L_HPMIX_GAIN_SFT) +@@ -955,6 +1040,30 @@ + #define RK3308_DAC_L_HPMIX_EN (0x1 << 0) + #define RK3308_DAC_L_HPMIX_DIS (0x0 << 0) + ++/* RK3308_DAC_ANA_CON14 - REG: 0x0478 */ ++#define RK3308_DAC_VCM_LINEOUT_EN (0x1 << 4) ++#define RK3308_DAC_VCM_LINEOUT_DIS (0x0 << 4) ++#define RK3308_DAC_CURRENT_CHARGE_SFT 0 ++#define RK3308_DAC_CURRENT_CHARGE_MSK (0xf << RK3308_DAC_CURRENT_CHARGE_SFT) ++ ++/* ++ * 1: Choose the current I ++ * 0: Don't choose the current I ++ */ ++#define RK3308_DAC_SEL_I(x) (x & 0xf) ++ ++/* RK3308_DAC_ANA_CON15 - REG: 0x047C */ ++#define RK3308_DAC_LINEOUT_POP_SOUND_R_SFT 4 ++#define RK3308_DAC_LINEOUT_POP_SOUND_R_MSK (0x3 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT) ++#define RK3308_DAC_R_SEL_DC_FROM_INTERNAL (0x2 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT) ++#define RK3308_DAC_R_SEL_DC_FROM_VCM (0x1 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT) ++#define RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL (0x0 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT) ++#define RK3308_DAC_LINEOUT_POP_SOUND_L_SFT 0 ++#define RK3308_DAC_LINEOUT_POP_SOUND_L_MSK (0x3 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) ++#define RK3308_DAC_L_SEL_DC_FROM_INTERNAL (0x2 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) ++#define RK3308_DAC_L_SEL_DC_FROM_VCM (0x1 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) ++#define RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL (0x0 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT) ++ + #define RK3308_HIFI 0x0 + + #endif /* __RK3308_CODEC_H__ */ +diff --git a/sound/soc/codecs/rk3308_codec_provider.h b/sound/soc/codecs/rk3308_codec_provider.h +new file mode 100644 +index 000000000000..68042b1328dc +--- /dev/null ++++ b/sound/soc/codecs/rk3308_codec_provider.h +@@ -0,0 +1,28 @@ ++/* ++ * rk3308_codec_provider.h -- RK3308 ALSA Soc Audio Driver ++ * ++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++ ++#ifndef __RK3308_CODEC_PROVIDER_H__ ++#define __RK3308_CODEC_PROVIDER_H__ ++ ++#ifdef CONFIG_SND_SOC_RK3308 ++extern void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_codec *codec, ++ struct snd_soc_jack *hpdet_jack); ++#endif ++ ++#endif /* __RK3308_CODEC_PROVIDER_H__ */ +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch new file mode 100644 index 000000000..821e69964 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch @@ -0,0 +1,50 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: ashthespy +Date: Mon, 3 Feb 2020 17:19:33 +0100 +Subject: arm64: dts: rockchip: Add acodec node for rk3308 + +Change-Id: I76f4a877711d33620bdef295e9047bdba26d4da4 +Signed-off-by: Xing Zheng +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 18 +++++++++- + 1 file changed, 17 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index 291f011800b2..dd221ee88722 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -548,7 +548,7 @@ rk_timer_rtc: rk-timer-rtc@ff1a0020 { + clock-names = "pclk", "timer"; + status = "disabled"; + }; +- ++ + saradc: saradc@ff1e0000 { + compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xff1e0000 0x0 0x100>; +@@ -933,6 +933,22 @@ cru: clock-controller@ff500000 { + assigned-clock-rates = <32768>; + }; + ++ acodec: acodec@ff560000 { ++ compatible = "rockchip,rk3308-codec"; ++ reg = <0x0 0xff560000 0x0 0x10000>; ++ rockchip,grf = <&grf>; ++ rockchip,detect-grf = <&detect_grf>; ++ interrupts = , ++ ; ++ clocks = <&cru PCLK_ACODEC>, ++ <&cru SCLK_I2S2_8CH_TX_OUT>, ++ <&cru SCLK_I2S2_8CH_RX_OUT>; ++ clock-names = "acodec", "mclk_tx", "mclk_rx"; ++ resets = <&cru SRST_ACODEC_P>; ++ reset-names = "acodec-reset"; ++ status = "disabled"; ++}; ++ + gic: interrupt-controller@ff580000 { + compatible = "arm,gic-400"; + reg = <0x0 0xff581000 0x0 0x1000>, +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch new file mode 100644 index 000000000..5855cf80a --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch @@ -0,0 +1,459 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: ashthespy +Date: Mon, 3 Feb 2020 19:35:42 +0100 +Subject: ASoC: rk3308_codec: replace codec to component + +--- + sound/soc/codecs/rk3308_codec.c | 159 +++++----- + sound/soc/codecs/rk3308_codec_provider.h | 2 +- + 2 files changed, 84 insertions(+), 77 deletions(-) + +diff --git a/sound/soc/codecs/rk3308_codec.c b/sound/soc/codecs/rk3308_codec.c +index 815e22fc346c..b6862fc5a3da 100644 +--- a/sound/soc/codecs/rk3308_codec.c ++++ b/sound/soc/codecs/rk3308_codec.c +@@ -31,7 +31,7 @@ + #include + #include + #include +-#include ++// #include + #include + #include + #include +@@ -156,7 +156,7 @@ struct rk3308_codec_priv { + struct gpio_desc *hp_ctl_gpio; + struct gpio_desc *spk_ctl_gpio; + struct gpio_desc *pa_drv_gpio; +- struct snd_soc_codec *codec; ++ struct snd_soc_component *component; + struct snd_soc_jack *hpdet_jack; + struct regulator *vcc_micbias; + u32 codec_ver; +@@ -883,8 +883,8 @@ static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = { + static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + + if (e->reg < 0 || e->reg > ADC_LR_GROUP_MAX - 1) { +@@ -904,8 +904,8 @@ static int rk3308_codec_agc_get(struct snd_kcontrol *kcontrol, + static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int value = ucontrol->value.integer.value[0]; + int grp = e->reg; +@@ -970,8 +970,8 @@ static int rk3308_codec_agc_put(struct snd_kcontrol *kcontrol, + static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int value; + int grp = e->reg; +@@ -998,8 +998,8 @@ static int rk3308_codec_agc_asr_get(struct snd_kcontrol *kcontrol, + static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int value; + int grp = e->reg; +@@ -1032,8 +1032,8 @@ static int rk3308_codec_agc_asr_put(struct snd_kcontrol *kcontrol, + static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int value; + int grp = e->reg; +@@ -1064,8 +1064,8 @@ static int rk3308_codec_mic_mute_get(struct snd_kcontrol *kcontrol, + static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int value; + int grp = e->reg; +@@ -1098,8 +1098,8 @@ static int rk3308_codec_mic_mute_put(struct snd_kcontrol *kcontrol, + static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rk3308->micbias_volt; + +@@ -1109,8 +1109,8 @@ static int rk3308_codec_micbias_volts_get(struct snd_kcontrol *kcontrol, + static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + unsigned int volt = ucontrol->value.integer.value[0]; + int ret; + +@@ -1133,8 +1133,8 @@ static int rk3308_codec_micbias_volts_put(struct snd_kcontrol *kcontrol, + static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rk3308->enable_micbias; + +@@ -1144,8 +1144,8 @@ static int rk3308_codec_main_micbias_get(struct snd_kcontrol *kcontrol, + static int rk3308_codec_main_micbias_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + unsigned int on = ucontrol->value.integer.value[0]; + + if (on) { +@@ -1168,8 +1168,8 @@ static int rk3308_codec_mic_gain_get(struct snd_kcontrol *kcontrol, + static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + unsigned int gain = ucontrol->value.integer.value[0]; + + if (gain > RK3308_ADC_CH1_MIC_GAIN_MAX) { +@@ -1197,8 +1197,8 @@ static int rk3308_codec_mic_gain_put(struct snd_kcontrol *kcontrol, + static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int value; + +@@ -1222,8 +1222,8 @@ static int rk3308_codec_hpf_get(struct snd_kcontrol *kcontrol, + static int rk3308_codec_hpf_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int value = ucontrol->value.integer.value[0]; + +@@ -1259,8 +1259,8 @@ static int rk3308_codec_hpout_l_get_tlv(struct snd_kcontrol *kcontrol, + static int rk3308_codec_hpout_l_put_tlv(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + unsigned int dgain = ucontrol->value.integer.value[0]; + + if (dgain > RK3308_DAC_L_HPOUT_GAIN_MAX) { +@@ -1283,8 +1283,8 @@ static int rk3308_codec_hpout_r_get_tlv(struct snd_kcontrol *kcontrol, + static int rk3308_codec_hpout_r_put_tlv(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +- struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + unsigned int dgain = ucontrol->value.integer.value[0]; + + if (dgain > RK3308_DAC_R_HPOUT_GAIN_MAX) { +@@ -1408,9 +1408,9 @@ static void rk3308_speaker_ctl(struct rk3308_codec_priv *rk3308, int on) + } + } + +-static int rk3308_codec_reset(struct snd_soc_codec *codec) ++static int rk3308_codec_reset(struct snd_soc_component *component) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + + reset_control_assert(rk3308->reset); + usleep_range(2000, 2500); /* estimated value */ +@@ -1452,10 +1452,10 @@ static int rk3308_codec_dac_dig_reset(struct rk3308_codec_priv *rk3308) + return 0; + } + +-static int rk3308_set_bias_level(struct snd_soc_codec *codec, ++static int rk3308_set_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + + switch (level) { + case SND_SOC_BIAS_ON: +@@ -1473,11 +1473,11 @@ static int rk3308_set_bias_level(struct snd_soc_codec *codec, + return 0; + } + +-static int rk3308_set_dai_fmt(struct snd_soc_dai *codec_dai, ++static int rk3308_set_dai_fmt(struct snd_soc_dai *dai, + unsigned int fmt) + { +- struct snd_soc_codec *codec = codec_dai->codec; +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = dai->component; ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0; + int idx, grp, is_master; + int type = ADC_TYPE_ALL; +@@ -1721,8 +1721,8 @@ static int rk3308_codec_update_adc_grps(struct rk3308_codec_priv *rk3308, + + static int rk3308_mute_stream(struct snd_soc_dai *dai, int mute, int stream) + { +- struct snd_soc_codec *codec = dai->codec; +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = dai->component; ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + int dgain; +@@ -3630,8 +3630,8 @@ static int rk3308_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) + { +- struct snd_soc_codec *codec = dai->codec; +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = dai->component; ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + struct snd_pcm_str *playback_str = + &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK]; + int type = ADC_TYPE_LOOPBACK; +@@ -3705,8 +3705,8 @@ static int rk3308_hw_params(struct snd_pcm_substream *substream, + static int rk3308_pcm_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) + { +- struct snd_soc_codec *codec = dai->codec; +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = dai->component; ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + int type = ADC_TYPE_LOOPBACK; + int idx, grp; + +@@ -3749,8 +3749,8 @@ static int rk3308_pcm_trigger(struct snd_pcm_substream *substream, + static void rk3308_pcm_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) + { +- struct snd_soc_codec *codec = dai->codec; +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct snd_soc_component *component = dai->component; ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + rk3308_codec_close_playback(rk3308); +@@ -3809,9 +3809,9 @@ static struct snd_soc_dai_driver rk3308_dai[] = { + }, + }; + +-static int rk3308_suspend(struct snd_soc_codec *codec) ++static int rk3308_suspend(struct snd_soc_component *component) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + + if (rk3308->no_deep_low_power) + goto out; +@@ -3822,13 +3822,13 @@ static int rk3308_suspend(struct snd_soc_codec *codec) + clk_disable_unprepare(rk3308->pclk); + + out: +- rk3308_set_bias_level(codec, SND_SOC_BIAS_OFF); ++ rk3308_set_bias_level(component, SND_SOC_BIAS_OFF); + return 0; + } + +-static int rk3308_resume(struct snd_soc_codec *codec) ++static int rk3308_resume(struct snd_soc_component *component) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + int ret = 0; + + if (rk3308->no_deep_low_power) +@@ -3857,7 +3857,7 @@ static int rk3308_resume(struct snd_soc_codec *codec) + + rk3308_codec_dlp_up(rk3308); + out: +- rk3308_set_bias_level(codec, SND_SOC_BIAS_STANDBY); ++ rk3308_set_bias_level(component, SND_SOC_BIAS_STANDBY); + return ret; + } + +@@ -3972,7 +3972,7 @@ static int rk3308_codec_dapm_mic_gains(struct rk3308_codec_priv *rk3308) + int ret; + + if (rk3308->codec_ver == ACODEC_VERSION_B) { +- ret = snd_soc_add_codec_controls(rk3308->codec, ++ ret = snd_soc_add_component_controls(rk3308->component, + mic_gains_b, + ARRAY_SIZE(mic_gains_b)); + if (ret) { +@@ -3982,7 +3982,7 @@ static int rk3308_codec_dapm_mic_gains(struct rk3308_codec_priv *rk3308) + return ret; + } + } else { +- ret = snd_soc_add_codec_controls(rk3308->codec, ++ ret = snd_soc_add_component_controls(rk3308->component, + mic_gains_a, + ARRAY_SIZE(mic_gains_a)); + if (ret) { +@@ -4081,15 +4081,15 @@ static int rk3308_codec_prepare(struct rk3308_codec_priv *rk3308) + return 0; + } + +-static int rk3308_probe(struct snd_soc_codec *codec) ++static int rk3308_probe(struct snd_soc_component *component) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + int ext_micbias; + +- rk3308->codec = codec; ++ rk3308->component = component; + rk3308_codec_set_dac_path_state(rk3308, PATH_IDLE); + +- rk3308_codec_reset(codec); ++ rk3308_codec_reset(component); + rk3308_codec_power_on(rk3308); + + /* From vendor recommend, disable micbias at first. */ +@@ -4108,9 +4108,9 @@ static int rk3308_probe(struct snd_soc_codec *codec) + return 0; + } + +-static int rk3308_remove(struct snd_soc_codec *codec) ++static void rk3308_remove(struct snd_soc_component *component) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + + rk3308_headphone_ctl(rk3308, 0); + rk3308_speaker_ctl(rk3308, 0); +@@ -4124,17 +4124,25 @@ static int rk3308_remove(struct snd_soc_codec *codec) + regcache_cache_only(rk3308->regmap, false); + regcache_sync(rk3308->regmap); + +- return 0; + } + +-static struct snd_soc_codec_driver soc_codec_dev_rk3308 = { +- .probe = rk3308_probe, +- .remove = rk3308_remove, +- .suspend = rk3308_suspend, +- .resume = rk3308_resume, +- .set_bias_level = rk3308_set_bias_level, +- .controls = rk3308_codec_dapm_controls, +- .num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls), ++static const struct snd_soc_component_driver soc_codec_dev_rk3308_component = { ++ .probe = rk3308_probe, ++ .remove = rk3308_remove, ++ .resume = rk3308_resume, ++ .suspend = rk3308_suspend, ++ .set_bias_level = rk3308_set_bias_level, ++ .controls = rk3308_codec_dapm_controls, ++ .num_controls = ARRAY_SIZE(rk3308_codec_dapm_controls), ++ // .dapm_widgets = rk3308_dapm_widgets, ++ // .num_dapm_widgets = ARRAY_SIZE(rk3308_dapm_widgets), ++ // .dapm_routes = rk3308_dapm_routes, ++ // .num_dapm_routes = ARRAY_SIZE(rk3308_dapm_routes), ++ // .suspend_bias_off = 1, ++ // .idle_bias_on = 1, ++ // .use_pmdown_time = 1, ++ .endianness = 1, ++ .legacy_dai_naming = 1, + }; + + static const struct reg_default rk3308_codec_reg_defaults[] = { +@@ -4299,14 +4307,14 @@ static irqreturn_t rk3308_codec_hpdet_isr(int irq, void *data) + return IRQ_HANDLED; + } + +-void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_codec *codec, ++void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_component *component, + struct snd_soc_jack *hpdet_jack); + EXPORT_SYMBOL_GPL(rk3308_codec_set_jack_detect_cb); + +-static void rk3308_codec_set_jack_detect(struct snd_soc_codec *codec, ++static void rk3308_codec_set_jack_detect(struct snd_soc_component *component, + struct snd_soc_jack *hpdet_jack) + { +- struct rk3308_codec_priv *rk3308 = snd_soc_codec_get_drvdata(codec); ++ struct rk3308_codec_priv *rk3308 = snd_soc_component_get_drvdata(component); + + rk3308->hpdet_jack = hpdet_jack; + +@@ -5114,10 +5122,10 @@ static int rk3308_platform_probe(struct platform_device *pdev) + + platform_set_drvdata(pdev, rk3308); + +- ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_rk3308, ++ ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3308_component, + rk3308_dai, ARRAY_SIZE(rk3308_dai)); + if (ret < 0) { +- dev_err(&pdev->dev, "Failed to register codec: %d\n", ret); ++ dev_err(&pdev->dev, "Failed to register component: %d\n", ret); + goto failed; + } + +@@ -5140,7 +5148,6 @@ static int rk3308_platform_remove(struct platform_device *pdev) + clk_disable_unprepare(rk3308->mclk_rx); + clk_disable_unprepare(rk3308->mclk_tx); + clk_disable_unprepare(rk3308->pclk); +- snd_soc_unregister_codec(&pdev->dev); + device_unregister(&rk3308->dev); + + return 0; +diff --git a/sound/soc/codecs/rk3308_codec_provider.h b/sound/soc/codecs/rk3308_codec_provider.h +index 68042b1328dc..34c1ef86a507 100644 +--- a/sound/soc/codecs/rk3308_codec_provider.h ++++ b/sound/soc/codecs/rk3308_codec_provider.h +@@ -21,7 +21,7 @@ + #define __RK3308_CODEC_PROVIDER_H__ + + #ifdef CONFIG_SND_SOC_RK3308 +-extern void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_codec *codec, ++extern void (*rk3308_codec_set_jack_detect_cb)(struct snd_soc_component *component, + struct snd_soc_jack *hpdet_jack); + #endif + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch new file mode 100644 index 000000000..f11c766eb --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch @@ -0,0 +1,115 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Igor Pecovnik +Date: Wed, 8 Sep 2021 17:51:34 +0200 +Subject: [ARCHEOLOGY] Bumping EDGE kernel to 5.14.y (#3125) + +> X-Git-Archeology: > recovered message: > * Bumping EDGE kernel to 5.14.y +> X-Git-Archeology: > recovered message: > Meson64: +> X-Git-Archeology: > recovered message: > - removing Odroid reboot shutdown patch since its probably not needed anymore +> X-Git-Archeology: > recovered message: > Rockchip64: +> X-Git-Archeology: > recovered message: > - removing Rockpi S. No interest to maintain this any further +> X-Git-Archeology: > recovered message: > - removing PBP suspend. Doesn't align. Need inspection if some other way was mainstreamed +> X-Git-Archeology: > recovered message: > - temporally removing Orangepi R1 +> X-Git-Archeology: > recovered message: > * Re-adding rockpis, pbp suspend, HFLPS170 wifi and cleanup +> X-Git-Archeology: > recovered message: > * Removing deprecated patch, fixing ap6256 wifi +> X-Git-Archeology: > recovered message: > * Re-enable Opi R1 plus, untest +> X-Git-Archeology: > recovered message: > * Add and fix Radxa Zero +> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 +> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 29 ++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index dd221ee88722..5f48dcee7548 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -138,6 +138,12 @@ arm-pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + ++ cpuinfo { ++ compatible = "rockchip,cpuinfo"; ++ nvmem-cells = <&cpu_id>; ++ nvmem-cell-names = "id"; ++ }; ++ + mac_clkin: external-mac-clock { + compatible = "fixed-clock"; + clock-frequency = <50000000>; +@@ -145,6 +151,29 @@ mac_clkin: external-mac-clock { + #clock-cells = <0>; + }; + ++ otp: otp@ff210000 { ++ compatible = "rockchip,rk3308-otp"; ++ reg = <0x0 0xff210000 0x0 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, ++ <&cru PCLK_OTP_PHY>; ++ clock-names = "otp", "apb_pclk", "phy"; ++ resets = <&cru SRST_OTP_PHY>; ++ reset-names = "phy"; ++ ++ /* Data cells */ ++ cpu_id: id@7 { ++ reg = <0x07 0x10>; ++ }; ++ cpu_leakage: cpu-leakage@17 { ++ reg = <0x17 0x1>; ++ }; ++ logic_leakage: logic-leakage@18 { ++ reg = <0x18 0x1>; ++ }; ++ }; ++ + psci { + compatible = "arm,psci-1.0"; + method = "smc"; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch new file mode 100644 index 000000000..e64c536bc --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch @@ -0,0 +1,99 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Igor Pecovnik +Date: Wed, 8 Sep 2021 17:51:34 +0200 +Subject: [ARCHEOLOGY] Bumping EDGE kernel to 5.14.y (#3125) + +> X-Git-Archeology: > recovered message: > * Bumping EDGE kernel to 5.14.y +> X-Git-Archeology: > recovered message: > Meson64: +> X-Git-Archeology: > recovered message: > - removing Odroid reboot shutdown patch since its probably not needed anymore +> X-Git-Archeology: > recovered message: > Rockchip64: +> X-Git-Archeology: > recovered message: > - removing Rockpi S. No interest to maintain this any further +> X-Git-Archeology: > recovered message: > - removing PBP suspend. Doesn't align. Need inspection if some other way was mainstreamed +> X-Git-Archeology: > recovered message: > - temporally removing Orangepi R1 +> X-Git-Archeology: > recovered message: > * Re-adding rockpis, pbp suspend, HFLPS170 wifi and cleanup +> X-Git-Archeology: > recovered message: > * Removing deprecated patch, fixing ap6256 wifi +> X-Git-Archeology: > recovered message: > * Re-enable Opi R1 plus, untest +> X-Git-Archeology: > recovered message: > * Add and fix Radxa Zero +> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 +> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 20 ++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index 5f48dcee7548..c5fe355c6deb 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -179,6 +179,26 @@ psci { + method = "smc"; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ drm_logo: drm-logo@00000000 { ++ compatible = "rockchip,drm-logo"; ++ reg = <0x0 0x0 0x0 0x0>; ++ }; ++ ++ ramoops: ramoops@110000 { ++ compatible = "ramoops"; ++ reg = <0x0 0x110000 0x0 0xf0000>; ++ record-size = <0x30000>; ++ console-size = <0xc0000>; ++ ftrace-size = <0x00000>; ++ pmsg-size = <0x00000>; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupts = , +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch new file mode 100644 index 000000000..42c9ba693 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch @@ -0,0 +1,64 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Piotr Szczepanik +Date: Mon, 24 Aug 2020 22:47:03 +0200 +Subject: Rockpro64 add pcie bus scan delay + +> X-Git-Archeology: - Revision 42e76b9277ad492e935cc76c2b37c9f6d882a675: https://github.com/armbian/build/commit/42e76b9277ad492e935cc76c2b37c9f6d882a675 +> X-Git-Archeology: Date: Mon, 24 Aug 2020 22:47:03 +0200 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch RockPro64 work led to heartbeat trigger +> X-Git-Archeology: +> X-Git-Archeology: - Revision 4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5: https://github.com/armbian/build/commit/4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5 +> X-Git-Archeology: Date: Wed, 02 Sep 2020 23:22:09 +0200 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switched rockchip64 curent to kernel 5.8.y (#2175) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 +> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 7be9e8b99590e32c0594365d00a2a2cfc3c4bd5a: https://github.com/armbian/build/commit/7be9e8b99590e32c0594365d00a2a2cfc3c4bd5a +> X-Git-Archeology: Date: Thu, 16 Dec 2021 05:17:33 -0500 +> X-Git-Archeology: From: Dan Pasanen +> X-Git-Archeology: Subject: rockchip-[current,edge]: add pcie hack and lsi scsi/sas support (#3351) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 588c2ec17e709dec19304fa50522459702ebfadd: https://github.com/armbian/build/commit/588c2ec17e709dec19304fa50522459702ebfadd +> X-Git-Archeology: Date: Fri, 23 Dec 2022 21:57:53 +0100 +> X-Git-Archeology: From: brentr +> X-Git-Archeology: Subject: Rockpis devtree mainlined (#4603) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +index bca2b50e0a93..1e7295215b58 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +@@ -663,6 +663,7 @@ &pcie0 { + pinctrl-0 = <&pcie_perst>; + vpcie12v-supply = <&vcc12v_dcin>; + vpcie3v3-supply = <&vcc3v3_pcie>; ++ bus-scan-delay-ms = <1000>; + status = "okay"; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpro64-change-rx_delay-for-gmac.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-change-rx_delay-for-gmac.patch new file mode 100644 index 000000000..4e7ed60cf --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-change-rx_delay-for-gmac.patch @@ -0,0 +1,26 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ayufan +Date: Sun, 30 Dec 2018 13:32:47 +0100 +Subject: ayufan: dts: rockpro64: change rx_delay for gmac + +Change-Id: Ib3899f684188aa1ed1545717af004bba53fe0e07 +--- + arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +index 1e7295215b58..25ee84e06874 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +@@ -307,7 +307,7 @@ &gmac { + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; +- rx_delay = <0x11>; ++ rx_delay = <0x20>; + status = "okay"; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpro64-fix-emmc.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-fix-emmc.patch new file mode 100644 index 000000000..7aeb8dc4f --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-fix-emmc.patch @@ -0,0 +1,123 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Martin Ayotte +Date: Wed, 5 Dec 2018 14:09:24 -0500 +Subject: [ARCHEOLOGY] fix PMIC_INT_L gpio conflicting with I2C8_SCL in + RockPro64 + +> X-Git-Archeology: - Revision 9324bde9b94db6c2f43ff1e75bedb74fbe6e29a1: https://github.com/armbian/build/commit/9324bde9b94db6c2f43ff1e75bedb74fbe6e29a1 +> X-Git-Archeology: Date: Wed, 05 Dec 2018 14:09:24 -0500 +> X-Git-Archeology: From: Martin Ayotte +> X-Git-Archeology: Subject: fix PMIC_INT_L gpio conflicting with I2C8_SCL in RockPro64 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8f82cb60b958ad235ee91899ab2ca8e4a8a2a33b: https://github.com/armbian/build/commit/8f82cb60b958ad235ee91899ab2ca8e4a8a2a33b +> X-Git-Archeology: Date: Mon, 31 Dec 2018 12:29:56 -0500 +> X-Git-Archeology: From: Martin Ayotte +> X-Git-Archeology: Subject: set lower speed for RockPro64 eMMC +> X-Git-Archeology: +> X-Git-Archeology: - Revision cbbbf0631969bf0e4578f4b1eef62c1aab115d79: https://github.com/armbian/build/commit/cbbbf0631969bf0e4578f4b1eef62c1aab115d79 +> X-Git-Archeology: Date: Tue, 01 Jan 2019 19:37:27 -0500 +> X-Git-Archeology: From: Martin Ayotte +> X-Git-Archeology: Subject: fix RockPi-4B naming + fix vcc5v0_host gpio pin +> X-Git-Archeology: +> X-Git-Archeology: - Revision a186fd498404fdae7d3a25dec64f014c590027d6: https://github.com/armbian/build/commit/a186fd498404fdae7d3a25dec64f014c590027d6 +> X-Git-Archeology: Date: Wed, 05 Feb 2020 00:19:00 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switched rockchip64-dev to mainline kernel 5.5.y (#1781) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 5e251dc4148f7a7e3fa61d440c5a268626624de3: https://github.com/armbian/build/commit/5e251dc4148f7a7e3fa61d440c5a268626624de3 +> X-Git-Archeology: Date: Mon, 06 Apr 2020 19:06:28 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Merged rockpi-s dev info rockchip64-dev and moved to 5.6.y (#1874) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37 +> X-Git-Archeology: Date: Sat, 18 Jul 2020 23:07:01 +0200 +> X-Git-Archeology: From: Werner +> X-Git-Archeology: Subject: Move rockchip/64 current to 5.7.y (#2099) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070 +> X-Git-Archeology: Date: Sun, 13 Dec 2020 22:13:03 -0500 +> X-Git-Archeology: From: tonymac32 +> X-Git-Archeology: Subject: [ rockchip64 ] Clean up patchset +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 +> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 +> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +index 25ee84e06874..f5f521986d43 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +@@ -17,6 +17,7 @@ aliases { + }; + + chosen { ++ bootargs = "mmc_cmdqueue=0 earlycon=uart8250,mmio32,0xff1a0000"; + stdout-path = "serial2:1500000n8"; + }; + +@@ -815,6 +816,7 @@ &sdmmc { + + &sdhci { + bus-width = <8>; ++ keep-power-in-suspend; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpro64-fix-spi1-flash-speed.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-fix-spi1-flash-speed.patch new file mode 100644 index 000000000..3fb67e1c6 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-fix-spi1-flash-speed.patch @@ -0,0 +1,105 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Martin Ayotte +Date: Sat, 5 Jan 2019 09:50:02 -0500 +Subject: [ARCHEOLOGY] slow SPIFlash to avoid errors + +> X-Git-Archeology: - Revision ea20f750bfead37ced7b604a44f8f014e317abad: https://github.com/armbian/build/commit/ea20f750bfead37ced7b604a44f8f014e317abad +> X-Git-Archeology: Date: Sat, 05 Jan 2019 09:50:02 -0500 +> X-Git-Archeology: From: Martin Ayotte +> X-Git-Archeology: Subject: slow SPIFlash to avoid errors +> X-Git-Archeology: +> X-Git-Archeology: - Revision a186fd498404fdae7d3a25dec64f014c590027d6: https://github.com/armbian/build/commit/a186fd498404fdae7d3a25dec64f014c590027d6 +> X-Git-Archeology: Date: Wed, 05 Feb 2020 00:19:00 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switched rockchip64-dev to mainline kernel 5.5.y (#1781) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 5e251dc4148f7a7e3fa61d440c5a268626624de3: https://github.com/armbian/build/commit/5e251dc4148f7a7e3fa61d440c5a268626624de3 +> X-Git-Archeology: Date: Mon, 06 Apr 2020 19:06:28 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Merged rockpi-s dev info rockchip64-dev and moved to 5.6.y (#1874) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37 +> X-Git-Archeology: Date: Sat, 18 Jul 2020 23:07:01 +0200 +> X-Git-Archeology: From: Werner +> X-Git-Archeology: Subject: Move rockchip/64 current to 5.7.y (#2099) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 40665cde86285060e6bdd5ef7dc33be6c301ec66: https://github.com/armbian/build/commit/40665cde86285060e6bdd5ef7dc33be6c301ec66 +> X-Git-Archeology: Date: Sun, 13 Dec 2020 23:22:08 -0500 +> X-Git-Archeology: From: tonymac32 +> X-Git-Archeology: Subject: [ rockchip64 ] Patch reorg round 2 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 +> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 +> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +index f5f521986d43..6eddc07a958f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +@@ -838,7 +838,7 @@ &spi1 { + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; +- spi-max-frequency = <10000000>; ++ spi-max-frequency = <3000000>; + }; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-rockpro64-work-led-heartbeat.patch b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-work-led-heartbeat.patch new file mode 100644 index 000000000..9e17aa826 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-rockpro64-work-led-heartbeat.patch @@ -0,0 +1,95 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Piotr Szczepanik +Date: Mon, 24 Aug 2020 22:47:03 +0200 +Subject: [ARCHEOLOGY] Switch RockPro64 work led to heartbeat trigger + +> X-Git-Archeology: - Revision 42e76b9277ad492e935cc76c2b37c9f6d882a675: https://github.com/armbian/build/commit/42e76b9277ad492e935cc76c2b37c9f6d882a675 +> X-Git-Archeology: Date: Mon, 24 Aug 2020 22:47:03 +0200 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch RockPro64 work led to heartbeat trigger +> X-Git-Archeology: +> X-Git-Archeology: - Revision d1eb0003854909824d17b529cd513feb542bf228: https://github.com/armbian/build/commit/d1eb0003854909824d17b529cd513feb542bf228 +> X-Git-Archeology: Date: Mon, 24 Aug 2020 23:11:20 +0200 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch RockPro64 work led to heartbeat trigger (in legacy too) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5: https://github.com/armbian/build/commit/4d4c3f58ffc1cbfbb060cbabc9eb414036a2fda5 +> X-Git-Archeology: Date: Wed, 02 Sep 2020 23:22:09 +0200 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switched rockchip64 curent to kernel 5.8.y (#2175) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 +> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 +> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +index 6eddc07a958f..eb1eebadb637 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +@@ -66,7 +66,7 @@ leds { + + work_led: led-0 { + label = "work"; +- default-state = "on"; ++ linux,default-trigger = "heartbeat"; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/board-tvbox-rk3318.patch b/patch/kernel/archive/rockchip64-6.6/board-tvbox-rk3318.patch new file mode 100644 index 000000000..5efef5224 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/board-tvbox-rk3318.patch @@ -0,0 +1,362 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paolo +Date: Thu, 23 Jun 2022 08:30:54 +0200 +Subject: [ARCHEOLOGY] rockchip64: add rk3318-box tvbox board patch and + configurations (#3921) + +> X-Git-Archeology: > recovered message: > * rockchip64: add rk3318-box tvbox board patch and configurations +> X-Git-Archeology: > recovered message: > * rockchip64: add missing bcm43342 patch for edge kernel +> X-Git-Archeology: - Revision 2ca6a9381db4b875533926e0eae9d3d17f68ad06: https://github.com/armbian/build/commit/2ca6a9381db4b875533926e0eae9d3d17f68ad06 +> X-Git-Archeology: Date: Thu, 23 Jun 2022 08:30:54 +0200 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: rockchip64: add rk3318-box tvbox board patch and configurations (#3921) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0310f955051adafee3a9701e7e54f01d6a496ff5: https://github.com/armbian/build/commit/0310f955051adafee3a9701e7e54f01d6a496ff5 +> X-Git-Archeology: Date: Sat, 09 Jul 2022 16:30:16 +0200 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: rockchip64: fix rk3318-box cpu voltages (#3976) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi | 311 ++++++++++ + 1 file changed, 311 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi +new file mode 100644 +index 000000000000..31a28d82952f +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3318-dram-default-timing.dtsi +@@ -0,0 +1,311 @@ ++/* ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#include ++#include ++ ++/ { ++ ddr_timing: ddr_timing { ++ compatible = "rockchip,ddr-timing"; ++ ddr3_speed_bin = ; ++ ddr4_speed_bin = ; ++ pd_idle = <0>; ++ sr_idle = <0>; ++ sr_mc_gate_idle = <0>; ++ srpd_lite_idle = <0>; ++ standby_idle = <0>; ++ ++ auto_pd_dis_freq = <1066>; ++ auto_sr_dis_freq = <800>; ++ ddr3_dll_dis_freq = <300>; ++ ddr4_dll_dis_freq = <625>; ++ phy_dll_dis_freq = <400>; ++ ++ ddr3_odt_dis_freq = <100>; ++ phy_ddr3_odt_dis_freq = <100>; ++ ddr3_drv = ; ++ ddr3_odt = ; ++ phy_ddr3_ca_drv = ; ++ phy_ddr3_ck_drv = ; ++ phy_ddr3_dq_drv = ; ++ phy_ddr3_odt = ; ++ ++ lpddr3_odt_dis_freq = <666>; ++ phy_lpddr3_odt_dis_freq = <666>; ++ lpddr3_drv = ; ++ lpddr3_odt = ; ++ phy_lpddr3_ca_drv = ; ++ phy_lpddr3_ck_drv = ; ++ phy_lpddr3_dq_drv = ; ++ phy_lpddr3_odt = ; ++ ++ lpddr4_odt_dis_freq = <800>; ++ phy_lpddr4_odt_dis_freq = <800>; ++ lpddr4_drv = ; ++ lpddr4_dq_odt = ; ++ lpddr4_ca_odt = ; ++ phy_lpddr4_ca_drv = ; ++ phy_lpddr4_ck_cs_drv = ; ++ phy_lpddr4_dq_drv = ; ++ phy_lpddr4_odt = ; ++ ++ ddr4_odt_dis_freq = <666>; ++ phy_ddr4_odt_dis_freq = <666>; ++ ddr4_drv = ; ++ ddr4_odt = ; ++ phy_ddr4_ca_drv = ; ++ phy_ddr4_ck_drv = ; ++ phy_ddr4_dq_drv = ; ++ phy_ddr4_odt = ; ++ ++ /* CA de-skew, one step is 47.8ps, range 0-15 */ ++ ddr3a1_ddr4a9_de-skew = <2>; ++ ddr3a0_ddr4a10_de-skew = <3>; ++ ddr3a3_ddr4a6_de-skew = <3>; ++ ddr3a2_ddr4a4_de-skew = <2>; ++ ddr3a5_ddr4a8_de-skew = <3>; ++ ddr3a4_ddr4a5_de-skew = <2>; ++ ddr3a7_ddr4a11_de-skew = <3>; ++ ddr3a6_ddr4a7_de-skew = <2>; ++ ddr3a9_ddr4a0_de-skew = <2>; ++ ddr3a8_ddr4a13_de-skew = <1>; ++ ddr3a11_ddr4a3_de-skew = <2>; ++ ddr3a10_ddr4cs0_de-skew = <2>; ++ ddr3a13_ddr4a2_de-skew = <1>; ++ ddr3a12_ddr4ba1_de-skew = <2>; ++ ddr3a15_ddr4odt0_de-skew = <3>; ++ ddr3a14_ddr4a1_de-skew = <2>; ++ ddr3ba1_ddr4a15_de-skew = <2>; ++ ddr3ba0_ddr4bg0_de-skew = <4>; ++ ddr3ras_ddr4cke_de-skew = <4>; ++ ddr3ba2_ddr4ba0_de-skew = <3>; ++ ddr3we_ddr4bg1_de-skew = <2>; ++ ddr3cas_ddr4a12_de-skew = <2>; ++ ddr3ckn_ddr4ckn_de-skew = <11>; ++ ddr3ckp_ddr4ckp_de-skew = <11>; ++ ddr3cke_ddr4a16_de-skew = <2>; ++ ddr3odt0_ddr4a14_de-skew = <4>; ++ ddr3cs0_ddr4act_de-skew = <4>; ++ ddr3reset_ddr4reset_de-skew = <7>; ++ ddr3cs1_ddr4cs1_de-skew = <7>; ++ ddr3odt1_ddr4odt1_de-skew = <7>; ++ ++ /* DATA de-skew ++ * RX one step is 25.1ps, range 0-15 ++ * TX one step is 47.8ps, range 0-15 ++ */ ++ cs0_dm0_rx_de-skew = <12>; ++ cs0_dm0_tx_de-skew = <10>; ++ cs0_dq0_rx_de-skew = <12>; ++ cs0_dq0_tx_de-skew = <10>; ++ cs0_dq1_rx_de-skew = <12>; ++ cs0_dq1_tx_de-skew = <10>; ++ cs0_dq2_rx_de-skew = <12>; ++ cs0_dq2_tx_de-skew = <10>; ++ cs0_dq3_rx_de-skew = <12>; ++ cs0_dq3_tx_de-skew = <10>; ++ cs0_dq4_rx_de-skew = <12>; ++ cs0_dq4_tx_de-skew = <10>; ++ cs0_dq5_rx_de-skew = <12>; ++ cs0_dq5_tx_de-skew = <10>; ++ cs0_dq6_rx_de-skew = <12>; ++ cs0_dq6_tx_de-skew = <10>; ++ cs0_dq7_rx_de-skew = <12>; ++ cs0_dq7_tx_de-skew = <10>; ++ cs0_dqs0_rx_de-skew = <10>; ++ cs0_dqs0p_tx_de-skew = <12>; ++ cs0_dqs0n_tx_de-skew = <12>; ++ ++ cs0_dm1_rx_de-skew = <10>; ++ cs0_dm1_tx_de-skew = <8>; ++ cs0_dq8_rx_de-skew = <10>; ++ cs0_dq8_tx_de-skew = <8>; ++ cs0_dq9_rx_de-skew = <10>; ++ cs0_dq9_tx_de-skew = <8>; ++ cs0_dq10_rx_de-skew = <10>; ++ cs0_dq10_tx_de-skew = <8>; ++ cs0_dq11_rx_de-skew = <10>; ++ cs0_dq11_tx_de-skew = <8>; ++ cs0_dq12_rx_de-skew = <10>; ++ cs0_dq12_tx_de-skew = <8>; ++ cs0_dq13_rx_de-skew = <10>; ++ cs0_dq13_tx_de-skew = <8>; ++ cs0_dq14_rx_de-skew = <10>; ++ cs0_dq14_tx_de-skew = <8>; ++ cs0_dq15_rx_de-skew = <10>; ++ cs0_dq15_tx_de-skew = <8>; ++ cs0_dqs1_rx_de-skew = <9>; ++ cs0_dqs1p_tx_de-skew = <10>; ++ cs0_dqs1n_tx_de-skew = <10>; ++ ++ cs0_dm2_rx_de-skew = <10>; ++ cs0_dm2_tx_de-skew = <9>; ++ cs0_dq16_rx_de-skew = <10>; ++ cs0_dq16_tx_de-skew = <9>; ++ cs0_dq17_rx_de-skew = <10>; ++ cs0_dq17_tx_de-skew = <9>; ++ cs0_dq18_rx_de-skew = <10>; ++ cs0_dq18_tx_de-skew = <9>; ++ cs0_dq19_rx_de-skew = <10>; ++ cs0_dq19_tx_de-skew = <9>; ++ cs0_dq20_rx_de-skew = <10>; ++ cs0_dq20_tx_de-skew = <9>; ++ cs0_dq21_rx_de-skew = <10>; ++ cs0_dq21_tx_de-skew = <9>; ++ cs0_dq22_rx_de-skew = <10>; ++ cs0_dq22_tx_de-skew = <9>; ++ cs0_dq23_rx_de-skew = <10>; ++ cs0_dq23_tx_de-skew = <9>; ++ cs0_dqs2_rx_de-skew = <9>; ++ cs0_dqs2p_tx_de-skew = <11>; ++ cs0_dqs2n_tx_de-skew = <11>; ++ ++ cs0_dm3_rx_de-skew = <7>; ++ cs0_dm3_tx_de-skew = <7>; ++ cs0_dq24_rx_de-skew = <7>; ++ cs0_dq24_tx_de-skew = <7>; ++ cs0_dq25_rx_de-skew = <7>; ++ cs0_dq25_tx_de-skew = <7>; ++ cs0_dq26_rx_de-skew = <7>; ++ cs0_dq26_tx_de-skew = <7>; ++ cs0_dq27_rx_de-skew = <7>; ++ cs0_dq27_tx_de-skew = <7>; ++ cs0_dq28_rx_de-skew = <7>; ++ cs0_dq28_tx_de-skew = <7>; ++ cs0_dq29_rx_de-skew = <7>; ++ cs0_dq29_tx_de-skew = <7>; ++ cs0_dq30_rx_de-skew = <7>; ++ cs0_dq30_tx_de-skew = <7>; ++ cs0_dq31_rx_de-skew = <7>; ++ cs0_dq31_tx_de-skew = <7>; ++ cs0_dqs3_rx_de-skew = <7>; ++ cs0_dqs3p_tx_de-skew = <10>; ++ cs0_dqs3n_tx_de-skew = <10>; ++ ++ cs1_dm0_rx_de-skew = <7>; ++ cs1_dm0_tx_de-skew = <8>; ++ cs1_dq0_rx_de-skew = <7>; ++ cs1_dq0_tx_de-skew = <8>; ++ cs1_dq1_rx_de-skew = <7>; ++ cs1_dq1_tx_de-skew = <8>; ++ cs1_dq2_rx_de-skew = <7>; ++ cs1_dq2_tx_de-skew = <8>; ++ cs1_dq3_rx_de-skew = <7>; ++ cs1_dq3_tx_de-skew = <8>; ++ cs1_dq4_rx_de-skew = <7>; ++ cs1_dq4_tx_de-skew = <8>; ++ cs1_dq5_rx_de-skew = <7>; ++ cs1_dq5_tx_de-skew = <8>; ++ cs1_dq6_rx_de-skew = <7>; ++ cs1_dq6_tx_de-skew = <8>; ++ cs1_dq7_rx_de-skew = <7>; ++ cs1_dq7_tx_de-skew = <8>; ++ cs1_dqs0_rx_de-skew = <6>; ++ cs1_dqs0p_tx_de-skew = <9>; ++ cs1_dqs0n_tx_de-skew = <9>; ++ ++ cs1_dm1_rx_de-skew = <7>; ++ cs1_dm1_tx_de-skew = <7>; ++ cs1_dq8_rx_de-skew = <7>; ++ cs1_dq8_tx_de-skew = <8>; ++ cs1_dq9_rx_de-skew = <7>; ++ cs1_dq9_tx_de-skew = <7>; ++ cs1_dq10_rx_de-skew = <7>; ++ cs1_dq10_tx_de-skew = <8>; ++ cs1_dq11_rx_de-skew = <7>; ++ cs1_dq11_tx_de-skew = <7>; ++ cs1_dq12_rx_de-skew = <7>; ++ cs1_dq12_tx_de-skew = <8>; ++ cs1_dq13_rx_de-skew = <7>; ++ cs1_dq13_tx_de-skew = <7>; ++ cs1_dq14_rx_de-skew = <7>; ++ cs1_dq14_tx_de-skew = <8>; ++ cs1_dq15_rx_de-skew = <7>; ++ cs1_dq15_tx_de-skew = <7>; ++ cs1_dqs1_rx_de-skew = <7>; ++ cs1_dqs1p_tx_de-skew = <9>; ++ cs1_dqs1n_tx_de-skew = <9>; ++ ++ cs1_dm2_rx_de-skew = <7>; ++ cs1_dm2_tx_de-skew = <8>; ++ cs1_dq16_rx_de-skew = <7>; ++ cs1_dq16_tx_de-skew = <8>; ++ cs1_dq17_rx_de-skew = <7>; ++ cs1_dq17_tx_de-skew = <8>; ++ cs1_dq18_rx_de-skew = <7>; ++ cs1_dq18_tx_de-skew = <8>; ++ cs1_dq19_rx_de-skew = <7>; ++ cs1_dq19_tx_de-skew = <8>; ++ cs1_dq20_rx_de-skew = <7>; ++ cs1_dq20_tx_de-skew = <8>; ++ cs1_dq21_rx_de-skew = <7>; ++ cs1_dq21_tx_de-skew = <8>; ++ cs1_dq22_rx_de-skew = <7>; ++ cs1_dq22_tx_de-skew = <8>; ++ cs1_dq23_rx_de-skew = <7>; ++ cs1_dq23_tx_de-skew = <8>; ++ cs1_dqs2_rx_de-skew = <6>; ++ cs1_dqs2p_tx_de-skew = <9>; ++ cs1_dqs2n_tx_de-skew = <9>; ++ ++ cs1_dm3_rx_de-skew = <7>; ++ cs1_dm3_tx_de-skew = <7>; ++ cs1_dq24_rx_de-skew = <7>; ++ cs1_dq24_tx_de-skew = <8>; ++ cs1_dq25_rx_de-skew = <7>; ++ cs1_dq25_tx_de-skew = <7>; ++ cs1_dq26_rx_de-skew = <7>; ++ cs1_dq26_tx_de-skew = <7>; ++ cs1_dq27_rx_de-skew = <7>; ++ cs1_dq27_tx_de-skew = <7>; ++ cs1_dq28_rx_de-skew = <7>; ++ cs1_dq28_tx_de-skew = <7>; ++ cs1_dq29_rx_de-skew = <7>; ++ cs1_dq29_tx_de-skew = <7>; ++ cs1_dq30_rx_de-skew = <7>; ++ cs1_dq30_tx_de-skew = <7>; ++ cs1_dq31_rx_de-skew = <7>; ++ cs1_dq31_tx_de-skew = <7>; ++ cs1_dqs3_rx_de-skew = <7>; ++ cs1_dqs3p_tx_de-skew = <9>; ++ cs1_dqs3n_tx_de-skew = <9>; ++ }; ++}; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/drv-spi-spidev-remove-warnings.patch b/patch/kernel/archive/rockchip64-6.6/drv-spi-spidev-remove-warnings.patch new file mode 100644 index 000000000..3a6d63592 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/drv-spi-spidev-remove-warnings.patch @@ -0,0 +1,32 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 2 Feb 2022 11:56:51 +0300 +Subject: drv:spi:spidev remove warnings + +--- + drivers/spi/spidev.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c +index d13dc15cc191..90d9a33a97bf 100644 +--- a/drivers/spi/spidev.c ++++ b/drivers/spi/spidev.c +@@ -704,6 +704,7 @@ static const struct file_operations spidev_fops = { + static struct class *spidev_class; + + static const struct spi_device_id spidev_spi_ids[] = { ++ { .name = "spi-dev" }, + { .name = "dh2228fv" }, + { .name = "ltc2488" }, + { .name = "sx1301" }, +@@ -732,6 +733,7 @@ static int spidev_of_check(struct device *dev) + } + + static const struct of_device_id spidev_dt_ids[] = { ++ { .compatible = "armbian,spi-dev", .data = &spidev_of_check }, + { .compatible = "cisco,spi-petra", .data = &spidev_of_check }, + { .compatible = "dh,dhcom-board", .data = &spidev_of_check }, + { .compatible = "lineartechnology,ltc2488", .data = &spidev_of_check }, +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3318-box.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3318-box.dts new file mode 100644 index 000000000..cfc43f647 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3318-box.dts @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Paolo Sabatino + */ + +/dts-v1/; +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/input/input.h" +#include "rk3328.dtsi" +#include "rk3318-dram-default-timing.dtsi" + +/ { + model = "Rockchip RK3318 BOX"; + compatible = "rockchip,rk3318-box", "rockchip,rk3328-box", "rockchip,rk3328"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdio; + mmc2 = &emmc; + mmc3 = &sdmmc_ext; + mmc4 = &sdio_ext; + }; + + /delete-node/ opp-table-0; + /delete-node/ gpu-opp-table; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1275000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000 950000 1200000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1050000 950000 1200000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000 950000 1200000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 950000 1200000>; + }; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc_keys: adc-keys { + + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "recovery"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + gmac_clkin: gmac-clkin { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0x00>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + vcc_18: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_io: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_pin>; + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + /* + * USB3 vbus + */ + vcc_host_vbus: vcc-host-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_vbus"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + }; + + /* + * USB2 OTG vbus + */ + vcc_otg_vbus: vcc-otg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_otg_vbus"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + }; + + vdd_arm: vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_logic: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; + + gpio_led: gpio-leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&working_led>; + + working { + gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + default-state = "on"; + }; + + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + /* + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_rts_gpio>; + BT,power_gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6330"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + }; + */ + + fd628_dev { + compatible = "fd628_dev"; + fd628_gpio_clk = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + fd628_gpio_dat = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + analog-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "ANALOG"; + + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "HDMI"; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + /* + * This node is a duplicate of sdmmc_ext: most common board do not use sdmmc_ext + * controller, so it is left unused. Some other boards use it as sdio controller + * for wifi and some others use it as sdcard controller. + * To handle the most critical situation, the controller will be configured as + * sdcard controller by default. An overlay can be set to disable the sdmmc_ext + * node and enable this sdio_ext in case wifi chips are attached to this. + */ + sdio_ext: mmc@ff5f0000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff5f0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, + <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMCEXT>; + reset-names = "reset"; + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <>; + non-removable; + num-slots = <1>; + pinctrl-0 = <&sdmmc0ext_cmd &sdmmc0ext_clk &sdmmc0ext_bus4>; + pinctrl-names = "default"; + supports-sdio; + status = "disabled"; + }; + +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + ddr_timing = <&ddr_timing>; + status = "disabled"; +}; + +&codec { + status = "okay"; + mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&emmc { + + supports-emmc; + no-sdio; + no-sd; + cap-mmc-highspeed; + disable-wp; + non-removable; + bus-width = <8>; + num-slots = <0x01>; + + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_18>; + + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <500>; + cd-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + disable-wp; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + supports-sd; + status = "okay"; + vmmc-supply = <&vcc_sd>; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + supports-sdio; + status = "okay"; +}; + +/* + * sdmmc_ext is configured as sdcard controller and enabled by default. + * In this way boards which have the sdcard attached to sdmmc_ext will work + * by default. In case the controller is not attached to anything, the + * kernel will just autodetect and give up. + */ +&sdmmc_ext { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <500>; + cd-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + disable-wp; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_dectn &sdmmc0ext_bus4>; + supports-sd; + status = "okay"; + vmmc-supply = <&vcc_sd>; +}; + +&gmac2phy { + phy-supply = <&vcc_phy>; + + phy-mode = "rmii"; + + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-rate = <50000000>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + tx_delay = <0x30>; + rx_delay = <0x10>; + + status = "okay"; + +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_logic>; +}; + +/* +&h265e { + status = "okay"; +}; +*/ + +&h265e_mmu { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&spdif { + pinctrl-0 = <&spdifm0_tx>; + status = "okay"; +}; + +&spdif_out { + status = "okay"; +}; + +&spdif_sound { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_18>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&clk_32k_out>; + + clk_32k { + clk_32k_out: clk-32k-out { + rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; + }; + }; + + leds { + working_led: working-led { + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none_2ma>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_4ma>;/*, + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none_4ma>;*/ + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + + /* + * SDIO host wake interrupt on YX_RK3328 board (sdio is attached to + * regular mmc controller mmc@ff510000) + */ + sdio_host_wake: sdio-host-wake { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* + * SDIO host wake interrupt on X88_PRO_B board (sdio is attached to + * alternative mmc controller mmc@ff5f0000) + */ + sdio_host_wake_ext: sdio-host-wake-ext { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + +}; + +/* +&vdec { + status = "okay"; + vcodec-supply = <&vdd_logic>; +}; +*/ + +&vdec_mmu { + status = "okay"; +}; + +&threshold { + temperature = <80000>; /* millicelsius */ +}; + +&target { + temperature = <95000>; /* millicelsius */ +}; + +&soc_crit { + temperature = <100000>; /* millicelsius */ +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart0 { + + status = "okay"; + +}; + +&uart2 { + /delete-property/ dmas; + /delete-property/ dma-names; + + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vpu { + status = "okay"; + vcodec-supply = <&vdd_logic>; +}; + +&vpu_mmu { + status = "okay"; +}; + +/* +&vepu { + status = "okay"; +}; +*/ + +&vepu_mmu { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +/* +&rga { + status = "okay"; +}; +*/ + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&analog_sound { + status = "okay"; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-neo3-rev02.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-neo3-rev02.dts new file mode 100644 index 000000000..496e334d3 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-neo3-rev02.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + */ + +/dts-v1/; +#include +#include "rk3328-nanopi-r2s.dts" + +/ { + model = "FriendlyElec NanoPi NEO3"; + compatible = "friendlyelec,nanopi-neo3", "rockchip,rk3328"; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key1>; + + button@0 { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + i2s-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "I2S Out"; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + + simple-audio-card,codec { + sound-dai = <&pcm5102>; + }; + }; + + pcm5102: pcm510x { + #sound-dai-cells = <0>; + compatible = "ti,pcm5102a"; + pcm510x,format = "i2s"; + }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc_rtl8153: vcc-rtl8153-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_en_drv>; + regulator-always-on; + regulator-name = "vcc_rtl8153"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + off-on-delay-us = <5000>; + enable-active-high; + }; +}; + +&mach { + hwrev = <2>; + model = "NanoPi NEO3"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_mclk + &i2s1_sclk + &i2s1_lrcktx + &i2s1_lrckrx + &i2s1_sdo + &i2s1_sdi>; + status = "okay"; +}; + +&spdif { + status = "okay"; + pinctrl-0 = <&spdifm0_tx>; +}; + +&emmc { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; +}; + +&leds { + status = "okay"; + +}; + +&leds_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&pwm2 { + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&pwm2_sleep_pin>; + status = "okay"; +}; + +&rk805 { + interrupt-parent = <&gpio1>; + interrupts = ; +}; + +&vccio_sd { + status = "okay"; +}; + +&io_domains { + vccio3-supply = <&vccio_sd>; +}; + +&sdmmc { + vqmmc-supply = <&vccio_sd>; + max-frequency = <150000000>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc_ext { + status = "disabled"; +}; + +&sdio_pwrseq { + status = "disabled"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pwm { + pwm2_sleep_pin: pwm2-sleep-pin { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + rockchip-key { + gpio_key1: gpio-key1 { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb30_en_drv: usb30-en-drv { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart1{ + status = "okay"; + pinctl-0 = <&uart1_xfer>; +}; + diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-r2-rev00.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-r2-rev00.dts new file mode 100644 index 000000000..8ba95189c --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-r2-rev00.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + */ + +/dts-v1/; +#include +#include "rk3328-nanopi-r2s.dts" + +/ { + model = "FriendlyElec NanoPi R2S"; + compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key1>; + + button@0 { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + vcc_rtl8153: vcc-rtl8153-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_en_drv>; + regulator-always-on; + regulator-name = "vcc_rtl8153"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + off-on-delay-us = <5000>; + enable-active-high; + }; +}; + +&mach { + hwrev = <0>; + model = "NanoPi R2S"; +}; + +&emmc { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; +}; + +&leds { + status = "okay"; + + led@2 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "lan_led"; + }; + + led@3 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "wan_led"; + }; +}; + +&rk805 { + interrupt-parent = <&gpio1>; + interrupts = ; +}; + +&vccio_sd { + status = "okay"; +}; + +&io_domains { + vccio3-supply = <&vccio_sd>; +}; + +&sdmmc { + vqmmc-supply = <&vccio_sd>; + max-frequency = <150000000>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc_ext { + status = "disabled"; +}; + +&sdio_pwrseq { + status = "disabled"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + gpio_key1: gpio-key1 { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb30_en_drv: usb30-en-drv { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-r2-rev06.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-r2-rev06.dts new file mode 100644 index 000000000..21be5a2c5 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-r2-rev06.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + */ + +/dts-v1/; + +#include "rk3328-nanopi-r2-rev00.dts" + +/ { + model = "FriendlyElec NanoPi R2C"; + compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; +}; + +&mach { + hwrev = <6>; + model = "NanoPi R2C"; +}; + +&rgmiim1_pins { + rockchip,pins = + /* mac_txclk */ + <1 RK_PB4 2 &pcfg_pull_none_8ma>, + /* mac_rxclk */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* mac_mdio */ + <1 RK_PC3 2 &pcfg_pull_none_2ma>, + /* mac_txen */ + <1 RK_PD1 2 &pcfg_pull_none_8ma>, + /* mac_clk */ + <1 RK_PC5 2 &pcfg_pull_none_2ma>, + /* mac_rxdv */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* mac_mdc */ + <1 RK_PC7 2 &pcfg_pull_none_2ma>, + /* mac_rxd1 */ + <1 RK_PB2 2 &pcfg_pull_none>, + /* mac_rxd0 */ + <1 RK_PB3 2 &pcfg_pull_none>, + /* mac_txd1 */ + <1 RK_PB0 2 &pcfg_pull_none_8ma>, + /* mac_txd0 */ + <1 RK_PB1 2 &pcfg_pull_none_8ma>, + /* mac_rxd3 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* mac_rxd2 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* mac_txd3 */ + <1 RK_PC0 2 &pcfg_pull_none_8ma>, + /* mac_txd2 */ + <1 RK_PC1 2 &pcfg_pull_none_8ma>, + + /* mac_txclk */ + <0 RK_PB0 1 &pcfg_pull_none>, + /* mac_txen */ + <0 RK_PB4 1 &pcfg_pull_none>, + /* mac_clk */ + <0 RK_PD0 1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 RK_PC0 1 &pcfg_pull_none>, + /* mac_txd0 */ + <0 RK_PC1 1 &pcfg_pull_none>, + /* mac_txd3 */ + <0 RK_PC7 1 &pcfg_pull_none>, + /* mac_txd2 */ + <0 RK_PC6 1 &pcfg_pull_none>; +}; + +/delete-node/ &rtl8211e; + +&gmac2io { + phy-handle = <ðphy3>; + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x22>; + rx_delay = <0x12>; + mdio { + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-id0000.011a", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupt-parent = <&gpio2>; + interrupts = ; + //reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + keep-clkout-on; + }; + }; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-r2-rev20.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-r2-rev20.dts new file mode 100644 index 000000000..ad327ca56 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-nanopi-r2-rev20.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + */ + +/dts-v1/; +#include "rk3328-nanopi-r2s.dts" + +/ { + model = "FriendlyElec NanoPi R2"; + compatible = "friendlyelec,nanopi-r2", "rockchip,rk3328"; +}; + +&mach { + hwrev = <0x20>; + model = "NanoPi R2"; +}; + +&gmac2io { + pinctrl-0 = <&rgmiim1_pins>, <&phy_intb>, <&phy_rstb>; +}; + +&rtl8211e { + interrupt-parent = <&gpio1>; + interrupts = ; +}; + +&pinctrl { + phy { + phy_intb: phy-intb { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3328-orangepi-r1-plus-lts.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-orangepi-r1-plus-lts.dts new file mode 100644 index 000000000..4e944e0c1 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-orangepi-r1-plus-lts.dts @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* Copyright (c) 2020 David Bauer + * Copyright (c) 2020 Shenzhen Xunlong Software CO.,Limited + * Copyright (c) 2021 AmadeusGhost + * Revised for Orange Pi R1 Plus LTS (c) 2022 schwar3kat + * Based on Orange Pi R1 plus + */ + +/dts-v1/; + +#include +#include +#include "rk3328.dtsi" + +/ { + model = "Xunlong Orange Pi R1 Plus LTS"; + compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; + + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clk: gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&reset_button_pin>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <50>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; + + lan_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "orangepi-r1-plus-lts:green:lan"; + }; + + sys_led: led-1 { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + label = "orangepi-r1-plus-lts:red:status"; + linux,default-trigger = "heartbeat"; + }; + + wan_led: led-2 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "orangepi-r1-plus-lts:green:wan"; + }; + }; + + vcc_io_sdio: sdmmcio-regulator { + compatible = "regulator-gpio"; + enable-active-high; + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdio_vcc_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_io_sdio"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-settling-time-us = <5000>; + regulator-type = "voltage"; + startup-delay-us = <2000>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&vcc_io_33>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc0m1_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io_33>; + }; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_5v_lan: vdd-5v-lan { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&lan_vdd_pin>; + pinctrl-names = "default"; + regulator-name = "vdd_5v_lan"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "disabled"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc_io_33>; + pinctrl-0 = <&rgmiim1_pins>; + pinctrl-names = "default"; + snps,aal; + status = "okay"; + phy-handle = <&yt8531c>; + tx_delay = <0x19>; + rx_delay = <0x05>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + yt8531c: ethernet-phy@0 { + compatible = "ethernet-phy-id4f51.e91b", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + motorcomm,clk-out-frequency-hz = <125000000>; + motorcomm,keep-pll-enabled; + motorcomm,auto-sleep-disabled; + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <15000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pmic_int_l>; + pinctrl-names = "default"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vdd_5v>; + vcc2-supply = <&vdd_5v>; + vcc3-supply = <&vdd_5v>; + vcc4-supply = <&vdd_5v>; + vcc5-supply = <&vcc_io_33>; + vcc6-supply = <&vdd_5v>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io_33: DCDC_REG4 { + regulator-name = "vcc_io_33"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + pmuio-supply = <&vcc_io_33>; + vccio1-supply = <&vcc_io_33>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io_sdio>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io_33>; + vccio6-supply = <&vcc_io_33>; + status = "okay"; +}; + +&pinctrl { + button { + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac2io { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_pin: sys-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lan { + lan_vdd_pin: lan-vdd-pin { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sd { + sdio_vcc_pin: sdio-vcc-pin { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-names = "default"; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_io_sdio>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; + dr_mode = "host"; +}; + +&usbdrd3 { + dr_mode = "host"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + snps,xhci-trb-ent-quirk; + + /* Second port is for USB 3.0 */ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; + realtek,led-data = <0x87>; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&spi0 { + max-freq = <48000000>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&dmc_opp_table { + opp-798000000 { + status = "disabled"; + }; + opp-840000000 { + status = "disabled"; + }; + opp-924000000 { + status = "disabled"; + }; + opp-1056000000 { + status = "disabled"; + }; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3328-z28pro.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-z28pro.dts new file mode 100644 index 000000000..0b2e21a13 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3328-z28pro.dts @@ -0,0 +1 @@ +#include "rk3328-rock64.dts" diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3399-nanopi-m4v2.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-nanopi-m4v2.dts new file mode 100644 index 000000000..094440ce3 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-nanopi-m4v2.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4V2 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4 Ver2.0"; + compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-init-microvolt = <900000>; + vin-supply = <&vcc5v0_core>; + }; +}; + +&gmac { + rx_delay = <0x16>; +}; + +&rk808 { + max-buck-steps-per-change = <4>; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; + diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3399-nanopi-r4se.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-nanopi-r4se.dts new file mode 100644 index 000000000..1c9d0c34f --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-nanopi-r4se.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3399-nanopi-r4s-enterprise.dts" + +/ { + model = "FriendlyElec NanoPi R4SE"; + compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399"; +}; + +&emmc_phy { + status = "okay"; +}; + +&sdhci { + status = "okay"; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3399-orangepi-4-lts.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-orangepi-4-lts.dts new file mode 100644 index 000000000..2f0baf9fd --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-orangepi-4-lts.dts @@ -0,0 +1,1334 @@ +/* + * SPDX-License-Identifier: (GPL-2.0+ or MIT) + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Akash Gajjar + * Copyright (c) 2020-2022 Armbian (chwe17, piter75, jock) + * + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "OrangePi 4 LTS"; + compatible = "xunlong,orangepi-4-lts", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + aliases { + spi1 = &spi1; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + usb_vbus: usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vbus-5v"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* 0.9 V supply, over PMIC + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + } + */ + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_pcie"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + }; + + es8316c_card: es8316c-card { + compatible = "simple-audio-card"; + + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip-es8316c"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + simple-audio-card,routing = + "MIC1", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&es8316c_codec>; + }; + + }; + + hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "hdmi-sound"; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + spdif-sound { + status = "disable"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disable"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + pwm_bl: backlight { + status = "disable"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + button@0 { + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + + led@1 { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + unisoc_uwe_bsp: uwe-bsp { + compatible = "unisoc,uwe_bsp"; + //wl-reg-on = <&gpio0 10 GPIO_ACTIVE_HIGH>; // handled by sdio-pwrseq + bt-reg-on = <&gpio0 9 GPIO_ACTIVE_HIGH>; + wl-wake-host-gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; + bt-wake-host-gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + sdio-ext-int-gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + unisoc,btwf-file-name = "/lib/firmware/uwe5622/wcnmodem-38222.bin"; + data-irq; + blksz-512; + keep-power-on; + status = "okay"; + }; + + sprd-wlan { + compatible = "sprd,uwe5622-wifi"; + status = "okay"; + }; + + sprd-mtty { + compatible = "sprd,mtty"; + sprd,name = "ttyBT"; + status = "okay"; + }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <328000000>; + opp-microvolt = <900000>; + }; + + opp01 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <900000>; + }; + + opp02 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + + }; + +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rstb>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_s3>; + phy-handle = <&yt8531c>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + yt8531c: ethernet-phy@0 { + compatible = "ethernet-phy-id4f51.e91b", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_intb>; + motorcomm,clk-out-frequency-hz = <125000000>; + motorcomm,keep-pll-enabled; + motorcomm,auto-sleep-disabled; + interrupt-parent = <&gpio3>; + interrupts = ; + }; + }; + +}; + +&spi1 { + status = "disable"; + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&spi1_gpio>; + + spidev0: spidev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&rga { + status = "okay"; +}; + +&cdn_dp { + status = "okay"; + extcon = <&fusb0>; + phys = <&tcphy0_dp>; +}; + +&hdmi { + /* remove the hdmi_i2c_xfer */ + pinctrl-0 = <&hdmi_cec>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; + ddc-i2c-bus = <&i2c7>; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio2>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vcc13-supply = <&vcc3v3_sys>; + vcc14-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc1v8: vcc1v8_s3: vcca1v8_s3: DCDC_REG4 { + regulator-name = "vcc1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-init-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + clock-frequency = <200000>; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + es8316c_codec: es8316c@11 { + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <17>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + //pinctrl-names = "default"; + //pinctrl-0 = <&i2s_8ch_mclk>; + status = "okay"; + }; + +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + fusb0: fusb30x@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + interrupt-parent = <&gpio1>; + interrupts = ; + vbus-supply = <&vbus_typec>; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "sink"; + + extcon-cables = <1 2 5 6 9 10 12 44>; + typec-altmodes = <0xff01 1 0x001c0000 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc_hs: endpoint { + remote-endpoint = + <&u2phy0_typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usbc_ss: endpoint { + remote-endpoint = + <&tcphy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc_dp: endpoint { + remote-endpoint = + <&tcphy0_typec_dp>; + }; + }; + }; + }; + + }; + + ft5x06_ts@38 { + compatible = "edt,edt-ft5x06", "ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + +}; + +&i2c7 { + status = "okay"; +}; + +&spdif { + status = "disable"; + pinctrl-0 = <&spdif_bus>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + #sound-dai-cells = <0>; +}; + +&i2s0 { + rockchip,i2s-broken-burst-len; + assigned-clocks = <&cru SCLK_I2SOUT_SRC>; + assigned-clock-parents = <&cru SCLK_I2S0_8CH>; + resets = <&cru SRST_I2S0_8CH>, <&cru SRST_H_I2S0_8CH>; + reset-names = "reset-m", "reset-h"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pcie_phy { + status = "okay"; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; +}; + +&pcie0 { + status = "okay"; + ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + max-link-speed = <1>; +}; + +&pwm_bl { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca1v8_s3>; /* TBD */ +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + supports-emmc; + non-removable; + keep-power-in-suspend; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&emmc_phy { + status = "okay"; +}; + +&sdio0 { + clock-frequency = <150000000>; + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms = <500>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tcphy0_dp { + port { + tcphy0_typec_dp: endpoint { + remote-endpoint = <&usbc_dp>; + }; + }; +}; + +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&usbc_ss>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&usb3_vbus>; + status = "okay"; + }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&usbc_hs>; + }; + }; + +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&usb_vbus>; + status = "okay"; + }; +}; + +&usbdrd3_0 { + status = "okay"; + extcon = <&fusb0>; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&sdmmc_bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_12ma>, + <4 RK_PB1 1 &pcfg_pull_up_12ma>, + <4 RK_PB2 1 &pcfg_pull_up_12ma>, + <4 RK_PB3 1 &pcfg_pull_up_12ma>; +}; + +&sdmmc_cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_12ma>; +}; + +&pinctrl { + + pcfg_pull_up_12ma: pcfg-pull-up-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + /delete-node/ hdmi-i2c-xfer; + }; + + i2s0 { + i2s_8ch_mclk: i2s-8ch-mclk { + rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rockchip-key { + power_key: power-key { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + leds_gpio: leds-gpio { + rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cam_pins { + cif_clkout_a: cif-clkout-a { + rockchip,pins = <2 11 3 &pcfg_pull_none>; + }; + + cif_clkout_a_sleep: cif-clkout-a-sleep { + rockchip,pins = <2 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam0_default_pins: cam0-default-pins { + rockchip,pins = + <4 27 0 &pcfg_pull_down>, + <2 11 3 &pcfg_pull_none>; + }; + + cam0_sleep_pins: cam0-sleep-pins { + rockchip,pins = + <4 27 3 &pcfg_pull_none>, + <2 11 0 &pcfg_pull_none>; + }; + + cam1_default_pins: cam1-default-pins { + rockchip,pins = + <0 12 RK_FUNC_GPIO &pcfg_pull_down>, + <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + spi1 { + spi1_gpio: spi1-gpio { + rockchip,pins = + <1 7 RK_FUNC_GPIO &pcfg_output_low>, + <1 8 RK_FUNC_GPIO &pcfg_output_low>, + <1 9 RK_FUNC_GPIO &pcfg_output_low>, + <1 10 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + bt { + bt_host_wake: bt-host-wake { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset: bt-reset { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake: bt-wake { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + phy_intb: phy-intb { + rockchip,pins = <3 RK_PB2 1 &pcfg_pull_up>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <3 RK_PB7 1 &pcfg_pull_none>; + }; + }; + +}; + +&hdmi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopl { + status = "disable"; +}; + +&dp_in_vopb { + status = "disable"; +}; +&dp_in_vopl { + status = "okay"; +}; + +&dmc { + #cooling-cells = <2>; /* min followed by max */ + + status = "okay"; + center-supply = <&vdd_log>; + operating-points-v2 = <&dmc_opp_table>; + + rockchip,pd-idle-ns = <160>; + rockchip,sr-idle-ns = <10240>; + rockchip,sr-mc-gate-idle-ns = <40960>; + rockchip,srpd-lite-idle-ns = <61440>; + rockchip,standby-idle-ns = <81920>; + + rockchip,ddr3_odt_dis_freq = <666000000>; + rockchip,lpddr3_odt_dis_freq = <666000000>; + rockchip,lpddr4_odt_dis_freq = <666000000>; + + rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>; + rockchip,srpd-lite-idle-dis-freq-hz = <0>; + rockchip,standby-idle-dis-freq-hz = <928000000>; + +}; + +&dfi { + status = "okay"; +}; + +/* + * Redefine some parameters for the thermal trip points for Opi4 LTS. + * First of all, the Soc does not like getting over 90°C. My sample + * froze at 94.4°C, so we lower the critical temprature to 90°C, hopefully + * giving enough room for safe reboot of the device. + * Big cores are getting throttled a bit when reaching 82°C, then at 85°C + * we aggressively throttle all the cores and even the memory controller. + * The GPU is handled by existing trip points in the base device tree, here + * we just set the same critical temperature as CPU. + */ +&cpu_alert0 { + temperature = <82000>; +}; + +&cpu_alert1 { + temperature = <85000>; +}; + +&cpu_crit { + temperatue = <90000>; +}; + +&gpu_crit { + temperatue = <90000>; +}; + +&cpu_thermal { + + cooling-maps { + + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT 3>, + <&cpu_b1 THERMAL_NO_LIMIT 3>; + }; + + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map2 { + trip = <&cpu_alert1>; + cooling-device = + <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + }; + +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3399-orangepi-4.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-orangepi-4.dts new file mode 100644 index 000000000..976d3f996 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-orangepi-4.dts @@ -0,0 +1,1194 @@ +/* + * SPDX-License-Identifier: (GPL-2.0+ or MIT) + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Akash Gajjar + * Copyright (c) 2020 Armbian (chwe17, piter75) + * + */ + +/dts-v1/; +#include +#include +#include +//#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "OrangePi 4"; + compatible = "xunlong,orangepi-4", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + aliases { + spi1 = &spi1; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + usb_vbus: usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vbus_typec"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* 0.9 V supply, over PMIC + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + } + */ + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_pcie"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + }; + + rt5651_card: rt5651-sound { + status = "okay"; + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + simple-audio-card,name = "realtek,rt5651-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "micbias1", + "IN2P", "Mic Jack", + "IN3P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&rt5651>; + }; + }; + + dw_hdmi_audio: dw-hdmi-audio { + status = "disable"; + compatible = "rockchip,dw-hdmi-audio"; + #sound-dai-cells = <0>; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + }; + + hdmi_dp_sound: hdmi-dp-sound { + status = "okay"; + compatible = "rockchip,rk3399-hdmi-dp"; + rockchip,cpu = <&i2s2>; + rockchip,codec = <&hdmi>, <&cdn_dp>; + }; + + spdif-sound { + status = "disable"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disable"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + pwm_bl: backlight { + status = "disable"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + + led@1 { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_s3>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&spi1 { + status = "disable"; + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&spi1_gpio>; + + spidev0: spidev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; +/* +&spi1 { + status = "okay"; + max-freq = <48000000>; + spidev@00 { + compatible = "linux,spidev"; + reg = <0x00>; + spi-max-frequency = <48000000>; + }; +}; +*/ + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_reset>; + }; + +}; + +&uart2 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&vpu { + status = "okay"; + /* 0 means ion, 1 means drm */ + //allocator = <0>; +}; + +&rga { + status = "disabled"; +}; + +&cdn_dp { + status = "okay"; + extcon = <&fusb0>; + phys = <&tcphy0_dp>; +}; + +&hdmi { + /* remove the hdmi_i2c_xfer */ + pinctrl-0 = <&hdmi_cec>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; + ddc-i2c-bus = <&i2c7>; + rockchip,defaultmode = <16>; /* CEA 1920x1080@60Hz */ +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vcc13-supply = <&vcc3v3_sys>; + vcc14-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc1v8: vcc1v8_s3: vcca1v8_s3: DCDC_REG4 { + regulator-name = "vcc1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-init-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + clock-frequency = <200000>; + + rt5651: rt5651@1a { + #sound-dai-cells = <0>; + compatible = "realtek,rt5651"; + reg = <0x1a>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + status = "okay"; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + fusb0: fusb30x@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + interrupt-parent = <&gpio1>; + interrupts = ; + vbus-supply = <&vbus_typec>; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "sink"; + + extcon-cables = <1 2 5 6 9 10 12 44>; + typec-altmodes = <0xff01 1 0x001c0000 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc_hs: endpoint { + remote-endpoint = + <&u2phy0_typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usbc_ss: endpoint { + remote-endpoint = + <&tcphy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc_dp: endpoint { + remote-endpoint = + <&tcphy0_typec_dp>; + }; + }; + }; + }; + + }; + + ft5x06_ts@38 { + compatible = "edt,edt-ft5x06", "ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + + /* + onewire_ts@2f { + compatible = "onewire"; + reg = <0x2f>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + }; */ +}; + +&i2c7 { + status = "okay"; +}; + +&spdif { + status = "disable"; + pinctrl-0 = <&spdif_bus>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + #sound-dai-cells = <0>; +}; + +&i2s1 { + assigned-clocks = <&cru SCLK_I2SOUT_SRC>; + assigned-clock-parents = <&cru SCLK_I2S1_8CH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>,<&i2s1_2ch_bus>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "okay"; +}; +/* +&i2s0 { + assigned-clocks = <&cru SCLK_I2S1_DIV>; + assigned-clock-parents = <&cru PLL_GPLL>; +};*/ + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pcie_phy { + status = "okay"; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; +}; + +&pcie0 { + status = "okay"; + ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + max-link-speed = <1>; +}; + +&pwm_bl { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca1v8_s3>; /* TBD */ +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + supports-emmc; + non-removable; + keep-power-in-suspend; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&emmc_phy { + status = "okay"; +}; + +&sdio0 { + clock-frequency = <50000000>; + clock-freq-min-max = <200000 50000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; +// sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tcphy0_dp { + port { + tcphy0_typec_dp: endpoint { + remote-endpoint = <&usbc_dp>; + }; + }; +}; + +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&usbc_ss>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&usb3_vbus>; + status = "okay"; + }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&usbc_hs>; + }; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&usb_vbus>; + status = "okay"; + }; +}; + +&usbdrd3_0 { + status = "okay"; + extcon = <&fusb0>; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&pinctrl { + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + /delete-node/ hdmi-i2c-xfer; + }; + + i2s1 { + i2s_8ch_mclk: i2s-8ch-mclk { + rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdmmc { + sdmmc0_det_l: sdmmc0-det-l { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rockchip-key { + power_key: power-key { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + leds_gpio: leds-gpio { + rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cam_pins { + cif_clkout_a: cif-clkout-a { + rockchip,pins = <2 11 3 &pcfg_pull_none>; + }; + + cif_clkout_a_sleep: cif-clkout-a-sleep { + rockchip,pins = <2 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cam0_default_pins: cam0-default-pins { + rockchip,pins = + <4 27 0 &pcfg_pull_down>, + <2 11 3 &pcfg_pull_none>; + }; + cam0_sleep_pins: cam0-sleep-pins { + rockchip,pins = + <4 27 3 &pcfg_pull_none>, + <2 11 0 &pcfg_pull_none>; + }; + + cam1_default_pins: cam1-default-pins { + rockchip,pins = + <0 12 RK_FUNC_GPIO &pcfg_pull_down>, + <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + spi1 { + spi1_gpio: spi1-gpio { + rockchip,pins = + <1 7 RK_FUNC_GPIO &pcfg_output_low>, + <1 8 RK_FUNC_GPIO &pcfg_output_low>, + <1 9 RK_FUNC_GPIO &pcfg_output_low>, + <1 10 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + bt { + bt_host_wake: bt-host-wake { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset: bt-reset { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake: bt-wake { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&hdmi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopl { + status = "disable"; +}; + +&dp_in_vopb { + status = "disable"; +}; +&dp_in_vopl { + status = "okay"; +}; + diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3399-rock-pi-4.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-rock-pi-4.dts new file mode 100644 index 000000000..8d0aa5346 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-rock-pi-4.dts @@ -0,0 +1 @@ +#include "rk3399-rock-pi-4b.dts" diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3399-rock-pi-4c.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-rock-pi-4c.dts new file mode 100644 index 000000000..4053ba726 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-rock-pi-4c.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" + +/ { + model = "Radxa ROCK Pi 4C"; + compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399"; + + aliases { + mmc2 = &sdio0; + }; +}; + +&es8316 { + pinctrl-0 = <&hp_detect &hp_int>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = ; +}; + +&sdio0 { + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sound { + hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; +}; + +&uart0 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&vcc5v0_host { + gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host_en { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3399-tinker-2.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-tinker-2.dts new file mode 100644 index 000000000..0f4b28ae0 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3399-tinker-2.dts @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2021 Thomas McKahan + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-op1-opp.dtsi" + +/ { + model = "Asus Tinker Board 2/2S"; + compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + board_info: board-info { + compatible = "board-info"; + + hw-id0 = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + hw-id1 = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + hw-id2 = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + + pid-id0 = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; + pid-id1 = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + pid-id2 = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; + + ddr-id1 = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + ddr-id2 = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + + pmic-reset = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pwr-led { + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + retain-state-suspended = <1>; + }; + + act-led { + gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + linux,default-trigger="mmc0"; + }; + + rsv-led { + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger="heartbeat"; + }; + }; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vbus_typec: vbus-5vout { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en_pin>; + regulator-name = "vbus_5vout"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + /* for rockchip boot on */ + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <900000>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&cdn_dp { + status = "okay"; + extcon = <&fusb0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&cru SCLK_MAC>; + clock_in_out = "input"; + assigned-clock-rates = <125000000>; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 16000 72000>; + tx_delay = <0x25>; + rx_delay = <0x20>; + wakeup-enable = "0"; + status = "okay"; +}; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc3v3_dsi: LDO_REG1 { + regulator-name = "vcc3v3_dsi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_csi: LDO_REG5 { + regulator-name = "vcc3v3_csi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: vdd_cpu_b@60 { + compatible = "fcs,fan53200"; + reg = <0x60>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-regulator"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + status = "okay"; + + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + + status = "okay"; + i2c-scl-rising-time-ns = <475>; + i2c-scl-falling-time-ns = <26>; + fusb0: fusb30x@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + interrupt-parent = <&gpio1>; + interrupts = ; + vbus-supply = <&vbus_typec>; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "sink"; + + extcon-cables = <1 2 5 6 9 10 12 44>; + typec-altmodes = <0xff01 1 0x001c0000 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc_hs: endpoint { + remote-endpoint = + <&u2phy0_typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usbc_ss: endpoint { + remote-endpoint = + <&tcphy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc_dp: endpoint { + remote-endpoint = + <&tcphy0_typec_dp>; + }; + }; + }; + }; + + + + + }; + + vdd_gpu: vdd_gpu@60 { + compatible = "fcs,fan53200"; + reg = <0x60>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-regulator"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + status = "okay"; + + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c8 { + + m24c08: m24c08@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + +&pwm0 { + status = "disabled"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&pwm3 { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + supports-emmc; + //mmc-hs400-enhanced-strobe; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&sdmmc { + clock-frequency = <150000000>; + clock-freq-min-max = <100000 150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + //sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_s3>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tcphy0_dp { + port { + tcphy0_typec_dp: endpoint { + remote-endpoint = <&usbc_dp>; + }; + }; +}; + +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&usbc_ss>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&usbc_hs>; + }; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&pinctrl { + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 18 RK_FUNC_GPIO &pcfg_pull_up>, + <0 9 RK_FUNC_GPIO &pcfg_pull_none>; /* GPIO0_B1 */ + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 17 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 14 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3566-orangepi-3b.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-orangepi-3b.dts new file mode 100644 index 000000000..0d385cfa2 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-orangepi-3b.dts @@ -0,0 +1,869 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ +/dts-v1/; + +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Rockchip RK3566 OPi 3B"; + compatible = "rockchip,rk3566-orangepi-3b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm7 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + + led@1 { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + sprd-mtty { + compatible = "sprd,mtty"; + sprd,name = "ttyBT"; + }; + + unisoc_uwe_bsp: uwe-bsp { + compatible = "unisoc,uwe_bsp"; + wl-reg-on = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + bt-reg-on = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + wl-wake-host-gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + bt-wake-host; + bt-wake-host-gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + sdio-ext-int-gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + unisoc,btwf-file-name = "/lib/firmware/wcnmodem.bin"; + blksz-512; + keep-power-on; + }; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* labeled +3.3v For PCIe only in schematic */ + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + //snps,reset-delays-us = <0 20000 100000>; + snps,reset-delays-us = <0 50000 200000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <1>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + #sound-dai-cells = <0>; + + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + mic-in-differential; + }; + }; +}; + +/* + * i2c3_m0 is exposed on the 40-pin (green connectors) + * pin 27 - i2c3_sda_m0 + * pin 28 - i2c3_scl_m0 + */ +&i2c3 { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + work-led { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp-hpd { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl_en: bl-en { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm7 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; +}; + +/* (debug) uart2 has connectors near the usb-c power, but also on the 40-pin pins 6 (tx) and 8 (rx) - don't wire both */ +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vbus>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3566-panther-x2.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-panther-x2.dts new file mode 100755 index 000000000..2d077f3bb --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3566-panther-x2.dts @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 tdleiyao + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Panther X2"; + compatible = "panther,x2", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + //Corresponds to the actual order + led_pwr: led-pwr { + label = "led-pwr"; + default-state = "on"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_pwr_enable_h>; + retain-state-suspended; + status = "okay"; + }; + + led_wifi: led-wifi { + label = "led-wifi"; + default-state = "off"; + gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_wifi_enable_h>; + retain-state-suspended; + status = "okay"; + }; + + led_eth: led-eth { + label = "led-eth"; + default-state = "off"; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_eth_enable_h>; + retain-state-suspended; + status = "okay"; + }; + + led_status: led-status { + label = "led-status"; + default-state = "on"; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_status_enable_h>; + retain-state-suspended; + status = "okay"; + }; + }; + + vbus: vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6236"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + status = "okay"; + }; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + status = "disabled"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + }; + }; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx + &i2s1m1_lrcktx &i2s1m1_lrckrx + &i2s1m1_sdi0 &i2s1m1_sdi1 + &i2s1m1_sdi2 &i2s1m1_sdi3 + &i2s1m1_sdo0 &i2s1m1_sdo1 + &i2s1m1_sdo2 &i2s1m1_sdo3>; + status = "disabled"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_pwr_enable_h: led-pwr-enable-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_wifi_enable_h: led-wifi-enable-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_eth_enable_h: led-eth-enable-h { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_status_enable_h: led-status-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + status = "okay"; + +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3568-hinlink-h66k.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3568-hinlink-h66k.dts new file mode 100644 index 000000000..f51e626f2 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3568-hinlink-h66k.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2022 AmadeusGhost +// Copyright (c) 2022 Flippy +// Copyright (c) 2023 amazingfate + +/dts-v1/; + +#include "rk3568-hinlink-h68k.dts" + +/ { + model = "HINLINK H66K"; + compatible = "hinlink,h66k", "rockchip,rk3568"; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + status = "disabled"; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3568-hinlink-h68k.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3568-hinlink-h68k.dts new file mode 100644 index 000000000..7eed082c4 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3568-hinlink-h68k.dts @@ -0,0 +1,889 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2022 AmadeusGhost +// Copyright (c) 2023 amazingfate + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "HINLINK H68K"; + compatible = "hinlink,h68k", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + + led-boot = &led_work; + led-failsafe = &led_work; + led-running = &led_work; + led-upgrade = &led_work; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&reset_button_pin>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <50>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_net_en>, <&led_sata_en>, <&led_work_en>; + + led_net: net { + label = "blue:net"; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + + led_sata: sata { + label = "amber:sata"; + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + }; + + led_work: work { + label = "green:work"; + gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_sys_en>; + + vin-supply = <&vcc5v0_sys>; + }; + + /* wifi power + for H68K-MAX & H69K-MAX + */ + vcc3v3_pcie2: vcc3v3-pcie2-regulator { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie2"; + regulator-boot-on; + + gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie2_en>; + vin-supply = <&vcc3v3_sys>; + }; + + /* eth 2.5g power + for H66K H69K + */ + vcc3v3_pcie3: vcc3v3-pcie3-regulator { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie3"; + regulator-boot-on; + + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie3_en>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + + vin-supply = <&vcc5v0_sys>; + + }; + + vcc3v3_sd_pwren: vcc3v3-sd-pwren-regulator { + compatible = "regulator-fixed"; + + regulator-name = "vcc3v3_sd_pwren"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; /* SD_PWREN */ + vin-supply = <&vcc3v3_sys>; + + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_sd_en>; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 127 163 255>; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm0 0 50000 0>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_thermal { + trips { + cpu_cool: cpu_cool { + temperature = <45000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_cool>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 3 THERMAL_NO_LIMIT>; + }; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 200000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 200000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #sound-dai-cells = <0>; + + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + phy-supply = <&vcc3v3_sys>; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + phy-supply = <&vcc3v3_sys>; + reg = <0x0>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie3>; + status = "okay"; + + pcie@0,0 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + rtl8125_1: pcie-eth@10,0 { + compatible = "pci10ec,8125"; + reg = <0x000000 0 0 0 0>; + realtek,led-data = <0x0200>; + }; + }; +}; + +&pcie3x2 { + num-lanes = <1>; + rockchip,init-delay-ms = <100>; + reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie3>; + status = "okay"; + + pcie@0,0 { + reg = <0x00200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + rtl8125_2: pcie-eth@20,0 { + compatible = "pci10ec,8125"; + reg = <0x000000 0 0 0 0>; + realtek,led-data = <0x0200>; + }; + }; +}; + +&pinctrl { + button { + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_work_en: led-work-en { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_sata_en: led-user-en { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_net_en: led-net-en { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc { + vcc3v3_sys_en: vcc3v3-sys-en { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sd { + vcc3v3_sd_en: vcc3v3-sd_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie2_en: vcc3v3_pcie2_en { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_pcie3_en: vcc3v3_pcie3_en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + vmmc-supply = <&vcc3v3_sd_pwren>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/patch/kernel/archive/rockchip64-6.6/general-add-miniDP-dt-doc.patch b/patch/kernel/archive/rockchip64-6.6/general-add-miniDP-dt-doc.patch new file mode 100644 index 000000000..c74bfad3e --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/general-add-miniDP-dt-doc.patch @@ -0,0 +1,133 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tony +Date: Wed, 3 Mar 2021 07:59:25 +0100 +Subject: [ARCHEOLOGY] RK3399 Typec DP (#2676) + +> X-Git-Archeology: > recovered message: > * RK3399 NanoPC-T4 Add Type-C alt mode DP +> X-Git-Archeology: > recovered message: > * rk3399 rockpi 4C add mini-DP (WIP) +> X-Git-Archeology: > recovered message: > * [ rockchip64 ] revert rockPi 4C DP patch +> X-Git-Archeology: > recovered message: > Add an extension to disable it, but leave for future work. +> X-Git-Archeology: - Revision 4971535c774a1f49a811baebc083ea028ced0300: https://github.com/armbian/build/commit/4971535c774a1f49a811baebc083ea028ced0300 +> X-Git-Archeology: Date: Wed, 03 Mar 2021 07:59:25 +0100 +> X-Git-Archeology: From: Tony +> X-Git-Archeology: Subject: RK3399 Typec DP (#2676) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml | 66 ++++++++++ + 1 file changed, 66 insertions(+) + +diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml +new file mode 100644 +index 000000000000..8110fbe2ddc2 +--- /dev/null ++++ b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml +@@ -0,0 +1,66 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/extcon/extcon-usbc-virtual-pd.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Type-C Virtual PD extcon ++ ++maintainers: ++ - Jagan Teki ++ ++description: | ++ USB Type-C protocol supports various modes of operations includes PD, ++ USB3, and Altmode. If the platform design supports a Type-C connector ++ then configuring these modes can be done via enumeration. ++ ++ However, there are some platforms that design these modes as separate ++ protocol connectors like design Display Port from on-chip USB3 controller. ++ So we can access Type-C Altmode Display Port via onboard Display Port ++ connector instead of a Type-C connector. These kinds of platforms require ++ an explicit extcon driver in order to handle Power Delivery and ++ Port Detection. ++ ++properties: ++ compatible: ++ const: linux,extcon-usbc-virtual-pd ++ ++ det-gpios: ++ description: Detect GPIO pin. Pin can be Display Port Detect or USB ID. ++ maxItems: 1 ++ ++ vpd-polarity: ++ description: USB Type-C Polarity. false for Normal and true for Flip. ++ type: boolean ++ ++ vpd-super-speed: ++ description: USB Super Speed. false for USB2 and true for USB3. ++ type: boolean ++ ++ vpd-data-role: ++ description: USB Data roles for Virtual Type-C. ++ $ref: /schemas/types.yaml#definitions/string ++ ++ enum: ++ - host ++ - device ++ - display-port ++ ++required: ++ - compatible ++ - det-gpios ++ - vpd-data-role ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ virtual_pd: virtual-pd { ++ compatible = "linux,extcon-usbc-virtual-pd"; ++ det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; ++ vpd-data-role = "display-port"; ++ vpd-super-speed; ++ }; +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/general-add-miniDP-virtual-extcon.patch b/patch/kernel/archive/rockchip64-6.6/general-add-miniDP-virtual-extcon.patch new file mode 100644 index 000000000..467a3655d --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/general-add-miniDP-virtual-extcon.patch @@ -0,0 +1,382 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tony +Date: Wed, 3 Mar 2021 07:59:25 +0100 +Subject: [ARCHEOLOGY] RK3399 Typec DP (#2676) + +> X-Git-Archeology: > recovered message: > * RK3399 NanoPC-T4 Add Type-C alt mode DP +> X-Git-Archeology: > recovered message: > * rk3399 rockpi 4C add mini-DP (WIP) +> X-Git-Archeology: > recovered message: > * [ rockchip64 ] revert rockPi 4C DP patch +> X-Git-Archeology: > recovered message: > Add an extension to disable it, but leave for future work. +> X-Git-Archeology: - Revision 4971535c774a1f49a811baebc083ea028ced0300: https://github.com/armbian/build/commit/4971535c774a1f49a811baebc083ea028ced0300 +> X-Git-Archeology: Date: Wed, 03 Mar 2021 07:59:25 +0100 +> X-Git-Archeology: From: Tony +> X-Git-Archeology: Subject: RK3399 Typec DP (#2676) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + drivers/extcon/Kconfig | 10 + + drivers/extcon/Makefile | 1 + + drivers/extcon/extcon-usbc-virtual-pd.c | 285 ++++++++++ + 3 files changed, 296 insertions(+) + +diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig +index 8de9023c2a38..21f0f856cacb 100644 +--- a/drivers/extcon/Kconfig ++++ b/drivers/extcon/Kconfig +@@ -191,4 +191,14 @@ config EXTCON_USBC_TUSB320 + Say Y here to enable support for USB Type C cable detection extcon + support using a TUSB320. + ++config EXTCON_USBC_VIRTUAL_PD ++ tristate "Virtual Type-C PD EXTCON support" ++ depends on GPIOLIB || COMPILE_TEST ++ help ++ Say Y here to enable Virtual Type-C PD extcon driver support, if ++ hardware platform designed Type-C modes separately. ++ ++ Example, of designing Display Port separately from Type-C Altmode ++ instead of accessing Altmode Display Port in Type-C connector. ++ + endif +diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile +index 1b390d934ca9..57c1e65bfcfd 100644 +--- a/drivers/extcon/Makefile ++++ b/drivers/extcon/Makefile +@@ -25,3 +25,4 @@ obj-$(CONFIG_EXTCON_SM5502) += extcon-sm5502.o + obj-$(CONFIG_EXTCON_USB_GPIO) += extcon-usb-gpio.o + obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o + obj-$(CONFIG_EXTCON_USBC_TUSB320) += extcon-usbc-tusb320.o ++obj-$(CONFIG_EXTCON_USBC_VIRTUAL_PD) += extcon-usbc-virtual-pd.o +diff --git a/drivers/extcon/extcon-usbc-virtual-pd.c b/drivers/extcon/extcon-usbc-virtual-pd.c +new file mode 100644 +index 000000000000..e0713670e33d +--- /dev/null ++++ b/drivers/extcon/extcon-usbc-virtual-pd.c +@@ -0,0 +1,285 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Type-C Virtual PD Extcon driver ++ * ++ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2019 Radxa Limited ++ * Copyright (c) 2019 Amarula Solutions(India) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const unsigned int vpd_cable[] = { ++ EXTCON_USB, ++ EXTCON_USB_HOST, ++ EXTCON_DISP_DP, ++ EXTCON_NONE, ++}; ++ ++enum vpd_data_role { ++ DR_NONE, ++ DR_HOST, ++ DR_DEVICE, ++ DR_DISPLAY_PORT, ++}; ++ ++enum vpd_polarity { ++ POLARITY_NORMAL, ++ POLARITY_FLIP, ++}; ++ ++enum vpd_usb_ss { ++ USB_SS_USB2, ++ USB_SS_USB3, ++}; ++ ++struct vpd_extcon { ++ struct device *dev; ++ struct extcon_dev *extcon; ++ struct gpio_desc *det_gpio; ++ ++ u8 polarity; ++ u8 usb_ss; ++ enum vpd_data_role data_role; ++ ++ int irq; ++ bool enable_irq; ++ struct work_struct work; ++ struct delayed_work irq_work; ++}; ++ ++static void vpd_extcon_irq_work(struct work_struct *work) ++{ ++ struct vpd_extcon *vpd = container_of(work, struct vpd_extcon, irq_work.work); ++ bool host_connected = false, device_connected = false, dp_connected = false; ++ union extcon_property_value property; ++ int det; ++ ++ det = vpd->det_gpio ? gpiod_get_raw_value(vpd->det_gpio) : 0; ++ if (det) { ++ device_connected = (vpd->data_role == DR_DEVICE) ? true : false; ++ host_connected = (vpd->data_role == DR_HOST) ? true : false; ++ dp_connected = (vpd->data_role == DR_DISPLAY_PORT) ? true : false; ++ } ++ ++ extcon_set_state(vpd->extcon, EXTCON_USB, host_connected); ++ extcon_set_state(vpd->extcon, EXTCON_USB_HOST, device_connected); ++ extcon_set_state(vpd->extcon, EXTCON_DISP_DP, dp_connected); ++ ++ property.intval = vpd->polarity; ++ extcon_set_property(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ extcon_set_property(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ extcon_set_property(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ ++ property.intval = vpd->usb_ss; ++ extcon_set_property(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS, property); ++ extcon_set_property(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS, property); ++ extcon_set_property(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS, property); ++ ++ extcon_sync(vpd->extcon, EXTCON_USB); ++ extcon_sync(vpd->extcon, EXTCON_USB_HOST); ++ extcon_sync(vpd->extcon, EXTCON_DISP_DP); ++} ++ ++static irqreturn_t vpd_extcon_irq_handler(int irq, void *dev_id) ++{ ++ struct vpd_extcon *vpd = dev_id; ++ ++ schedule_delayed_work(&vpd->irq_work, msecs_to_jiffies(10)); ++ ++ return IRQ_HANDLED; ++} ++ ++static enum vpd_data_role vpd_extcon_data_role(struct vpd_extcon *vpd) ++{ ++ const char *const data_roles[] = { ++ [DR_NONE] = "NONE", ++ [DR_HOST] = "host", ++ [DR_DEVICE] = "device", ++ [DR_DISPLAY_PORT] = "display-port", ++ }; ++ struct device *dev = vpd->dev; ++ int ret; ++ const char *dr; ++ ++ ret = device_property_read_string(dev, "vpd-data-role", &dr); ++ if (ret < 0) ++ return DR_NONE; ++ ++ ret = match_string(data_roles, ARRAY_SIZE(data_roles), dr); ++ ++ return (ret < 0) ? DR_NONE : ret; ++} ++ ++static int vpd_extcon_parse_dts(struct vpd_extcon *vpd) ++{ ++ struct device *dev = vpd->dev; ++ bool val = false; ++ int ret; ++ ++ val = device_property_read_bool(dev, "vpd-polarity"); ++ if (val) ++ vpd->polarity = POLARITY_FLIP; ++ else ++ vpd->polarity = POLARITY_NORMAL; ++ ++ val = device_property_read_bool(dev, "vpd-super-speed"); ++ if (val) ++ vpd->usb_ss = USB_SS_USB3; ++ else ++ vpd->usb_ss = USB_SS_USB2; ++ ++ vpd->data_role = vpd_extcon_data_role(vpd); ++ ++ vpd->det_gpio = devm_gpiod_get_optional(dev, "det", GPIOD_OUT_LOW); ++ if (IS_ERR(vpd->det_gpio)) { ++ ret = PTR_ERR(vpd->det_gpio); ++ dev_warn(dev, "failed to get det gpio: %d\n", ret); ++ return ret; ++ } ++ ++ vpd->irq = gpiod_to_irq(vpd->det_gpio); ++ if (vpd->irq < 0) { ++ dev_err(dev, "failed to get irq for gpio: %d\n", vpd->irq); ++ return vpd->irq; ++ } ++ ++ ret = devm_request_threaded_irq(dev, vpd->irq, NULL, ++ vpd_extcon_irq_handler, ++ IRQF_TRIGGER_FALLING | ++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, ++ NULL, vpd); ++ if (ret) ++ dev_err(dev, "failed to request gpio irq\n"); ++ ++ return ret; ++} ++ ++static int vpd_extcon_probe(struct platform_device *pdev) ++{ ++ struct vpd_extcon *vpd; ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ vpd = devm_kzalloc(dev, sizeof(*vpd), GFP_KERNEL); ++ if (!vpd) ++ return -ENOMEM; ++ ++ vpd->dev = dev; ++ ret = vpd_extcon_parse_dts(vpd); ++ if (ret) ++ return ret; ++ ++ INIT_DELAYED_WORK(&vpd->irq_work, vpd_extcon_irq_work); ++ ++ vpd->extcon = devm_extcon_dev_allocate(dev, vpd_cable); ++ if (IS_ERR(vpd->extcon)) { ++ dev_err(dev, "allocat extcon failed\n"); ++ return PTR_ERR(vpd->extcon); ++ } ++ ++ ret = devm_extcon_dev_register(dev, vpd->extcon); ++ if (ret) { ++ dev_err(dev, "register extcon failed: %d\n", ret); ++ return ret; ++ } ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_VBUS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_VBUS); ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS); ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ ++ platform_set_drvdata(pdev, vpd); ++ ++ vpd_extcon_irq_work(&vpd->irq_work.work); ++ ++ return 0; ++} ++ ++static int vpd_extcon_remove(struct platform_device *pdev) ++{ ++ struct vpd_extcon *vpd = platform_get_drvdata(pdev); ++ ++ cancel_delayed_work_sync(&vpd->irq_work); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int vpd_extcon_suspend(struct device *dev) ++{ ++ struct vpd_extcon *vpd = dev_get_drvdata(dev); ++ ++ if (!vpd->enable_irq) { ++ disable_irq_nosync(vpd->irq); ++ vpd->enable_irq = true; ++ } ++ ++ return 0; ++} ++ ++static int vpd_extcon_resume(struct device *dev) ++{ ++ struct vpd_extcon *vpd = dev_get_drvdata(dev); ++ ++ if (vpd->enable_irq) { ++ enable_irq(vpd->irq); ++ vpd->enable_irq = false; ++ } ++ ++ return 0; ++} ++#endif ++ ++static SIMPLE_DEV_PM_OPS(vpd_extcon_pm_ops, ++ vpd_extcon_suspend, vpd_extcon_resume); ++ ++static const struct of_device_id vpd_extcon_dt_match[] = { ++ { .compatible = "linux,extcon-usbc-virtual-pd", }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver vpd_extcon_driver = { ++ .probe = vpd_extcon_probe, ++ .remove = vpd_extcon_remove, ++ .driver = { ++ .name = "extcon-usbc-virtual-pd", ++ .pm = &vpd_extcon_pm_ops, ++ .of_match_table = vpd_extcon_dt_match, ++ }, ++}; ++ ++module_platform_driver(vpd_extcon_driver); ++ ++MODULE_AUTHOR("Jagan Teki "); ++MODULE_DESCRIPTION("Type-C Virtual PD extcon driver"); ++MODULE_LICENSE("GPL v2"); +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/general-add-overlay-compilation-support.patch b/patch/kernel/archive/rockchip64-6.6/general-add-overlay-compilation-support.patch new file mode 100644 index 000000000..7357d074e --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/general-add-overlay-compilation-support.patch @@ -0,0 +1,413 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: zador-blood-stained +Date: Sat, 11 Feb 2017 20:32:53 +0300 +Subject: [ARCHEOLOGY] Rename, split and improve H3 DT overlays + +> X-Git-Archeology: > recovered message: > Fix OPi Zero DT +> X-Git-Archeology: > recovered message: > Improve DT loading reliability +> X-Git-Archeology: - Revision bacf56710491e3307e0fb2bc1c828dad828c9f23: https://github.com/armbian/build/commit/bacf56710491e3307e0fb2bc1c828dad828c9f23 +> X-Git-Archeology: Date: Sat, 11 Feb 2017 20:32:53 +0300 +> X-Git-Archeology: From: zador-blood-stained +> X-Git-Archeology: Subject: Rename, split and improve H3 DT overlays +> X-Git-Archeology: +> X-Git-Archeology: - Revision c7bbc3257e8dcbf75398301602150fe9f1666c86: https://github.com/armbian/build/commit/c7bbc3257e8dcbf75398301602150fe9f1666c86 +> X-Git-Archeology: Date: Sun, 26 Feb 2017 19:46:15 +0300 +> X-Git-Archeology: From: zador-blood-stained +> X-Git-Archeology: Subject: Initial A20 overlays support for sunxi-next kernel +> X-Git-Archeology: +> X-Git-Archeology: - Revision caf4b1b037e7510cae7edd1b5f75482eed41b547: https://github.com/armbian/build/commit/caf4b1b037e7510cae7edd1b5f75482eed41b547 +> X-Git-Archeology: Date: Mon, 13 Mar 2017 20:32:37 +0300 +> X-Git-Archeology: From: zador-blood-stained +> X-Git-Archeology: Subject: Add new A20 overlays +> X-Git-Archeology: +> X-Git-Archeology: - Revision b30fcea3f95804175199bc1865a7e39cdf07cf73: https://github.com/armbian/build/commit/b30fcea3f95804175199bc1865a7e39cdf07cf73 +> X-Git-Archeology: Date: Sun, 14 May 2017 17:59:35 +0300 +> X-Git-Archeology: From: zador-blood-stained +> X-Git-Archeology: Subject: Update sunxi-next branch to 4.11 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 20240e9669055030076e69452cf6a1ccb368cc2e: https://github.com/armbian/build/commit/20240e9669055030076e69452cf6a1ccb368cc2e +> X-Git-Archeology: Date: Tue, 30 May 2017 21:30:38 -0400 +> X-Git-Archeology: From: Martin Ayotte +> X-Git-Archeology: Subject: add overlays to sunxi-dev +> X-Git-Archeology: +> X-Git-Archeology: - Revision b0fcb64aaca589359338a500e7bc07eb7ca1cb71: https://github.com/armbian/build/commit/b0fcb64aaca589359338a500e7bc07eb7ca1cb71 +> X-Git-Archeology: Date: Thu, 07 Dec 2017 07:09:10 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Temporally disabling broken patches on sunxi DEV branch +> X-Git-Archeology: +> X-Git-Archeology: - Revision 2123e539ed288e3355ef3d3adc79788a187f62df: https://github.com/armbian/build/commit/2123e539ed288e3355ef3d3adc79788a187f62df +> X-Git-Archeology: Date: Thu, 15 Feb 2018 11:21:51 +0200 +> X-Git-Archeology: From: Stefan Mavrodiev +> X-Git-Archeology: Subject: Add overlays support for upstream kernel +> X-Git-Archeology: +> X-Git-Archeology: - Revision 2c08ec8f5a210de35f9482f482ac01ea15381792: https://github.com/armbian/build/commit/2c08ec8f5a210de35f9482f482ac01ea15381792 +> X-Git-Archeology: Date: Thu, 24 May 2018 13:32:29 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Merge sunxi family into stable +> X-Git-Archeology: +> X-Git-Archeology: - Revision 1a12994e79b6ef173dc58efe4df8919cb6cc7781: https://github.com/armbian/build/commit/1a12994e79b6ef173dc58efe4df8919cb6cc7781 +> X-Git-Archeology: Date: Tue, 17 Jul 2018 15:53:30 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Moving sunxi-next to 4.17.y (#1049) +> X-Git-Archeology: +> X-Git-Archeology: - Revision a57ce78b37f8dd2eb94a3836f4a7f6969f2ffd72: https://github.com/armbian/build/commit/a57ce78b37f8dd2eb94a3836f4a7f6969f2ffd72 +> X-Git-Archeology: Date: Tue, 21 Aug 2018 10:41:10 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Reverting sunxi/sunxi64 NEXT to 4.14. (#1087) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 871bed1a24e21952f7aeb1981c26ad5fc573be9d: https://github.com/armbian/build/commit/871bed1a24e21952f7aeb1981c26ad5fc573be9d +> X-Git-Archeology: Date: Tue, 04 Dec 2018 16:25:53 -0500 +> X-Git-Archeology: From: Martin Ayotte +> X-Git-Archeology: Subject: add overlay-compilation-support to meson64-dev +> X-Git-Archeology: +> X-Git-Archeology: - Revision 7c5fb27d79d1c737fc2ca92a1069226e9aae2154: https://github.com/armbian/build/commit/7c5fb27d79d1c737fc2ca92a1069226e9aae2154 +> X-Git-Archeology: Date: Wed, 09 Jan 2019 23:33:47 -0500 +> X-Git-Archeology: From: Thomas McKahan +> X-Git-Archeology: Subject: [ meson64-next ] Shift Next to 4.19 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 2fa7c680c29a144214706dda35c2a6afdd708858: https://github.com/armbian/build/commit/2fa7c680c29a144214706dda35c2a6afdd708858 +> X-Git-Archeology: Date: Thu, 21 Mar 2019 14:57:07 -0400 +> X-Git-Archeology: From: Martin Ayotte +> X-Git-Archeology: Subject: fix overlay patch +> X-Git-Archeology: +> X-Git-Archeology: - Revision a040785d4299e10255d87fdfcfa70b56e0b6779f: https://github.com/armbian/build/commit/a040785d4299e10255d87fdfcfa70b56e0b6779f +> X-Git-Archeology: Date: Sun, 04 Aug 2019 18:05:50 -0400 +> X-Git-Archeology: From: chwe17 +> X-Git-Archeology: Subject: Tinkerboard camera support (#1482) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3 +> X-Git-Archeology: Date: Tue, 19 Nov 2019 23:25:39 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Remove K<4, change branches, new features (#1586) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 23604e8a0dcdf81ec6c28ccd4b2a64b90816d8e7: https://github.com/armbian/build/commit/23604e8a0dcdf81ec6c28ccd4b2a64b90816d8e7 +> X-Git-Archeology: Date: Fri, 19 Jun 2020 17:27:27 +0200 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: Introducing Rockchip RK322X SoC support (#2032) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 99afbdfe7e08334bb5dde05c4f3dab536e87224e: https://github.com/armbian/build/commit/99afbdfe7e08334bb5dde05c4f3dab536e87224e +> X-Git-Archeology: Date: Fri, 26 Jun 2020 15:53:20 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump meson64 current to 5.7.y (#2069) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37 +> X-Git-Archeology: Date: Sat, 18 Jul 2020 23:07:01 +0200 +> X-Git-Archeology: From: Werner +> X-Git-Archeology: Subject: Move rockchip/64 current to 5.7.y (#2099) +> X-Git-Archeology: +> X-Git-Archeology: - Revision caa47bad650f82cb8045d19c384595b1760bd9e1: https://github.com/armbian/build/commit/caa47bad650f82cb8045d19c384595b1760bd9e1 +> X-Git-Archeology: Date: Sat, 18 Jul 2020 23:08:52 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Move sunxi/64 current to 5.7, legacy to 5.4 (#2098) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 804a6b60d4c2724ada9eb975e3caf2d9753beba9: https://github.com/armbian/build/commit/804a6b60d4c2724ada9eb975e3caf2d9753beba9 +> X-Git-Archeology: Date: Fri, 28 Aug 2020 18:48:55 +0200 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: Moved rk322x-dev to rk322x-current (current now is 5.7.y) (#2153) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 661371868def63655e46e8c513d8ba0f42cf4066: https://github.com/armbian/build/commit/661371868def63655e46e8c513d8ba0f42cf4066 +> X-Git-Archeology: Date: Fri, 28 Aug 2020 19:26:08 +0200 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Enable overlays for rk3399-legacy (#2144) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 4cdf3c3d0e31fb9fa05d9b818915d54c465dffa0: https://github.com/armbian/build/commit/4cdf3c3d0e31fb9fa05d9b818915d54c465dffa0 +> X-Git-Archeology: Date: Sun, 18 Oct 2020 14:43:30 -0400 +> X-Git-Archeology: From: tonymac32 +> X-Git-Archeology: Subject: [ rockchip ] add overlay compilation support +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 +> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 3b3d85e25c2ecde30df7b5274fc6f1b9c0299ea2: https://github.com/armbian/build/commit/3b3d85e25c2ecde30df7b5274fc6f1b9c0299ea2 +> X-Git-Archeology: Date: Sat, 22 May 2021 17:08:44 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Upgrade EDGE to 5.12.y (#2825) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e21e82b546d3817e69ec062bb1e56c63c33e9c21: https://github.com/armbian/build/commit/e21e82b546d3817e69ec062bb1e56c63c33e9c21 +> X-Git-Archeology: Date: Wed, 21 Jul 2021 00:46:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Upgrading sunxi, sunxi64, imx6, jetson-nano, mvebu and mvebu64 EDGE to 5.13 (#3042) +> X-Git-Archeology: +> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 +> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 +> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) +> X-Git-Archeology: +> X-Git-Archeology: - Revision f15bc37276f8a06c024628b41905a7255934e93b: https://github.com/armbian/build/commit/f15bc37276f8a06c024628b41905a7255934e93b +> X-Git-Archeology: Date: Sat, 11 Sep 2021 12:51:28 +0000 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rk322x: add back edge kernel patches lost in the process, hardware cursor dedicated plane +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 4c3dcbf4fcd3616999cb91a1dddfa74668eb6de9: https://github.com/armbian/build/commit/4c3dcbf4fcd3616999cb91a1dddfa74668eb6de9 +> X-Git-Archeology: Date: Tue, 09 Nov 2021 21:58:35 +0100 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: Rockchip 5.15 (#3242) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4 +> X-Git-Archeology: Date: Tue, 11 Jan 2022 15:26:11 +0100 +> X-Git-Archeology: From: Oleg +> X-Git-Archeology: Subject: move kernel edge to 5.16 (#3387) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 1e37959e5381a0a1d1eaf0629cdc19658f30df9a: https://github.com/armbian/build/commit/1e37959e5381a0a1d1eaf0629cdc19658f30df9a +> X-Git-Archeology: Date: Thu, 10 Feb 2022 20:32:58 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bumping sunxi/64, xu4, rockchip and mvebu64 to 5.16.y (#3453) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41 +> X-Git-Archeology: Date: Sun, 20 Mar 2022 22:58:21 +0100 +> X-Git-Archeology: From: Oleg +> X-Git-Archeology: Subject: Adding Pine64 Quartz64a as WIP target (#3539) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 2fe1ddfe451d3a3dba01e4ba1204d2b9fe7eb44e: https://github.com/armbian/build/commit/2fe1ddfe451d3a3dba01e4ba1204d2b9fe7eb44e +> X-Git-Archeology: Date: Sat, 26 Mar 2022 17:59:23 +0000 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rockchip: add tinkerboard overlays for current 5.15 kernel +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0777be9e754c8bd24cff0297226b5158564bbc96: https://github.com/armbian/build/commit/0777be9e754c8bd24cff0297226b5158564bbc96 +> X-Git-Archeology: Date: Sun, 10 Apr 2022 16:45:06 +0200 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rk322x: move edge flavour to kernel 5.17, adapt patches were necessary +> X-Git-Archeology: +> X-Git-Archeology: - Revision 49b2aba89124b15a0f6b81ccf44b3792b6b35497: https://github.com/armbian/build/commit/49b2aba89124b15a0f6b81ccf44b3792b6b35497 +> X-Git-Archeology: Date: Mon, 11 Apr 2022 22:05:28 +0200 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rockchip: copy patch archive from 5.16 to 5.17 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c +> X-Git-Archeology: Date: Sun, 24 Apr 2022 22:33:47 +0200 +> X-Git-Archeology: From: Oleg +> X-Git-Archeology: Subject: move kernel media edge to 5.17 (#3704) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 3c4189e311ca60427d47dae796620a9fc98dc1f3: https://github.com/armbian/build/commit/3c4189e311ca60427d47dae796620a9fc98dc1f3 +> X-Git-Archeology: Date: Sun, 29 May 2022 17:15:36 +0200 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: rockchip: upgrade edge kernel to v5.18 (#3842) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 809ce98a75163e3d37cffae811e1d19fd0758ef4: https://github.com/armbian/build/commit/809ce98a75163e3d37cffae811e1d19fd0758ef4 +> X-Git-Archeology: Date: Sun, 29 May 2022 17:26:16 +0200 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: rk322x: move edge kernel to v5.18 (#3844) +> X-Git-Archeology: +> X-Git-Archeology: - Revision d064b2dce2a58299bff98e8ccb275fec861777e9: https://github.com/armbian/build/commit/d064b2dce2a58299bff98e8ccb275fec861777e9 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 19:10:25 +0200 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rk322x: advance edge kernel to 5.19 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision c87542aba26b01703746d3db94ac0820575b23b2: https://github.com/armbian/build/commit/c87542aba26b01703746d3db94ac0820575b23b2 +> X-Git-Archeology: Date: Thu, 04 Aug 2022 11:20:06 +0200 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: rockchip: switch edge kernel to v5.19 (#4045) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 73691a9e24440e0a8104b2c25d168ba8947a10ad: https://github.com/armbian/build/commit/73691a9e24440e0a8104b2c25d168ba8947a10ad +> X-Git-Archeology: Date: Thu, 04 Aug 2022 21:50:40 +0200 +> X-Git-Archeology: From: Ricardo Pardini +> X-Git-Archeology: Subject: meson64: edge: rework to kernel 5.19 (#3941) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 1b12209ded2c356df514e3dd99bd945c0afd7a32: https://github.com/armbian/build/commit/1b12209ded2c356df514e3dd99bd945c0afd7a32 +> X-Git-Archeology: Date: Tue, 25 Oct 2022 20:38:31 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump meson64 edge to 6.0.y (#4341) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 35db7a3995d0d6e92638a0ed173e7252a927e339: https://github.com/armbian/build/commit/35db7a3995d0d6e92638a0ed173e7252a927e339 +> X-Git-Archeology: Date: Tue, 15 Nov 2022 20:19:17 +0100 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: rk322x: bump kernel to 6.0 (#4443) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ed2c6d3c6764e9da4f54cb3b210e5106864dfa0f: https://github.com/armbian/build/commit/ed2c6d3c6764e9da4f54cb3b210e5106864dfa0f +> X-Git-Archeology: Date: Tue, 15 Nov 2022 20:22:47 +0100 +> X-Git-Archeology: From: Paolo +> X-Git-Archeology: Subject: rockchip: advance edge kernel to v6.0 (#4445) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 5b46bd7273909a2a9688efe85c4d45d00d407865: https://github.com/armbian/build/commit/5b46bd7273909a2a9688efe85c4d45d00d407865 +> X-Git-Archeology: Date: Mon, 12 Dec 2022 08:02:25 +0100 +> X-Git-Archeology: From: Ricardo Pardini +> X-Git-Archeology: Subject: `meson64-6.0` kernel patches: mbox formatting, archeology to find lost authors/descriptions; rebase against 6.0.12; no actual changes (#4546) +> X-Git-Archeology: +> X-Git-Archeology: - Revision eb7d4a0bd20e56118f9c8c9089c063154c58a239: https://github.com/armbian/build/commit/eb7d4a0bd20e56118f9c8c9089c063154c58a239 +> X-Git-Archeology: Date: Mon, 12 Dec 2022 08:02:49 +0100 +> X-Git-Archeology: From: Ricardo Pardini +> X-Git-Archeology: Subject: `meson64`: bump `edge` to `6.1-rc8` (#4554) +> X-Git-Archeology: +> X-Git-Archeology: - Revision c0001d566b3770dae722c47180dcb942bed7006a: https://github.com/armbian/build/commit/c0001d566b3770dae722c47180dcb942bed7006a +> X-Git-Archeology: Date: Wed, 14 Dec 2022 01:43:31 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump bcm, imx, mvebu64 and xu4 EDGE to 6.1.y (#4560) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 80dffbc7611bd76d675fcf74d352e1c55ce51f29: https://github.com/armbian/build/commit/80dffbc7611bd76d675fcf74d352e1c55ce51f29 +> X-Git-Archeology: Date: Tue, 10 Jan 2023 00:31:35 +0100 +> X-Git-Archeology: From: Ricardo Pardini +> X-Git-Archeology: Subject: `meson64`: `edge`: bump to `6.2` - copy patches as-is from 6.1 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 0ea5a3547b393059da92da9925a76bccef93631a: https://github.com/armbian/build/commit/0ea5a3547b393059da92da9925a76bccef93631a +> X-Git-Archeology: Date: Tue, 10 Jan 2023 00:31:41 +0100 +> X-Git-Archeology: From: Ricardo Pardini +> X-Git-Archeology: Subject: `meson64`: `edge`: bump to `6.2` - rebased patches against tag `v6.2-rc3` +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8652bf3d37c9d9f7d87588dc1f97e82626dac489: https://github.com/armbian/build/commit/8652bf3d37c9d9f7d87588dc1f97e82626dac489 +> X-Git-Archeology: Date: Sun, 12 Feb 2023 21:20:35 +0100 +> X-Git-Archeology: From: Joao Assuncao +> X-Git-Archeology: Subject: Adds SPI, I2C, and PWM DTS overlays for odroid-m1 (#4825) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 3f704692a7933a67b5e8cc6ff690d92ef3a5e735: https://github.com/armbian/build/commit/3f704692a7933a67b5e8cc6ff690d92ef3a5e735 +> X-Git-Archeology: Date: Fri, 24 Mar 2023 23:12:56 +0100 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rockchip: bump edge kernel to 6.2 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 5930e5e536d6b2f1a1446b8910648d7b0183919e: https://github.com/armbian/build/commit/5930e5e536d6b2f1a1446b8910648d7b0183919e +> X-Git-Archeology: Date: Fri, 24 Mar 2023 23:14:09 +0100 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rk322x: move edge kernel to 6.2 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 98b6aec55439c5aa8cee13898451e0969f7df9ce: https://github.com/armbian/build/commit/98b6aec55439c5aa8cee13898451e0969f7df9ce +> X-Git-Archeology: Date: Thu, 27 Apr 2023 21:30:02 +0200 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rk322x: bump edge kernel to 6.3 +> X-Git-Archeology: +> X-Git-Archeology: - Revision da0ab48b7939235608c8fc042c61ae997681e865: https://github.com/armbian/build/commit/da0ab48b7939235608c8fc042c61ae997681e865 +> X-Git-Archeology: Date: Thu, 27 Apr 2023 21:31:27 +0200 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rockchip: bump edge kernel to 6.3 +> X-Git-Archeology: +> X-Git-Archeology: - Revision 7a5cd0b246d3f0ae5949b6afa5a59081bd2376e9: https://github.com/armbian/build/commit/7a5cd0b246d3f0ae5949b6afa5a59081bd2376e9 +> X-Git-Archeology: Date: Sat, 29 Apr 2023 07:46:18 +0200 +> X-Git-Archeology: From: Paolo Sabatino +> X-Git-Archeology: Subject: rockchip: fix dtbs_install step for overlays +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + arch/arm/boot/.gitignore | 2 + + scripts/Makefile.dtbinst | 14 ++++++- + scripts/Makefile.lib | 20 ++++++++++ + 3 files changed, 35 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore +index 8c759326baf4..e6ce8f6ad4b1 100644 +--- a/arch/arm/boot/.gitignore ++++ b/arch/arm/boot/.gitignore +@@ -4,3 +4,5 @@ zImage + xipImage + bootpImage + uImage ++*.dtb* ++*.scr +diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst +index 4405d5b67578..4adbe6644d0c 100644 +--- a/scripts/Makefile.dtbinst ++++ b/scripts/Makefile.dtbinst +@@ -18,9 +18,12 @@ include $(srctree)/scripts/Kbuild.include + include $(kbuild-file) + + dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-))) ++dtbos := $(addprefix $(dst)/, $(dtbo-y)) ++scrs := $(addprefix $(dst)/, $(scr-y)) ++readmes := $(addprefix $(dst)/, $(dtbotxt-y)) + subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m)) + +-__dtbs_install: $(dtbs) $(subdirs) ++__dtbs_install: $(dtbs) $(dtbos) $(scrs) $(readmes) $(subdirs) + @: + + quiet_cmd_dtb_install = INSTALL $@ +@@ -32,6 +35,15 @@ $(dst)/%.dtb: $(obj)/%.dtb + $(dst)/%.dtbo: $(obj)/%.dtbo + $(call cmd,dtb_install) + ++$(dst)/%.dtbo: $(obj)/%.dtbo ++ $(call cmd,dtb_install) ++ ++$(dst)/%.scr: $(obj)/%.scr ++ $(call cmd,dtb_install) ++ ++$(dst)/README.rockchip-overlays: $(src)/README.rockchip-overlays ++ $(call cmd,dtb_install) ++ + PHONY += $(subdirs) + $(subdirs): + $(Q)$(MAKE) $(dtbinst)=$@ dst=$(if $(CONFIG_ARCH_WANT_FLAT_DTB_INSTALL),$(dst),$(patsubst $(obj)/%,$(dst)/%,$@)) +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index 68d0134bdbf9..9ea801a22569 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -343,6 +343,9 @@ DTC ?= $(objtree)/scripts/dtc/dtc + DTC_FLAGS += -Wno-interrupt_provider \ + -Wno-unique_unit_address + ++# Overlay support ++DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg ++ + # Disable noisy checks by default + ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) + DTC_FLAGS += -Wno-unit_address_vs_reg \ +@@ -421,6 +424,23 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE + $(call if_changed_dep,dtc) + ++quiet_cmd_dtco = DTCO $@ ++cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \ ++ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ ++ $(DTC) -O dtb -o $@ -b 0 \ ++ -i $(dir $<) $(DTC_FLAGS) \ ++ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ ++ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ++ ++$(obj)/%.dtbo: $(src)/%.dts FORCE ++ $(call if_changed_dep,dtco) ++ ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) ++ + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + + # Bzip2 +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/general-add-overlay-configfs.patch b/patch/kernel/archive/rockchip64-6.6/general-add-overlay-configfs.patch new file mode 100644 index 000000000..2627c36dc --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/general-add-overlay-configfs.patch @@ -0,0 +1,401 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: schwar3kat <61094841+schwar3kat@users.noreply.github.com> +Date: Mon, 16 Jan 2023 22:57:26 +1300 +Subject: OF: DT-Overlay configfs interface + +Commit message: Clean up mbox format in general-add-overlay-configfs.patch. No diff changes. + +Below patch is a squash of 4 commits borrowed from ayufan's +https://github.com/ayufan-rock64/linux-mainline-kernel repo: + +This is a port of Pantelis Antoniou's v3 port that makes use of the +upstreamed configfs support for binary attributes. + +Original commit message: +Add a runtime interface to using configfs for generic device tree overlay +usage. With it its possible to use device tree overlays without having +to use a per-platform overlay manager. +Please see Documentation/devicetree/configfs-overlays.txt for more info. + +Changes since v2: +- Removed ifdef CONFIG_OF_OVERLAY (since for now it's required) +- Created a documentation entry +- Slight rewording in Kconfig +- Fix build errors + +Changes since v1: +- of_resolve() -> of_resolve_phandles(). + +Signed-off-by: Pantelis Antoniou +Signed-off-by: Phil Elwell +--- + Documentation/devicetree/configfs-overlays.txt | 31 + + drivers/of/Kconfig | 7 + + drivers/of/Makefile | 1 + + drivers/of/configfs.c | 290 ++++++++++ + 4 files changed, 329 insertions(+) + +diff --git a/Documentation/devicetree/configfs-overlays.txt b/Documentation/devicetree/configfs-overlays.txt +new file mode 100644 +index 000000000000..5fa43e064307 +--- /dev/null ++++ b/Documentation/devicetree/configfs-overlays.txt +@@ -0,0 +1,31 @@ ++Howto use the configfs overlay interface. ++ ++A device-tree configfs entry is created in /config/device-tree/overlays ++and and it is manipulated using standard file system I/O. ++Note that this is a debug level interface, for use by developers and ++not necessarily something accessed by normal users due to the ++security implications of having direct access to the kernel's device tree. ++ ++* To create an overlay you mkdir the directory: ++ ++ # mkdir /config/device-tree/overlays/foo ++ ++* Either you echo the overlay firmware file to the path property file. ++ ++ # echo foo.dtbo >/config/device-tree/overlays/foo/path ++ ++* Or you cat the contents of the overlay to the dtbo file ++ ++ # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo ++ ++The overlay file will be applied, and devices will be created/destroyed ++as required. ++ ++To remove it simply rmdir the directory. ++ ++ # rmdir /config/device-tree/overlays/foo ++ ++The rationalle of the dual interface (firmware & direct copy) is that each is ++better suited to different use patterns. The firmware interface is what's ++intended to be used by hardware managers in the kernel, while the copy interface ++make sense for developers (since it avoids problems with namespaces). +diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig +index da9826accb1b..52ffe3e8930f 100644 +--- a/drivers/of/Kconfig ++++ b/drivers/of/Kconfig +@@ -102,4 +102,11 @@ config OF_OVERLAY + config OF_NUMA + bool + ++config OF_CONFIGFS ++ bool "Device Tree Overlay ConfigFS interface" ++ select CONFIGFS_FS ++ select OF_OVERLAY ++ help ++ Enable a simple user-space driven DT overlay interface. ++ + endif # OF +diff --git a/drivers/of/Makefile b/drivers/of/Makefile +index eff624854575..61bd05f08ca1 100644 +--- a/drivers/of/Makefile ++++ b/drivers/of/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-y = base.o cpu.o device.o module.o platform.o property.o + obj-$(CONFIG_OF_KOBJ) += kobj.o ++obj-$(CONFIG_OF_CONFIGFS) += configfs.o + obj-$(CONFIG_OF_DYNAMIC) += dynamic.o + obj-$(CONFIG_OF_FLATTREE) += fdt.o + obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o +diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c +new file mode 100644 +index 000000000000..5dd509e8fc87 +--- /dev/null ++++ b/drivers/of/configfs.c +@@ -0,0 +1,290 @@ ++/* ++ * Configfs entries for device-tree ++ * ++ * Copyright (C) 2013 - Pantelis Antoniou ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "of_private.h" ++ ++struct cfs_overlay_item { ++ struct config_item item; ++ ++ char path[PATH_MAX]; ++ ++ const struct firmware *fw; ++ struct device_node *overlay; ++ int ov_id; ++ ++ void *dtbo; ++ int dtbo_size; ++}; ++ ++static int create_overlay(struct cfs_overlay_item *overlay, void *blob, u32 blob_size) ++{ ++ int err; ++ ++ err = of_overlay_fdt_apply(blob, blob_size, &overlay->ov_id); ++ if (err < 0) { ++ pr_err("%s: Failed to create overlay (err=%d)\n", ++ __func__, err); ++ goto out_err; ++ } ++ ++out_err: ++ return err; ++} ++ ++static inline struct cfs_overlay_item *to_cfs_overlay_item( ++ struct config_item *item) ++{ ++ return item ? container_of(item, struct cfs_overlay_item, item) : NULL; ++} ++ ++static ssize_t cfs_overlay_item_path_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ return sprintf(page, "%s\n", overlay->path); ++} ++ ++static ssize_t cfs_overlay_item_path_store(struct config_item *item, ++ const char *page, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ const char *p = page; ++ char *s; ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy to path buffer (and make sure it's always zero terminated */ ++ count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); ++ overlay->path[sizeof(overlay->path) - 1] = '\0'; ++ ++ /* strip trailing newlines */ ++ s = overlay->path + strlen(overlay->path); ++ while (s > overlay->path && *--s == '\n') ++ *s = '\0'; ++ ++ pr_debug("%s: path is '%s'\n", __func__, overlay->path); ++ ++ err = request_firmware(&overlay->fw, overlay->path, NULL); ++ if (err != 0) ++ goto out_err; ++ ++ err = create_overlay(overlay, (void *)overlay->fw->data, overlay->fw->size); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ ++ release_firmware(overlay->fw); ++ overlay->fw = NULL; ++ ++ overlay->path[0] = '\0'; ++ return err; ++} ++ ++static ssize_t cfs_overlay_item_status_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ return sprintf(page, "%s\n", ++ overlay->ov_id >= 0 ? "applied" : "unapplied"); ++} ++ ++CONFIGFS_ATTR(cfs_overlay_item_, path); ++CONFIGFS_ATTR_RO(cfs_overlay_item_, status); ++ ++static struct configfs_attribute *cfs_overlay_attrs[] = { ++ &cfs_overlay_item_attr_path, ++ &cfs_overlay_item_attr_status, ++ NULL, ++}; ++ ++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, ++ void *buf, size_t max_count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ pr_debug("%s: buf=%p max_count=%zu\n", __func__, ++ buf, max_count); ++ ++ if (overlay->dtbo == NULL) ++ return 0; ++ ++ /* copy if buffer provided */ ++ if (buf != NULL) { ++ /* the buffer must be large enough */ ++ if (overlay->dtbo_size > max_count) ++ return -ENOSPC; ++ ++ memcpy(buf, overlay->dtbo, overlay->dtbo_size); ++ } ++ ++ return overlay->dtbo_size; ++} ++ ++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, ++ const void *buf, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy the contents */ ++ overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); ++ if (overlay->dtbo == NULL) ++ return -ENOMEM; ++ ++ overlay->dtbo_size = count; ++ ++ err = create_overlay(overlay, overlay->dtbo, overlay->dtbo_size); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ kfree(overlay->dtbo); ++ overlay->dtbo = NULL; ++ overlay->dtbo_size = 0; ++ ++ return err; ++} ++ ++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); ++ ++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { ++ &cfs_overlay_item_attr_dtbo, ++ NULL, ++}; ++ ++static void cfs_overlay_release(struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ if (overlay->ov_id >= 0) ++ of_overlay_remove(&overlay->ov_id); ++ if (overlay->fw) ++ release_firmware(overlay->fw); ++ /* kfree with NULL is safe */ ++ kfree(overlay->dtbo); ++ kfree(overlay); ++} ++ ++static struct configfs_item_operations cfs_overlay_item_ops = { ++ .release = cfs_overlay_release, ++}; ++ ++static struct config_item_type cfs_overlay_type = { ++ .ct_item_ops = &cfs_overlay_item_ops, ++ .ct_attrs = cfs_overlay_attrs, ++ .ct_bin_attrs = cfs_overlay_bin_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *cfs_overlay_group_make_item( ++ struct config_group *group, const char *name) ++{ ++ struct cfs_overlay_item *overlay; ++ ++ overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); ++ if (!overlay) ++ return ERR_PTR(-ENOMEM); ++ overlay->ov_id = -1; ++ ++ config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); ++ return &overlay->item; ++} ++ ++static void cfs_overlay_group_drop_item(struct config_group *group, ++ struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ config_item_put(&overlay->item); ++} ++ ++static struct configfs_group_operations overlays_ops = { ++ .make_item = cfs_overlay_group_make_item, ++ .drop_item = cfs_overlay_group_drop_item, ++}; ++ ++static struct config_item_type overlays_type = { ++ .ct_group_ops = &overlays_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct configfs_group_operations of_cfs_ops = { ++ /* empty - we don't allow anything to be created */ ++}; ++ ++static struct config_item_type of_cfs_type = { ++ .ct_group_ops = &of_cfs_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++struct config_group of_cfs_overlay_group; ++ ++static struct configfs_subsystem of_cfs_subsys = { ++ .su_group = { ++ .cg_item = { ++ .ci_namebuf = "device-tree", ++ .ci_type = &of_cfs_type, ++ }, ++ }, ++ .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), ++}; ++ ++static int __init of_cfs_init(void) ++{ ++ int ret; ++ ++ pr_info("%s\n", __func__); ++ ++ config_group_init(&of_cfs_subsys.su_group); ++ config_group_init_type_name(&of_cfs_overlay_group, "overlays", ++ &overlays_type); ++ configfs_add_default_group(&of_cfs_overlay_group, ++ &of_cfs_subsys.su_group); ++ ++ ret = configfs_register_subsystem(&of_cfs_subsys); ++ if (ret != 0) { ++ pr_err("%s: failed to register subsys\n", __func__); ++ goto out; ++ } ++ pr_info("%s: OK\n", __func__); ++out: ++ return ret; ++} ++late_initcall(of_cfs_init); +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.6/general-add-panel-simple-dsi.patch b/patch/kernel/archive/rockchip64-6.6/general-add-panel-simple-dsi.patch new file mode 100644 index 000000000..69d564ddd --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.6/general-add-panel-simple-dsi.patch @@ -0,0 +1,856 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: simple <991605149@qq.com> +Date: Sun, 12 Sep 2021 20:06:02 +0200 +Subject: [ARCHEOLOGY] general add panel simple dsi (#3140) + +> X-Git-Archeology: > recovered message: > * Backporting patch to 5.10 kernel makes sense. Lets do it. +> X-Git-Archeology: > recovered message: > Co-authored-by: iamdrq +> X-Git-Archeology: > recovered message: > Co-authored-by: Igor Pecovnik +> X-Git-Archeology: - Revision 15819f00e21238e36ca70f6d8445efd6157fbe66: https://github.com/armbian/build/commit/15819f00e21238e36ca70f6d8445efd6157fbe66 +> X-Git-Archeology: Date: Sun, 12 Sep 2021 20:06:02 +0200 +> X-Git-Archeology: From: simple <991605149@qq.com> +> X-Git-Archeology: Subject: general add panel simple dsi (#3140) +> X-Git-Archeology: +> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e +> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4 +> X-Git-Archeology: Date: Tue, 11 Jan 2022 15:26:11 +0100 +> X-Git-Archeology: From: Oleg +> X-Git-Archeology: Subject: move kernel edge to 5.16 (#3387) +> X-Git-Archeology: +> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d +> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 +> X-Git-Archeology: From: Piotr Szczepanik +> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f +> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 +> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 +> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 +> X-Git-Archeology: From: Jianfeng Liu +> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 +> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 +> X-Git-Archeology: From: Igor Pecovnik +> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 3b78b57fe367e60ad874d9e16ff1cd67957f8382: https://github.com/armbian/build/commit/3b78b57fe367e60ad874d9e16ff1cd67957f8382 +> X-Git-Archeology: Date: Sat, 24 Dec 2022 09:43:51 +0100 +> X-Git-Archeology: From: simple <991605149@qq.com> +> X-Git-Archeology: Subject: Fix general-add-panel-simple-dsi.patch on linux6.1 (#4607) +> X-Git-Archeology: +> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 +> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 +> X-Git-Archeology: From: amazingfate +> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 +> X-Git-Archeology: +--- + drivers/gpu/drm/panel/Makefile | 1 + + drivers/gpu/drm/panel/panel-simple-dsi.c | 772 ++++++++++ + 2 files changed, 773 insertions(+) + +diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile +index 30cf553c8d1d..04e219b32c08 100644 +--- a/drivers/gpu/drm/panel/Makefile ++++ b/drivers/gpu/drm/panel/Makefile +@@ -9,6 +9,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o + obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o + obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o + obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o ++obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple-dsi.o + obj-$(CONFIG_DRM_PANEL_EDP) += panel-edp.o + obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o + obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o +diff --git a/drivers/gpu/drm/panel/panel-simple-dsi.c b/drivers/gpu/drm/panel/panel-simple-dsi.c +new file mode 100644 +index 000000000000..e3c8dcf8cb5e +--- /dev/null ++++ b/drivers/gpu/drm/panel/panel-simple-dsi.c +@@ -0,0 +1,772 @@ ++/* ++ * Copyright (C) 2021 ++ * This simple dsi driver porting from rock-chip panel-simple.c on linux-4.4 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include