diff --git a/config/kernel/linux-media-current.config b/config/kernel/linux-media-current.config index 8146f1b23..05733acbf 100644 --- a/config/kernel/linux-media-current.config +++ b/config/kernel/linux-media-current.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.18.19 Kernel Configuration +# Linux/arm64 5.19.5 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y @@ -32,9 +32,9 @@ CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYSVIPC_COMPAT=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_WATCH_QUEUE is not set @@ -142,7 +142,6 @@ CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU=y -CONFIG_TASKS_RUDE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y @@ -216,6 +215,8 @@ CONFIG_RD_LZO=y CONFIG_RD_LZ4=y CONFIG_RD_ZSTD=y CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_EMBED is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y @@ -247,7 +248,6 @@ CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y @@ -264,17 +264,6 @@ CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y -# CONFIG_COMPAT_BRK is not set -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -CONFIG_SLAB_MERGE_DEFAULT=y -CONFIG_SLAB_FREELIST_RANDOM=y -# CONFIG_SLAB_FREELIST_HARDENED is not set -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -CONFIG_SLUB_CPU_PARTIAL=y CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y @@ -501,12 +490,14 @@ CONFIG_ARM64_EPAN=y # end of ARMv8.7 architectural features CONFIG_ARM64_SVE=y +CONFIG_ARM64_SME=y CONFIG_ARM64_MODULE_PLTS=y CONFIG_ARM64_PSEUDO_NMI=y # CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set CONFIG_RELOCATABLE=y CONFIG_RANDOMIZE_BASE=y CONFIG_RANDOMIZE_MODULE_REGION_FULL=y +CONFIG_ARCH_NR_GPIO=0 # end of Kernel Features # @@ -519,8 +510,6 @@ CONFIG_EFI=y CONFIG_DMI=y # end of Boot options -CONFIG_SYSVIPC_COMPAT=y - # # Power management options # @@ -654,7 +643,7 @@ CONFIG_ACPI_CONFIGFS=m # CONFIG_ACPI_PFRUT is not set CONFIG_ACPI_IORT=y CONFIG_ACPI_GTDT=y -CONFIG_ACPI_AGDI=y +# CONFIG_ACPI_AGDI is not set CONFIG_ACPI_PPTT=y CONFIG_ACPI_PCC=y CONFIG_PMIC_OPREGION=y @@ -686,6 +675,8 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=m CONFIG_CRYPTO_SHA3_ARM64=m CONFIG_CRYPTO_SM3_ARM64_CE=m CONFIG_CRYPTO_SM4_ARM64_CE=m +# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m CONFIG_CRYPTO_AES_ARM64=y @@ -796,6 +787,7 @@ CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y # # GCOV-based kernel profiling @@ -807,7 +799,6 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set -# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y @@ -817,6 +808,7 @@ CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_MODULE_SIG=y @@ -937,6 +929,41 @@ CONFIG_COREDUMP=y # # Memory Management options # +CONFIG_ZPOOL=y +CONFIG_SWAP=y +CONFIG_ZSWAP=y +CONFIG_ZSWAP_DEFAULT_ON=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd" +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="z3fold" +CONFIG_ZBUD=y +CONFIG_Z3FOLD=y +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +# CONFIG_COMPAT_BRK is not set CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y @@ -946,8 +973,8 @@ CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -# CONFIG_MEMORY_HOTPLUG is not set CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_MEMORY_HOTPLUG is not set CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_MEMORY_BALLOON=y @@ -968,6 +995,7 @@ CONFIG_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y # CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_USE_PERCPU_NUMA_NODE_ID=y @@ -978,41 +1006,25 @@ CONFIG_CMA=y CONFIG_CMA_DEBUGFS=y # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 -CONFIG_ZSWAP=y -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set -CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y -CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd" -# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y -# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT="z3fold" -CONFIG_ZSWAP_DEFAULT_ON=y -CONFIG_ZPOOL=y -CONFIG_ZBUD=y -CONFIG_Z3FOLD=y -CONFIG_ZSMALLOC=y -# CONFIG_ZSMALLOC_STAT is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set CONFIG_PAGE_IDLE_FLAG=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y +CONFIG_VM_EVENT_COUNTERS=y CONFIG_PERCPU_STATS=y # CONFIG_GUP_TEST is not set -# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_MAPPING_DIRTY_HELPERS=y CONFIG_SECRETMEM=y # CONFIG_ANON_VMA_NAME is not set +# CONFIG_USERFAULTFD is not set # # Data Access Monitoring @@ -1825,6 +1837,8 @@ CONFIG_CAN_C_CAN_PCI=m CONFIG_CAN_CC770=m CONFIG_CAN_CC770_ISA=m CONFIG_CAN_CC770_PLATFORM=m +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set # CONFIG_CAN_IFI_CANFD is not set CONFIG_CAN_M_CAN=m CONFIG_CAN_M_CAN_PCI=m @@ -2172,6 +2186,7 @@ CONFIG_CXL_PCI=m CONFIG_CXL_ACPI=m CONFIG_CXL_MEM=m CONFIG_CXL_PORT=m +CONFIG_CXL_SUSPEND=y # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set @@ -2192,11 +2207,15 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +# CONFIG_FW_LOADER_COMPRESS_ZSTD is not set CONFIG_FW_CACHE=y +# CONFIG_FW_UPLOAD is not set # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -2242,6 +2261,7 @@ CONFIG_VEXPRESS_CONFIG=y CONFIG_MHI_BUS=m # CONFIG_MHI_BUS_DEBUG is not set CONFIG_MHI_BUS_PCI_GENERIC=m +# CONFIG_MHI_BUS_EP is not set # end of Bus devices CONFIG_CONNECTOR=m @@ -2260,10 +2280,10 @@ CONFIG_ARM_SCMI_HAVE_MSG=y CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y CONFIG_ARM_SCMI_TRANSPORT_SMC=y -CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y +# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y -CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE=y +# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set CONFIG_ARM_SCMI_POWER_DOMAIN=y # end of ARM System Control and Management Interface Protocol @@ -2299,13 +2319,14 @@ CONFIG_EFI_CAPSULE_LOADER=m CONFIG_EFI_TEST=m CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_EFI_DISABLE_PCI_DMA=y +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EFI_COCO_SECRET is not set # end of EFI (Extensible Firmware Interface) Support CONFIG_UEFI_CPER=y CONFIG_UEFI_CPER_ARM=y -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y -# CONFIG_EFI_DISABLE_RUNTIME is not set CONFIG_ARM_PSCI_FW=y CONFIG_ARM_PSCI_CHECKER=y CONFIG_HAVE_ARM_SMCCC=y @@ -2545,7 +2566,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y CONFIG_NVME_MULTIPATH=y -CONFIG_NVME_VERBOSE_ERRORS=y +# CONFIG_NVME_VERBOSE_ERRORS is not set CONFIG_NVME_HWMON=y CONFIG_NVME_FABRICS=m CONFIG_NVME_FC=m @@ -2587,7 +2608,7 @@ CONFIG_DW_XDATA_PCIE=m CONFIG_XILINX_SDFEC=m CONFIG_MISC_RTSX=m # CONFIG_HISI_HIKEY_USB is not set -CONFIG_OPEN_DICE=m +# CONFIG_OPEN_DICE is not set # CONFIG_C2PORT is not set # @@ -2615,6 +2636,7 @@ CONFIG_CB710_DEBUG_ASSUMPTIONS=y # CONFIG_SENSORS_LIS3_I2C is not set CONFIG_ALTERA_STAPL=m +# CONFIG_VMWARE_VMCI is not set CONFIG_GENWQE=m CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 CONFIG_ECHO=m @@ -2702,15 +2724,6 @@ CONFIG_SCSI_MPT3SAS_MAX_SGE=128 # CONFIG_SCSI_MPT2SAS is not set CONFIG_SCSI_MPI3MR=m # CONFIG_SCSI_SMARTPQI is not set -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PCI=m -# CONFIG_SCSI_UFS_DWC_TC_PCI is not set -CONFIG_SCSI_UFSHCD_PLATFORM=y -# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set -# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set -# CONFIG_SCSI_UFS_BSG is not set -CONFIG_SCSI_UFS_HPB=y -CONFIG_SCSI_UFS_HWMON=y # CONFIG_SCSI_HPTIOP is not set # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set @@ -2777,8 +2790,8 @@ CONFIG_AHCI_CEVA=y CONFIG_AHCI_TEGRA=y CONFIG_AHCI_XGENE=y CONFIG_AHCI_QORIQ=y -# CONFIG_SATA_INIC162X is not set -# CONFIG_SATA_ACARD_AHCI is not set +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m CONFIG_SATA_SIL24=y CONFIG_ATA_SFF=y @@ -3192,6 +3205,7 @@ CONFIG_OCTEONTX2_MBOX=m # CONFIG_OCTEONTX2_AF is not set CONFIG_OCTEONTX2_PF=m CONFIG_OCTEONTX2_VF=m +# CONFIG_OCTEON_EP is not set # CONFIG_PRESTERA is not set CONFIG_NET_VENDOR_MELLANOX=y CONFIG_MLX4_EN=m @@ -3211,8 +3225,8 @@ CONFIG_MLX5_CLS_ACT=y CONFIG_MLX5_TC_SAMPLE=y CONFIG_MLX5_CORE_EN_DCB=y # CONFIG_MLX5_CORE_IPOIB is not set -# CONFIG_MLX5_IPSEC is not set -# CONFIG_MLX5_TLS is not set +# CONFIG_MLX5_EN_IPSEC is not set +# CONFIG_MLX5_EN_TLS is not set CONFIG_MLX5_SW_STEERING=y # CONFIG_MLX5_SF is not set # CONFIG_MLXSW_CORE is not set @@ -3294,6 +3308,7 @@ CONFIG_NET_VENDOR_SIS=y CONFIG_NET_VENDOR_SOLARFLARE=y # CONFIG_SFC is not set # CONFIG_SFC_FALCON is not set +# CONFIG_SFC_SIENA is not set CONFIG_NET_VENDOR_SMSC=y CONFIG_SMC91X=y # CONFIG_EPIC100 is not set @@ -3349,6 +3364,7 @@ CONFIG_SFP=m # CONFIG_AMD_PHY=m CONFIG_ADIN_PHY=m +CONFIG_ADIN1100_PHY=m CONFIG_AQUANTIA_PHY=m CONFIG_AX88796B_PHY=m CONFIG_BROADCOM_PHY=m @@ -3390,6 +3406,7 @@ CONFIG_DP83TC811_PHY=m CONFIG_DP83848_PHY=m # CONFIG_DP83867_PHY is not set CONFIG_DP83869_PHY=m +CONFIG_DP83TD510_PHY=m CONFIG_VITESSE_PHY=m # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set @@ -3698,6 +3715,8 @@ CONFIG_WILC1000=m CONFIG_WILC1000_SDIO=m CONFIG_WILC1000_SPI=m # CONFIG_WILC1000_HW_OOB_INTR is not set +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_PLFXLC is not set CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=m CONFIG_RT2400PCI=m @@ -3767,7 +3786,9 @@ CONFIG_RTW89=m CONFIG_RTW89_CORE=m CONFIG_RTW89_PCI=m CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852C=m CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852CE=m # CONFIG_RTW89_DEBUGMSG is not set # CONFIG_RTW89_DEBUGFS is not set CONFIG_WLAN_VENDOR_RSI=y @@ -3776,6 +3797,8 @@ CONFIG_RSI_91X=m CONFIG_RSI_SDIO=m CONFIG_RSI_USB=m CONFIG_RSI_COEX=y +CONFIG_WLAN_VENDOR_SILABS=y +CONFIG_WFX=m CONFIG_WLAN_VENDOR_ST=y CONFIG_CW1200=m CONFIG_CW1200_WLAN_SDIO=m @@ -3792,13 +3815,13 @@ CONFIG_WLCORE_SDIO=m CONFIG_WILINK_PLATFORM_DATA=y CONFIG_RTL8723DU=m CONFIG_RTL8723DS=m -CONFIG_RTL8822CS=m -CONFIG_RTL8822BU=m -CONFIG_RTL8821CU=m -CONFIG_88XXAU=m -CONFIG_RTL8192EU=m -CONFIG_RTL8189FS=m -CONFIG_RTL8189ES=m +# CONFIG_RTL8822CS is not set +# CONFIG_RTL8822BU is not set +# CONFIG_RTL8821CU is not set +# CONFIG_88XXAU is not set +# CONFIG_RTL8192EU is not set +# CONFIG_RTL8189FS is not set +# CONFIG_RTL8189ES is not set CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m @@ -3825,7 +3848,6 @@ CONFIG_HDLC_RAW_ETH=m CONFIG_IEEE802154_DRIVERS=m CONFIG_IEEE802154_FAKELB=m CONFIG_IEEE802154_AT86RF230=m -# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set CONFIG_IEEE802154_MRF24J40=m CONFIG_IEEE802154_CC2520=m CONFIG_IEEE802154_ATUSB=m @@ -3844,6 +3866,7 @@ CONFIG_WWAN_HWSIM=m CONFIG_MHI_WWAN_CTRL=m CONFIG_MHI_WWAN_MBIM=m # CONFIG_RPMSG_WWAN_CTRL is not set +# CONFIG_MTK_T7XX is not set # end of Wireless WAN CONFIG_XEN_NETDEV_FRONTEND=m @@ -3969,6 +3992,7 @@ CONFIG_JOYSTICK_PSXPAD_SPI_FF=y CONFIG_JOYSTICK_PXRC=m CONFIG_JOYSTICK_QWIIC=m CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_SENSEHAT=m CONFIG_INPUT_TABLET=y # CONFIG_TABLET_USB_ACECAD is not set # CONFIG_TABLET_USB_AIPTEK is not set @@ -4110,6 +4134,7 @@ CONFIG_INPUT_DA7280_HAPTICS=m # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_IQS7222=m # CONFIG_INPUT_CMA3000 is not set CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y CONFIG_INPUT_SOC_BUTTON_ARRAY=m @@ -4136,7 +4161,7 @@ CONFIG_RMI4_F55=y # Hardware I/O ports # CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_SERPORT=y CONFIG_SERIO_AMBAKMI=y # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y @@ -4700,7 +4725,7 @@ CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set CONFIG_GENERIC_ADC_BATTERY=m -CONFIG_IP5XXX_POWER=m +# CONFIG_IP5XXX_POWER is not set # CONFIG_TEST_POWER is not set CONFIG_CHARGER_ADP5061=m CONFIG_BATTERY_CW2015=m @@ -4859,7 +4884,9 @@ CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=m CONFIG_SENSORS_NTC_THERMISTOR=m CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775_CORE=m CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT6775_I2C=m CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m @@ -4868,9 +4895,6 @@ CONFIG_SENSORS_NZXT_KRAKEN2=m CONFIG_SENSORS_OCC_P8_I2C=m CONFIG_SENSORS_OCC=m CONFIG_SENSORS_PCF8591=m -CONFIG_SENSORS_PECI_CPUTEMP=m -CONFIG_SENSORS_PECI_DIMMTEMP=m -CONFIG_SENSORS_PECI=m CONFIG_PMBUS=m CONFIG_SENSORS_PMBUS=m # CONFIG_SENSORS_ADM1266 is not set @@ -4905,8 +4929,7 @@ CONFIG_SENSORS_MP2888=m # CONFIG_SENSORS_MP2975 is not set # CONFIG_SENSORS_MP5023 is not set CONFIG_SENSORS_PIM4328=m -CONFIG_SENSORS_PLI1209BC=m -# CONFIG_SENSORS_PLI1209BC_REGULATOR is not set +# CONFIG_SENSORS_PLI1209BC is not set CONFIG_SENSORS_PM6764TR=m CONFIG_SENSORS_PXE1610=m CONFIG_SENSORS_Q54SJ108A2=m @@ -4915,6 +4938,7 @@ CONFIG_SENSORS_TPS40422=m CONFIG_SENSORS_TPS53679=m CONFIG_SENSORS_UCD9000=m CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_XDPE152=m CONFIG_SENSORS_XDPE122=m # CONFIG_SENSORS_XDPE122_REGULATOR is not set CONFIG_SENSORS_ZL6100=m @@ -4927,7 +4951,7 @@ CONFIG_SENSORS_SHT3x=m CONFIG_SENSORS_SHT4x=m CONFIG_SENSORS_SHTC1=m CONFIG_SENSORS_SIS5595=m -CONFIG_SENSORS_SY7636A=m +# CONFIG_SENSORS_SY7636A is not set CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_EMC1403=m CONFIG_SENSORS_EMC2103=m @@ -4955,7 +4979,7 @@ CONFIG_SENSORS_TMP103=m CONFIG_SENSORS_TMP108=m CONFIG_SENSORS_TMP401=m CONFIG_SENSORS_TMP421=m -CONFIG_SENSORS_TMP464=m +# CONFIG_SENSORS_TMP464 is not set CONFIG_SENSORS_TMP513=m CONFIG_SENSORS_VEXPRESS=m CONFIG_SENSORS_VIA686A=m @@ -5040,7 +5064,7 @@ CONFIG_ARM_SBSA_WATCHDOG=y CONFIG_DW_WATCHDOG=y CONFIG_RN5T618_WATCHDOG=m # CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_MAX77620_WATCHDOG is not set +CONFIG_MAX77620_WATCHDOG=m CONFIG_TEGRA_WATCHDOG=m CONFIG_ARM_SMC_WATCHDOG=y # CONFIG_ALIM7101_WDT is not set @@ -5152,7 +5176,7 @@ CONFIG_MFD_RK808=y CONFIG_MFD_RN5T618=m CONFIG_MFD_SEC_CORE=y # CONFIG_MFD_SI476X_CORE is not set -# CONFIG_MFD_SIMPLE_MFD_I2C is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m CONFIG_MFD_SM501=m CONFIG_MFD_SM501_GPIO=y # CONFIG_MFD_SKY81452 is not set @@ -5287,6 +5311,7 @@ CONFIG_REGULATOR_ROHM=m CONFIG_REGULATOR_RT4831=m CONFIG_REGULATOR_RT5033=m # CONFIG_REGULATOR_RT5190A is not set +CONFIG_REGULATOR_RT5759=m CONFIG_REGULATOR_RT6160=m CONFIG_REGULATOR_RT6245=m CONFIG_REGULATOR_RTQ2134=m @@ -5356,7 +5381,7 @@ CONFIG_CEC_PIN=y # # CEC support # -CONFIG_MEDIA_CEC_RC=y +# CONFIG_MEDIA_CEC_RC is not set CONFIG_CEC_PIN_ERROR_INJ=y CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_CEC_CH7322=m @@ -5558,7 +5583,7 @@ CONFIG_DVB_USB_AF9005_REMOTE=m CONFIG_DVB_USB_AZ6027=m CONFIG_DVB_USB_CINERGY_T2=m CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_CXUSB_ANALOG=y +# CONFIG_DVB_USB_CXUSB_ANALOG is not set CONFIG_DVB_USB_DIB0700=m CONFIG_DVB_USB_DIB3000MC=m CONFIG_DVB_USB_DIBUSB_MB=m @@ -5844,7 +5869,7 @@ CONFIG_VIDEO_APTINA_PLL=m CONFIG_VIDEO_CCS_PLL=m CONFIG_VIDEO_HI556=m CONFIG_VIDEO_HI846=m -CONFIG_VIDEO_HI847=m +# CONFIG_VIDEO_HI847 is not set CONFIG_VIDEO_IMX208=m CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m @@ -5867,9 +5892,9 @@ CONFIG_VIDEO_MT9V011=m CONFIG_VIDEO_MT9V032=m CONFIG_VIDEO_MT9V111=m CONFIG_VIDEO_NOON010PC30=m -CONFIG_VIDEO_OG01A1B=m +# CONFIG_VIDEO_OG01A1B is not set CONFIG_VIDEO_OV02A10=m -CONFIG_VIDEO_OV08D10=m +# CONFIG_VIDEO_OV08D10 is not set CONFIG_VIDEO_OV13858=m CONFIG_VIDEO_OV13B10=m CONFIG_VIDEO_OV2640=m @@ -6261,15 +6286,13 @@ CONFIG_DVB_DUMMY_FE=m # # Graphics support # +CONFIG_TEGRA_HOST1X_CONTEXT_BUS=y CONFIG_TEGRA_HOST1X=m CONFIG_TEGRA_HOST1X_FIREWALL=y CONFIG_DRM=m CONFIG_DRM_MIPI_DBI=m CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_DP_AUX_BUS=m -# CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_DP_HELPER=m CONFIG_DRM_KMS_HELPER=m # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set @@ -6277,6 +6300,12 @@ CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_DP_AUX_BUS=m +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set CONFIG_DRM_DP_CEC=y CONFIG_DRM_TTM=m CONFIG_DRM_VRAM_HELPER=m @@ -6365,6 +6394,7 @@ CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m CONFIG_DRM_PANEL_LG_LB035Q02=m # CONFIG_DRM_PANEL_LG_LG4573 is not set CONFIG_DRM_PANEL_NEC_NL8048HL11=m +CONFIG_DRM_PANEL_NEWVISION_NV3052C=m CONFIG_DRM_PANEL_NOVATEK_NT35510=m CONFIG_DRM_PANEL_NOVATEK_NT35560=m # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set @@ -6422,6 +6452,7 @@ CONFIG_DRM_CROS_EC_ANX7688=m CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_ITE_IT6505=m CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9211=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_ITE_IT66121=m @@ -6456,6 +6487,7 @@ CONFIG_DRM_I2C_ADV7511_CEC=y CONFIG_DRM_DW_HDMI=m CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +CONFIG_DRM_DW_HDMI_GP_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=m CONFIG_DRM_DW_MIPI_DSI=m # end of Display Interface Bridges @@ -6490,6 +6522,7 @@ CONFIG_DRM_TIDSS=m CONFIG_DRM_GUD=m CONFIG_DRM_SSD130X=m CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m CONFIG_DRM_LEGACY=y # CONFIG_DRM_TDFX is not set # CONFIG_DRM_R128 is not set @@ -6666,6 +6699,7 @@ CONFIG_SND_ALOOP=m CONFIG_SND_VIRMIDI=m CONFIG_SND_MTPAV=m CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SERIAL_GENERIC=m CONFIG_SND_MPU401=m CONFIG_SND_AC97_POWER_SAVE=y CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 @@ -6801,7 +6835,7 @@ CONFIG_SND_SOC=m CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_COMPRESS=y -CONFIG_SND_SOC_ACPI=m +CONFIG_SND_SOC_UTILS_KUNIT_TEST=m CONFIG_SND_SOC_ADI=m CONFIG_SND_SOC_ADI_AXI_I2S=m CONFIG_SND_SOC_ADI_AXI_SPDIF=m @@ -6844,7 +6878,6 @@ CONFIG_SND_SOC_IMG_PARALLEL_OUT=m CONFIG_SND_SOC_IMG_SPDIF_IN=m CONFIG_SND_SOC_IMG_SPDIF_OUT=m CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m -CONFIG_SND_SOC_INTEL_AVS=m CONFIG_SND_SOC_MTK_BTCVSD=m CONFIG_SND_SOC_ROCKCHIP=m CONFIG_SND_SOC_ROCKCHIP_I2S=m @@ -6877,6 +6910,7 @@ CONFIG_SND_SOC_TEGRA30_I2S=m CONFIG_SND_SOC_TEGRA210_AHUB=m CONFIG_SND_SOC_TEGRA210_DMIC=m CONFIG_SND_SOC_TEGRA210_I2S=m +CONFIG_SND_SOC_TEGRA186_ASRC=m CONFIG_SND_SOC_TEGRA186_DSPK=m CONFIG_SND_SOC_TEGRA210_ADMAIF=m CONFIG_SND_SOC_TEGRA210_MVC=m @@ -6969,6 +7003,10 @@ CONFIG_SND_SOC_CS35L41_LIB=m CONFIG_SND_SOC_CS35L41=m CONFIG_SND_SOC_CS35L41_SPI=m CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L45_TABLES=m +CONFIG_SND_SOC_CS35L45=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L45_I2C=m CONFIG_SND_SOC_CS42L42=m CONFIG_SND_SOC_CS42L51=m CONFIG_SND_SOC_CS42L51_I2C=m @@ -7037,6 +7075,7 @@ CONFIG_SND_SOC_MAX98373=m CONFIG_SND_SOC_MAX98373_I2C=m CONFIG_SND_SOC_MAX98373_SDW=m CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m CONFIG_SND_SOC_MAX9850=m CONFIG_SND_SOC_MAX9860=m CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m @@ -7071,6 +7110,7 @@ CONFIG_SND_SOC_RT298=m CONFIG_SND_SOC_RT1011=m CONFIG_SND_SOC_RT1015=m CONFIG_SND_SOC_RT1015P=m +CONFIG_SND_SOC_RT1016=m CONFIG_SND_SOC_RT1019=m CONFIG_SND_SOC_RT1305=m CONFIG_SND_SOC_RT1308=m @@ -7181,6 +7221,8 @@ CONFIG_SND_SOC_WM8711=m CONFIG_SND_SOC_WM8727=m CONFIG_SND_SOC_WM8728=m CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m CONFIG_SND_SOC_WM8737=m CONFIG_SND_SOC_WM8741=m CONFIG_SND_SOC_WM8750=m @@ -7332,6 +7374,7 @@ CONFIG_LOGIWHEELS_FF=y CONFIG_HID_MAGICMOUSE=m CONFIG_HID_MALTRON=m CONFIG_HID_MAYFLASH=m +CONFIG_HID_MEGAWORLD_FF=m CONFIG_HID_REDRAGON=m CONFIG_HID_MICROSOFT=m CONFIG_HID_MONTEREY=m @@ -7352,14 +7395,14 @@ CONFIG_HID_PICOLCD_LCD=y CONFIG_HID_PICOLCD_LEDS=y CONFIG_HID_PICOLCD_CIR=y CONFIG_HID_PLANTRONICS=m -CONFIG_HID_RAZER=m +# CONFIG_HID_RAZER is not set CONFIG_HID_PRIMAX=m CONFIG_HID_RETRODE=m CONFIG_HID_ROCCAT=m CONFIG_HID_SAITEK=m CONFIG_HID_SAMSUNG=m CONFIG_HID_SEMITEK=m -CONFIG_HID_SIGMAMICRO=m +# CONFIG_HID_SIGMAMICRO is not set CONFIG_HID_SONY=m CONFIG_SONY_FF=y CONFIG_HID_SPEEDLINK=m @@ -7810,6 +7853,7 @@ CONFIG_TYPEC_WUSB3801=m # # USB Type-C Multiplexer/DeMultiplexer Switch support # +CONFIG_TYPEC_MUX_FSA4480=m CONFIG_TYPEC_MUX_PI3USB30532=m # end of USB Type-C Multiplexer/DeMultiplexer Switch support @@ -7875,7 +7919,16 @@ CONFIG_MMC_SDHCI_XENON=y CONFIG_MMC_SDHCI_OMAP=m CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_SDHCI_EXTERNAL_DMA=y -CONFIG_MMC_LITEX=m +# CONFIG_MMC_LITEX is not set +CONFIG_SCSI_UFSHCD=y +# CONFIG_SCSI_UFS_BSG is not set +CONFIG_SCSI_UFS_HPB=y +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_UFSHCD_PCI=m +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=y +# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -7941,6 +7994,10 @@ CONFIG_LEDS_LM3697=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set +# +# RGB LED drivers +# + # # LED Triggers # @@ -8089,7 +8146,7 @@ CONFIG_RTC_DRV_EFI=y # CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set -CONFIG_RTC_DRV_OPTEE=m +# CONFIG_RTC_DRV_OPTEE is not set # CONFIG_RTC_DRV_ZYNQMP is not set CONFIG_RTC_DRV_CROS_EC=y CONFIG_RTC_DRV_NTXEC=m @@ -8131,6 +8188,7 @@ CONFIG_HISI_DMA=m CONFIG_MV_XOR_V2=y CONFIG_PL330_DMA=y CONFIG_PLX_DMA=m +CONFIG_TEGRA186_GPC_DMA=m CONFIG_TEGRA20_APB_DMA=y CONFIG_TEGRA210_ADMA=m # CONFIG_XILINX_DMA is not set @@ -8186,13 +8244,14 @@ CONFIG_VFIO_PCI_CORE=y CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_INTX=y CONFIG_VFIO_PCI=y -# CONFIG_MLX5_VFIO_PCI is not set +CONFIG_MLX5_VFIO_PCI=m # CONFIG_HISI_ACC_VFIO_PCI is not set # CONFIG_VFIO_PLATFORM is not set # CONFIG_VFIO_MDEV is not set CONFIG_VIRT_DRIVERS=y CONFIG_VMGENID=y CONFIG_NITRO_ENCLAVES=m +CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI_LIB=y CONFIG_VIRTIO_PCI_LIB_LEGACY=y @@ -8254,6 +8313,7 @@ CONFIG_XEN_PRIVCMD=y CONFIG_XEN_EFI=y CONFIG_XEN_AUTO_XLATE=y CONFIG_XEN_FRONT_PGDIR_SHBUF=m +# CONFIG_XEN_VIRTIO is not set # end of Xen driver support # CONFIG_GREYBUS is not set @@ -8338,7 +8398,7 @@ CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y # CONFIG_VIDEO_MAX96712 is not set -# CONFIG_VIDEO_ROCKCHIP_VDEC is not set +CONFIG_VIDEO_ROCKCHIP_VDEC=m CONFIG_VIDEO_ZORAN=m # CONFIG_VIDEO_ZORAN_DC30 is not set # CONFIG_VIDEO_ZORAN_ZR36060 is not set @@ -8351,7 +8411,6 @@ CONFIG_DVB_BUDGET_PATCH=m CONFIG_DVB_SP8870=m # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set -# CONFIG_UNISYSSPAR is not set CONFIG_COMMON_CLK_XLNX_CLKWZRD=m CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m @@ -8395,9 +8454,13 @@ CONFIG_HMS_ANYBUSS_BUS=m # CONFIG_ARCX_ANYBUS_CONTROLLER is not set # CONFIG_HMS_PROFINET is not set # CONFIG_QLGE is not set -CONFIG_WFX=m + +# +# VME Device Drivers +# # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y +CONFIG_CHROMEOS_ACPI=m # CONFIG_CHROMEOS_TBMC is not set CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y @@ -8648,6 +8711,7 @@ CONFIG_EXTCON_PTN5150=m CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USBC_CROS_EC=y CONFIG_EXTCON_USBC_TUSB320=m +# CONFIG_EXTCON_USBC_VIRTUAL_PD is not set CONFIG_MEMORY=y # CONFIG_ARM_PL172_MPMC is not set CONFIG_TEGRA_MC=y @@ -8681,8 +8745,9 @@ CONFIG_ADXL345_SPI=m CONFIG_ADXL355=m CONFIG_ADXL355_I2C=m CONFIG_ADXL355_SPI=m -# CONFIG_ADXL367_SPI is not set -# CONFIG_ADXL367_I2C is not set +CONFIG_ADXL367=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m CONFIG_ADXL372=m CONFIG_ADXL372_SPI=m CONFIG_ADXL372_I2C=m @@ -9261,6 +9326,7 @@ CONFIG_PWM_NTXEC=m # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_TEGRA=y +CONFIG_PWM_XILINX=m # # IRQ chip support @@ -9274,6 +9340,7 @@ CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ITS_PCI=y # CONFIG_AL_FIC is not set +# CONFIG_XILINX_INTC is not set CONFIG_PARTITION_PERCPU=y # end of IRQ chip support @@ -9300,7 +9367,7 @@ CONFIG_BCM_KONA_USB2_PHY=m CONFIG_PHY_CADENCE_TORRENT=m CONFIG_PHY_CADENCE_DPHY=m -CONFIG_PHY_CADENCE_DPHY_RX=m +# CONFIG_PHY_CADENCE_DPHY_RX is not set CONFIG_PHY_CADENCE_SIERRA=m # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_PXA_28NM_HSIC is not set @@ -9319,8 +9386,8 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB3=m CONFIG_PHY_ROCKCHIP_PCIE=y -CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y CONFIG_PHY_SAMSUNG_USB2=y @@ -9394,13 +9461,7 @@ CONFIG_OF_FPGA_REGION=m # CONFIG_FPGA_DFL is not set # CONFIG_FSI is not set CONFIG_TEE=y - -# -# TEE drivers -# CONFIG_OPTEE=y -# end of TEE drivers - CONFIG_MULTIPLEXER=y # @@ -9426,8 +9487,8 @@ CONFIG_MOST=m # CONFIG_MOST_USB_HDM is not set # CONFIG_MOST_CDEV is not set CONFIG_MOST_SND=m -CONFIG_PECI=m -CONFIG_PECI_CPU=m +# CONFIG_PECI is not set +# CONFIG_HTE is not set # end of Device Drivers # @@ -9500,7 +9561,7 @@ CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_IOSTAT=y -CONFIG_F2FS_UNFAIR_RWSEM=y +# CONFIG_F2FS_UNFAIR_RWSEM is not set CONFIG_ZONEFS_FS=m CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -9547,6 +9608,7 @@ CONFIG_FSCACHE_STATS=y CONFIG_CACHEFILES=m # CONFIG_CACHEFILES_DEBUG is not set # CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set # end of Caches # @@ -9598,6 +9660,9 @@ CONFIG_TMPFS_XATTR=y CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y +CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y @@ -9862,6 +9927,8 @@ CONFIG_KEYS=y CONFIG_KEYS_REQUEST_CACHE=y CONFIG_PERSISTENT_KEYRINGS=y CONFIG_TRUSTED_KEYS=y +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_TRUSTED_KEYS_TEE=y CONFIG_ENCRYPTED_KEYS=y # CONFIG_USER_DECRYPTED_DATA is not set CONFIG_KEY_DH_OPERATIONS=y @@ -9969,6 +10036,10 @@ CONFIG_INIT_STACK_NONE=y CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RANDSTRUCT_FULL is not set +# CONFIG_RANDSTRUCT_PERFORMANCE is not set # end of Kernel hardening options # end of Security options @@ -10070,7 +10141,6 @@ CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_XXHASH=y CONFIG_CRYPTO_BLAKE2B=y -CONFIG_CRYPTO_BLAKE2S=m CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRC64_ROCKSOFT=y CONFIG_CRYPTO_GHASH=y @@ -10084,6 +10154,7 @@ CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m +# CONFIG_CRYPTO_SM3_GENERIC is not set CONFIG_CRYPTO_STREEBOG=m CONFIG_CRYPTO_WP512=m @@ -10107,6 +10178,7 @@ CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m +# CONFIG_CRYPTO_SM4_GENERIC is not set CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_TWOFISH_COMMON=m @@ -10167,6 +10239,7 @@ CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=m CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set # # Certificates for signature checking @@ -10182,6 +10255,7 @@ CONFIG_SECONDARY_TRUSTED_KEYRING=y CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" # CONFIG_SYSTEM_REVOCATION_LIST is not set +# CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE is not set # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y @@ -10225,8 +10299,6 @@ CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_SM3=m -CONFIG_CRYPTO_LIB_SM4=m # end of Crypto library routines CONFIG_LIB_MEMNEQ=y @@ -10363,6 +10435,8 @@ CONFIG_SG_SPLIT=y CONFIG_SG_POOL=y CONFIG_MEMREGION=y CONFIG_ARCH_STACKWALK=y +CONFIG_STACKDEPOT=y +CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines @@ -10435,6 +10509,7 @@ CONFIG_HAVE_ARCH_KCSAN=y # # CONFIG_NET_DEV_REFCNT_TRACKER is not set # CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set # end of Networking Debugging # @@ -10442,7 +10517,10 @@ CONFIG_HAVE_ARCH_KCSAN=y # # CONFIG_PAGE_EXTENSION is not set # CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set # CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_TABLE_CHECK is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set # CONFIG_DEBUG_RODATA_TEST is not set @@ -10451,8 +10529,6 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -10544,6 +10620,7 @@ CONFIG_TORTURE_TEST=m CONFIG_RCU_TORTURE_TEST=m # CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 CONFIG_RCU_TRACE=y # CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging diff --git a/config/kernel/linux-media-edge.config b/config/kernel/linux-media-edge.config index d7cae7f46..0c34bcc25 100644 --- a/config/kernel/linux-media-edge.config +++ b/config/kernel/linux-media-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.19.3 Kernel Configuration +# Linux/arm64 6.0.0-rc7 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y @@ -13,7 +13,6 @@ CONFIG_LD_VERSION=23200 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=122 @@ -74,6 +73,8 @@ CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_TIME_KUNIT_TEST=m +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -172,6 +173,7 @@ CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y @@ -306,6 +308,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BCMBCA is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set @@ -320,6 +323,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_NPCM is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set @@ -373,6 +377,8 @@ CONFIG_ARM64_ERRATUM_2051678=y CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y CONFIG_ARM64_ERRATUM_2054223=y CONFIG_ARM64_ERRATUM_2067961=y +CONFIG_ARM64_ERRATUM_2441009=y +CONFIG_ARM64_ERRATUM_2457168=y CONFIG_CAVIUM_ERRATUM_22375=y CONFIG_CAVIUM_ERRATUM_23144=y CONFIG_CAVIUM_ERRATUM_23154=y @@ -480,7 +486,6 @@ CONFIG_ARM64_TLB_RANGE=y CONFIG_AS_HAS_ARMV8_5=y CONFIG_ARM64_BTI=y CONFIG_ARM64_E0PD=y -CONFIG_ARCH_RANDOM=y # end of ARMv8.5 architectural features # @@ -523,6 +528,7 @@ CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -556,7 +562,6 @@ CONFIG_DT_IDLE_GENPD=y # # ARM CPU Idle Drivers # -CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # end of ARM CPU Idle Drivers @@ -609,6 +614,7 @@ CONFIG_ACPI_SPCR_TABLE=y CONFIG_ACPI_AC=y CONFIG_ACPI_BATTERY=y CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_VIDEO=y CONFIG_ACPI_FAN=y # CONFIG_ACPI_TAD is not set CONFIG_ACPI_DOCK=y @@ -648,6 +654,7 @@ CONFIG_ACPI_PPTT=y CONFIG_ACPI_PCC=y CONFIG_PMIC_OPREGION=y CONFIG_ACPI_VIOT=y +CONFIG_ACPI_PRMT=y CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_HAVE_KVM=y CONFIG_HAVE_KVM_IRQCHIP=y @@ -678,6 +685,7 @@ CONFIG_CRYPTO_SM4_ARM64_CE=m # CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set # CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set CONFIG_CRYPTO_GHASH_ARM64_CE=y +# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y @@ -701,6 +709,7 @@ CONFIG_JUMP_LABEL=y CONFIG_UPROBES=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_KRETPROBES=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y @@ -747,7 +756,7 @@ CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_ARCH_SUPPORTS_CFI_CLANG=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y @@ -788,6 +797,7 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y # # GCOV-based kernel profiling @@ -992,9 +1002,11 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y # CONFIG_HWPOISON_INJECT is not set +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_TRANSPARENT_HUGEPAGE=y # CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y @@ -1012,11 +1024,11 @@ CONFIG_PAGE_IDLE_FLAG=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y -CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y +CONFIG_GET_FREE_REGION=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PERCPU_STATS=y # CONFIG_GUP_TEST is not set @@ -1035,6 +1047,7 @@ CONFIG_DAMON_PADDR=y # CONFIG_DAMON_SYSFS is not set # CONFIG_DAMON_DBGFS is not set CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_LRU_SORT=y # end of Data Access Monitoring # end of Memory Management options @@ -1259,6 +1272,7 @@ CONFIG_NFT_FIB_NETDEV=m CONFIG_NFT_REJECT_NETDEV=m CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m +CONFIG_NF_FLOW_TABLE_PROCFS=y CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XTABLES_COMPAT=y @@ -1601,6 +1615,7 @@ CONFIG_NET_DSA_TAG_OCELOT_8021Q=m CONFIG_NET_DSA_TAG_QCA=m CONFIG_NET_DSA_TAG_RTL4_A=m CONFIG_NET_DSA_TAG_RTL8_4=m +CONFIG_NET_DSA_TAG_RZN1_A5PSW=m CONFIG_NET_DSA_TAG_LAN9303=m CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m @@ -1818,70 +1833,6 @@ CONFIG_CAN_BCM=m CONFIG_CAN_GW=m CONFIG_CAN_J1939=m # CONFIG_CAN_ISOTP is not set - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=m -CONFIG_CAN_VXCAN=m -CONFIG_CAN_SLCAN=m -CONFIG_CAN_DEV=m -CONFIG_CAN_CALC_BITTIMING=y -# CONFIG_CAN_FLEXCAN is not set -CONFIG_CAN_GRCAN=m -CONFIG_CAN_KVASER_PCIEFD=m -CONFIG_CAN_XILINXCAN=m -CONFIG_CAN_C_CAN=m -CONFIG_CAN_C_CAN_PLATFORM=m -CONFIG_CAN_C_CAN_PCI=m -CONFIG_CAN_CC770=m -CONFIG_CAN_CC770_ISA=m -CONFIG_CAN_CC770_PLATFORM=m -# CONFIG_CAN_CTUCANFD_PCI is not set -# CONFIG_CAN_CTUCANFD_PLATFORM is not set -# CONFIG_CAN_IFI_CANFD is not set -CONFIG_CAN_M_CAN=m -CONFIG_CAN_M_CAN_PCI=m -CONFIG_CAN_M_CAN_PLATFORM=m -CONFIG_CAN_M_CAN_TCAN4X5X=m -CONFIG_CAN_PEAK_PCIEFD=m -CONFIG_CAN_SJA1000=m -CONFIG_CAN_EMS_PCI=m -CONFIG_CAN_F81601=m -CONFIG_CAN_KVASER_PCI=m -CONFIG_CAN_PEAK_PCI=m -CONFIG_CAN_PEAK_PCIEC=y -CONFIG_CAN_PLX_PCI=m -CONFIG_CAN_SJA1000_ISA=m -CONFIG_CAN_SJA1000_PLATFORM=m -CONFIG_CAN_SOFTING=m - -# -# CAN SPI interfaces -# -CONFIG_CAN_HI311X=m -CONFIG_CAN_MCP251X=m -CONFIG_CAN_MCP251XFD=m -# CONFIG_CAN_MCP251XFD_SANITY is not set -# end of CAN SPI interfaces - -# -# CAN USB interfaces -# -CONFIG_CAN_8DEV_USB=m -CONFIG_CAN_EMS_USB=m -CONFIG_CAN_ESD_USB2=m -CONFIG_CAN_ETAS_ES58X=m -CONFIG_CAN_GS_USB=m -CONFIG_CAN_KVASER_USB=m -CONFIG_CAN_MCBA_USB=m -CONFIG_CAN_PEAK_USB=m -CONFIG_CAN_UCAN=m -# end of CAN USB interfaces - -# CONFIG_CAN_DEBUG_DEVICES is not set -# end of CAN Device Drivers - CONFIG_BT=m CONFIG_BT_BREDR=y CONFIG_BT_RFCOMM=m @@ -2093,6 +2044,7 @@ CONFIG_PCI_QUIRKS=y CONFIG_PCI_STUB=y # CONFIG_PCI_PF_STUB is not set CONFIG_PCI_ATS=y +CONFIG_PCI_DOE=y CONFIG_PCI_ECAM=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y @@ -2187,6 +2139,7 @@ CONFIG_CXL_ACPI=m CONFIG_CXL_MEM=m CONFIG_CXL_PORT=m CONFIG_CXL_SUSPEND=y +CONFIG_CXL_REGION=y # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set @@ -2285,6 +2238,7 @@ CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set CONFIG_ARM_SCMI_POWER_DOMAIN=y +CONFIG_ARM_SCMI_POWER_CONTROL=m # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=y @@ -2549,7 +2503,6 @@ CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 CONFIG_BLK_DEV_DRBD=m # CONFIG_DRBD_FAULT_INJECTION is not set CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_SX8=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 @@ -2559,10 +2512,12 @@ CONFIG_XEN_BLKDEV_FRONTEND=m CONFIG_XEN_BLKDEV_BACKEND=m CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_UBLK=m # # NVME Support # +CONFIG_NVME_COMMON=y CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y CONFIG_NVME_MULTIPATH=y @@ -2571,12 +2526,14 @@ CONFIG_NVME_HWMON=y CONFIG_NVME_FABRICS=m CONFIG_NVME_FC=m CONFIG_NVME_TCP=m +CONFIG_NVME_AUTH=y CONFIG_NVME_TARGET=m CONFIG_NVME_TARGET_PASSTHRU=y CONFIG_NVME_TARGET_LOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_TCP=m +CONFIG_NVME_TARGET_AUTH=y # end of NVME Support # @@ -2609,6 +2566,7 @@ CONFIG_XILINX_SDFEC=m CONFIG_MISC_RTSX=m # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +CONFIG_VCPU_STALL_DETECTOR=m # CONFIG_C2PORT is not set # @@ -2725,6 +2683,8 @@ CONFIG_SCSI_MPT3SAS_MAX_SGE=128 CONFIG_SCSI_MPI3MR=m # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_HPTIOP is not set +CONFIG_SCSI_BUSLOGIC=m +CONFIG_SCSI_FLASHPOINT=y # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set # CONFIG_XEN_SCSI_FRONTEND is not set @@ -3033,22 +2993,19 @@ CONFIG_NET_DSA_LANTIQ_GSWIP=m CONFIG_NET_DSA_MT7530=m CONFIG_NET_DSA_MV88E6060=m CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m -CONFIG_NET_DSA_MICROCHIP_KSZ9477=m CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m -CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m -CONFIG_NET_DSA_MICROCHIP_KSZ8795=m -CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m +CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m CONFIG_NET_DSA_MV88E6XXX=m # CONFIG_NET_DSA_MV88E6XXX_PTP is not set # CONFIG_NET_DSA_MSCC_SEVILLE is not set CONFIG_NET_DSA_AR9331=m +CONFIG_NET_DSA_QCA8K=m CONFIG_NET_DSA_SJA1105=m # CONFIG_NET_DSA_SJA1105_PTP is not set CONFIG_NET_DSA_XRS700X=m CONFIG_NET_DSA_XRS700X_I2C=m CONFIG_NET_DSA_XRS700X_MDIO=m -CONFIG_NET_DSA_QCA8K=m CONFIG_NET_DSA_REALTEK=m CONFIG_NET_DSA_REALTEK_MDIO=m CONFIG_NET_DSA_REALTEK_SMI=m @@ -3191,6 +3148,8 @@ CONFIG_I40EVF=m # CONFIG_ICE is not set CONFIG_FM10K=m # CONFIG_IGC is not set +CONFIG_NET_VENDOR_WANGXUN=y +# CONFIG_TXGBE is not set CONFIG_JME=m CONFIG_NET_VENDOR_LITEX=y CONFIG_LITEX_LITEETH=m @@ -3257,7 +3216,6 @@ CONFIG_NATSEMI=m CONFIG_NS83820=m CONFIG_NET_VENDOR_NETERION=y # CONFIG_S2IO is not set -# CONFIG_VXGE is not set CONFIG_NET_VENDOR_NETRONOME=y # CONFIG_NFP is not set CONFIG_NET_VENDOR_8390=y @@ -3373,6 +3331,7 @@ CONFIG_BCM7XXX_PHY=m CONFIG_BCM84881_PHY=m CONFIG_BCM87XX_PHY=m CONFIG_BCM_NET_PHYLIB=m +CONFIG_BCM_NET_PHYPTP=m CONFIG_CICADA_PHY=m # CONFIG_CORTINA_PHY is not set CONFIG_DAVICOM_PHY=m @@ -3410,6 +3369,67 @@ CONFIG_DP83TD510_PHY=m CONFIG_VITESSE_PHY=m # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_RX_OFFLOAD=y +# CONFIG_CAN_CAN327 is not set +# CONFIG_CAN_FLEXCAN is not set +CONFIG_CAN_GRCAN=m +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_XILINXCAN=m +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PLATFORM=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_CC770=m +CONFIG_CAN_CC770_ISA=m +CONFIG_CAN_CC770_PLATFORM=m +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +# CONFIG_CAN_IFI_CANFD is not set +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SOFTING=m + +# +# CAN SPI interfaces +# +CONFIG_CAN_HI311X=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +# CONFIG_CAN_MCP251XFD_SANITY is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y @@ -4212,7 +4232,6 @@ CONFIG_SERIAL_8250_NR_UARTS=8 CONFIG_SERIAL_8250_RUNTIME_UARTS=8 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set CONFIG_SERIAL_8250_RSA=y @@ -4313,6 +4332,7 @@ CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y # CONFIG_TCG_TIS is not set # CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C is not set CONFIG_TCG_TIS_I2C_CR50=m # CONFIG_TCG_TIS_I2C_ATMEL is not set CONFIG_TCG_TIS_I2C_INFINEON=y @@ -4470,6 +4490,7 @@ CONFIG_SPI_NXP_FLEXSPI=m CONFIG_SPI_GPIO=m CONFIG_SPI_FSL_LIB=m CONFIG_SPI_FSL_SPI=m +CONFIG_SPI_MICROCHIP_CORE=m CONFIG_SPI_OC_TINY=m CONFIG_SPI_PL022=y # CONFIG_SPI_PXA2XX is not set @@ -4593,7 +4614,6 @@ CONFIG_GPIO_LOGICVC=m CONFIG_GPIO_MB86S7X=m CONFIG_GPIO_PL061=y CONFIG_GPIO_ROCKCHIP=y -CONFIG_GPIO_SAMA5D2_PIOBU=m # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y CONFIG_GPIO_TEGRA=y @@ -4786,7 +4806,6 @@ CONFIG_HWMON_VID=m CONFIG_SENSORS_AD7314=m CONFIG_SENSORS_AD7414=m CONFIG_SENSORS_AD7418=m -CONFIG_SENSORS_ADM1021=m CONFIG_SENSORS_ADM1025=m CONFIG_SENSORS_ADM1026=m CONFIG_SENSORS_ADM1029=m @@ -4855,7 +4874,6 @@ CONFIG_SENSORS_MAX31730=m CONFIG_SENSORS_MAX6620=m CONFIG_SENSORS_MAX6621=m CONFIG_SENSORS_MAX6639=m -CONFIG_SENSORS_MAX6642=m CONFIG_SENSORS_MAX6650=m CONFIG_SENSORS_MAX6697=m CONFIG_SENSORS_MAX31790=m @@ -4914,6 +4932,7 @@ CONFIG_SENSORS_IRPS5401=m CONFIG_SENSORS_ISL68137=m CONFIG_SENSORS_LM25066=m # CONFIG_SENSORS_LM25066_REGULATOR is not set +CONFIG_SENSORS_LT7182S=m CONFIG_SENSORS_LTC2978=m CONFIG_SENSORS_LTC2978_REGULATOR=y CONFIG_SENSORS_LTC3815=m @@ -5520,7 +5539,6 @@ CONFIG_USB_PWC=m # CONFIG_USB_PWC_DEBUG is not set CONFIG_USB_PWC_INPUT_EVDEV=y CONFIG_USB_S2255=m -CONFIG_USB_STKWEBCAM=m CONFIG_VIDEO_USBTV=m CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y @@ -5866,6 +5884,7 @@ CONFIG_VIDEO_IR_I2C=m # CONFIG_VIDEO_APTINA_PLL=m CONFIG_VIDEO_CCS_PLL=m +# CONFIG_VIDEO_AR0521 is not set CONFIG_VIDEO_HI556=m CONFIG_VIDEO_HI846=m # CONFIG_VIDEO_HI847 is not set @@ -6285,6 +6304,7 @@ CONFIG_DVB_DUMMY_FE=m # # Graphics support # +CONFIG_APERTURE_HELPERS=y CONFIG_TEGRA_HOST1X_CONTEXT_BUS=y CONFIG_TEGRA_HOST1X=m CONFIG_TEGRA_HOST1X_FIREWALL=y @@ -6375,6 +6395,7 @@ CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_EDP=m +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m @@ -6471,6 +6492,7 @@ CONFIG_DRM_TOSHIBA_TC358764=m # CONFIG_DRM_TOSHIBA_TC358767 is not set CONFIG_DRM_TOSHIBA_TC358768=m # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set CONFIG_DRM_TI_SN65DSI83=m # CONFIG_DRM_TI_SN65DSI86 is not set @@ -6495,8 +6517,10 @@ CONFIG_DRM_ETNAVIV=m CONFIG_DRM_ETNAVIV_THERMAL=y CONFIG_DRM_HISI_HIBMC=m CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_LOGICVC=m CONFIG_DRM_MXS=y CONFIG_DRM_MXSFB=m +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set CONFIG_DRM_BOCHS=m # CONFIG_DRM_CIRRUS_QEMU is not set @@ -6678,7 +6702,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +CONFIG_SND_CTL_INPUT_VALIDATION=y CONFIG_SND_VMASTER=y CONFIG_SND_CTL_LED=m CONFIG_SND_SEQUENCER=m @@ -6787,6 +6813,7 @@ CONFIG_SND_HDA_INPUT_BEEP=y CONFIG_SND_HDA_INPUT_BEEP_MODE=1 CONFIG_SND_HDA_PATCH_LOADER=y CONFIG_SND_HDA_SCODEC_CS35L41=m +CONFIG_SND_HDA_CS_DSP_CONTROLS=m CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m CONFIG_SND_HDA_CODEC_REALTEK=m @@ -6835,12 +6862,14 @@ CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_COMPRESS=y CONFIG_SND_SOC_UTILS_KUNIT_TEST=m +CONFIG_SND_SOC_ACPI=m CONFIG_SND_SOC_ADI=m CONFIG_SND_SOC_ADI_AXI_I2S=m CONFIG_SND_SOC_ADI_AXI_SPDIF=m CONFIG_SND_SOC_AMD_ACP=m CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m # CONFIG_SND_AMD_ACP_CONFIG is not set CONFIG_SND_ATMEL_SOC=m CONFIG_SND_SOC_MIKROE_PROTO=m @@ -6865,6 +6894,7 @@ CONFIG_SND_SOC_FSL_ESAI=m CONFIG_SND_SOC_FSL_MICFIL=m CONFIG_SND_SOC_FSL_EASRC=m CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_UTILS=m CONFIG_SND_SOC_FSL_RPMSG=m CONFIG_SND_SOC_IMX_AUDMUX=m # end of SoC Audio for Freescale CPUs @@ -6909,6 +6939,7 @@ CONFIG_SND_SOC_TEGRA30_I2S=m CONFIG_SND_SOC_TEGRA210_AHUB=m CONFIG_SND_SOC_TEGRA210_DMIC=m CONFIG_SND_SOC_TEGRA210_I2S=m +CONFIG_SND_SOC_TEGRA210_OPE=m CONFIG_SND_SOC_TEGRA186_ASRC=m CONFIG_SND_SOC_TEGRA186_DSPK=m CONFIG_SND_SOC_TEGRA210_ADMAIF=m @@ -7054,6 +7085,7 @@ CONFIG_SND_SOC_ES8328_SPI=m CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_HDAC_HDMI=m CONFIG_SND_SOC_HDAC_HDA=m +CONFIG_SND_SOC_HDA=m CONFIG_SND_SOC_ICS43432=m CONFIG_SND_SOC_INNO_RK3036=m CONFIG_SND_SOC_ISABELLE=m @@ -7167,6 +7199,7 @@ CONFIG_SND_SOC_TAS2552=m CONFIG_SND_SOC_TAS2562=m CONFIG_SND_SOC_TAS2764=m CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m CONFIG_SND_SOC_TAS5086=m CONFIG_SND_SOC_TAS571X=m CONFIG_SND_SOC_TAS5720=m @@ -7260,6 +7293,7 @@ CONFIG_SND_SOC_WM9705=m CONFIG_SND_SOC_WM9712=m CONFIG_SND_SOC_WM9713=m CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m CONFIG_SND_SOC_ZL38060=m CONFIG_SND_SOC_LM4857=m CONFIG_SND_SOC_MAX9759=m @@ -7445,6 +7479,7 @@ CONFIG_USB_HIDDEV=y # CONFIG_I2C_HID_ACPI=m CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m CONFIG_I2C_HID_OF_GOODIX=m # end of I2C HID support @@ -7703,6 +7738,7 @@ CONFIG_USB_HSIC_USB3503=y CONFIG_USB_HSIC_USB4604=m CONFIG_USB_LINK_LAYER_TEST=m CONFIG_USB_CHAOSKEY=m +CONFIG_USB_ONBOARD_HUB=m CONFIG_USB_ATM=m CONFIG_USB_SPEEDTOUCH=m CONFIG_USB_CXACRU=m @@ -7843,7 +7879,9 @@ CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_UCSI=m CONFIG_UCSI_CCG=m CONFIG_UCSI_ACPI=m +CONFIG_UCSI_STM32G0=m CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_ANX7411=m CONFIG_TYPEC_RT1719=m CONFIG_TYPEC_HD3SS3220=m CONFIG_TYPEC_STUSB160X=m @@ -7886,6 +7924,7 @@ CONFIG_MMC_SDHCI_ACPI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y CONFIG_MMC_SDHCI_OF_ASPEED=m +CONFIG_MMC_SDHCI_OF_ASPEED_TEST=y CONFIG_MMC_SDHCI_OF_AT91=m CONFIG_MMC_SDHCI_OF_DWCMSHC=m CONFIG_MMC_SDHCI_CADENCE=y @@ -8069,6 +8108,7 @@ CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_HYM8563=y # CONFIG_RTC_DRV_MAX6900 is not set CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_NCT3018Y=m CONFIG_RTC_DRV_RK808=y # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set @@ -8255,7 +8295,6 @@ CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI_LIB=y CONFIG_VIRTIO_PCI_LIB_LEGACY=y CONFIG_VIRTIO_MENU=y -# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_PCI_LEGACY=y CONFIG_VIRTIO_VDPA=m @@ -8395,20 +8434,21 @@ CONFIG_SERIO_NVEC_PS2=m CONFIG_NVEC_POWER=m CONFIG_NVEC_PAZ00=m CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_HANTRO_ROCKCHIP=y -# CONFIG_VIDEO_MAX96712 is not set -CONFIG_VIDEO_ROCKCHIP_VDEC=m -CONFIG_VIDEO_ZORAN=m -# CONFIG_VIDEO_ZORAN_DC30 is not set -# CONFIG_VIDEO_ZORAN_ZR36060 is not set -CONFIG_VIDEO_TEGRA=m -CONFIG_VIDEO_TEGRA_TPG=y CONFIG_DVB_AV7110_IR=y CONFIG_DVB_AV7110=m CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_PATCH=m CONFIG_DVB_SP8870=m +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_HANTRO_ROCKCHIP=y +# CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_ROCKCHIP_VDEC=m +CONFIG_VIDEO_STKWEBCAM=m +CONFIG_VIDEO_TEGRA=m +CONFIG_VIDEO_TEGRA_TPG=y +CONFIG_VIDEO_ZORAN=m +# CONFIG_VIDEO_ZORAN_DC30 is not set +# CONFIG_VIDEO_ZORAN_ZR36060 is not set # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set CONFIG_COMMON_CLK_XLNX_CLKWZRD=m @@ -8454,10 +8494,7 @@ CONFIG_HMS_ANYBUSS_BUS=m # CONFIG_ARCX_ANYBUS_CONTROLLER is not set # CONFIG_HMS_PROFINET is not set # CONFIG_QLGE is not set - -# -# VME Device Drivers -# +# CONFIG_VME_BUS is not set # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y CONFIG_CHROMEOS_ACPI=m @@ -8477,6 +8514,7 @@ CONFIG_CROS_EC_SYSFS=y CONFIG_CROS_EC_TYPEC=m CONFIG_CROS_USBPD_NOTIFY=y # CONFIG_CHROMEOS_PRIVACY_SCREEN is not set +# CONFIG_CROS_KUNIT is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_SURFACE_PLATFORMS=y # CONFIG_SURFACE_3_POWER_OPREGION is not set @@ -8541,6 +8579,7 @@ CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_MMIO=y CONFIG_ROCKCHIP_TIMER=y CONFIG_TEGRA_TIMER=y +CONFIG_TEGRA186_TIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y @@ -8640,6 +8679,12 @@ CONFIG_SOC_BRCMSTB=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# CONFIG_A64FX_DIAG is not set +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -9200,6 +9245,8 @@ CONFIG_HID_SENSOR_INCLINOMETER_3D=m CONFIG_HID_SENSOR_DEVICE_ROTATION=m # end of Inclinometer sensors +CONFIG_IIO_FORMAT_KUNIT_TEST=m + # # Triggers - standalone # @@ -9313,11 +9360,11 @@ CONFIG_MAX31865=m # end of Temperature sensors # CONFIG_NTB is not set -# CONFIG_VME_BUS is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_CLK=m CONFIG_PWM_CROS_EC=m CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set @@ -9348,7 +9395,9 @@ CONFIG_PARTITION_PERCPU=y CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SCMI=y +CONFIG_RESET_SIMPLE=y # CONFIG_RESET_TI_SYSCON is not set +CONFIG_RESET_TI_TPS380X=m CONFIG_RESET_TEGRA_BPMP=y # @@ -9415,6 +9464,7 @@ CONFIG_ARM_SMMU_V3_PMU=m CONFIG_ARM_DMC620_PMU=m CONFIG_HISI_PMU=y # CONFIG_HISI_PCIE_PMU is not set +CONFIG_HNS3_PMU=m # end of Performance monitor support CONFIG_RAS=y @@ -9423,7 +9473,7 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_LIBNVDIMM is not set @@ -9459,6 +9509,7 @@ CONFIG_ALTERA_FREEZE_BRIDGE=m CONFIG_FPGA_REGION=m CONFIG_OF_FPGA_REGION=m # CONFIG_FPGA_DFL is not set +CONFIG_FPGA_MGR_MICROCHIP_SPI=m # CONFIG_FSI is not set CONFIG_TEE=y CONFIG_OPTEE=y @@ -9768,27 +9819,6 @@ CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y # CONFIG_EROFS_FS_ZIP is not set -CONFIG_AUFS_FS=m -CONFIG_AUFS_BRANCH_MAX_127=y -# CONFIG_AUFS_BRANCH_MAX_511 is not set -# CONFIG_AUFS_BRANCH_MAX_1023 is not set -# CONFIG_AUFS_BRANCH_MAX_32767 is not set -CONFIG_AUFS_SBILIST=y -CONFIG_AUFS_HNOTIFY=y -CONFIG_AUFS_HFSNOTIFY=y -CONFIG_AUFS_EXPORT=y -CONFIG_AUFS_INO_T_64=y -CONFIG_AUFS_XATTR=y -CONFIG_AUFS_FHSM=y -CONFIG_AUFS_RDU=y -CONFIG_AUFS_DIRREN=y -CONFIG_AUFS_SHWH=y -CONFIG_AUFS_BR_RAMFS=y -CONFIG_AUFS_BR_FUSE=y -CONFIG_AUFS_POLL=y -CONFIG_AUFS_BR_HFSPLUS=y -CONFIG_AUFS_BDEV_LOOP=y -# CONFIG_AUFS_DEBUG is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V2=m @@ -9914,6 +9944,7 @@ CONFIG_NLS_MAC_ROMANIAN=m CONFIG_NLS_MAC_TURKISH=m CONFIG_NLS_UTF8=m CONFIG_DLM=m +CONFIG_DLM_DEPRECATED_API=y # CONFIG_DLM_DEBUG is not set CONFIG_UNICODE=y # CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set @@ -9963,9 +9994,12 @@ CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init" CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/sbin/init" # CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING is not set CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y CONFIG_SECURITY_APPARMOR_HASH=y CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y -# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y # CONFIG_SECURITY_LOADPIN is not set CONFIG_SECURITY_YAMA=y CONFIG_SECURITY_SAFESETID=y @@ -10090,7 +10124,7 @@ CONFIG_CRYPTO_ENGINE=m # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y -# CONFIG_CRYPTO_DH_RFC7919_GROUPS is not set +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=m @@ -10124,6 +10158,7 @@ CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_KEYWRAP=m CONFIG_CRYPTO_NHPOLY1305=y CONFIG_CRYPTO_ADIANTUM=m +# CONFIG_CRYPTO_HCTR2 is not set CONFIG_CRYPTO_ESSIV=m # @@ -10176,6 +10211,7 @@ CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_ARIA is not set CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m # CONFIG_CRYPTO_SM4_GENERIC is not set @@ -10218,6 +10254,13 @@ CONFIG_CRYPTO_DEV_ATMEL_I2C=m CONFIG_CRYPTO_DEV_ATMEL_ECC=m CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m # CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set CONFIG_CRYPTO_DEV_NITROX=m CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m @@ -10280,6 +10323,7 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y CONFIG_INDIRECT_PIO=y +# CONFIG_TRACE_MMIO_ACCESS is not set # # Crypto library routines @@ -10298,6 +10342,7 @@ CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -10436,12 +10481,13 @@ CONFIG_SG_POOL=y CONFIG_MEMREGION=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines +CONFIG_GENERIC_IOREMAP=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_ASN1_ENCODER=y +CONFIG_POLYNOMIAL=m # # Kernel hacking @@ -10529,6 +10575,7 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -10674,6 +10721,7 @@ CONFIG_PROBE_EVENTS=y # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set # CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_RV is not set # CONFIG_SAMPLES is not set CONFIG_STRICT_DEVMEM=y # CONFIG_IO_STRICT_DEVMEM is not set @@ -10701,6 +10749,7 @@ CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set +# CONFIG_CPUMASK_KUNIT_TEST is not set # CONFIG_TEST_LIST_SORT is not set CONFIG_TEST_MIN_HEAP=m # CONFIG_TEST_SORT is not set diff --git a/config/sources/families/media.conf b/config/sources/families/media.conf index fe5e96c60..c79d1a093 100644 --- a/config/sources/families/media.conf +++ b/config/sources/families/media.conf @@ -69,7 +69,7 @@ case $BRANCH in current) - KERNELBRANCH="branch:linux-5.18.y" + KERNELBRANCH="branch:linux-5.19.y" LINUXCONFIG='linux-media-'$BRANCH if [[ $BOARD == station-p2 || $BOARD == station-m2 || $BOARD == quartz64a || $BOARD == bananapir2pro ]]; then @@ -86,8 +86,8 @@ case $BRANCH in ;; edge) + KERNELBRANCH="tag:v6.0" KERNELPATCHDIR='media-'$BRANCH - KERNELBRANCH='branch:linux-5.19.y' LINUXFAMILY=media LINUXCONFIG='linux-media-'$BRANCH diff --git a/packages/bsp/common/usr/lib/armbian/armbian-hardware-optimization b/packages/bsp/common/usr/lib/armbian/armbian-hardware-optimization index ed7e90705..ebfcd13b9 100755 --- a/packages/bsp/common/usr/lib/armbian/armbian-hardware-optimization +++ b/packages/bsp/common/usr/lib/armbian/armbian-hardware-optimization @@ -208,7 +208,7 @@ prepare_board() { echo 32768 >/proc/sys/net/core/rps_sock_flow_entries echo 32768 >/sys/class/net/eth0/queues/rx-0/rps_flow_cnt ;; - rk3399) + rk3399|media) for i in $(awk -F':' '/gpu/{print $1}' /proc/irq/$i/smp_affinity done diff --git a/patch/kernel/archive/media-5.18/050-linux-1001-v4l2-rockchip.patch b/patch/kernel/archive/media-5.18/050-linux-1001-v4l2-rockchip.patch deleted file mode 100644 index 858d62224..000000000 --- a/patch/kernel/archive/media-5.18/050-linux-1001-v4l2-rockchip.patch +++ /dev/null @@ -1,1044 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 10:18:16 +0000 -Subject: [PATCH] WIP: media: rkvdec: continue to gate clock when decoding - finish - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index bd106b23f4a0..5d1d50e4fd57 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1021,7 +1021,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - state = (status & RKVDEC_RDY_STA) ? - VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; - -- writel(0, rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); - if (cancel_delayed_work(&rkvdec->watchdog_work)) { - struct rkvdec_ctx *ctx; - -@@ -1042,7 +1043,8 @@ static void rkvdec_watchdog_func(struct work_struct *work) - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - if (ctx) { - dev_err(rkvdec->dev, "Frame processing timed out!\n"); -- writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); - writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); - rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); - } - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 10:16:01 +0000 -Subject: [PATCH] WIP: media: rkvdec: pm runtime dont use autosuspend before - disable and cleanup - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 5d1d50e4fd57..18f36e8546d9 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1138,9 +1138,9 @@ static int rkvdec_remove(struct platform_device *pdev) - { - struct rkvdec_dev *rkvdec = platform_get_drvdata(pdev); - -- rkvdec_v4l2_cleanup(rkvdec); -- pm_runtime_disable(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); -+ rkvdec_v4l2_cleanup(rkvdec); - return 0; - } - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 11:23:04 +0000 -Subject: [PATCH] WIP: media: rkvdec: h264: return early when no reference - pictures - -NOTE: also change from a switch statement to access reflists from a pointer array, -should simplify once we add support for field reference list - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 18 +++++------------- - 1 file changed, 5 insertions(+), 13 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index c9a551dbd9bc..6ce11b736363 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -734,6 +734,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - const struct v4l2_ctrl_h264_sps *sps = run->sps; - struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; - u32 max_frame_num = 1 << (sps->log2_max_frame_num_minus4 + 4); -+ u8 *reflists[3] = { h264_ctx->reflists.p, h264_ctx->reflists.b0, h264_ctx->reflists.b1 }; - - u32 *hw_rps = priv_tbl->rps; - u32 i, j; -@@ -741,6 +742,9 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - memset(hw_rps, 0, sizeof(priv_tbl->rps)); - -+ if (!h264_ctx->reflists.num_valid) -+ return; -+ - /* - * Assign an invalid pic_num if DPB entry at that position is inactive. - * If we assign 0 in that position hardware will treat that as a real -@@ -763,19 +767,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { - for (i = 0; i < h264_ctx->reflists.num_valid; i++) { - bool dpb_valid = run->ref_buf_idx[i] >= 0; -- u8 idx = 0; -- -- switch (j) { -- case 0: -- idx = h264_ctx->reflists.p[i]; -- break; -- case 1: -- idx = h264_ctx->reflists.b0[i]; -- break; -- case 2: -- idx = h264_ctx->reflists.b1[i]; -- break; -- } -+ u8 idx = reflists[j][i]; - - if (idx >= ARRAY_SIZE(dec_params->dpb)) - continue; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 14:42:27 +0000 -Subject: [PATCH] WIP: media: rkvdec: h264: add field decoding support - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 79 ++++++++++++++++++---- - 1 file changed, 64 insertions(+), 15 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 6ce11b736363..9c3f08c94800 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -737,7 +737,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - u8 *reflists[3] = { h264_ctx->reflists.p, h264_ctx->reflists.b0, h264_ctx->reflists.b1 }; - - u32 *hw_rps = priv_tbl->rps; -- u32 i, j; -+ u32 i, j, k; - u16 *p = (u16 *)hw_rps; - - memset(hw_rps, 0, sizeof(priv_tbl->rps)); -@@ -764,16 +764,69 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - p[i] = dpb[i].frame_num - max_frame_num; - } - -- for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { -- for (i = 0; i < h264_ctx->reflists.num_valid; i++) { -- bool dpb_valid = run->ref_buf_idx[i] >= 0; -- u8 idx = reflists[j][i]; -+ if (!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) { -+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { -+ for (i = 0; i < h264_ctx->reflists.num_valid; i++) { -+ bool dpb_valid = run->ref_buf_idx[i] >= 0; -+ u8 idx = reflists[j][i]; - -- if (idx >= ARRAY_SIZE(dec_params->dpb)) -- continue; -+ if (idx >= ARRAY_SIZE(dec_params->dpb)) -+ continue; - -- set_ps_field(hw_rps, DPB_INFO(i, j), -- idx | dpb_valid << 4); -+ set_ps_field(hw_rps, DPB_INFO(i, j), -+ idx | dpb_valid << 4); -+ } -+ } -+ return; -+ } -+ -+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { -+ enum v4l2_h264_field_reference a_parity = -+ (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) -+ ? V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF; -+ enum v4l2_h264_field_reference b_parity = -+ (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) -+ ? V4L2_H264_TOP_FIELD_REF : V4L2_H264_BOTTOM_FIELD_REF; -+ u32 flags = V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM; -+ i = 0; -+ -+ for (k = 0; k < 2; k++) { -+ u8 a = 0; -+ u8 b = 0; -+ u32 long_term = k ? V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM : 0; -+ -+ while (a < h264_ctx->reflists.num_valid || b < h264_ctx->reflists.num_valid) { -+ for (; a < h264_ctx->reflists.num_valid; a++) { -+ u8 idx = reflists[j][a]; -+ if (idx >= ARRAY_SIZE(dec_params->dpb)) -+ continue; -+ if ((dpb[idx].reference & a_parity) == a_parity && -+ (dpb[idx].flags & flags) == long_term) { -+ set_ps_field(hw_rps, DPB_INFO(i, j), -+ idx | (1 << 4)); -+ set_ps_field(hw_rps, BOTTOM_FLAG(i, j), -+ a_parity == V4L2_H264_BOTTOM_FIELD_REF); -+ i++; -+ a++; -+ break; -+ } -+ } -+ for (; b < h264_ctx->reflists.num_valid; b++) { -+ u8 idx = reflists[j][b]; -+ if (idx >= ARRAY_SIZE(dec_params->dpb)) -+ continue; -+ if ((dpb[idx].reference & b_parity) == b_parity && -+ (dpb[idx].flags & flags) == long_term) { -+ set_ps_field(hw_rps, DPB_INFO(i, j), -+ idx | (1 << 4)); -+ set_ps_field(hw_rps, BOTTOM_FLAG(i, j), -+ b_parity == V4L2_H264_BOTTOM_FIELD_REF); -+ i++; -+ b++; -+ break; -+ } -+ } -+ } - } - } - } -@@ -968,10 +1021,6 @@ static void config_registers(struct rkvdec_ctx *ctx, - rkvdec->regs + RKVDEC_REG_H264_BASE_REFER15); - } - -- /* -- * Since support frame mode only -- * top_field_order_cnt is the same as bottom_field_order_cnt -- */ - reg = RKVDEC_CUR_POC(dec_params->top_field_order_cnt); - writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 29 Oct 2019 01:26:02 +0000 -Subject: [PATCH] RFC: media: hantro: Fix H264 decoding of field encoded - content - -This still need code cleanup and formatting - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/hantro/hantro_h264.c | 91 ++++++++++++++++------ - 1 file changed, 69 insertions(+), 22 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index 0b4d2491be3b..7b56a68c176c 100644 ---- a/drivers/staging/media/hantro/hantro_h264.c -+++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -227,30 +227,67 @@ static void prepare_table(struct hantro_ctx *ctx) - { - const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; - const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; -+ const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; - struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; - const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; - u32 dpb_longterm = 0; - u32 dpb_valid = 0; - int i; - -- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { -- tbl->poc[i * 2] = dpb[i].top_field_order_cnt; -- tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; -+ /* -+ * Set up bit maps of valid and long term DPBs. -+ * NOTE: The bits are reversed, i.e. MSb is DPB 0. -+ */ -+ if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) || (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) { -+ for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) { -+ // check for correct reference use -+ enum v4l2_h264_field_reference parity = (i & 0x1) ? -+ V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF; -+ if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE && -+ dpb[i / 2].reference & parity) -+ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i); -+ -+ if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -+ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i); -+ } - -- /* -- * Set up bit maps of valid and long term DPBs. -- * NOTE: The bits are reversed, i.e. MSb is DPB 0. -- */ -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) -- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -+ ctx->h264_dec.dpb_valid = dpb_valid; -+ ctx->h264_dec.dpb_longterm = dpb_longterm; -+ } else { -+ for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) -+ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -+ -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -+ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -+ } -+ -+ ctx->h264_dec.dpb_valid = dpb_valid << 16; -+ ctx->h264_dec.dpb_longterm = dpb_longterm << 16; - } -- ctx->h264_dec.dpb_valid = dpb_valid << 16; -- ctx->h264_dec.dpb_longterm = dpb_longterm << 16; - -- tbl->poc[32] = dec_param->top_field_order_cnt; -- tbl->poc[33] = dec_param->bottom_field_order_cnt; -+ for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) { -+ tbl->poc[i * 2] = dpb[i].top_field_order_cnt; -+ tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; -+ } else { -+ tbl->poc[i * 2] = 0; -+ tbl->poc[i * 2 + 1] = 0; -+ } -+ } -+ -+ if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) || !(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) { -+ if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) -+ tbl->poc[32] = (dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) ? -+ dec_param->bottom_field_order_cnt : -+ dec_param->top_field_order_cnt; -+ else -+ tbl->poc[32] = min(dec_param->top_field_order_cnt, dec_param->bottom_field_order_cnt); -+ tbl->poc[33] = 0; -+ } else { -+ tbl->poc[32] = dec_param->top_field_order_cnt; -+ tbl->poc[33] = dec_param->bottom_field_order_cnt; -+ }; - - assemble_scaling_list(ctx); - } -@@ -258,8 +295,7 @@ static void prepare_table(struct hantro_ctx *ctx) - static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a, - const struct v4l2_h264_dpb_entry *b) - { -- return a->top_field_order_cnt == b->top_field_order_cnt && -- a->bottom_field_order_cnt == b->bottom_field_order_cnt; -+ return a->reference_ts == b->reference_ts; - } - - static void update_dpb(struct hantro_ctx *ctx) -@@ -273,13 +309,13 @@ static void update_dpb(struct hantro_ctx *ctx) - - /* Disable all entries by default. */ - for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) -- ctx->h264_dec.dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; -+ ctx->h264_dec.dpb[i].flags = 0; - - /* Try to match new DPB entries with existing ones by their POCs. */ - for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) { - const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i]; - -- if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) - continue; - - /* -@@ -290,8 +326,7 @@ static void update_dpb(struct hantro_ctx *ctx) - struct v4l2_h264_dpb_entry *cdpb; - - cdpb = &ctx->h264_dec.dpb[j]; -- if (cdpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE || -- !dpb_entry_match(cdpb, ndpb)) -+ if (!dpb_entry_match(cdpb, ndpb)) - continue; - - *cdpb = *ndpb; -@@ -327,7 +362,10 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, - unsigned int dpb_idx) - { - struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; -+ const struct v4l2_ctrl_h264_decode_params *dec_param = ctx->h264_dec.ctrls.decode; - dma_addr_t dma_addr = 0; -+ s32 cur_poc; -+ u32 flags; - - if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) - dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts); -@@ -345,7 +383,16 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, - dma_addr = hantro_get_dec_buf_addr(ctx, buf); - } - -- return dma_addr; -+ cur_poc = dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD ? -+ dec_param->bottom_field_order_cnt : -+ dec_param->top_field_order_cnt; -+ flags = dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD ? 0x2 : 0; -+ flags |= abs(dpb[dpb_idx].top_field_order_cnt - cur_poc) < -+ abs(dpb[dpb_idx].bottom_field_order_cnt - cur_poc) ? -+ 0x1 : 0; -+ -+ return dma_addr | flags; -+ - } - - u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Oct 2020 13:27:12 +0200 -Subject: [PATCH] media: hantro: adapt to match 5.11 H.264 uapi changes - -Signed-off-by: Alex Bee ---- - drivers/staging/media/hantro/hantro_h264.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index 7b56a68c176c..befa69d5c855 100644 ---- a/drivers/staging/media/hantro/hantro_h264.c -+++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -241,10 +241,10 @@ static void prepare_table(struct hantro_ctx *ctx) - if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) || (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) { - for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) { - // check for correct reference use -- enum v4l2_h264_field_reference parity = (i & 0x1) ? -+ u8 parity = (i & 0x1) ? - V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF; - if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE && -- dpb[i / 2].reference & parity) -+ dpb[i / 2].fields & parity) - dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i); - - if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Oct 2020 13:42:01 +0200 -Subject: [PATCH] media: rkvdec: adapt to match 5.11 H.264 uapi changes - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 9c3f08c94800..7238117b6cf4 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -783,10 +783,10 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - } - - for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { -- enum v4l2_h264_field_reference a_parity = -+ u8 a_parity = - (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) - ? V4L2_H264_BOTTOM_FIELD_REF : V4L2_H264_TOP_FIELD_REF; -- enum v4l2_h264_field_reference b_parity = -+ u8 b_parity = - (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) - ? V4L2_H264_TOP_FIELD_REF : V4L2_H264_BOTTOM_FIELD_REF; - u32 flags = V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM; -@@ -802,7 +802,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - u8 idx = reflists[j][a]; - if (idx >= ARRAY_SIZE(dec_params->dpb)) - continue; -- if ((dpb[idx].reference & a_parity) == a_parity && -+ if ((dpb[idx].fields & a_parity) == a_parity && - (dpb[idx].flags & flags) == long_term) { - set_ps_field(hw_rps, DPB_INFO(i, j), - idx | (1 << 4)); -@@ -817,7 +817,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - u8 idx = reflists[j][b]; - if (idx >= ARRAY_SIZE(dec_params->dpb)) - continue; -- if ((dpb[idx].reference & b_parity) == b_parity && -+ if ((dpb[idx].fields & b_parity) == b_parity && - (dpb[idx].flags & flags) == long_term) { - set_ps_field(hw_rps, DPB_INFO(i, j), - idx | (1 << 4)); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Randy Li -Date: Sun, 6 Jan 2019 01:48:37 +0800 -Subject: [PATCH] soc: rockchip: power-domain: export idle request - -We need to put the power status of HEVC IP into IDLE unless -we can't reset that IP or the SoC would crash down. -rockchip_pmu_idle_request(dev, true)---> enter idle -rockchip_pmu_idle_request(dev, false)---> exit idle - -Signed-off-by: Caesar Wang -Signed-off-by: Jeffy Chen -Signed-off-by: Randy Li ---- - drivers/soc/rockchip/pm_domains.c | 23 +++++++++++++++++++++++ - include/linux/rockchip_pmu.h | 15 +++++++++++++++ - include/soc/rockchip/pm_domains.h | 18 ++++++++++++++++++ - 3 files changed, 56 insertions(+) - create mode 100644 include/linux/rockchip_pmu.h - create mode 100644 include/soc/rockchip/pm_domains.h - -diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c -index 0868b7d406fb..fddb4022c376 100644 ---- a/drivers/soc/rockchip/pm_domains.c -+++ b/drivers/soc/rockchip/pm_domains.c -@@ -204,6 +204,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, - return 0; - } - -+int rockchip_pmu_idle_request(struct device *dev, bool idle) -+{ -+ struct generic_pm_domain *genpd; -+ struct rockchip_pm_domain *pd; -+ int ret; -+ -+ if (IS_ERR_OR_NULL(dev)) -+ return -EINVAL; -+ -+ if (IS_ERR_OR_NULL(dev->pm_domain)) -+ return -EINVAL; -+ -+ genpd = pd_to_genpd(dev->pm_domain); -+ pd = to_rockchip_pd(genpd); -+ -+ mutex_lock(&pd->pmu->mutex); -+ ret = rockchip_pmu_set_idle_request(pd, idle); -+ mutex_unlock(&pd->pmu->mutex); -+ -+ return ret; -+} -+EXPORT_SYMBOL(rockchip_pmu_idle_request); -+ - static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd) - { - int i; -diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h -new file mode 100644 -index 000000000000..720b3314e71a ---- /dev/null -+++ b/include/linux/rockchip_pmu.h -@@ -0,0 +1,15 @@ -+/* -+ * pm_domain.h - Definitions and headers related to device power domains. -+ * -+ * Copyright (C) 2017 Randy Li . -+ * -+ * This file is released under the GPLv2. -+ */ -+ -+#ifndef _LINUX_ROCKCHIP_PM_H -+#define _LINUX_ROCKCHIP_PM_H -+#include -+ -+int rockchip_pmu_idle_request(struct device *dev, bool idle); -+ -+#endif /* _LINUX_ROCKCHIP_PM_H */ -diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h -new file mode 100644 -index 000000000000..690db6118636 ---- /dev/null -+++ b/include/soc/rockchip/pm_domains.h -@@ -0,0 +1,18 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+#ifndef __SOC_ROCKCHIP_PM_DOMAINS_H -+#define __SOC_ROCKCHIP_PM_DOMAINS_H -+ -+#include -+ -+struct device; -+ -+#ifdef CONFIG_ROCKCHIP_PM_DOMAINS -+int rockchip_pmu_idle_request(struct device *dev, bool idle); -+#else -+static inline int rockchip_pmu_idle_request(struct device *dev, bool idle) -+{ -+ return -ENOTSUPP; -+} -+#endif -+ -+#endif - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 20 May 2020 17:04:47 +0200 -Subject: [PATCH] WIP: media: rkvdec: implement reset controls - ---- - .../bindings/media/rockchip,vdec.yaml | 19 +++++++ - drivers/staging/media/rkvdec/rkvdec-regs.h | 5 ++ - drivers/staging/media/rkvdec/rkvdec.c | 53 +++++++++++++++++++ - drivers/staging/media/rkvdec/rkvdec.h | 11 +++- - 4 files changed, 87 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index 089f11d21b25..3f4772c8d095 100644 ---- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -51,6 +51,18 @@ properties: - iommus: - maxItems: 1 - -+ resets: -+ maxItems: 6 -+ -+ reset-names: -+ items: -+ - const: video_h -+ - const: video_a -+ - const: video_core -+ - const: video_cabac -+ - const: niu_a -+ - const: niu_h -+ - required: - - compatible - - reg -@@ -58,6 +70,8 @@ required: - - clocks - - clock-names - - power-domains -+ - resets -+ - reset-names - - additionalProperties: false - -@@ -76,6 +90,11 @@ examples: - clock-names = "axi", "ahb", "cabac", "core"; - power-domains = <&power RK3399_PD_VDU>; - iommus = <&vdec_mmu>; -+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, -+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, -+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - }; - - ... -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 15b9bee92016..3acc914888f6 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -28,6 +28,11 @@ - #define RKVDEC_SOFTRST_EN_P BIT(20) - #define RKVDEC_FORCE_SOFTRESET_VALID BIT(21) - #define RKVDEC_SOFTRESET_RDY BIT(22) -+#define RKVDEC_ERR_MASK (RKVDEC_BUS_STA \ -+ | RKVDEC_ERR_STA \ -+ | RKVDEC_TIMEOUT_STA \ -+ | RKVDEC_BUF_EMPTY_STA \ -+ | RKVDEC_COLMV_REF_ERR_STA ) - - #define RKVDEC_REG_SYSCTRL 0x008 - #define RKVDEC_IN_ENDIAN BIT(0) -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 18f36e8546d9..8d2495bee04d 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -10,12 +10,15 @@ - */ - - #include -+#include - #include - #include - #include - #include - #include - #include -+#include -+#include - #include - #include - #include -@@ -722,6 +725,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, - - pm_runtime_mark_last_busy(rkvdec->dev); - pm_runtime_put_autosuspend(rkvdec->dev); -+ -+ if (result == VB2_BUF_STATE_ERROR && -+ rkvdec->reset_mask == RESET_NONE) -+ rkvdec->reset_mask |= RESET_SOFT; -+ - rkvdec_job_finish_no_pm(ctx, result); - } - -@@ -759,6 +767,33 @@ static void rkvdec_device_run(void *priv) - - if (WARN_ON(!desc)) - return; -+ if (rkvdec->reset_mask != RESET_NONE) { -+ -+ if (rkvdec->reset_mask & RESET_SOFT) { -+ writel(RKVDEC_SOFTRST_EN_P, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ udelay(RKVDEC_RESET_DELAY); -+ if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT) -+ & RKVDEC_SOFTRESET_RDY) -+ dev_info_ratelimited(rkvdec->dev, -+ "softreset failed\n"); -+ } -+ -+ if (rkvdec->reset_mask & RESET_HARD) { -+ rockchip_pmu_idle_request(rkvdec->dev, true); -+ ret = reset_control_assert(rkvdec->rstc); -+ if (!ret) { -+ udelay(RKVDEC_RESET_DELAY); -+ ret = reset_control_deassert(rkvdec->rstc); -+ } -+ rockchip_pmu_idle_request(rkvdec->dev, false); -+ if (ret) -+ dev_notice_ratelimited(rkvdec->dev, -+ "hardreset failed\n"); -+ } -+ rkvdec->reset_mask = RESET_NONE; -+ pm_runtime_suspend(rkvdec->dev); -+ } - - ret = pm_runtime_resume_and_get(rkvdec->dev); - if (ret < 0) { -@@ -1026,6 +1061,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - if (cancel_delayed_work(&rkvdec->watchdog_work)) { - struct rkvdec_ctx *ctx; - -+ if (state == VB2_BUF_STATE_ERROR) { -+ rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ? -+ RESET_HARD : RESET_SOFT; -+ } -+ - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - rkvdec_job_finish(ctx, state); - } -@@ -1043,6 +1083,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - if (ctx) { - dev_err(rkvdec->dev, "Frame processing timed out!\n"); -+ rkvdec->reset_mask |= RESET_HARD; - writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, - rkvdec->regs + RKVDEC_REG_INTERRUPT); - writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); -@@ -1118,6 +1159,18 @@ static int rkvdec_probe(struct platform_device *pdev) - return ret; - } - -+ -+ rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, false, true); -+ if (IS_ERR(rkvdec->rstc)) { -+ dev_err(&pdev->dev, -+ "get resets failed %ld\n", PTR_ERR(rkvdec->rstc)); -+ return PTR_ERR(rkvdec->rstc); -+ } else { -+ dev_dbg(&pdev->dev, -+ "requested %d resets\n", -+ reset_control_get_count(&pdev->dev)); -+ } -+ - pm_runtime_set_autosuspend_delay(&pdev->dev, 100); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index c26c472baa6f..f360f2ef799f 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -11,10 +11,11 @@ - #ifndef RKVDEC_H_ - #define RKVDEC_H_ - -+#include - #include -+#include - #include - #include --#include - - #include - #include -@@ -22,6 +23,12 @@ - #include - #include - -+#define RESET_NONE 0 -+#define RESET_SOFT BIT(0) -+#define RESET_HARD BIT(1) -+ -+#define RKVDEC_RESET_DELAY 5 -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -94,6 +101,8 @@ struct rkvdec_dev { - void __iomem *regs; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; -+ struct reset_control *rstc; -+ u8 reset_mask; - }; - - struct rkvdec_ctx { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Tue, 18 Aug 2020 11:38:04 +0200 -Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399 - ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index e21b93d57300..638224b6ff70 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1053,7 +1053,10 @@ power-domain@RK3399_PD_VCODEC { - power-domain@RK3399_PD_VDU { - reg = ; - clocks = <&cru ACLK_VDU>, -- <&cru HCLK_VDU>; -+ <&cru HCLK_VDU>, -+ <&cru SCLK_VDU_CA>, -+ <&cru SCLK_VDU_CORE>; -+ - pm_qos = <&qos_video_m1_r>, - <&qos_video_m1_w>; - #power-domain-cells = <0>; -@@ -1326,6 +1329,11 @@ vdec: video-codec@ff660000 { - clock-names = "axi", "ahb", "cabac", "core"; - iommus = <&vdec_mmu>; - power-domains = <&power RK3399_PD_VDU>; -+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, -+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, -+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - }; - - vdec_mmu: iommu@ff660480 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Fri, 1 Jan 2021 12:11:12 +0200 -Subject: [PATCH] arm64: dts: rockchip: fix RK3399 vdec register witdh - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 638224b6ff70..533a031c7e24 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1322,7 +1322,7 @@ vpu_mmu: iommu@ff650800 { - - vdec: video-codec@ff660000 { - compatible = "rockchip,rk3399-vdec"; -- reg = <0x0 0xff660000 0x0 0x400>; -+ reg = <0x0 0xff660000 0x0 0x480>; - interrupts = ; - clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, - <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 19 Aug 2020 21:12:54 +0200 -Subject: [PATCH] arm64: dts: rockchip: add rkvdec node for RK3328 - -Signed-off-by: Alex Bee ---- - .../bindings/media/rockchip,vdec.yaml | 3 +++ - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 ++++++++++++++++++- - 2 files changed, 27 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index 3f4772c8d095..21a78372dae6 100644 ---- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -20,6 +20,9 @@ properties: - - items: - - const: rockchip,rk3228-vdec - - const: rockchip,rk3399-vdec -+ - items: -+ - const: rockchip,rk3328-vdec -+ - const: rockchip,rk3399-vdec - - reg: - maxItems: 1 -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 908cacb91c6a..d8a812a7d23b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -306,6 +306,10 @@ power-domain@RK3328_PD_HEVC { - }; - power-domain@RK3328_PD_VIDEO { - reg = ; -+ clocks = <&cru ACLK_RKVDEC>, -+ <&cru HCLK_RKVDEC>, -+ <&cru SCLK_VDEC_CABAC>, -+ <&cru SCLK_VDEC_CORE>; - #power-domain-cells = <0>; - }; - power-domain@RK3328_PD_VPU { -@@ -660,6 +664,25 @@ vpu_mmu: iommu@ff350800 { - power-domains = <&power RK3328_PD_VPU>; - }; - -+ rkvdec: video-codec@ff360000 { -+ compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; -+ reg = <0x0 0xff360000 0x0 0x480>; -+ interrupts = ; -+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, -+ <&cru SCLK_VDEC_CORE>; -+ assigned-clock-rates = <400000000>, <400000000>, <300000000>; -+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, -+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; -+ clock-names = "axi", "ahb", "cabac", "core"; -+ iommus = <&rkvdec_mmu>; -+ power-domains = <&power RK3328_PD_VIDEO>; -+ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>, -+ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>, -+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; -+ }; -+ - rkvdec_mmu: iommu@ff360480 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; -@@ -667,7 +690,7 @@ rkvdec_mmu: iommu@ff360480 { - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -- status = "disabled"; -+ power-domains = <&power RK3328_PD_VIDEO>; - }; - - vop: vop@ff370000 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 21 Aug 2021 16:12:36 +0200 -Subject: [PATCH] media: hantro: rockchip: Increase RK3288's max ACLK - -Required to proper decode H.264@4K - -Signed-off-by: Alex Bee ---- - drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 +++++++++++--- - 1 file changed, 11 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index f372f767d4ff..f0014823a093 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -15,7 +15,8 @@ - #include "rockchip_vpu2_regs.h" - - #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) --#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) -+#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) -+#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000) - - /* - * Supported formats. -@@ -273,13 +274,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) - return 0; - } - --static int rockchip_vpu_hw_init(struct hantro_dev *vpu) -+static int rk3288_vpu_hw_init(struct hantro_dev *vpu) - { - /* Bump ACLK to max. possible freq. to improve performance. */ - clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); - return 0; - } - -+static int rockchip_vpu_hw_init(struct hantro_dev *vpu) -+{ -+ /* Bump ACLK to max. possible freq. to improve performance. */ -+ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); -+ return 0; -+} -+ - static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -512,7 +520,7 @@ const struct hantro_variant rk3288_vpu_variant = { - .codec_ops = rk3288_vpu_codec_ops, - .irqs = rockchip_vpu1_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), -- .init = rockchip_vpu_hw_init, -+ .init = rk3288_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 16 Jan 2022 18:38:23 +0100 -Subject: [PATCH] media: rkvdec: split vp9/h264 decoded_fmts - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec.c | 14 +++++++++----- - 1 file changed, 9 insertions(+), 5 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 19b31bef0bb3..63385d92880e 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -152,13 +152,17 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), - }; - --static const u32 rkvdec_h264_vp9_decoded_fmts[] = { -+static const u32 rkvdec_h264_decoded_fmts[] = { - V4L2_PIX_FMT_NV12, - V4L2_PIX_FMT_NV15, - V4L2_PIX_FMT_NV16, - V4L2_PIX_FMT_NV20, - }; - -+static const u32 rkvdec_vp9_decoded_fmts[] = { -+ V4L2_PIX_FMT_NV12, -+}; -+ - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_STATELESS_VP9_FRAME, -@@ -192,8 +196,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_h264_ctrls, - .ops = &rkvdec_h264_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_decoded_fmts, - }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -207,8 +211,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_vp9_ctrls, - .ops = &rkvdec_vp9_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), -+ .decoded_fmts = rkvdec_vp9_decoded_fmts, - } - }; - diff --git a/patch/kernel/archive/media-5.19/210-linux-0002-rockchip-from-list.patch b/patch/kernel/archive/media-5.19/210-linux-0002-rockchip-from-list.patch index c039e12eb..5afb775c2 100644 --- a/patch/kernel/archive/media-5.19/210-linux-0002-rockchip-from-list.patch +++ b/patch/kernel/archive/media-5.19/210-linux-0002-rockchip-from-list.patch @@ -270,7 +270,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c -index 368f10405e13..238d70df6c80 100644 +index 4b70cbfc6d5d..5329f983db15 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1356,6 +1356,14 @@ void mmc_power_off(struct mmc_host *host) @@ -305,10 +305,10 @@ Signed-off-by: Alex Bee 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 39db0b85b4da..d0410ae4def2 100644 +index 49ae15708a0b..60348d517efb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -975,6 +975,20 @@ usb_host0_ohci: usb@ff5d0000 { +@@ -993,6 +993,20 @@ usb_host0_ohci: usb@ff5d0000 { status = "disabled"; }; @@ -346,10 +346,10 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index d0410ae4def2..cc46855aba46 100644 +index 60348d517efb..d7e44d174d7b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -853,6 +853,8 @@ sdmmc: mmc@ff500000 { +@@ -871,6 +871,8 @@ sdmmc: mmc@ff500000 { clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <150000000>; @@ -358,7 +358,7 @@ index d0410ae4def2..cc46855aba46 100644 status = "disabled"; }; -@@ -865,6 +867,8 @@ sdio: mmc@ff510000 { +@@ -883,6 +885,8 @@ sdio: mmc@ff510000 { clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <150000000>; @@ -367,7 +367,7 @@ index d0410ae4def2..cc46855aba46 100644 status = "disabled"; }; -@@ -877,6 +881,8 @@ emmc: mmc@ff520000 { +@@ -895,6 +899,8 @@ emmc: mmc@ff520000 { clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <150000000>; diff --git a/patch/kernel/archive/media-5.18/020-linux-0011-v4l2-from-list.patch b/patch/kernel/archive/media-5.19/211-linux-0011-v4l2-from-list.patch similarity index 70% rename from patch/kernel/archive/media-5.18/020-linux-0011-v4l2-from-list.patch rename to patch/kernel/archive/media-5.19/211-linux-0011-v4l2-from-list.patch index 8ae520924..363d3ef7f 100644 --- a/patch/kernel/archive/media-5.18/020-linux-0011-v4l2-from-list.patch +++ b/patch/kernel/archive/media-5.19/211-linux-0011-v4l2-from-list.patch @@ -1,133 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:33 +0000 -Subject: [PATCH] media: rkvdec: h264: Fix reference frame_num wrap for second - field - -When decoding the second field in a complementary field pair the second -field is sharing the same frame_num with the first field. - -Currently the frame_num for the first field is wrapped when it matches the -field being decoded, this cause issues to decode the second field in a -complementary field pair. - -Fix this by using inclusive comparison, less than or equal. - -Signed-off-by: Jonas Karlman -Reviewed-by: Ezequiel Garcia ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 951e19231da2..3becb0186062 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -752,7 +752,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - continue; - - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM || -- dpb[i].frame_num < dec_params->frame_num) { -+ dpb[i].frame_num <= dec_params->frame_num) { - p[i] = dpb[i].frame_num; - continue; - } - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:34 +0000 -Subject: [PATCH] media: rkvdec: Ensure decoded resolution fit coded resolution - -Ensure decoded CAPTURE buffer resolution is larger or equal to the coded -OPTUPT buffer resolution. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index ad2624c30843..efd316550807 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -268,6 +268,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - pix_mp->pixelformat = coded_desc->decoded_fmts[0]; - - /* Always apply the frmsize constraint of the coded end. */ -+ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -+ pix_mp->height = max(pix_mp->height, ctx->coded_fmt.fmt.pix_mp.height); - v4l2_apply_frmsize_constraints(&pix_mp->width, - &pix_mp->height, - &coded_desc->frmsize); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:34 +0000 -Subject: [PATCH] media: rkvdec: h264: Validate and use pic width and height in - mbs - -The width and height in mbs is currently configured based on OUTPUT buffer -resolution, this works for frame pictures but can cause issues for field -pictures. - -When frame_mbs_only_flag is 0 the height in mbs should be height of -the field instead of height of frame. - -Validate pic_width_in_mbs_minus1 and pic_height_in_map_units_minus1 -against OUTPUT buffer resolution and use these values to configure HW. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 4 ++-- - drivers/staging/media/rkvdec/rkvdec.c | 10 ++++++++++ - 2 files changed, 12 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 3becb0186062..a379e43147fb 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -671,8 +671,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4); - WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO), - DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG); -- WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.width, 16), PIC_WIDTH_IN_MBS); -- WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.height, 16), PIC_HEIGHT_IN_MBS); -+ WRITE_PPS(sps->pic_width_in_mbs_minus1 + 1, PIC_WIDTH_IN_MBS); -+ WRITE_PPS(sps->pic_height_in_map_units_minus1 + 1, PIC_HEIGHT_IN_MBS); - WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY), - FRAME_MBS_ONLY_FLAG); - WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD), -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index efd316550807..c88e817cac0a 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -29,8 +29,11 @@ - - static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { -+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -+ - if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { - const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; -+ unsigned int width, height; - /* - * TODO: The hardware supports 10-bit and 4:2:2 profiles, - * but it's currently broken in the driver. -@@ -45,6 +48,13 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - if (sps->bit_depth_luma_minus8 != 0) - /* Only 8-bit is supported */ - return -EINVAL; -+ -+ width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -+ height = (sps->pic_height_in_map_units_minus1 + 1) * 16; -+ -+ if (width > ctx->coded_fmt.fmt.pix_mp.width || -+ height > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; - } - return 0; - } - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 6 Jul 2020 21:54:35 +0000 @@ -298,10 +168,10 @@ index 287488016ff2..01f8a50586eb 100644 { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 }, { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 }, diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 51289d4741dc..e6f2c65e24ca 100644 +index 21470de62d72..cb7496c084f6 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1299,6 +1299,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) +@@ -1306,6 +1306,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break; case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break; case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break; @@ -311,10 +181,10 @@ index 51289d4741dc..e6f2c65e24ca 100644 case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break; case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index df8b9c486ba1..9845ce720b4e 100644 +index 343b95107fce..3a5d6290a379 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h -@@ -602,6 +602,9 @@ struct v4l2_pix_format { +@@ -603,6 +603,9 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ @@ -342,10 +212,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 503ae683d0fd..88f5f4bb320b 100644 +index 2992fb87cf72..54fc3a6d0902 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -893,9 +893,9 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -915,9 +915,9 @@ static void config_registers(struct rkvdec_ctx *ctx, dma_addr_t rlc_addr; dma_addr_t refer_addr; u32 rlc_len; @@ -358,7 +228,7 @@ index 503ae683d0fd..88f5f4bb320b 100644 u32 yuv_virstride = 0; u32 offset; dma_addr_t dst_addr; -@@ -906,8 +906,8 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -928,8 +928,8 @@ static void config_registers(struct rkvdec_ctx *ctx, f = &ctx->decoded_fmt; dst_fmt = &f->fmt.pix_mp; @@ -387,7 +257,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index c88e817cac0a..d4ae792874bb 100644 +index 7bab7586918c..40cc791aef26 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -27,6 +27,17 @@ @@ -408,7 +278,7 @@ index c88e817cac0a..d4ae792874bb 100644 static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -@@ -212,13 +223,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) +@@ -192,13 +203,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; @@ -425,7 +295,7 @@ index c88e817cac0a..d4ae792874bb 100644 } static int rkvdec_enum_framesizes(struct file *file, void *priv, -@@ -284,13 +291,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, +@@ -264,13 +271,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, &pix_mp->height, &coded_desc->frmsize); @@ -454,15 +324,15 @@ and 4:2:2 content. Signed-off-by: Jonas Karlman --- - drivers/staging/media/rkvdec/rkvdec.c | 59 ++++++++++++++++++++++++--- + drivers/staging/media/rkvdec/rkvdec.c | 67 +++++++++++++++++++++++---- drivers/staging/media/rkvdec/rkvdec.h | 2 + - 2 files changed, 55 insertions(+), 6 deletions(-) + 2 files changed, 61 insertions(+), 8 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index d4ae792874bb..3cbb1d26b972 100644 +index 40cc791aef26..e93e1cb0f829 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -38,6 +38,16 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, +@@ -38,19 +38,56 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, pix_mp->field = V4L2_FIELD_NONE; } @@ -479,21 +349,24 @@ index d4ae792874bb..3cbb1d26b972 100644 static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -@@ -60,6 +70,10 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - /* Only 8-bit is supported */ - return -EINVAL; + const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; -+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) -+ /* Only current valid format */ -+ return -EINVAL; +- if (desc->ops->try_ctrl) +- return desc->ops->try_ctrl(ctx, ctrl); ++ if (desc->ops->try_ctrl) { ++ int ret; ++ ret = desc->ops->try_ctrl(ctx, ctrl); ++ if (ret) ++ return ret; ++ } ++ ++ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) ++ /* Only current valid format */ ++ return -EINVAL; ++ ++ return 0; ++} + - width = (sps->pic_width_in_mbs_minus1 + 1) * 16; - height = (sps->pic_height_in_map_units_minus1 + 1) * 16; - -@@ -70,8 +84,27 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - return 0; - } - +static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); @@ -508,17 +381,17 @@ index d4ae792874bb..3cbb1d26b972 100644 + rkvdec_fill_decoded_pixfmt(ctx, pix_mp); + } + } -+ -+ return 0; -+} -+ + + return 0; + } + static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { .try_ctrl = rkvdec_try_ctrl, + .s_ctrl = rkvdec_s_ctrl, }; static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { -@@ -221,6 +254,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) +@@ -201,6 +238,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) { struct v4l2_format *f = &ctx->decoded_fmt; @@ -526,7 +399,7 @@ index d4ae792874bb..3cbb1d26b972 100644 rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -@@ -276,13 +310,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, +@@ -256,13 +294,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, if (WARN_ON(!coded_desc)) return -EINVAL; @@ -550,7 +423,7 @@ index d4ae792874bb..3cbb1d26b972 100644 /* Always apply the frmsize constraint of the coded end. */ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -@@ -346,6 +384,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, +@@ -326,6 +368,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, return ret; ctx->decoded_fmt = *f; @@ -558,7 +431,7 @@ index d4ae792874bb..3cbb1d26b972 100644 return 0; } -@@ -446,6 +485,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, +@@ -429,6 +472,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, if (WARN_ON(!ctx->coded_fmt_desc)) return -EINVAL; @@ -574,7 +447,7 @@ index d4ae792874bb..3cbb1d26b972 100644 return -EINVAL; diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 2f4ea1786b93..c26c472baa6f 100644 +index 633335ebb9c4..b9e219438bc9 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) @@ -585,7 +458,7 @@ index 2f4ea1786b93..c26c472baa6f 100644 int (*start)(struct rkvdec_ctx *ctx); void (*stop)(struct rkvdec_ctx *ctx); int (*run)(struct rkvdec_ctx *ctx); -@@ -99,6 +100,7 @@ struct rkvdec_ctx { +@@ -101,6 +102,7 @@ struct rkvdec_ctx { struct v4l2_fh fh; struct v4l2_format coded_fmt; struct v4l2_format decoded_fmt; @@ -609,15 +482,39 @@ for the provided SPS control. Signed-off-by: Jonas Karlman --- - drivers/staging/media/rkvdec/rkvdec-h264.c | 20 ++++++++++++++++++++ - drivers/staging/media/rkvdec/rkvdec.c | 19 +++++++++---------- - 2 files changed, 29 insertions(+), 10 deletions(-) + drivers/staging/media/rkvdec/rkvdec-h264.c | 33 ++++++++++++++++------ + drivers/staging/media/rkvdec/rkvdec.c | 19 +++++++++---- + 2 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 88f5f4bb320b..c9a551dbd9bc 100644 +index 54fc3a6d0902..af530b05a789 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -1021,6 +1021,25 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, +@@ -1044,19 +1044,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, + { + unsigned int width, height; + +- /* +- * TODO: The hardware supports 10-bit and 4:2:2 profiles, +- * but it's currently broken in the driver. +- * Reject them for now, until it's fixed. +- */ +- if (sps->chroma_format_idc > 1) +- /* Only 4:0:0 and 4:2:0 are supported */ ++ if (sps->chroma_format_idc > 2) ++ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */ + return -EINVAL; + if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) + /* Luma and chroma bit depth mismatch */ + return -EINVAL; +- if (sps->bit_depth_luma_minus8 != 0) +- /* Only 8-bit is supported */ ++ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) ++ /* Only 8-bit and 10-bit is supported */ + return -EINVAL; + + width = (sps->pic_width_in_mbs_minus1 + 1) * 16; +@@ -1077,6 +1072,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, return 0; } @@ -643,7 +540,7 @@ index 88f5f4bb320b..c9a551dbd9bc 100644 static int rkvdec_h264_start(struct rkvdec_ctx *ctx) { struct rkvdec_dev *rkvdec = ctx->dev; -@@ -1124,6 +1143,7 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx) +@@ -1198,6 +1212,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { .adjust_fmt = rkvdec_h264_adjust_fmt, @@ -652,7 +549,7 @@ index 88f5f4bb320b..c9a551dbd9bc 100644 .stop = rkvdec_h264_stop, .run = rkvdec_h264_run, diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 3cbb1d26b972..bd106b23f4a0 100644 +index e93e1cb0f829..4f5436c89e08 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, @@ -664,34 +561,12 @@ index 3cbb1d26b972..bd106b23f4a0 100644 pix_mp->plane_fmt[0].sizeimage += 128 * DIV_ROUND_UP(pix_mp->width, 16) * DIV_ROUND_UP(pix_mp->height, 16); -@@ -55,19 +55,15 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { - const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; - unsigned int width, height; -- /* -- * TODO: The hardware supports 10-bit and 4:2:2 profiles, -- * but it's currently broken in the driver. -- * Reject them for now, until it's fixed. -- */ -- if (sps->chroma_format_idc > 1) -- /* Only 4:0:0 and 4:2:0 are supported */ -+ -+ if (sps->chroma_format_idc > 2) -+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */ - return -EINVAL; - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) - /* Luma and chroma bit depth mismatch */ - return -EINVAL; -- if (sps->bit_depth_luma_minus8 != 0) -- /* Only 8-bit is supported */ -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ - return -EINVAL; +@@ -136,8 +136,11 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { + .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), + }; - if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) -@@ -155,6 +151,9 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - - static const u32 rkvdec_h264_vp9_decoded_fmts[] = { +-static const u32 rkvdec_h264_vp9_decoded_fmts[] = { ++static const u32 rkvdec_h264_decoded_fmts[] = { V4L2_PIX_FMT_NV12, + V4L2_PIX_FMT_NV15, + V4L2_PIX_FMT_NV16, @@ -699,3 +574,86 @@ index 3cbb1d26b972..bd106b23f4a0 100644 }; static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { +@@ -160,6 +163,10 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { + .num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs), + }; + ++static const u32 rkvdec_vp9_decoded_fmts[] = { ++ V4L2_PIX_FMT_NV12, ++}; ++ + static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, +@@ -173,8 +180,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + }, + .ctrls = &rkvdec_h264_ctrls, + .ops = &rkvdec_h264_fmt_ops, +- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), +- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), ++ .decoded_fmts = rkvdec_h264_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, + }, + { +@@ -189,8 +196,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + }, + .ctrls = &rkvdec_vp9_ctrls, + .ops = &rkvdec_vp9_fmt_ops, +- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), +- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), ++ .decoded_fmts = rkvdec_vp9_decoded_fmts, + } + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 27 Mar 2022 14:18:07 +0200 +Subject: [PATCH] media: rkvdec-h264: Don't hardcode SPS/PPS parameters + +Some SPS/PPS parameters are currently hardcoded in the driver +even though so do exist in the uapi which is stable by now. + +Use them instead of hardcoding them. + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec-h264.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c +index af530b05a789..f31b7c021d82 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-h264.c ++++ b/drivers/staging/media/rkvdec/rkvdec-h264.c +@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, + + #define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) + /* write sps */ +- WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID); +- WRITE_PPS(0xff, PROFILE_IDC); +- WRITE_PPS(1, CONSTRAINT_SET3_FLAG); ++ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); ++ WRITE_PPS(sps->profile_idc, PROFILE_IDC); ++ WRITE_PPS((sps->constraint_set_flags & 1 << 3) ? 1 : 0, CONSTRAINT_SET3_FLAG); + WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); + WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA); + WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA); +- WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); ++ WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS), ++ QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); + WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4); + WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES); + WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE); +@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, + DIRECT_8X8_INFERENCE_FLAG); + + /* write pps */ +- WRITE_PPS(0xff, PIC_PARAMETER_SET_ID); +- WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID); ++ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); ++ WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); + WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE), + ENTROPY_CODING_MODE_FLAG); + WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT), diff --git a/patch/kernel/archive/media-5.18/030-linux-0020-drm-from-list.patch b/patch/kernel/archive/media-5.19/212-linux-0020-drm-from-list.patch similarity index 56% rename from patch/kernel/archive/media-5.18/030-linux-0020-drm-from-list.patch rename to patch/kernel/archive/media-5.19/212-linux-0020-drm-from-list.patch index 7fb50ab8d..4b796a94e 100644 --- a/patch/kernel/archive/media-5.18/030-linux-0020-drm-from-list.patch +++ b/patch/kernel/archive/media-5.19/212-linux-0020-drm-from-list.patch @@ -24,7 +24,7 @@ Reviewed-by: Sandy Huang 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c -index 25837b1d6639..f11080d63331 100644 +index 07741b678798..5ec38456dc5d 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -261,6 +261,14 @@ const struct drm_format_info *__drm_format_info(u32 format) @@ -43,7 +43,7 @@ index 25837b1d6639..f11080d63331 100644 .num_planes = 3, .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0, diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h -index 7f652c96845b..37824734633c 100644 +index f1972154a594..b972d0adfa2e 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -285,6 +285,8 @@ extern "C" { @@ -76,10 +76,10 @@ Reviewed-by: Sandy Huang 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index a25b98b7f5bd..91ded8a096ba 100644 +index 74562d40f639..9560f82ce880 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -262,6 +262,18 @@ static bool has_rb_swapped(uint32_t format) +@@ -274,6 +274,18 @@ static bool has_uv_swapped(uint32_t format) } } @@ -98,21 +98,23 @@ index a25b98b7f5bd..91ded8a096ba 100644 static enum vop_data_format vop_convert_format(uint32_t format) { switch (format) { -@@ -277,10 +289,13 @@ static enum vop_data_format vop_convert_format(uint32_t format) +@@ -289,12 +301,15 @@ static enum vop_data_format vop_convert_format(uint32_t format) case DRM_FORMAT_BGR565: return VOP_FMT_RGB565; case DRM_FORMAT_NV12: + case DRM_FORMAT_NV15: + case DRM_FORMAT_NV21: return VOP_FMT_YUV420SP; case DRM_FORMAT_NV16: + case DRM_FORMAT_NV20: + case DRM_FORMAT_NV61: return VOP_FMT_YUV422SP; case DRM_FORMAT_NV24: + case DRM_FORMAT_NV30: + case DRM_FORMAT_NV42: return VOP_FMT_YUV444SP; default: - DRM_ERROR("unsupported format[%08x]\n", format); -@@ -931,7 +946,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -948,7 +963,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); @@ -126,7 +128,7 @@ index a25b98b7f5bd..91ded8a096ba 100644 offset += (src->y1 >> 16) * fb->pitches[0]; dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; -@@ -957,6 +977,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -974,6 +994,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, } VOP_WIN_SET(vop, win, format, format); @@ -134,7 +136,7 @@ index a25b98b7f5bd..91ded8a096ba 100644 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); -@@ -973,7 +994,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -990,7 +1011,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, uv_obj = fb->obj[1]; rk_uv_obj = to_rockchip_obj(uv_obj); @@ -148,23 +150,23 @@ index a25b98b7f5bd..91ded8a096ba 100644 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 857d97cdc67c..b7169010622a 100644 +index ba88addc1a75..567f226930b2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -165,6 +165,7 @@ struct vop_win_phy { +@@ -179,6 +179,7 @@ struct vop_win_phy { struct vop_reg enable; struct vop_reg gate; struct vop_reg format; + struct vop_reg fmt_10; struct vop_reg rb_swap; + struct vop_reg uv_swap; struct vop_reg act_info; - struct vop_reg dsp_info; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 1f7353f0684a..474cc8807ac9 100644 +index d03dd0402923..3b39b5a5f100 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -50,6 +50,23 @@ static const uint32_t formats_win_full[] = { - DRM_FORMAT_NV24, +@@ -53,6 +53,23 @@ static const uint32_t formats_win_full[] = { + DRM_FORMAT_NV42, }; +static const uint32_t formats_win_full_10[] = { @@ -187,7 +189,7 @@ index 1f7353f0684a..474cc8807ac9 100644 static const uint64_t format_modifiers_win_full[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID, -@@ -613,11 +630,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { +@@ -621,11 +638,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { static const struct vop_win_phy rk3288_win01_data = { .scl = &rk3288_win_full_scl, @@ -200,9 +202,9 @@ index 1f7353f0684a..474cc8807ac9 100644 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), + .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), + .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15), .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), -@@ -747,11 +765,12 @@ static const struct vop_intr rk3368_vop_intr = { +@@ -756,11 +774,12 @@ static const struct vop_intr rk3368_vop_intr = { static const struct vop_win_phy rk3368_win01_data = { .scl = &rk3288_win_full_scl, @@ -215,9 +217,9 @@ index 1f7353f0684a..474cc8807ac9 100644 .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), + .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4), .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), + .uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15), .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), - .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), -@@ -896,11 +915,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { +@@ -906,11 +925,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { static const struct vop_win_phy rk3399_win01_data = { .scl = &rk3288_win_full_scl, @@ -230,135 +232,5 @@ index 1f7353f0684a..474cc8807ac9 100644 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), + .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), - .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22), - .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Qinglang Miao -Date: Tue, 1 Dec 2020 20:54:57 +0800 -Subject: [PATCH] drm/rockchip: cdn-dp: fix reference leak when - pm_runtime_get_sync fails - -The PM reference count is not expected to be incremented on -return in cdn_dp_clk_enable. - -However, pm_runtime_get_sync will increment the PM reference -count even failed. Forgetting to putting operation will result -in a reference leak here. - -Replace it with pm_runtime_resume_and_get to keep usage -counter balanced. - -Fixes: efe0220fc2d2 ("drm/rockchip: cdn-dp: Fix error handling") -Reported-by: Hulk Robot -Signed-off-by: Qinglang Miao ---- - drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c -index 16497c31d9f9..e46963577854 100644 ---- a/drivers/gpu/drm/rockchip/cdn-dp-core.c -+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c -@@ -100,7 +100,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp) - goto err_core_clk; - } - -- ret = pm_runtime_get_sync(dp->dev); -+ ret = pm_runtime_resume_and_get(dp->dev); - if (ret < 0) { - DRM_DEV_ERROR(dp->dev, "cannot get pm runtime %d\n", ret); - goto err_pm_runtime_get; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Qinglang Miao -Date: Tue, 1 Dec 2020 20:54:58 +0800 -Subject: [PATCH] drm/rockchip: vop: fix reference leak when - pm_runtime_get_sync fails - -The PM reference count is not expected to be incremented on -return in functions vop_enable and vop_enable. - -However, pm_runtime_get_sync will increment the PM reference -count even failed. Forgetting to putting operation will result -in a reference leak here. - -Replace it with pm_runtime_resume_and_get to keep usage -counter balanced. - -Fixes: 5e570373c015 ("drm/rockchip: vop: Enable pm domain before vop_initial") -Reported-by: Hulk Robot -Signed-off-by: Qinglang Miao ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 91ded8a096ba..967f29625d7c 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -603,7 +603,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) - struct vop *vop = to_vop(crtc); - int ret, i; - -- ret = pm_runtime_get_sync(vop->dev); -+ ret = pm_runtime_resume_and_get(vop->dev); - if (ret < 0) { - DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); - return ret; -@@ -1953,7 +1953,7 @@ static int vop_initial(struct vop *vop) - return PTR_ERR(vop->dclk); - } - -- ret = pm_runtime_get_sync(vop->dev); -+ ret = pm_runtime_resume_and_get(vop->dev); - if (ret < 0) { - DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); - return ret; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Qinglang Miao -Date: Tue, 1 Dec 2020 20:54:59 +0800 -Subject: [PATCH] drm/rockchip: lvds: fix reference leak when - pm_runtime_get_sync fails - -The PM reference count is not expected to be incremented on -return in functions rk3288_lvds_poweron and px30_lvds_poweron. - -However, pm_runtime_get_sync will increment the PM reference -count even failed. Forgetting to putting operation will result -in a reference leak here. - -Replace it with pm_runtime_resume_and_get to keep usage -counter balanced. - -Fixes: cca1705c3d89 ("drm/rockchip: lvds: Add PX30 support") -Reported-by: Hulk Robot -Signed-off-by: Qinglang Miao ---- - drivers/gpu/drm/rockchip/rockchip_lvds.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c -index be74c87a8be4..288462fd5d8e 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_lvds.c -+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c -@@ -146,7 +146,7 @@ static int rk3288_lvds_poweron(struct rockchip_lvds *lvds) - DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); - return ret; - } -- ret = pm_runtime_get_sync(lvds->dev); -+ ret = pm_runtime_resume_and_get(lvds->dev); - if (ret < 0) { - DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); - clk_disable(lvds->pclk); -@@ -330,7 +330,7 @@ static int px30_lvds_poweron(struct rockchip_lvds *lvds) - { - int ret; - -- ret = pm_runtime_get_sync(lvds->dev); -+ ret = pm_runtime_resume_and_get(lvds->dev); - if (ret < 0) { - DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); - return ret; - + .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15), + .x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21), diff --git a/patch/kernel/archive/media-5.18/040-linux-1000-drm-rockchip.patch b/patch/kernel/archive/media-5.19/213-linux-1000-drm-rockchip.patch similarity index 90% rename from patch/kernel/archive/media-5.18/040-linux-1000-drm-rockchip.patch rename to patch/kernel/archive/media-5.19/213-linux-1000-drm-rockchip.patch index bacd09c88..0e9ec6c13 100644 --- a/patch/kernel/archive/media-5.18/040-linux-1000-drm-rockchip.patch +++ b/patch/kernel/archive/media-5.19/213-linux-1000-drm-rockchip.patch @@ -13,10 +13,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 967f29625d7c..08940fecaac3 100644 +index 9560f82ce880..c3fea637974f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1575,7 +1575,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) +@@ -1595,7 +1595,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) { struct rockchip_crtc_state *rockchip_state; @@ -47,10 +47,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 08940fecaac3..084d060051da 100644 +index c3fea637974f..e736c735ec38 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1180,6 +1180,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) +@@ -1200,6 +1200,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&vop->irq_lock, flags); } @@ -110,7 +110,7 @@ index 08940fecaac3..084d060051da 100644 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) -@@ -1558,6 +1611,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, +@@ -1578,6 +1631,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, } static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { @@ -133,10 +133,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 084d060051da..5b28c707b44c 100644 +index e736c735ec38..2b765ec02a6e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1218,6 +1218,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1238,6 +1238,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, if (!vop_crtc_is_tmds(crtc)) return MODE_OK; @@ -154,15 +154,16 @@ Subject: [PATCH] drm/rockchip: vop: define max output resolution supported Signed-off-by: Jonas Karlman --- - drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 6 ++++++ - drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 7 +++++++ - 2 files changed, 13 insertions(+) + drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 6 ++++++ + drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 5 ----- + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 7 +++++++ + 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index b7169010622a..0b1984585082 100644 +index 567f226930b2..8db9ea4055f6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -197,6 +197,11 @@ struct vop_win_data { +@@ -212,6 +212,11 @@ struct vop_win_data { enum drm_plane_type type; }; @@ -174,7 +175,7 @@ index b7169010622a..0b1984585082 100644 struct vop_data { uint32_t version; const struct vop_intr *intr; -@@ -209,6 +214,7 @@ struct vop_data { +@@ -224,6 +229,7 @@ struct vop_data { const struct vop_win_data *win; unsigned int win_size; unsigned int lut_size; @@ -182,11 +183,27 @@ index b7169010622a..0b1984585082 100644 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) #define VOP_FEATURE_INTERNAL_RGB BIT(1) +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +index c727093a06d6..f1234a151130 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +@@ -27,11 +27,6 @@ enum win_dly_mode { + VOP2_DLY_MODE_MAX, + }; + +-struct vop_rect { +- int width; +- int height; +-}; +- + enum vop2_scale_up_mode { + VOP2_SCALE_UP_NRST_NBOR, + VOP2_SCALE_UP_BIL, diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 474cc8807ac9..1d750cc492ec 100644 +index 3b39b5a5f100..0a9b64a62483 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -734,6 +734,7 @@ static const struct vop_intr rk3288_vop_intr = { +@@ -743,6 +743,7 @@ static const struct vop_intr rk3288_vop_intr = { static const struct vop_data rk3288_vop = { .version = VOP_VERSION(3, 1), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -194,7 +211,7 @@ index 474cc8807ac9..1d750cc492ec 100644 .intr = &rk3288_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -835,6 +836,7 @@ static const struct vop_misc rk3368_misc = { +@@ -845,6 +846,7 @@ static const struct vop_misc rk3368_misc = { static const struct vop_data rk3368_vop = { .version = VOP_VERSION(3, 2), @@ -202,7 +219,7 @@ index 474cc8807ac9..1d750cc492ec 100644 .intr = &rk3368_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -856,6 +858,7 @@ static const struct vop_intr rk3366_vop_intr = { +@@ -866,6 +868,7 @@ static const struct vop_intr rk3366_vop_intr = { static const struct vop_data rk3366_vop = { .version = VOP_VERSION(3, 4), @@ -210,7 +227,7 @@ index 474cc8807ac9..1d750cc492ec 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -963,6 +966,7 @@ static const struct vop_afbc rk3399_vop_afbc = { +@@ -976,6 +979,7 @@ static const struct vop_afbc rk3399_vop_afbc = { static const struct vop_data rk3399_vop_big = { .version = VOP_VERSION(3, 5), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -218,7 +235,7 @@ index 474cc8807ac9..1d750cc492ec 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -989,6 +993,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { +@@ -1002,6 +1006,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { static const struct vop_data rk3399_vop_lit = { .version = VOP_VERSION(3, 6), @@ -226,7 +243,7 @@ index 474cc8807ac9..1d750cc492ec 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -1009,6 +1014,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { +@@ -1022,6 +1027,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { static const struct vop_data rk3228_vop = { .version = VOP_VERSION(3, 7), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -234,7 +251,7 @@ index 474cc8807ac9..1d750cc492ec 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -1080,6 +1086,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { +@@ -1093,6 +1099,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { static const struct vop_data rk3328_vop = { .version = VOP_VERSION(3, 8), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -256,10 +273,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 5b28c707b44c..f906eb758b33 100644 +index 2b765ec02a6e..92caec48ccd8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1212,6 +1212,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1232,6 +1232,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) { struct vop *vop = to_vop(crtc); @@ -267,7 +284,7 @@ index 5b28c707b44c..f906eb758b33 100644 long rounded_rate; long lowest, highest; -@@ -1233,6 +1234,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1253,6 +1254,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, if (rounded_rate > highest) return MODE_CLOCK_HIGH; @@ -278,7 +295,7 @@ index 5b28c707b44c..f906eb758b33 100644 return MODE_OK; } -@@ -1241,8 +1246,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, +@@ -1261,8 +1266,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *adjusted_mode) { struct vop *vop = to_vop(crtc); @@ -340,10 +357,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 830bdd5e9b7c..08c4ea2b6bf2 100644 +index c14f88893868..4411ca8fd7ed 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -181,7 +181,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { +@@ -193,7 +193,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { static const struct dw_hdmi_phy_config rockchip_phy_config[] = { /*pixelclk symbol term vlev*/ { 74250000, 0x8009, 0x0004, 0x0272}, @@ -367,10 +384,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 08c4ea2b6bf2..546970b36dd2 100644 +index 4411ca8fd7ed..bec381cde0bc 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -183,6 +183,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { +@@ -195,6 +195,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { { 74250000, 0x8009, 0x0004, 0x0272}, { 165000000, 0x802b, 0x0004, 0x0209}, { 297000000, 0x8039, 0x0005, 0x028d}, @@ -397,10 +414,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 546970b36dd2..3bbd90e2e40b 100644 +index bec381cde0bc..72c1d65c7b75 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -160,20 +160,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { +@@ -172,20 +172,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { /* pixelclk bpp8 bpp10 bpp12 */ { @@ -455,10 +472,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 69 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 3bbd90e2e40b..2cdaeb76ab9e 100644 +index 72c1d65c7b75..0370bb247fcb 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -79,80 +79,88 @@ struct rockchip_hdmi { +@@ -91,80 +91,88 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { { @@ -628,10 +645,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 2cdaeb76ab9e..279d900e3e51 100644 +index 0370bb247fcb..55c0b8dddad5 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -221,19 +221,11 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -242,19 +242,11 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *info, const struct drm_display_mode *mode) { @@ -667,10 +684,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 279d900e3e51..20c37b22b3eb 100644 +index 55c0b8dddad5..dadd2f6ef39a 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -225,7 +225,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -246,7 +246,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, (info->max_tmds_clock && mode->clock > info->max_tmds_clock)) return MODE_CLOCK_HIGH; @@ -693,10 +710,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 20c37b22b3eb..f8001dd8dca7 100644 +index dadd2f6ef39a..62fbeaecbc92 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -306,6 +306,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, +@@ -327,6 +327,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, { struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; @@ -721,10 +738,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index f8001dd8dca7..8b957af7c61a 100644 +index 62fbeaecbc92..a4583fa1643e 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -396,9 +396,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { +@@ -417,9 +417,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { .mode_valid = dw_hdmi_rockchip_mode_valid, @@ -734,7 +751,7 @@ index f8001dd8dca7..8b957af7c61a 100644 .phy_data = &rk3228_chip_data, .phy_ops = &rk3228_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", -@@ -433,9 +430,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { +@@ -454,9 +451,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { .mode_valid = dw_hdmi_rockchip_mode_valid, @@ -752,39 +769,28 @@ Subject: [PATCH] drm/rockchip: dw-hdmi: encoder error handling Signed-off-by: Jonas Karlman --- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 25 +++++++++++++++------ - 1 file changed, 18 insertions(+), 7 deletions(-) + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 8b957af7c61a..303c6e81ca4f 100644 +index a4583fa1643e..1bac3c741ee2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -518,8 +518,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -558,7 +558,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, if (IS_ERR(hdmi->phy)) { ret = PTR_ERR(hdmi->phy); if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); -- return ret; + DRM_DEV_ERROR(hdmi->dev, "Failed to get phy: %d\n", ret); -+ goto err_disable_clk; - } - - ret = clk_prepare_enable(hdmi->vpll_clk); -@@ -524,8 +524,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - - ret = clk_prepare_enable(hdmi->vpll_clk); - if (ret) { -- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", -- ret); -+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable vpll: %d\n", ret); return ret; } -@@ -530,7 +530,11 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -590,7 +590,12 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, } drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); ++ + ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); + if (ret) { + DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret); @@ -793,27 +799,14 @@ index 8b957af7c61a..303c6e81ca4f 100644 platform_set_drvdata(pdev, hdmi); -@@ -542,10 +545,18 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - */ - if (IS_ERR(hdmi->hdmi)) { - ret = PTR_ERR(hdmi->hdmi); -- drm_encoder_cleanup(encoder); -- clk_disable_unprepare(hdmi->vpll_clk); -+ if (ret != -EPROBE_DEFER) -+ DRM_DEV_ERROR(hdmi->dev, "Failed to init dw-hdmi bridge: %d\n", ret); -+ goto err_encoder_cleanup; - } +@@ -609,6 +614,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, -+ return 0; -+ -+err_encoder_cleanup: -+ drm_encoder_cleanup(encoder); + err_bind: + drm_encoder_cleanup(encoder); +err_disable_clk: -+ clk_disable_unprepare(hdmi->vpll_clk); -+ - return ret; - } - + clk_disable_unprepare(hdmi->ref_clk); + err_clk: + regulator_disable(hdmi->avdd_1v8); From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -850,10 +843,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 1d750cc492ec..91bdb85fdfd3 100644 +index 0a9b64a62483..6446f2158d30 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -731,7 +731,7 @@ static const struct vop_intr rk3288_vop_intr = { +@@ -740,7 +740,7 @@ static const struct vop_intr rk3288_vop_intr = { .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), }; @@ -862,7 +855,7 @@ index 1d750cc492ec..91bdb85fdfd3 100644 .version = VOP_VERSION(3, 1), .feature = VOP_FEATURE_OUTPUT_RGB10, .max_output = { 3840, 2160 }, -@@ -744,6 +744,19 @@ static const struct vop_data rk3288_vop = { +@@ -753,6 +753,19 @@ static const struct vop_data rk3288_vop = { .lut_size = 1024, }; @@ -882,7 +875,7 @@ index 1d750cc492ec..91bdb85fdfd3 100644 static const int rk3368_vop_intrs[] = { FS_INTR, 0, 0, -@@ -1109,8 +1122,10 @@ static const struct of_device_id vop_driver_dt_match[] = { +@@ -1122,8 +1135,10 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3066_vop }, { .compatible = "rockchip,rk3188-vop", .data = &rk3188_vop }, @@ -907,10 +900,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index aaaa61875701..7160118864df 100644 +index 487b0e03d4b4..c60eacab8a79 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1016,7 +1016,7 @@ rga: rga@ff920000 { +@@ -1017,7 +1017,7 @@ rga: rga@ff920000 { }; vopb: vop@ff930000 { @@ -919,7 +912,7 @@ index aaaa61875701..7160118864df 100644 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; interrupts = ; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; -@@ -1065,7 +1065,7 @@ vopb_mmu: iommu@ff930300 { +@@ -1066,7 +1066,7 @@ vopb_mmu: iommu@ff930300 { }; vopl: vop@ff940000 { @@ -943,7 +936,7 @@ Signed-off-by: Jonas Karlman 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index f08d0fded61f..0af70d3839dd 100644 +index 3e1be9894ed1..170d291448df 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -137,7 +137,8 @@ struct dw_hdmi_phy_data { @@ -956,7 +949,7 @@ index f08d0fded61f..0af70d3839dd 100644 }; struct dw_hdmi { -@@ -1442,7 +1443,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) +@@ -1584,7 +1585,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) */ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_plat_data *pdata, @@ -966,7 +959,7 @@ index f08d0fded61f..0af70d3839dd 100644 { const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; -@@ -1517,9 +1519,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, +@@ -1659,9 +1661,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, /* Write to the PHY as configured by the platform */ if (pdata->configure_phy) @@ -993,10 +986,10 @@ index 18ed14911b98..9c75095a25c5 100644 const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params; diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index 2a1f85f9a8a3..85be16b9cfbf 100644 +index f668e75fbabe..48fb72f9614f 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h -@@ -154,7 +154,8 @@ struct dw_hdmi_plat_data { +@@ -159,7 +159,8 @@ struct dw_hdmi_plat_data { const struct dw_hdmi_curr_ctrl *cur_ctr; const struct dw_hdmi_phy_config *phy_config; int (*configure_phy)(struct dw_hdmi *hdmi, void *data, @@ -1020,10 +1013,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 0af70d3839dd..48a343c9bcc3 100644 +index 170d291448df..507b7bf4c7fd 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1449,6 +1449,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1591,6 +1591,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; @@ -1031,7 +1024,7 @@ index 0af70d3839dd..48a343c9bcc3 100644 /* TOFIX Will need 420 specific PHY configuration tables */ -@@ -1458,11 +1459,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1600,11 +1601,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, break; for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) @@ -1045,7 +1038,7 @@ index 0af70d3839dd..48a343c9bcc3 100644 break; if (mpll_config->mpixelclock == ~0UL || -@@ -1470,11 +1471,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1612,11 +1613,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, phy_config->mpixelclock == ~0UL) return -EINVAL; @@ -1079,10 +1072,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 48a343c9bcc3..90e683c65cbe 100644 +index 507b7bf4c7fd..2eb0f3cf1516 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1451,7 +1451,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1593,7 +1593,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; int depth; @@ -1094,10 +1087,10 @@ index 48a343c9bcc3..90e683c65cbe 100644 /* PLL/MPLL Cfg - always match on final entry */ for (; mpll_config->mpixelclock != ~0UL; mpll_config++) diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index 85be16b9cfbf..bf45a37170ea 100644 +index 48fb72f9614f..02554d324b4b 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h -@@ -151,6 +151,7 @@ struct dw_hdmi_plat_data { +@@ -156,6 +156,7 @@ struct dw_hdmi_plat_data { /* Synopsys PHY support */ const struct dw_hdmi_mpll_config *mpll_cfg; @@ -1117,10 +1110,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 303c6e81ca4f..73fad678b6ee 100644 +index 1bac3c741ee2..1bf68ddc124c 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -221,8 +221,15 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -242,8 +242,15 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *info, const struct drm_display_mode *mode) { @@ -1138,14 +1131,14 @@ index 303c6e81ca4f..73fad678b6ee 100644 return MODE_CLOCK_HIGH; return drm_mode_validate_size(mode, 3840, 2160); -@@ -495,6 +502,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -531,6 +538,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + return -ENOMEM; hdmi->dev = &pdev->dev; - hdmi->chip_data = plat_data->phy_data; + plat_data->priv_data = plat_data; + hdmi->chip_data = plat_data->phy_data; plat_data->phy_data = hdmi; - encoder = &hdmi->encoder; - + encoder = &hdmi->encoder.encoder; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -1158,10 +1151,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 73fad678b6ee..6471d601b98b 100644 +index 1bf68ddc124c..454c7bba0969 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -165,6 +165,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { +@@ -177,6 +177,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { } }; @@ -1208,7 +1201,7 @@ index 73fad678b6ee..6471d601b98b 100644 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { /* pixelclk bpp8 bpp10 bpp12 */ { -@@ -453,6 +493,7 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { +@@ -474,6 +514,7 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { .mode_valid = dw_hdmi_rockchip_mode_valid, .mpll_cfg = rockchip_mpll_cfg, @@ -1229,10 +1222,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 6471d601b98b..9af45fdfbd19 100644 +index 454c7bba0969..cb8b2135ddf0 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -205,6 +205,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { +@@ -217,6 +217,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { } }; @@ -1279,7 +1272,7 @@ index 6471d601b98b..9af45fdfbd19 100644 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { /* pixelclk bpp8 bpp10 bpp12 */ { -@@ -458,6 +498,7 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { +@@ -479,6 +519,7 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { .mode_valid = dw_hdmi_rockchip_mode_valid, .mpll_cfg = rockchip_mpll_cfg, @@ -1302,25 +1295,40 @@ atomic_get_input_bus_fmts and support for 8-bit RGB 4:4:4. Signed-off-by: Jonas Karlman --- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 110 ++++++++++++++------ - 1 file changed, 78 insertions(+), 32 deletions(-) + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 117 +++++++++++++------- + 1 file changed, 80 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 9af45fdfbd19..134c2db8d0fe 100644 +index cb8b2135ddf0..da4a829baded 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -68,6 +68,7 @@ struct rockchip_hdmi { +@@ -72,6 +72,7 @@ struct rockchip_hdmi_chip_data { + struct rockchip_hdmi { struct device *dev; struct regmap *regmap; - struct drm_encoder encoder; + struct drm_bridge bridge; + struct rockchip_encoder encoder; const struct rockchip_hdmi_chip_data *chip_data; - struct clk *vpll_clk; - struct clk *grf_clk; -@@ -315,30 +316,20 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, - return drm_mode_validate_size(mode, 3840, 2160); + struct clk *ref_clk; +@@ -82,11 +83,9 @@ struct rockchip_hdmi { + struct phy *phy; + }; + +-static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) ++static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) + { +- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); +- +- return container_of(rkencoder, struct rockchip_hdmi, encoder); ++ return container_of(bridge, struct rockchip_hdmi, bridge); } + static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { +@@ -335,31 +334,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, + + return drm_mode_validate_size(mode, 3840, 2160); + } +- -static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) +static void +dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, @@ -1336,7 +1344,7 @@ index 9af45fdfbd19..134c2db8d0fe 100644 - struct drm_display_mode *adj_mode) -{ - return true; -+ clk_set_rate(hdmi->vpll_clk, adjusted_mode->clock * 1000); ++ clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000); } -static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, @@ -1345,19 +1353,19 @@ index 9af45fdfbd19..134c2db8d0fe 100644 +static void dw_hdmi_rockchip_bridge_enable(struct drm_bridge *bridge) { - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); -- -- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000); ++ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); ++ struct drm_encoder *encoder = bridge->encoder; + +- clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); -} - -static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) -{ - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); -+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); -+ struct drm_encoder *encoder = bridge->encoder; u32 val; int ret; -@@ -366,10 +357,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) +@@ -387,10 +376,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) ret ? "LIT" : "BIG"); } @@ -1382,7 +1390,7 @@ index 9af45fdfbd19..134c2db8d0fe 100644 { struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); -@@ -379,12 +381,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, +@@ -400,12 +400,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, return 0; } @@ -1427,7 +1435,7 @@ index 9af45fdfbd19..134c2db8d0fe 100644 }; static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, -@@ -565,6 +593,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -602,6 +628,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, struct dw_hdmi_plat_data *plat_data; const struct of_device_id *match; struct drm_device *drm = data; @@ -1435,11 +1443,12 @@ index 9af45fdfbd19..134c2db8d0fe 100644 struct drm_encoder *encoder; struct rockchip_hdmi *hdmi; int ret; -@@ -618,19 +647,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - goto err_disable_clk; +@@ -679,20 +706,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + RK3568_HDMI_SCLIN_MSK)); } - drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); +- ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); if (ret) { DRM_DEV_ERROR(hdmi->dev, "Failed to init encoder: %d\n", ret); @@ -1456,12 +1465,12 @@ index 9af45fdfbd19..134c2db8d0fe 100644 /* - * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), -+ * If dw_hdmi_probe() fails we'll never call dw_hdmi_remove(), ++ * If dw_hdmi_probe() fails we'll never call dw_hdmi_unbind(), * which would have called the encoder cleanup. Do it manually. */ if (IS_ERR(hdmi->hdmi)) { -@@ -640,8 +671,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - goto err_encoder_cleanup; +@@ -700,8 +728,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + goto err_bind; } + next_bridge = of_drm_find_bridge(pdev->dev.of_node); @@ -1481,18 +1490,18 @@ index 9af45fdfbd19..134c2db8d0fe 100644 +err_dw_hdmi_remove: + dw_hdmi_remove(hdmi->hdmi); - err_encoder_cleanup: + err_bind: drm_encoder_cleanup(encoder); err_disable_clk: -@@ -655,7 +701,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, +@@ -719,7 +762,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, { struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); - dw_hdmi_unbind(hdmi->hdmi); + dw_hdmi_remove(hdmi->hdmi); - clk_disable_unprepare(hdmi->vpll_clk); - } + clk_disable_unprepare(hdmi->ref_clk); + regulator_disable(hdmi->avdd_1v8); From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -1505,10 +1514,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 4 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index f906eb758b33..ee6f7f653754 100644 +index 92caec48ccd8..3e2a0ce1a137 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1874,19 +1874,10 @@ static int vop_create_crtc(struct vop *vop) +@@ -1894,19 +1894,10 @@ static int vop_create_crtc(struct vop *vop) int ret; int i; @@ -1528,7 +1537,7 @@ index f906eb758b33..ee6f7f653754 100644 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 0, &vop_plane_funcs, win_data->phy->data_formats, -@@ -1919,32 +1910,13 @@ static int vop_create_crtc(struct vop *vop) +@@ -1939,32 +1930,13 @@ static int vop_create_crtc(struct vop *vop) drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); } @@ -1578,7 +1587,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -index 3aa37e177667..a2b59faa9184 100644 +index 0d2cb4f3922b..e46965d16dd0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -132,6 +132,8 @@ void rockchip_drm_mode_config_init(struct drm_device *dev) @@ -1589,12 +1598,12 @@ index 3aa37e177667..a2b59faa9184 100644 + dev->mode_config.funcs = &rockchip_drm_mode_config_funcs; dev->mode_config.helper_private = &rockchip_mode_config_helpers; - } + diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index ee6f7f653754..350391e92c46 100644 +index 3e2a0ce1a137..3c1c415b039e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1851,7 +1851,7 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1871,7 +1871,7 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1603,7 +1612,7 @@ index ee6f7f653754..350391e92c46 100644 const struct vop_win_data *win_data) { unsigned int flags = 0; -@@ -1861,6 +1861,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, +@@ -1881,6 +1881,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, if (flags) drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | flags); @@ -1612,7 +1621,7 @@ index ee6f7f653754..350391e92c46 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1892,7 +1894,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1912,7 +1914,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1633,10 +1642,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 350391e92c46..6f72c52db2d2 100644 +index 3c1c415b039e..1df221b7007d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1851,8 +1851,23 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1871,8 +1871,23 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1661,7 +1670,7 @@ index 350391e92c46..6f72c52db2d2 100644 { unsigned int flags = 0; -@@ -1863,6 +1878,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, +@@ -1883,6 +1898,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, DRM_MODE_ROTATE_0 | flags); drm_plane_create_zpos_immutable_property(plane, zpos); @@ -1681,7 +1690,7 @@ index 350391e92c46..6f72c52db2d2 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1894,7 +1922,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1914,7 +1942,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1707,10 +1716,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 7160118864df..402492268dad 100644 +index c60eacab8a79..d1ae42757242 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1025,6 +1025,8 @@ vopb: vop@ff930000 { +@@ -1026,6 +1026,8 @@ vopb: vop@ff930000 { resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; reset-names = "axi", "ahb", "dclk"; iommus = <&vopb_mmu>; @@ -1951,10 +1960,10 @@ Subject: [PATCH] HACK: dts: rockchip: do not use vopl for hdmi 2 files changed, 18 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 402492268dad..eb9d3bdf1d5e 100644 +index d1ae42757242..7b2cde230b87 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1082,11 +1082,6 @@ vopl_out: port { +@@ -1083,11 +1083,6 @@ vopl_out: port { #address-cells = <1>; #size-cells = <0>; @@ -1966,7 +1975,7 @@ index 402492268dad..eb9d3bdf1d5e 100644 vopl_out_edp: endpoint@1 { reg = <1>; remote-endpoint = <&edp_in_vopl>; -@@ -1226,10 +1221,6 @@ hdmi_in_vopb: endpoint@0 { +@@ -1227,10 +1222,6 @@ hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; @@ -1978,10 +1987,10 @@ index 402492268dad..eb9d3bdf1d5e 100644 }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index d3cdf6f42a30..e21b93d57300 100644 +index fbd0346624e6..b0620c45820c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1702,11 +1702,6 @@ vopl_out_edp: endpoint@1 { +@@ -1725,11 +1725,6 @@ vopl_out_edp: endpoint@1 { remote-endpoint = <&edp_in_vopl>; }; @@ -1993,7 +2002,7 @@ index d3cdf6f42a30..e21b93d57300 100644 vopl_out_mipi1: endpoint@3 { reg = <3>; remote-endpoint = <&mipi1_in_vopl>; -@@ -1900,10 +1895,6 @@ hdmi_in_vopb: endpoint@0 { +@@ -1923,10 +1918,6 @@ hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; @@ -2016,10 +2025,10 @@ Subject: [PATCH] WIP: drm/bridge: dw-hdmi: limit mode and bus format to 1 file changed, 76 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 90e683c65cbe..419fd9124d7b 100644 +index 2eb0f3cf1516..3b0ce3f22d3e 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1860,6 +1860,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, +@@ -2002,6 +2002,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); } @@ -2041,7 +2050,7 @@ index 90e683c65cbe..419fd9124d7b 100644 static void hdmi_av_composer(struct dw_hdmi *hdmi, const struct drm_display_info *display, const struct drm_display_mode *mode) -@@ -1871,29 +1886,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, +@@ -2013,29 +2028,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, unsigned int vdisplay, hdisplay; vmode->mpixelclock = mode->clock * 1000; @@ -2074,7 +2083,7 @@ index 90e683c65cbe..419fd9124d7b 100644 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); /* Set up HDMI_FC_INVIDCONF */ -@@ -2529,8 +2526,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2662,8 +2659,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) * - MEDIA_BUS_FMT_RGB888_1X24, */ @@ -2098,7 +2107,7 @@ index 90e683c65cbe..419fd9124d7b 100644 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, -@@ -2542,8 +2552,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2675,8 +2685,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_display_info *info = &conn->display_info; struct drm_display_mode *mode = &crtc_state->mode; u8 max_bpc = conn_state->max_requested_bpc; @@ -2107,7 +2116,7 @@ index 90e683c65cbe..419fd9124d7b 100644 u32 *output_fmts; unsigned int i = 0; -@@ -2566,29 +2574,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2700,29 +2708,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, * If the current mode enforces 4:2:0, force the output but format * to 4:2:0 and do not add the YUV422/444/RGB formats */ @@ -2149,7 +2158,7 @@ index 90e683c65cbe..419fd9124d7b 100644 } /* -@@ -2597,40 +2609,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2731,40 +2743,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, */ if (max_bpc >= 16 && info->bpc == 16) { @@ -2212,7 +2221,7 @@ index 90e683c65cbe..419fd9124d7b 100644 *num_output_fmts = i; -@@ -2811,11 +2834,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, +@@ -2945,11 +2968,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, struct dw_hdmi *hdmi = bridge->driver_private; const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; enum drm_mode_status mode_status = MODE_OK; @@ -2240,23 +2249,24 @@ Date: Fri, 20 Dec 2019 08:12:42 +0000 Subject: [PATCH] WIP: drm/rockchip: dw_hdmi: add 10-bit rgb bus format --- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 + + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 42 +++++++++++++++++++++ + drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 134c2db8d0fe..cba63dd5e8c8 100644 +index da4a829baded..66e463d58a0b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -77,6 +77,7 @@ struct rockchip_hdmi { +@@ -83,6 +83,8 @@ struct rockchip_hdmi { + struct phy *phy; }; - #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) +#define to_crtc_state(x) container_of(x, struct drm_crtc_state, x) - - static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - { -@@ -322,6 +323,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, ++ + static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) + { + return container_of(bridge, struct rockchip_hdmi, bridge); +@@ -340,6 +342,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *adjusted_mode) { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); @@ -2266,23 +2276,12 @@ index 134c2db8d0fe..cba63dd5e8c8 100644 + if (hdmi->phy) + phy_set_bus_width(hdmi->phy, s->bus_width); - clk_set_rate(hdmi->vpll_clk, adjusted_mode->clock * 1000); + clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000); } -@@ -360,6 +366,7 @@ static void dw_hdmi_rockchip_bridge_enable(struct drm_bridge *bridge) - static bool is_rgb(u32 format) +@@ -380,6 +387,17 @@ static bool is_rgb(u32 format) { switch (format) { -+ case MEDIA_BUS_FMT_RGB101010_1X30: case MEDIA_BUS_FMT_RGB888_1X24: - return true; - default: -@@ -367,6 +374,16 @@ static bool is_rgb(u32 format) - } - } - -+static bool is_10bit(u32 format) -+{ -+ switch (format) { + case MEDIA_BUS_FMT_RGB101010_1X30: + return true; + default: @@ -2290,10 +2289,14 @@ index 134c2db8d0fe..cba63dd5e8c8 100644 + } +} + - static int - dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, -@@ -374,9 +391,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, ++static bool is_10bit(u32 format) ++{ ++ switch (format) { ++ case MEDIA_BUS_FMT_RGB101010_1X30: + return true; + default: + return false; +@@ -393,9 +411,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, struct drm_connector_state *conn_state) { struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); @@ -2318,7 +2321,7 @@ index 134c2db8d0fe..cba63dd5e8c8 100644 return 0; } -@@ -388,10 +420,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -407,10 +440,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, u32 output_fmt, unsigned int *num_input_fmts) { @@ -2339,14 +2342,13 @@ index 134c2db8d0fe..cba63dd5e8c8 100644 return NULL; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -index aa0909e8edf9..59716b037205 100644 +index 1641440837af..381e5ccab5f3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -31,6 +31,8 @@ struct rockchip_crtc_state { - int output_bpc; - int output_flags; - bool enable_afbc; -+ u32 bus_format; +@@ -34,6 +34,7 @@ struct rockchip_crtc_state { + u32 bus_format; + u32 bus_flags; + int color_space; + int bus_width; }; #define to_rockchip_crtc_state(s) \ @@ -2363,10 +2365,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 419fd9124d7b..21b4e5873630 100644 +index 3b0ce3f22d3e..cd806742c010 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1647,6 +1647,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, +@@ -1789,6 +1789,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, const struct drm_connector *connector, const struct drm_display_mode *mode) { @@ -2374,7 +2376,7 @@ index 419fd9124d7b..21b4e5873630 100644 struct hdmi_avi_infoframe frame; u8 val; -@@ -1704,6 +1705,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, +@@ -1846,6 +1847,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; } @@ -2383,7 +2385,7 @@ index 419fd9124d7b..21b4e5873630 100644 /* * The Designware IP uses a different byte format from standard * AVI info frames, though generally the bits are in the correct -@@ -2417,7 +2420,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, +@@ -2550,7 +2553,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, if (!crtc) return 0; @@ -2393,7 +2395,7 @@ index 419fd9124d7b..21b4e5873630 100644 crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); -@@ -2485,6 +2489,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2618,6 +2622,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) drm_connector_attach_max_bpc_property(connector, 8, 16); @@ -2416,10 +2418,10 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv444 support 4 files changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index cba63dd5e8c8..6429892ac4df 100644 +index 66e463d58a0b..4fad844a18af 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -62,6 +62,7 @@ struct rockchip_hdmi_chip_data { +@@ -67,6 +67,7 @@ struct rockchip_hdmi_chip_data { int lcdsel_grf_reg; u32 lcdsel_big; u32 lcdsel_lit; @@ -2427,7 +2429,7 @@ index cba63dd5e8c8..6429892ac4df 100644 }; struct rockchip_hdmi { -@@ -374,10 +375,22 @@ static bool is_rgb(u32 format) +@@ -394,10 +395,22 @@ static bool is_rgb(u32 format) } } @@ -2450,7 +2452,7 @@ index cba63dd5e8c8..6429892ac4df 100644 return true; default: return false; -@@ -394,12 +407,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, +@@ -414,12 +427,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, struct drm_atomic_state *state = bridge_state->base.state; struct drm_crtc_state *old_crtc_state; struct rockchip_crtc_state *old_state; @@ -2473,7 +2475,7 @@ index cba63dd5e8c8..6429892ac4df 100644 s->bus_width = is_10bit(format) ? 10 : 8; old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); -@@ -433,7 +456,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -453,7 +476,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, if (!has_10bit && is_10bit(output_fmt)) return NULL; @@ -2485,7 +2487,7 @@ index cba63dd5e8c8..6429892ac4df 100644 return NULL; input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL); -@@ -583,6 +609,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { +@@ -603,6 +629,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { static struct rockchip_hdmi_chip_data rk3328_chip_data = { .lcdsel_grf_reg = -1, @@ -2494,10 +2496,10 @@ index cba63dd5e8c8..6429892ac4df 100644 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 6f72c52db2d2..68251bb45459 100644 +index 1df221b7007d..ac3802c3be21 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -326,6 +326,17 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -341,6 +341,17 @@ static int vop_convert_afbc_format(uint32_t format) return -EINVAL; } @@ -2515,7 +2517,7 @@ index 6f72c52db2d2..68251bb45459 100644 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, uint32_t dst, bool is_horizontal, int vsu_mode, int *vskiplines) -@@ -1392,6 +1403,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1412,6 +1423,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, u16 vact_end = vact_st + vdisplay; uint32_t pin_pol, val; int dither_bpc = s->output_bpc ? s->output_bpc : 10; @@ -2523,7 +2525,7 @@ index 6f72c52db2d2..68251bb45459 100644 int ret; if (old_state && old_state->self_refresh_active) { -@@ -1465,6 +1477,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1485,6 +1497,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2532,7 +2534,7 @@ index 6f72c52db2d2..68251bb45459 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); else -@@ -1480,6 +1494,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1500,6 +1514,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2555,10 +2557,10 @@ index 6f72c52db2d2..68251bb45459 100644 val = hact_st << 16; val |= hact_end; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 0b1984585082..72dd670bf2a7 100644 +index 8db9ea4055f6..e9f256bd8d5a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -103,10 +103,16 @@ struct vop_common { +@@ -117,10 +117,16 @@ struct vop_common { struct vop_reg mmu_en; struct vop_reg out_mode; struct vop_reg standby; @@ -2576,10 +2578,10 @@ index 0b1984585082..72dd670bf2a7 100644 struct vop_intr { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 91bdb85fdfd3..6abf72b6a751 100644 +index 6446f2158d30..7c4c3e299760 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -696,6 +696,11 @@ static const struct vop_common rk3288_common = { +@@ -705,6 +705,11 @@ static const struct vop_common rk3288_common = { .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), @@ -2591,7 +2593,7 @@ index 91bdb85fdfd3..6abf72b6a751 100644 }; /* -@@ -1063,6 +1068,10 @@ static const struct vop_output rk3328_output = { +@@ -1076,6 +1081,10 @@ static const struct vop_output rk3328_output = { static const struct vop_misc rk3328_misc = { .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), @@ -2602,7 +2604,7 @@ index 91bdb85fdfd3..6abf72b6a751 100644 }; static const struct vop_common rk3328_common = { -@@ -1075,6 +1084,11 @@ static const struct vop_common rk3328_common = { +@@ -1088,6 +1097,11 @@ static const struct vop_common rk3328_common = { .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), @@ -2628,10 +2630,10 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv420 support 4 files changed, 47 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 6429892ac4df..257770ea2dc7 100644 +index 4fad844a18af..d57e953ce585 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -386,9 +386,21 @@ static bool is_yuv444(u32 format) +@@ -406,9 +406,21 @@ static bool is_yuv444(u32 format) } } @@ -2653,7 +2655,7 @@ index 6429892ac4df..257770ea2dc7 100644 case MEDIA_BUS_FMT_RGB101010_1X30: case MEDIA_BUS_FMT_YUV10_1X30: return true; -@@ -425,6 +437,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, +@@ -445,6 +457,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, s->bus_width = is_10bit(format) ? 10 : 8; @@ -2665,7 +2667,7 @@ index 6429892ac4df..257770ea2dc7 100644 old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); if (old_crtc_state && !crtc_state->mode_changed) { old_state = to_rockchip_crtc_state(old_crtc_state); -@@ -445,6 +462,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -465,6 +482,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); struct drm_encoder *encoder = bridge->encoder; @@ -2673,7 +2675,7 @@ index 6429892ac4df..257770ea2dc7 100644 u32 *input_fmt; bool has_10bit = true; -@@ -459,6 +477,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -479,6 +497,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, if (is_yuv444(output_fmt)) { if (!hdmi->chip_data->ycbcr_444_allowed) return NULL; @@ -2683,7 +2685,7 @@ index 6429892ac4df..257770ea2dc7 100644 } else if (!is_rgb(output_fmt)) return NULL; -@@ -619,6 +640,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { +@@ -639,6 +660,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { .phy_name = "inno_dw_hdmi_phy2", .phy_force_vendor = true, .use_drm_infoframe = true, @@ -2692,10 +2694,10 @@ index 6429892ac4df..257770ea2dc7 100644 static struct rockchip_hdmi_chip_data rk3399_chip_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 68251bb45459..fb0ceda19fa4 100644 +index ac3802c3be21..04a135730b12 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -327,6 +327,19 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -342,6 +342,19 @@ static int vop_convert_afbc_format(uint32_t format) } static bool is_yuv_output(uint32_t bus_format) @@ -2711,20 +2713,20 @@ index 68251bb45459..fb0ceda19fa4 100644 + } +} + -+static bool has_uv_swapped(uint32_t bus_format) ++static bool bus_fmt_has_uv_swapped(uint32_t bus_format) { switch (bus_format) { case MEDIA_BUS_FMT_YUV8_1X24: -@@ -1477,7 +1490,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1497,7 +1510,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; - VOP_REG_SET(vop, common, dsp_data_swap, yuv_output ? 2 : 0); -+ VOP_REG_SET(vop, common, dsp_data_swap, has_uv_swapped(s->bus_format) ? 2 : 0); ++ VOP_REG_SET(vop, common, dsp_data_swap, bus_fmt_has_uv_swapped(s->bus_format) ? 2 : 0); if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); -@@ -1494,6 +1507,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1514,6 +1527,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2735,10 +2737,10 @@ index 68251bb45459..fb0ceda19fa4 100644 VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 72dd670bf2a7..a997578e174a 100644 +index e9f256bd8d5a..c5c8d3887081 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -105,6 +105,7 @@ struct vop_common { +@@ -119,6 +119,7 @@ struct vop_common { struct vop_reg standby; struct vop_reg overlay_mode; @@ -2746,7 +2748,7 @@ index 72dd670bf2a7..a997578e174a 100644 struct vop_reg dsp_data_swap; struct vop_reg dsp_out_yuv; struct vop_reg dsp_background; -@@ -269,11 +270,12 @@ struct vop_data { +@@ -284,11 +285,12 @@ struct vop_data { /* * display output interface supported by rockchip lcdc */ @@ -2764,10 +2766,10 @@ index 72dd670bf2a7..a997578e174a 100644 /* output flags */ #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 6abf72b6a751..bcdfa9de3d62 100644 +index 7c4c3e299760..1aecdcf63da9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -698,6 +698,7 @@ static const struct vop_common rk3288_common = { +@@ -707,6 +707,7 @@ static const struct vop_common rk3288_common = { .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16), @@ -2775,7 +2777,7 @@ index 6abf72b6a751..bcdfa9de3d62 100644 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), -@@ -1086,6 +1087,7 @@ static const struct vop_common rk3328_common = { +@@ -1099,6 +1100,7 @@ static const struct vop_common rk3328_common = { .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), @@ -2795,10 +2797,10 @@ Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 257770ea2dc7..78b77b31436a 100644 +index d57e953ce585..42457f7d9bc9 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -595,6 +595,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { +@@ -615,6 +615,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { static struct rockchip_hdmi_chip_data rk3228_chip_data = { .lcdsel_grf_reg = -1, @@ -2806,7 +2808,7 @@ index 257770ea2dc7..78b77b31436a 100644 }; static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { -@@ -603,6 +604,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { +@@ -623,6 +624,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { .phy_ops = &rk3228_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", .phy_force_vendor = true, @@ -2830,10 +2832,10 @@ Signed-off-by: Alex Bee 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 78b77b31436a..976dd3c9c26f 100644 +index 42457f7d9bc9..90cc3b33e2a0 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -305,16 +305,30 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -325,16 +325,30 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, const struct drm_display_mode *mode) { struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data; @@ -2865,7 +2867,7 @@ index 78b77b31436a..976dd3c9c26f 100644 + return drm_mode_validate_size(mode, 3840, 2160); } - + static void From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee @@ -2878,10 +2880,10 @@ Subject: [PATCH] !fixup drm/rockchip: rk3368's vop does not support 10-bit 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index bcdfa9de3d62..d70c61d64155 100644 +index 1aecdcf63da9..870e388c2345 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -785,8 +785,8 @@ static const struct vop_intr rk3368_vop_intr = { +@@ -794,8 +794,8 @@ static const struct vop_intr rk3368_vop_intr = { static const struct vop_win_phy rk3368_win01_data = { .scl = &rk3288_win_full_scl, @@ -2904,10 +2906,10 @@ Signed-off-by: Alex Bee 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index d70c61d64155..5b79d7911ad7 100644 +index 870e388c2345..4ba8f79582db 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -1103,12 +1103,36 @@ static const struct vop_intr rk3328_vop_intr = { +@@ -1116,12 +1116,36 @@ static const struct vop_intr rk3328_vop_intr = { .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), }; @@ -2958,10 +2960,10 @@ Subject: [PATCH] rockchip: vop: force skip lines if image too big 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index fb0ceda19fa4..0513649886e1 100644 +index 04a135730b12..96a301501584 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -941,6 +941,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -958,6 +958,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, int format; int is_yuv = fb->format->is_yuv; int i; @@ -2969,7 +2971,7 @@ index fb0ceda19fa4..0513649886e1 100644 /* * can't update plane when vop is disabled. -@@ -959,8 +960,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -976,8 +977,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, obj = fb->obj[0]; rk_obj = to_rockchip_obj(obj); @@ -2985,7 +2987,7 @@ index fb0ceda19fa4..0513649886e1 100644 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); dsp_info = (drm_rect_height(dest) - 1) << 16; -@@ -1002,7 +1009,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1019,7 +1026,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, VOP_WIN_SET(vop, win, format, format); VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); @@ -2994,7 +2996,7 @@ index fb0ceda19fa4..0513649886e1 100644 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); VOP_WIN_SET(vop, win, y_mir_en, -@@ -1026,7 +1033,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1043,7 +1050,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, offset += (src->y1 >> 16) * fb->pitches[1] / vsub; dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; @@ -3018,10 +3020,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index cc46855aba46..908cacb91c6a 100644 +index d7e44d174d7b..5519347232f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -793,8 +793,8 @@ cru: clock-controller@ff440000 { +@@ -811,8 +811,8 @@ cru: clock-controller@ff440000 { <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, @@ -3089,7 +3091,7 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 21b4e5873630..e694655845e9 100644 +index cd806742c010..772cc629c35d 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -81,15 +81,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { @@ -3449,10 +3451,10 @@ Signed-off-by: Algea Cao 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index e694655845e9..fb3ed58d0e77 100644 +index 772cc629c35d..428e057dd415 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1061,7 +1061,7 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi) +@@ -1178,7 +1178,7 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi) if (is_color_space_interpolation(hdmi)) interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; else if (is_color_space_decimation(hdmi)) @@ -3479,23 +3481,23 @@ Signed-off-by: Alex Bee 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 976dd3c9c26f..a5929367ddbe 100644 +index 90cc3b33e2a0..3c0796c5743d 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -329,7 +329,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -349,7 +349,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, return MODE_CLOCK_HIGH; } - return drm_mode_validate_size(mode, 3840, 2160); + return MODE_OK; } - static void + dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 0513649886e1..ab2935df35c5 100644 +index 96a301501584..a89f96ab3974 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -402,8 +402,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, +@@ -417,8 +417,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, if (info->is_yuv) is_yuv = true; @@ -3566,10 +3568,10 @@ Signed-off-by: Jonas Karlman 4 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c -index cd9cb354dc2c..b9a3d7af4a0b 100644 +index 8bf91b5a7d0e..ad8a2e5a31ac 100644 --- a/drivers/media/cec/core/cec-adap.c +++ b/drivers/media/cec/core/cec-adap.c -@@ -1614,8 +1614,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) +@@ -1671,8 +1671,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) if (IS_ERR_OR_NULL(adap)) return; @@ -3587,10 +3589,10 @@ index cd9cb354dc2c..b9a3d7af4a0b 100644 } EXPORT_SYMBOL_GPL(cec_s_phys_addr); diff --git a/drivers/media/cec/core/cec-core.c b/drivers/media/cec/core/cec-core.c -index 551689d371a7..e3e038021e29 100644 +index af358e901b5f..bece8c56e5af 100644 --- a/drivers/media/cec/core/cec-core.c +++ b/drivers/media/cec/core/cec-core.c -@@ -28,6 +28,10 @@ static bool debug_phys_addr; +@@ -40,6 +40,10 @@ static bool debug_phys_addr; module_param(debug_phys_addr, bool, 0644); MODULE_PARM_DESC(debug_phys_addr, "add CEC_CAP_PHYS_ADDR if set"); @@ -3601,7 +3603,7 @@ index 551689d371a7..e3e038021e29 100644 static dev_t cec_dev_t; /* Active devices */ -@@ -174,6 +178,8 @@ static void cec_devnode_unregister(struct cec_adapter *adap) +@@ -188,6 +192,8 @@ static void cec_devnode_unregister(struct cec_adapter *adap) mutex_unlock(&devnode->lock); @@ -3610,7 +3612,7 @@ index 551689d371a7..e3e038021e29 100644 mutex_lock(&adap->lock); __cec_s_phys_addr(adap, CEC_PHYS_ADDR_INVALID, false); __cec_s_log_addrs(adap, NULL, false); -@@ -232,6 +238,17 @@ static const struct file_operations cec_error_inj_fops = { +@@ -246,6 +252,17 @@ static const struct file_operations cec_error_inj_fops = { }; #endif @@ -3628,7 +3630,7 @@ index 551689d371a7..e3e038021e29 100644 struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, void *priv, const char *name, u32 caps, u8 available_las) -@@ -269,6 +286,7 @@ struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, +@@ -283,6 +300,7 @@ struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, INIT_LIST_HEAD(&adap->transmit_queue); INIT_LIST_HEAD(&adap->wait_queue); init_waitqueue_head(&adap->kthread_waitq); @@ -3637,10 +3639,10 @@ index 551689d371a7..e3e038021e29 100644 /* adap->devnode initialization */ INIT_LIST_HEAD(&adap->devnode.fhs); diff --git a/drivers/media/cec/core/cec-priv.h b/drivers/media/cec/core/cec-priv.h -index 9bbd05053d42..d479dbd50528 100644 +index b78df931aa74..ebbea63ea9de 100644 --- a/drivers/media/cec/core/cec-priv.h +++ b/drivers/media/cec/core/cec-priv.h -@@ -27,6 +27,7 @@ static inline bool msg_is_raw(const struct cec_msg *msg) +@@ -37,6 +37,7 @@ static inline bool msg_is_raw(const struct cec_msg *msg) /* cec-core.c */ extern int cec_debug; @@ -3649,10 +3651,10 @@ index 9bbd05053d42..d479dbd50528 100644 void cec_put_device(struct cec_devnode *devnode); diff --git a/include/media/cec.h b/include/media/cec.h -index 208c9613c07e..6cea463b37bd 100644 +index abee41ae02d0..544eedb5d671 100644 --- a/include/media/cec.h +++ b/include/media/cec.h -@@ -217,6 +217,8 @@ struct cec_adapter { +@@ -236,6 +236,8 @@ struct cec_adapter { struct task_struct *kthread; wait_queue_head_t kthread_waitq; @@ -3681,10 +3683,10 @@ Signed-off-by: Alex Bee 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index fb3ed58d0e77..29ed45025745 100644 +index 428e057dd415..9f13f2aa87d1 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -3038,18 +3038,11 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) +@@ -3172,18 +3172,11 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) * ask the source to re-read the EDID. */ if (intr_stat & @@ -3704,7 +3706,7 @@ index fb3ed58d0e77..29ed45025745 100644 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { enum drm_connector_status status = phy_int_pol & HDMI_PHY_HPD ? connector_status_connected -@@ -3063,6 +3056,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) +@@ -3197,6 +3190,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) drm_helper_hpd_irq_event(hdmi->bridge.dev); drm_bridge_hpd_notify(&hdmi->bridge, status); } diff --git a/patch/kernel/archive/media-5.19/214-linux-1001-v4l2-rockchip.patch b/patch/kernel/archive/media-5.19/214-linux-1001-v4l2-rockchip.patch new file mode 100644 index 000000000..ecc91ff0d --- /dev/null +++ b/patch/kernel/archive/media-5.19/214-linux-1001-v4l2-rockchip.patch @@ -0,0 +1,626 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 23 May 2020 10:18:16 +0000 +Subject: [PATCH] WIP: media: rkvdec: continue to gate clock when decoding + finish + +Signed-off-by: Jonas Karlman +--- + drivers/staging/media/rkvdec/rkvdec.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 4f5436c89e08..06c23512e1a7 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -1016,7 +1016,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) + state = (status & RKVDEC_RDY_STA) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + +- writel(0, rkvdec->regs + RKVDEC_REG_INTERRUPT); ++ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E, ++ rkvdec->regs + RKVDEC_REG_INTERRUPT); + if (cancel_delayed_work(&rkvdec->watchdog_work)) { + struct rkvdec_ctx *ctx; + +@@ -1037,7 +1038,8 @@ static void rkvdec_watchdog_func(struct work_struct *work) + ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); + if (ctx) { + dev_err(rkvdec->dev, "Frame processing timed out!\n"); +- writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); ++ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, ++ rkvdec->regs + RKVDEC_REG_INTERRUPT); + writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); + rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); + } + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 23 May 2020 10:16:01 +0000 +Subject: [PATCH] WIP: media: rkvdec: pm runtime dont use autosuspend before + disable and cleanup + +Signed-off-by: Jonas Karlman +--- + drivers/staging/media/rkvdec/rkvdec.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 06c23512e1a7..630ef09ab70b 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -1127,9 +1127,9 @@ static int rkvdec_remove(struct platform_device *pdev) + { + struct rkvdec_dev *rkvdec = platform_get_drvdata(pdev); + +- rkvdec_v4l2_cleanup(rkvdec); +- pm_runtime_disable(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ rkvdec_v4l2_cleanup(rkvdec); + return 0; + } + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Randy Li +Date: Sun, 6 Jan 2019 01:48:37 +0800 +Subject: [PATCH] soc: rockchip: power-domain: export idle request + +We need to put the power status of HEVC IP into IDLE unless +we can't reset that IP or the SoC would crash down. +rockchip_pmu_idle_request(dev, true)---> enter idle +rockchip_pmu_idle_request(dev, false)---> exit idle + +Signed-off-by: Caesar Wang +Signed-off-by: Jeffy Chen +Signed-off-by: Randy Li +--- + drivers/soc/rockchip/pm_domains.c | 23 +++++++++++++++++++++++ + include/linux/rockchip_pmu.h | 15 +++++++++++++++ + include/soc/rockchip/pm_domains.h | 6 ++++++ + 3 files changed, 44 insertions(+) + create mode 100644 include/linux/rockchip_pmu.h + +diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c +index 89795abac951..ffb5d62c9d52 100644 +--- a/drivers/soc/rockchip/pm_domains.c ++++ b/drivers/soc/rockchip/pm_domains.c +@@ -309,6 +309,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, + return 0; + } + ++int rockchip_pmu_idle_request(struct device *dev, bool idle) ++{ ++ struct generic_pm_domain *genpd; ++ struct rockchip_pm_domain *pd; ++ int ret; ++ ++ if (IS_ERR_OR_NULL(dev)) ++ return -EINVAL; ++ ++ if (IS_ERR_OR_NULL(dev->pm_domain)) ++ return -EINVAL; ++ ++ genpd = pd_to_genpd(dev->pm_domain); ++ pd = to_rockchip_pd(genpd); ++ ++ mutex_lock(&pd->pmu->mutex); ++ ret = rockchip_pmu_set_idle_request(pd, idle); ++ mutex_unlock(&pd->pmu->mutex); ++ ++ return ret; ++} ++EXPORT_SYMBOL(rockchip_pmu_idle_request); ++ + static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd) + { + int i; +diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h +new file mode 100644 +index 000000000000..720b3314e71a +--- /dev/null ++++ b/include/linux/rockchip_pmu.h +@@ -0,0 +1,15 @@ ++/* ++ * pm_domain.h - Definitions and headers related to device power domains. ++ * ++ * Copyright (C) 2017 Randy Li . ++ * ++ * This file is released under the GPLv2. ++ */ ++ ++#ifndef _LINUX_ROCKCHIP_PM_H ++#define _LINUX_ROCKCHIP_PM_H ++#include ++ ++int rockchip_pmu_idle_request(struct device *dev, bool idle); ++ ++#endif /* _LINUX_ROCKCHIP_PM_H */ +diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h +index 7dbd941fc937..c5a59dd71754 100644 +--- a/include/soc/rockchip/pm_domains.h ++++ b/include/soc/rockchip/pm_domains.h +@@ -10,6 +10,7 @@ + + int rockchip_pmu_block(void); + void rockchip_pmu_unblock(void); ++int rockchip_pmu_idle_request(struct device *dev, bool idle); + + #else /* CONFIG_ROCKCHIP_PM_DOMAINS */ + +@@ -20,6 +21,11 @@ static inline int rockchip_pmu_block(void) + + static inline void rockchip_pmu_unblock(void) { } + ++static inline int rockchip_pmu_idle_request(struct device *dev, bool idle) ++{ ++ return -ENOTSUPP; ++} ++ + #endif /* CONFIG_ROCKCHIP_PM_DOMAINS */ + + #endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */ + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 20 May 2020 17:04:47 +0200 +Subject: [PATCH] WIP: media: rkvdec: implement reset controls + +--- + .../bindings/media/rockchip,vdec.yaml | 19 +++++++ + drivers/staging/media/rkvdec/rkvdec-regs.h | 5 ++ + drivers/staging/media/rkvdec/rkvdec.c | 53 +++++++++++++++++++ + drivers/staging/media/rkvdec/rkvdec.h | 11 +++- + 4 files changed, 87 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +index 3bcfb8e12333..dd6958df1de8 100644 +--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml ++++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +@@ -53,6 +53,18 @@ properties: + iommus: + maxItems: 1 + ++ resets: ++ maxItems: 6 ++ ++ reset-names: ++ items: ++ - const: video_h ++ - const: video_a ++ - const: video_core ++ - const: video_cabac ++ - const: niu_a ++ - const: niu_h ++ + required: + - compatible + - reg +@@ -60,6 +72,8 @@ required: + - clocks + - clock-names + - power-domains ++ - resets ++ - reset-names + + additionalProperties: false + +@@ -78,6 +92,11 @@ examples: + clock-names = "axi", "ahb", "cabac", "core"; + power-domains = <&power RK3399_PD_VDU>; + iommus = <&vdec_mmu>; ++ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, ++ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, ++ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; ++ reset-names = "video_h", "video_a", "video_core", "video_cabac", ++ "niu_a", "niu_h"; + }; + + ... +diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h +index 15b9bee92016..3acc914888f6 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-regs.h ++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h +@@ -28,6 +28,11 @@ + #define RKVDEC_SOFTRST_EN_P BIT(20) + #define RKVDEC_FORCE_SOFTRESET_VALID BIT(21) + #define RKVDEC_SOFTRESET_RDY BIT(22) ++#define RKVDEC_ERR_MASK (RKVDEC_BUS_STA \ ++ | RKVDEC_ERR_STA \ ++ | RKVDEC_TIMEOUT_STA \ ++ | RKVDEC_BUF_EMPTY_STA \ ++ | RKVDEC_COLMV_REF_ERR_STA ) + + #define RKVDEC_REG_SYSCTRL 0x008 + #define RKVDEC_IN_ENDIAN BIT(0) +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 630ef09ab70b..b6d5b26a93c2 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -10,12 +10,15 @@ + */ + + #include ++#include + #include + #include + #include + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -717,6 +720,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, + + pm_runtime_mark_last_busy(rkvdec->dev); + pm_runtime_put_autosuspend(rkvdec->dev); ++ ++ if (result == VB2_BUF_STATE_ERROR && ++ rkvdec->reset_mask == RESET_NONE) ++ rkvdec->reset_mask |= RESET_SOFT; ++ + rkvdec_job_finish_no_pm(ctx, result); + } + +@@ -754,6 +762,33 @@ static void rkvdec_device_run(void *priv) + + if (WARN_ON(!desc)) + return; ++ if (rkvdec->reset_mask != RESET_NONE) { ++ ++ if (rkvdec->reset_mask & RESET_SOFT) { ++ writel(RKVDEC_SOFTRST_EN_P, ++ rkvdec->regs + RKVDEC_REG_INTERRUPT); ++ udelay(RKVDEC_RESET_DELAY); ++ if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT) ++ & RKVDEC_SOFTRESET_RDY) ++ dev_info_ratelimited(rkvdec->dev, ++ "softreset failed\n"); ++ } ++ ++ if (rkvdec->reset_mask & RESET_HARD) { ++ rockchip_pmu_idle_request(rkvdec->dev, true); ++ ret = reset_control_assert(rkvdec->rstc); ++ if (!ret) { ++ udelay(RKVDEC_RESET_DELAY); ++ ret = reset_control_deassert(rkvdec->rstc); ++ } ++ rockchip_pmu_idle_request(rkvdec->dev, false); ++ if (ret) ++ dev_notice_ratelimited(rkvdec->dev, ++ "hardreset failed\n"); ++ } ++ rkvdec->reset_mask = RESET_NONE; ++ pm_runtime_suspend(rkvdec->dev); ++ } + + ret = pm_runtime_resume_and_get(rkvdec->dev); + if (ret < 0) { +@@ -1021,6 +1056,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) + if (cancel_delayed_work(&rkvdec->watchdog_work)) { + struct rkvdec_ctx *ctx; + ++ if (state == VB2_BUF_STATE_ERROR) { ++ rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ? ++ RESET_HARD : RESET_SOFT; ++ } ++ + ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); + rkvdec_job_finish(ctx, state); + } +@@ -1038,6 +1078,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) + ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); + if (ctx) { + dev_err(rkvdec->dev, "Frame processing timed out!\n"); ++ rkvdec->reset_mask |= RESET_HARD; + writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, + rkvdec->regs + RKVDEC_REG_INTERRUPT); + writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); +@@ -1107,6 +1148,18 @@ static int rkvdec_probe(struct platform_device *pdev) + return ret; + } + ++ ++ rkvdec->rstc = devm_reset_control_array_get(&pdev->dev, false, true); ++ if (IS_ERR(rkvdec->rstc)) { ++ dev_err(&pdev->dev, ++ "get resets failed %ld\n", PTR_ERR(rkvdec->rstc)); ++ return PTR_ERR(rkvdec->rstc); ++ } else { ++ dev_dbg(&pdev->dev, ++ "requested %d resets\n", ++ reset_control_get_count(&pdev->dev)); ++ } ++ + pm_runtime_set_autosuspend_delay(&pdev->dev, 100); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); +diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h +index b9e219438bc9..f02f79c405f0 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.h ++++ b/drivers/staging/media/rkvdec/rkvdec.h +@@ -11,10 +11,11 @@ + #ifndef RKVDEC_H_ + #define RKVDEC_H_ + ++#include + #include ++#include + #include + #include +-#include + + #include + #include +@@ -22,6 +23,12 @@ + #include + #include + ++#define RESET_NONE 0 ++#define RESET_SOFT BIT(0) ++#define RESET_HARD BIT(1) ++ ++#define RKVDEC_RESET_DELAY 5 ++ + struct rkvdec_ctx; + + struct rkvdec_ctrl_desc { +@@ -96,6 +103,8 @@ struct rkvdec_dev { + void __iomem *regs; + struct mutex vdev_lock; /* serializes ioctls */ + struct delayed_work watchdog_work; ++ struct reset_control *rstc; ++ u8 reset_mask; + }; + + struct rkvdec_ctx { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Tue, 18 Aug 2020 11:38:04 +0200 +Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399 + +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index b0620c45820c..e797271ef6b4 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1062,7 +1062,10 @@ power-domain@RK3399_PD_VCODEC { + power-domain@RK3399_PD_VDU { + reg = ; + clocks = <&cru ACLK_VDU>, +- <&cru HCLK_VDU>; ++ <&cru HCLK_VDU>, ++ <&cru SCLK_VDU_CA>, ++ <&cru SCLK_VDU_CORE>; ++ + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; + #power-domain-cells = <0>; +@@ -1345,6 +1348,11 @@ vdec: video-codec@ff660000 { + clock-names = "axi", "ahb", "cabac", "core"; + iommus = <&vdec_mmu>; + power-domains = <&power RK3399_PD_VDU>; ++ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, ++ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, ++ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; ++ reset-names = "video_h", "video_a", "video_core", "video_cabac", ++ "niu_a", "niu_h"; + }; + + vdec_mmu: iommu@ff660480 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 1 Jan 2021 12:11:12 +0200 +Subject: [PATCH] arm64: dts: rockchip: fix RK3399 vdec register witdh + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index e797271ef6b4..748eb7368e6a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1341,7 +1341,7 @@ vpu_mmu: iommu@ff650800 { + + vdec: video-codec@ff660000 { + compatible = "rockchip,rk3399-vdec"; +- reg = <0x0 0xff660000 0x0 0x400>; ++ reg = <0x0 0xff660000 0x0 0x480>; + interrupts = ; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 16:12:36 +0200 +Subject: [PATCH] media: hantro: rockchip: Increase RK3288's max ACLK + +Required to proper decode H.264@4K + +Signed-off-by: Alex Bee +--- + drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index fc96501f3bc8..f31550c21172 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -15,7 +15,8 @@ + #include "rockchip_vpu2_regs.h" + + #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) +-#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) ++#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) ++#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000) + + /* + * Supported formats. +@@ -273,13 +274,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) + return 0; + } + +-static int rockchip_vpu_hw_init(struct hantro_dev *vpu) ++static int rk3288_vpu_hw_init(struct hantro_dev *vpu) + { + /* Bump ACLK to max. possible freq. to improve performance. */ + clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); + return 0; + } + ++static int rockchip_vpu_hw_init(struct hantro_dev *vpu) ++{ ++ /* Bump ACLK to max. possible freq. to improve performance. */ ++ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); ++ return 0; ++} ++ + static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) + { + struct hantro_dev *vpu = ctx->dev; +@@ -507,7 +515,7 @@ const struct hantro_variant rk3288_vpu_variant = { + .codec_ops = rk3288_vpu_codec_ops, + .irqs = rockchip_vpu1_irqs, + .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), +- .init = rockchip_vpu_hw_init, ++ .init = rk3288_vpu_hw_init, + .clk_names = rockchip_vpu_clk_names, + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 3 Apr 2022 13:45:57 +0200 +Subject: [PATCH] media: hantro: rockchip: Enable H.264 codec for RK3399 + +--- + drivers/staging/media/hantro/rockchip_vpu_hw.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index f31550c21172..304d7b359295 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -544,7 +544,7 @@ const struct hantro_variant rk3399_vpu_variant = { + .dec_fmts = rk3399_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), + .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | +- HANTRO_VP8_DECODER, ++ HANTRO_VP8_DECODER | HANTRO_H264_DECODER, + .codec_ops = rk3399_vpu_codec_ops, + .irqs = rockchip_vpu2_irqs, + .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs), + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 4 Jul 2021 15:19:44 +0200 +Subject: [PATCH] media: rkvdec: disable QoS for VP9 (corruptions on RK3328 + otherwise) + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++ + drivers/staging/media/rkvdec/rkvdec-vp9.c | 8 ++++++++ + 2 files changed, 10 insertions(+) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h +index 3acc914888f6..265f5234f4eb 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-regs.h ++++ b/drivers/staging/media/rkvdec/rkvdec-regs.h +@@ -222,6 +222,8 @@ + #define RKVDEC_REG_H264_ERR_E 0x134 + #define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) + ++#define RKVDEC_QOS_CTRL 0x18C ++ + #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 + #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 + +diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c +index 311a12656072..ea270262bbed 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-vp9.c ++++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c +@@ -802,6 +802,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) + struct rkvdec_dev *rkvdec = ctx->dev; + struct rkvdec_vp9_run run = { }; + int ret; ++ u32 reg; + + ret = rkvdec_vp9_run_preamble(ctx, &run); + if (ret) { +@@ -823,6 +824,13 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) + writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); + + writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); ++ ++ /* disable QOS for RK3328 - no effect on other SoCs */ ++ reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL); ++ reg |= 0xFFFF; ++ reg &= (~BIT(12)); ++ writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL); ++ + /* Start decoding! */ + writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | + RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Thu, 16 Jun 2022 13:15:09 +0200 +Subject: [PATCH] arm64: dts: use correct PLL for vdec core + +vdec core should use codec pll for proper operation, by default +it uses general pll (GPLL) - as all other clocks would +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 748eb7368e6a..658ec3b00445 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1346,6 +1346,8 @@ vdec: video-codec@ff660000 { + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; ++ assigned-clocks = <&cru ACLK_VDU>; ++ assigned-clock-parents = <&cru PLL_CPLL>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3399_PD_VDU>; + resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Thu, 16 Jun 2022 13:18:22 +0200 +Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3328 + +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 5519347232f6..431c4ec198be 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -674,6 +674,11 @@ vdec: video-codec@ff360000 { + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <400000000>, <400000000>, <300000000>; ++ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>, ++ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>, ++ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>; ++ reset-names = "video_h", "video_a", "video_core", "video_cabac", ++ "niu_a", "niu_h"; + iommus = <&vdec_mmu>; + power-domains = <&power RK3328_PD_VIDEO>; + }; diff --git a/patch/kernel/archive/media-5.19/215-linux-1002-for-libreelec.patch b/patch/kernel/archive/media-5.19/215-linux-1002-for-libreelec.patch new file mode 100644 index 000000000..3e70d40a6 --- /dev/null +++ b/patch/kernel/archive/media-5.19/215-linux-1002-for-libreelec.patch @@ -0,0 +1,636 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 2 Sep 2020 19:52:02 +0200 +Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and + cooling cell for RK3328 + +Note: since the regulator that supplies the GPU usually also supplies +other SoC components, we have to make sure voltage is never lower then +1050 mV - also disable 500 MHz for now, since it will crash if rkvdec +is running at the same time (voltage to high) + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 ++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 431c4ec198be..e4977669b16a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -300,6 +300,11 @@ power: power-controller { + #address-cells = <1>; + #size-cells = <0>; + ++ power-domain@RK3328_PD_GPU { ++ reg = ; ++ clocks = <&cru ACLK_GPU>; ++ #power-domain-cells = <0>; ++ }; + power-domain@RK3328_PD_HEVC { + reg = ; + #power-domain-cells = <0>; +@@ -539,6 +544,11 @@ map0 { + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; ++ map1 { ++ trip = <&target>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <4096>; ++ }; + }; + }; + +@@ -620,7 +630,32 @@ gpu: gpu@ff300000 { + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; ++ operating-points-v2 = <&gpu_opp_table>; ++ power-domains = <&power RK3328_PD_GPU>; + resets = <&cru SRST_GPU_A>; ++ #cooling-cells = <2>; ++ }; ++ ++ gpu_opp_table: gpu-opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-200000000 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <1050000>; ++ }; ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <1050000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <1050000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <1150000>; ++ status = "disabled"; ++ }; + }; + + h265e_mmu: iommu@ff330200 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Tue, 2 Feb 2021 17:22:21 +0200 +Subject: [PATCH] ARM: dts: RK3288 miqi add hdmi sound nodes + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rk3288-miqi.dts | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts +index 713f55e143c6..8d30c49f406e 100644 +--- a/arch/arm/boot/dts/rk3288-miqi.dts ++++ b/arch/arm/boot/dts/rk3288-miqi.dts +@@ -78,6 +78,21 @@ vcc_sys: vsys-regulator { + regulator-always-on; + regulator-boot-on; + }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "HDMI"; ++ simple-audio-card,mclk-fs = <512>; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s>; ++ }; ++ }; + }; + + &cpu0 { +@@ -284,6 +299,11 @@ &i2c5 { + status = "okay"; + }; + ++&i2s { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ + &io_domains { + status = "okay"; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 2 Apr 2021 17:54:22 +0200 +Subject: [PATCH] ARM/arm64: dts: rockchip: align sound card names + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rk3288-tinker.dtsi | 2 +- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi +index 9c1e38c54eae..ee332fc9cf1f 100644 +--- a/arch/arm/boot/dts/rk3288-tinker.dtsi ++++ b/arch/arm/boot/dts/rk3288-tinker.dtsi +@@ -75,7 +75,7 @@ sdio_pwrseq: sdio-pwrseq { + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; +- simple-audio-card,name = "rockchip,tinker-codec"; ++ simple-audio-card,name = "HDMI"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 658ec3b00445..925d320dea86 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1892,7 +1892,7 @@ hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; +- simple-audio-card,name = "hdmi-sound"; ++ simple-audio-card,name = "HDMI"; + status = "disabled"; + + simple-audio-card,cpu { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 10 Feb 2021 18:44:56 +0200 +Subject: [PATCH] HACK: drm/gem: suppress warning about missing vm_flags + +Signed-off-by: Alex Bee +--- + drivers/gpu/drm/drm_gem.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c +index eb0c2d041f13..9256eadb8a3e 100644 +--- a/drivers/gpu/drm/drm_gem.c ++++ b/drivers/gpu/drm/drm_gem.c +@@ -1053,7 +1053,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, + ret = obj->funcs->mmap(obj, vma); + if (ret) + goto err_drm_gem_object_put; +- WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); ++ //WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); + } else { + if (!vma->vm_ops) { + ret = -EINVAL; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 25 Mar 2018 22:17:06 +0200 +Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation + +--- + sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------ + 1 file changed, 52 insertions(+), 61 deletions(-) + +diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c +index b773466619b2..e53950e85631 100644 +--- a/sound/soc/codecs/hdmi-codec.c ++++ b/sound/soc/codecs/hdmi-codec.c +@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { + */ + static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { + { .ca_id = 0x00, .n_ch = 2, +- .mask = FL | FR}, +- /* 2.1 */ +- { .ca_id = 0x01, .n_ch = 4, +- .mask = FL | FR | LFE}, +- /* Dolby Surround */ ++ .mask = FL | FR }, ++ { .ca_id = 0x03, .n_ch = 4, ++ .mask = FL | FR | LFE | FC }, + { .ca_id = 0x02, .n_ch = 4, + .mask = FL | FR | FC }, +- /* surround51 */ ++ { .ca_id = 0x01, .n_ch = 4, ++ .mask = FL | FR | LFE }, + { .ca_id = 0x0b, .n_ch = 6, +- .mask = FL | FR | LFE | FC | RL | RR}, +- /* surround40 */ +- { .ca_id = 0x08, .n_ch = 6, +- .mask = FL | FR | RL | RR }, +- /* surround41 */ +- { .ca_id = 0x09, .n_ch = 6, +- .mask = FL | FR | LFE | RL | RR }, +- /* surround50 */ ++ .mask = FL | FR | LFE | FC | RL | RR }, + { .ca_id = 0x0a, .n_ch = 6, + .mask = FL | FR | FC | RL | RR }, +- /* 6.1 */ +- { .ca_id = 0x0f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | RC }, +- /* surround71 */ ++ { .ca_id = 0x09, .n_ch = 6, ++ .mask = FL | FR | LFE | RL | RR }, ++ { .ca_id = 0x08, .n_ch = 6, ++ .mask = FL | FR | RL | RR }, ++ { .ca_id = 0x07, .n_ch = 6, ++ .mask = FL | FR | LFE | FC | RC }, ++ { .ca_id = 0x06, .n_ch = 6, ++ .mask = FL | FR | FC | RC }, ++ { .ca_id = 0x05, .n_ch = 6, ++ .mask = FL | FR | LFE | RC }, ++ { .ca_id = 0x04, .n_ch = 6, ++ .mask = FL | FR | RC }, + { .ca_id = 0x13, .n_ch = 8, + .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, +- /* others */ +- { .ca_id = 0x03, .n_ch = 8, +- .mask = FL | FR | LFE | FC }, +- { .ca_id = 0x04, .n_ch = 8, +- .mask = FL | FR | RC}, +- { .ca_id = 0x05, .n_ch = 8, +- .mask = FL | FR | LFE | RC }, +- { .ca_id = 0x06, .n_ch = 8, +- .mask = FL | FR | FC | RC }, +- { .ca_id = 0x07, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RC }, +- { .ca_id = 0x0c, .n_ch = 8, +- .mask = FL | FR | RC | RL | RR }, +- { .ca_id = 0x0d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RC }, +- { .ca_id = 0x0e, .n_ch = 8, +- .mask = FL | FR | FC | RL | RR | RC }, +- { .ca_id = 0x10, .n_ch = 8, +- .mask = FL | FR | RL | RR | RLC | RRC }, +- { .ca_id = 0x11, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, + { .ca_id = 0x12, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | RLC | RRC }, +- { .ca_id = 0x14, .n_ch = 8, +- .mask = FL | FR | FLC | FRC }, +- { .ca_id = 0x15, .n_ch = 8, +- .mask = FL | FR | LFE | FLC | FRC }, +- { .ca_id = 0x16, .n_ch = 8, +- .mask = FL | FR | FC | FLC | FRC }, +- { .ca_id = 0x17, .n_ch = 8, +- .mask = FL | FR | LFE | FC | FLC | FRC }, +- { .ca_id = 0x18, .n_ch = 8, +- .mask = FL | FR | RC | FLC | FRC }, +- { .ca_id = 0x19, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FLC | FRC }, +- { .ca_id = 0x1a, .n_ch = 8, +- .mask = FL | FR | RC | FC | FLC | FRC }, +- { .ca_id = 0x1b, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FC | FLC | FRC }, +- { .ca_id = 0x1c, .n_ch = 8, +- .mask = FL | FR | RL | RR | FLC | FRC }, +- { .ca_id = 0x1d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | FLC | FRC }, + { .ca_id = 0x1e, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | FLC | FRC }, +- { .ca_id = 0x1f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, ++ { .ca_id = 0x11, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | FLC | FRC }, ++ { .ca_id = 0x10, .n_ch = 8, ++ .mask = FL | FR | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1c, .n_ch = 8, ++ .mask = FL | FR | RL | RR | FLC | FRC }, ++ { .ca_id = 0x0f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | RC }, ++ { .ca_id = 0x1b, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0e, .n_ch = 8, ++ .mask = FL | FR | FC | RL | RR | RC }, ++ { .ca_id = 0x1a, .n_ch = 8, ++ .mask = FL | FR | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RC }, ++ { .ca_id = 0x19, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FLC | FRC }, ++ { .ca_id = 0x0c, .n_ch = 8, ++ .mask = FL | FR | RC | RL | RR }, ++ { .ca_id = 0x18, .n_ch = 8, ++ .mask = FL | FR | RC | FLC | FRC }, ++ { .ca_id = 0x17, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | FLC | FRC }, ++ { .ca_id = 0x16, .n_ch = 8, ++ .mask = FL | FR | FC | FLC | FRC }, ++ { .ca_id = 0x15, .n_ch = 8, ++ .mask = FL | FR | LFE | FLC | FRC }, ++ { .ca_id = 0x14, .n_ch = 8, ++ .mask = FL | FR | FLC | FRC }, + }; + + struct hdmi_codec_priv { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 27 Feb 2021 17:52:02 +0100 +Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1 board + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 40bf808642b9..27a1799027c2 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -57,6 +57,24 @@ ir-receiver { + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + linux,rc-map-name = "rc-beelink-gs1"; + }; ++ ++ spdif_sound: spdif-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_dit>; ++ }; ++ }; ++ ++ spdif_dit: spdif-dit { ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0>; ++ }; + }; + + &analog_sound { +@@ -325,6 +343,11 @@ &sdmmc { + status = "okay"; + }; + ++&spdif { ++ pinctrl-0 = <&spdifm0_tx>; ++ status = "okay"; ++}; ++ + &tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 27 Feb 2021 18:01:13 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add ir-receiver node for RK3328 ROC CC + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +index aa22a0c22265..a78fbddd21df 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator { + regulator-boot-on; + }; + ++ ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&ir_int>; ++ pinctrl-names = "default"; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -308,6 +315,13 @@ &io_domains { + }; + + &pinctrl { ++ ++ ir { ++ ir_int: ir-int { ++ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Mon, 1 Mar 2021 21:24:15 +0100 +Subject: [PATCH] ARM: dts: add cec pinctrl for RK3288 miqi board + +--- + arch/arm/boot/dts/rk3288-miqi.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts +index 8d30c49f406e..6d90db5a3b75 100644 +--- a/arch/arm/boot/dts/rk3288-miqi.dts ++++ b/arch/arm/boot/dts/rk3288-miqi.dts +@@ -145,6 +145,8 @@ &gpu { + + &hdmi { + ddc-i2c-bus = <&i2c5>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec_c0>; + status = "okay"; + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Mon, 1 Mar 2021 19:22:15 +0100 +Subject: [PATCH] HACK: arm64: dts: enable FE phy for Beelink A1 also + +--- + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 27a1799027c2..7de9dfa71d89 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 { + }; + }; + ++&gmac2phy { ++ clock_in_out = "output"; ++ assigned-clock-rate = <50000000>; ++ assigned-clocks = <&cru SCLK_MAC2PHY>; ++ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; ++ status = "okay"; ++}; ++ + &gpu { + mali-supply = <&vdd_logic>; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 26 Feb 2019 20:45:14 +0000 +Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error + +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +index c8f44bcb298a..d4280ce4542c 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +@@ -4,6 +4,7 @@ + * + * Copyright (C) 2015-2017 Russell King. + */ ++#include + #include + #include + #include +@@ -129,8 +130,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + + dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0); + +- if (stat & CEC_STAT_ERROR_INIT) { +- cec->tx_status = CEC_TX_STATUS_ERROR; ++ /* Status with both done and error_initiator bits have been seen ++ * on Rockchip RK3328 devices, transmit attempt seems to have failed ++ * when this happens, report as low drive and block cec-framework ++ * 100ms before core retransmits the failed message, this seems to ++ * mitigate the issue with failed transmit attempts. ++ */ ++ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) { ++ pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat); ++ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_DONE) { +@@ -141,6 +149,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + cec->tx_status = CEC_TX_STATUS_NACK; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; ++ } else if (stat & CEC_STAT_ERROR_INIT) { ++ cec->tx_status = CEC_TX_STATUS_ERROR; ++ cec->tx_done = true; ++ ret = IRQ_WAKE_THREAD; + } + + if (stat & CEC_STAT_EOM) { +@@ -173,6 +185,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data) + + if (cec->tx_done) { + cec->tx_done = false; ++ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE) ++ msleep(100); + cec_transmit_attempt_done(adap, cec->tx_status); + } + if (cec->rx_done) { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 5 May 2021 19:11:12 +0200 +Subject: [PATCH] arm64: boot: dts: Increase ACLK_PERILP0 clock rate for RK3399 + +As per vendor kernel. Leaving this clock at the lower rate will +result in poor DMA controller performance + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 925d320dea86..037732441f92 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1478,7 +1478,7 @@ cru: clock-controller@ff760000 { + <1000000000>, + <150000000>, <75000000>, + <37500000>, +- <100000000>, <100000000>, ++ <300000000>, <100000000>, + <50000000>, <600000000>, + <100000000>, <50000000>, + <400000000>, <400000000>, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 17:04:46 +0200 +Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 Beelink A1 + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 7de9dfa71d89..e857e5a727f4 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -389,6 +389,11 @@ &usb_host0_ehci { + status = "okay"; + }; + ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 30 Oct 2021 12:19:19 +0200 +Subject: [PATCH] WIP: drm: bridge: dw-hdmi: switch from .hw_parmas to .prepare + for i2s + +Seems to be the only way to get AES bits correctly as set by +userspace. +TODO: check other consequences. + +Signed-off-by: Alex Bee +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +index f50b47ac11a8..d9b3c8c29e6f 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +@@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset) + return audio->read(hdmi, offset); + } + +-static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, +- struct hdmi_codec_daifmt *fmt, +- struct hdmi_codec_params *hparms) ++static int dw_hdmi_i2s_prepare(struct device *dev, void *data, ++ struct hdmi_codec_daifmt *fmt, ++ struct hdmi_codec_params *hparms) + { + struct dw_hdmi_i2s_audio_data *audio = data; + struct dw_hdmi *hdmi = audio->hdmi; +@@ -178,7 +178,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(struct device *dev, void *data, + } + + static const struct hdmi_codec_ops dw_hdmi_i2s_ops = { +- .hw_params = dw_hdmi_i2s_hw_params, ++ .prepare = dw_hdmi_i2s_prepare, + .audio_startup = dw_hdmi_i2s_audio_startup, + .audio_shutdown = dw_hdmi_i2s_audio_shutdown, + .get_eld = dw_hdmi_i2s_get_eld, diff --git a/patch/kernel/archive/media-5.18/070-linux-2000-v4l2-wip-rkvdec-hevc.patch b/patch/kernel/archive/media-5.19/216-linux-2000-v4l2-wip-rkvdec-hevc.patch similarity index 97% rename from patch/kernel/archive/media-5.18/070-linux-2000-v4l2-wip-rkvdec-hevc.patch rename to patch/kernel/archive/media-5.19/216-linux-2000-v4l2-wip-rkvdec-hevc.patch index 78efb47a1..5d85089dd 100644 --- a/patch/kernel/archive/media-5.18/070-linux-2000-v4l2-wip-rkvdec-hevc.patch +++ b/patch/kernel/archive/media-5.19/216-linux-2000-v4l2-wip-rkvdec-hevc.patch @@ -11,7 +11,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index ef63bc205756..a808894e8c76 100644 +index 01ccda48d8c5..a536dab3f8a7 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h @@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { @@ -49,7 +49,7 @@ index ef63bc205756..a808894e8c76 100644 __u64 flags; }; -@@ -202,7 +207,10 @@ struct v4l2_ctrl_hevc_slice_params { +@@ -200,7 +205,10 @@ struct v4l2_ctrl_hevc_slice_params { __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; @@ -72,7 +72,7 @@ Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index a808894e8c76..f1b8756521b9 100644 +index a536dab3f8a7..c8618dc68fc7 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h @@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps { @@ -85,7 +85,7 @@ index a808894e8c76..f1b8756521b9 100644 __u64 flags; }; -@@ -210,7 +211,9 @@ struct v4l2_ctrl_hevc_slice_params { +@@ -208,7 +209,9 @@ struct v4l2_ctrl_hevc_slice_params { __u16 short_term_ref_pic_set_size; __u16 long_term_ref_pic_set_size; @@ -2338,13 +2338,13 @@ index 000000000000..c3cceba837c2 + memset(hw_ps, 0, sizeof(*hw_ps)); + + for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), + REF_PIC_LONG_TERM_L0(i)); + WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); + } + + for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), + REF_PIC_LONG_TERM_L1(i)); + WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); + } @@ -2665,10 +2665,10 @@ index 265f5234f4eb..4319ee3ccbbc 100644 #define RKVDEC_MODE_VP9 2 #define RKVDEC_RPS_MODE BIT(24) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 63385d92880e..7340972faead 100644 +index b6d5b26a93c2..7e8674e7d501 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -147,6 +147,58 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { +@@ -134,6 +134,58 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { }, }; @@ -2727,9 +2727,9 @@ index 63385d92880e..7340972faead 100644 static const struct rkvdec_ctrls rkvdec_h264_ctrls = { .ctrls = rkvdec_h264_ctrl_descs, .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), -@@ -199,6 +251,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), +@@ -187,6 +239,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .decoded_fmts = rkvdec_h264_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, }, + { + .fourcc = V4L2_PIX_FMT_HEVC_SLICE, @@ -2750,10 +2750,10 @@ index 63385d92880e..7340972faead 100644 .fourcc = V4L2_PIX_FMT_VP9_FRAME, .frmsize = { diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index f360f2ef799f..53719e825c70 100644 +index f02f79c405f0..d6222a2588be 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -131,6 +131,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); +@@ -133,6 +133,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; @@ -2858,7 +2858,7 @@ index c3cceba837c2..5c341b5fa534 100644 rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); - reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0); -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0); ++ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); } @@ -2874,10 +2874,10 @@ index c3cceba837c2..5c341b5fa534 100644 V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); run->slices_params = ctrl ? ctrl->p_cur.p : NULL; diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 7340972faead..722d9912b332 100644 +index 7e8674e7d501..0f877acfba27 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -163,6 +163,9 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { +@@ -150,6 +150,9 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { { .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, }, @@ -2894,18 +2894,54 @@ Date: Sat, 1 Aug 2020 12:24:58 +0000 Subject: [PATCH] WIP: media: rkvdec: add HEVC format validation --- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 11 +++++++++++ - drivers/staging/media/rkvdec/rkvdec.c | 23 +++++++++++++++++++++- - 2 files changed, 33 insertions(+), 1 deletion(-) + drivers/staging/media/rkvdec/rkvdec-hevc.c | 55 +++++++++++++++++++++- + drivers/staging/media/rkvdec/rkvdec.c | 3 +- + 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 5c341b5fa534..8ea2ad9f4f3a 100644 +index 5c341b5fa534..ac06039140bc 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2418,6 +2418,16 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, +@@ -2208,13 +2208,13 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + memset(hw_ps, 0, sizeof(*hw_ps)); + + for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { +- WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L0(i)); + WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); + } + + for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { +- WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L1(i)); + WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); + } +@@ -2418,17 +2418,58 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, return 0; } ++static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, ++ const struct v4l2_ctrl_hevc_sps *sps) ++{ ++ if (sps->chroma_format_idc > 1) ++ /* Only 4:0:0 and 4:2:0 are supported */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) ++ /* Luma and chroma bit depth mismatch */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) ++ /* Only 8-bit and 10-bit is supported */ ++ return -EINVAL; ++ ++ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || ++ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) ++ return -EINVAL; ++ ++ return 0; ++} ++ +static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) +{ + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; @@ -2919,46 +2955,53 @@ index 5c341b5fa534..8ea2ad9f4f3a 100644 static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) { struct rkvdec_dev *rkvdec = ctx->dev; -@@ -2521,6 +2531,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) + struct rkvdec_hevc_priv_tbl *priv_tbl; + struct rkvdec_hevc_ctx *hevc_ctx; ++ struct v4l2_ctrl *ctrl; + int ret; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_MPEG_VIDEO_HEVC_SPS); ++ if (!ctrl) ++ return -EINVAL; ++ ++ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ if (ret) ++ return ret; ++ + hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); + if (!hevc_ctx) + return -ENOMEM; + ++ + priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), + &hevc_ctx->priv_tbl.dma, GFP_KERNEL); + if (!priv_tbl) { +@@ -2519,9 +2560,19 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) + return 0; + } + ++static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) ++ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ ++ return 0; ++} ++ const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .valid_fmt = rkvdec_hevc_valid_fmt, .start = rkvdec_hevc_start, .stop = rkvdec_hevc_stop, .run = rkvdec_hevc_run, ++ .try_ctrl = rkvdec_hevc_try_ctrl, ++ .valid_fmt = rkvdec_hevc_valid_fmt, + }; diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 722d9912b332..62e728777cd4 100644 +index 0f877acfba27..9f6a619499ab 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -79,6 +79,26 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - if (width > ctx->coded_fmt.fmt.pix_mp.width || - height > ctx->coded_fmt.fmt.pix_mp.height) - return -EINVAL; -+ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) { -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) -+ /* Only current valid format */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; - } - return 0; - } -@@ -87,7 +107,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) +@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); @@ -2967,7 +3010,7 @@ index 722d9912b332..62e728777cd4 100644 ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); if (ctx->valid_fmt) { struct v4l2_pix_format_mplane *pix_mp; -@@ -156,6 +176,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { +@@ -143,6 +143,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { }, { .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, @@ -2988,7 +3031,7 @@ Signed-off-by: Alex Bee 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 8ea2ad9f4f3a..58ae8a1a4ff3 100644 +index ac06039140bc..99bfb937facc 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -2165,9 +2165,9 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, @@ -3015,7 +3058,7 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 58ae8a1a4ff3..55bf61a84165 100644 +index 99bfb937facc..b5bb4c083dbc 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -2196,8 +2196,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -3053,11 +3096,11 @@ Subject: [PATCH] WIP: media: rkvdec: hevc: implement lowdelay Signed-off-by: Alex Bee --- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) + drivers/staging/media/rkvdec/rkvdec-hevc.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 55bf61a84165..db33f9d357cf 100644 +index b5bb4c083dbc..8467084165df 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -2187,6 +2187,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -3076,13 +3119,14 @@ index 55bf61a84165..db33f9d357cf 100644 hw_ps = &priv_tbl->rps[j]; memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2211,18 +2213,23 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), +@@ -2211,18 +2213,24 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), REF_PIC_LONG_TERM_L0(i)); WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); + -+ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt[0] > sl_params->slice_pic_order_cnt) ++ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) + lowdelay = 0; ++ } for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { @@ -3090,7 +3134,7 @@ index 55bf61a84165..db33f9d357cf 100644 REF_PIC_LONG_TERM_L1(i)); WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); + -+ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt[0] > sl_params->slice_pic_order_cnt) ++ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) + lowdelay = 0; } @@ -3120,12 +3164,12 @@ the better soultion than duplicatiing code for every newly added IP. Signed-off-by: Alex Bee --- - drivers/staging/media/rkvdec/rkvdec.c | 104 ++++++++++++++++++-------- + drivers/staging/media/rkvdec/rkvdec.c | 105 ++++++++++++++++++-------- drivers/staging/media/rkvdec/rkvdec.h | 10 +++ - 2 files changed, 84 insertions(+), 30 deletions(-) + 2 files changed, 85 insertions(+), 30 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 62e728777cd4..a5552ccc9460 100644 +index 9f6a619499ab..2d1a388e20fe 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -14,6 +14,7 @@ @@ -3136,53 +3180,53 @@ index 62e728777cd4..a5552ccc9460 100644 #include #include #include -@@ -260,21 +261,6 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { +@@ -227,6 +228,22 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { }; static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { -- { -- .fourcc = V4L2_PIX_FMT_H264_SLICE, -- .frmsize = { -- .min_width = 48, -- .max_width = 4096, -- .step_width = 16, -- .min_height = 48, -- .max_height = 2304, -- .step_height = 16, -- }, -- .ctrls = &rkvdec_h264_ctrls, -- .ops = &rkvdec_h264_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -- .decoded_fmts = rkvdec_h264_decoded_fmts, -- }, - { - .fourcc = V4L2_PIX_FMT_HEVC_SLICE, - .frmsize = { -@@ -289,6 +275,23 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_hevc_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), - .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_HEVC, -+ }, + { -+ .fourcc = V4L2_PIX_FMT_H264_SLICE, ++ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, + .frmsize = { -+ .min_width = 48, ++ .min_width = 64, + .max_width = 4096, -+ .step_width = 16, -+ .min_height = 48, ++ .step_width = 64, ++ .min_height = 64, + .max_height = 2304, + .step_height = 16, + }, -+ .ctrls = &rkvdec_h264_ctrls, -+ .ops = &rkvdec_h264_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_decoded_fmts, ++ .ctrls = &rkvdec_hevc_ctrls, ++ .ops = &rkvdec_hevc_fmt_ops, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), ++ .decoded_fmts = rkvdec_hevc_decoded_fmts, ++ .capability = RKVDEC_CAPABILITY_HEVC, ++ }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .frmsize = { +@@ -242,21 +259,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), + .decoded_fmts = rkvdec_h264_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, +- }, +- { +- .fourcc = V4L2_PIX_FMT_HEVC_SLICE, +- .frmsize = { +- .min_width = 64, +- .max_width = 4096, +- .step_width = 64, +- .min_height = 64, +- .max_height = 2304, +- .step_height = 16, +- }, +- .ctrls = &rkvdec_hevc_ctrls, +- .ops = &rkvdec_hevc_fmt_ops, +- .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), +- .decoded_fmts = rkvdec_hevc_decoded_fmts, + .capability = RKVDEC_CAPABILITY_H264, }, { .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -304,16 +307,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -272,16 +275,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .ops = &rkvdec_vp9_fmt_ops, .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), .decoded_fmts = rkvdec_vp9_decoded_fmts, @@ -3217,7 +3261,7 @@ index 62e728777cd4..a5552ccc9460 100644 return &rkvdec_coded_fmts[i]; } -@@ -336,7 +354,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) +@@ -304,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) { struct v4l2_format *f = &ctx->coded_fmt; @@ -3226,7 +3270,7 @@ index 62e728777cd4..a5552ccc9460 100644 rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -@@ -363,11 +381,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, +@@ -331,11 +349,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, struct v4l2_frmsizeenum *fsize) { const struct rkvdec_coded_fmt_desc *fmt; @@ -3241,7 +3285,7 @@ index 62e728777cd4..a5552ccc9460 100644 if (!fmt) return -EINVAL; -@@ -438,10 +458,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, +@@ -406,10 +426,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); const struct rkvdec_coded_fmt_desc *desc; @@ -3256,7 +3300,7 @@ index 62e728777cd4..a5552ccc9460 100644 } v4l2_apply_frmsize_constraints(&pix_mp->width, -@@ -519,7 +540,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, +@@ -487,7 +508,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, if (ret) return ret; @@ -3266,7 +3310,7 @@ index 62e728777cd4..a5552ccc9460 100644 if (!desc) return -EINVAL; ctx->coded_fmt_desc = desc; -@@ -567,7 +589,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, +@@ -538,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, static int rkvdec_enum_output_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f) { @@ -3278,7 +3322,7 @@ index 62e728777cd4..a5552ccc9460 100644 return -EINVAL; f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; -@@ -975,14 +1000,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) +@@ -946,14 +971,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) int ret; for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) @@ -3300,7 +3344,7 @@ index 62e728777cd4..a5552ccc9460 100644 } ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -@@ -1186,8 +1214,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1157,8 +1185,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) } } @@ -3319,7 +3363,7 @@ index 62e728777cd4..a5552ccc9460 100644 { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1199,6 +1236,7 @@ static const char * const rkvdec_clk_names[] = { +@@ -1170,6 +1207,7 @@ static const char * const rkvdec_clk_names[] = { static int rkvdec_probe(struct platform_device *pdev) { struct rkvdec_dev *rkvdec; @@ -3327,7 +3371,7 @@ index 62e728777cd4..a5552ccc9460 100644 unsigned int i; int ret, irq; -@@ -1224,6 +1262,12 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1195,6 +1233,13 @@ static int rkvdec_probe(struct platform_device *pdev) if (ret) return ret; @@ -3336,12 +3380,13 @@ index 62e728777cd4..a5552ccc9460 100644 + return -EINVAL; + + rkvdec->capabilities = variant->capabilities; ++ + rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rkvdec->regs)) return PTR_ERR(rkvdec->regs); diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 53719e825c70..d2096ec351e1 100644 +index d6222a2588be..ad8e83884121 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -29,6 +29,10 @@ @@ -3366,15 +3411,15 @@ index 53719e825c70..d2096ec351e1 100644 struct rkvdec_coded_fmt_ops { int (*adjust_fmt)(struct rkvdec_ctx *ctx, struct v4l2_format *f); -@@ -89,6 +97,7 @@ struct rkvdec_coded_fmt_desc { - const struct rkvdec_coded_fmt_ops *ops; +@@ -91,6 +99,7 @@ struct rkvdec_coded_fmt_desc { unsigned int num_decoded_fmts; const u32 *decoded_fmts; + u32 subsystem_flags; + unsigned int capability; }; struct rkvdec_dev { -@@ -103,6 +112,7 @@ struct rkvdec_dev { +@@ -105,6 +114,7 @@ struct rkvdec_dev { struct delayed_work watchdog_work; struct reset_control *rstc; u8 reset_mask; @@ -3397,10 +3442,10 @@ Signed-off-by: Alex Bee 1 file changed, 8 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index a5552ccc9460..5fc6d30fd7c4 100644 +index 2d1a388e20fe..c2de6fcb6419 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1220,11 +1220,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { +@@ -1191,11 +1191,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { RKVDEC_CAPABILITY_VP9 }; @@ -3432,10 +3477,10 @@ Signed-off-by: Alex Bee 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index eb9d3bdf1d5e..2c1f0a7e0603 100644 +index 7b2cde230b87..59fba3ac6aae 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1247,6 +1247,25 @@ vpu_mmu: iommu@ff9a0800 { +@@ -1248,6 +1248,25 @@ vpu_mmu: iommu@ff9a0800 { power-domains = <&power RK3288_PD_VIDEO>; }; @@ -3461,7 +3506,7 @@ index eb9d3bdf1d5e..2c1f0a7e0603 100644 hevc_mmu: iommu@ff9c0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1254,7 +1273,7 @@ hevc_mmu: iommu@ff9c0440 { +@@ -1255,7 +1274,7 @@ hevc_mmu: iommu@ff9c0440 { clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -3470,3 +3515,27 @@ index eb9d3bdf1d5e..2c1f0a7e0603 100644 }; gpu: gpu@ffa30000 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 3 Apr 2022 14:39:14 +0200 +Subject: [PATCH] WIP: media: rkvdec: hevc: Use chroma_format_idc from + v4l2_ctrl_hevc_sps + +--- + drivers/staging/media/rkvdec/rkvdec-hevc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c +index 8467084165df..a7dc8262f6d7 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c ++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c +@@ -2048,7 +2048,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, + /* write sps */ + WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); + WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); +- WRITE_PPS(1, CHROMA_FORMAT_IDC); ++ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); + WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); + WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); + WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); diff --git a/patch/kernel/archive/media-5.18/080-linux-2001-v4l2-wip-iep-driver.patch b/patch/kernel/archive/media-5.19/217-linux-2001-v4l2-wip-iep-driver.patch similarity index 98% rename from patch/kernel/archive/media-5.18/080-linux-2001-v4l2-wip-iep-driver.patch rename to patch/kernel/archive/media-5.19/217-linux-2001-v4l2-wip-iep-driver.patch index 1fbe8f3bd..6ed5f6332 100644 --- a/patch/kernel/archive/media-5.18/080-linux-2001-v4l2-wip-iep-driver.patch +++ b/patch/kernel/archive/media-5.19/217-linux-2001-v4l2-wip-iep-driver.patch @@ -96,23 +96,46 @@ Subject: [PATCH] media: rockchip: Add Rockchip IEP driver Signed-off-by: Alex Bee --- - drivers/media/platform/Makefile | 1 + + drivers/media/platform/rockchip/Kconfig | 1 + + drivers/media/platform/rockchip/Makefile | 1 + + drivers/media/platform/rockchip/iep/Kconfig | 16 + drivers/media/platform/rockchip/iep/Makefile | 5 + .../media/platform/rockchip/iep/iep-regs.h | 291 +++++ - .../media/platform/rockchip/iep/Kconfig | 16 + drivers/media/platform/rockchip/iep/iep.c | 1089 +++++++++++++++++ drivers/media/platform/rockchip/iep/iep.h | 112 ++ - 6 files changed, 1512 insertions(+) + 7 files changed, 1515 insertions(+) + create mode 100644 drivers/media/platform/rockchip/iep/Kconfig create mode 100644 drivers/media/platform/rockchip/iep/Makefile create mode 100644 drivers/media/platform/rockchip/iep/iep-regs.h create mode 100644 drivers/media/platform/rockchip/iep/iep.c create mode 100644 drivers/media/platform/rockchip/iep/iep.h -diff --git /dev/null b/drivers/media/platform/rockchip/iep/Kconfig -index cf4adc64c953..79b850a71449 100644 +diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig +index b41d3960c1b4..9ff362805ded 100644 +--- a/drivers/media/platform/rockchip/Kconfig ++++ b/drivers/media/platform/rockchip/Kconfig +@@ -2,5 +2,6 @@ + + comment "Rockchip media platform drivers" + ++source "drivers/media/platform/rockchip/iep/Kconfig" + source "drivers/media/platform/rockchip/rga/Kconfig" + source "drivers/media/platform/rockchip/rkisp1/Kconfig" +diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile +index 4f782b876ac9..c075ecc2fa14 100644 +--- a/drivers/media/platform/rockchip/Makefile ++++ b/drivers/media/platform/rockchip/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only ++obj-y += iep/ + obj-y += rga/ + obj-y += rkisp1/ +diff --git a/drivers/media/platform/rockchip/iep/Kconfig b/drivers/media/platform/rockchip/iep/Kconfig +new file mode 100644 +index 000000000000..d95155a95133 --- /dev/null +++ b/drivers/media/platform/rockchip/iep/Kconfig -@@ -0,0 +1,16 @@ config VIDEO_RENESAS_VSP1 +@@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config VIDEO_ROCKCHIP_IEP @@ -129,25 +152,6 @@ index cf4adc64c953..79b850a71449 100644 + images. The driver currently implements YUV deinterlacing only. + To compile this driver as a module, choose M here: the module + will be called rockchip-iep -diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig ---- a/drivers/media/platform/rockchip/Kconfig 2022-04-24 04:43:48.781195873 +0000 -+++ b/drivers/media/platform/rockchip/Kconfig 2022-04-24 04:39:04.394777975 +0000 -@@ -2,5 +2,6 @@ - - comment "Rockchip media platform drivers" - -+source "drivers/media/platform/rockchip/iep/Kconfig" - source "drivers/media/platform/rockchip/rga/Kconfig" - source "drivers/media/platform/rockchip/rkisp1/Kconfig" -diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile -index a148553babfc..08fcccdbbb49 100644 ---- a/drivers/media/platform/rockchip/Makefile -+++ b/drivers/media/platform/rockchip/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only -+obj-y += iep/ - obj-y += rga/ - obj-y += rkisp1/ diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile new file mode 100644 index 000000000000..5c89b3277469 @@ -1683,7 +1687,7 @@ Signed-off-by: Alex Bee 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index e4c6a33b4b7e..54a3d0022363 100644 +index e4977669b16a..6c0cbc9cea61 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -760,6 +760,28 @@ vop_mmu: iommu@ff373f00 { @@ -1727,10 +1731,10 @@ Signed-off-by: Alex Bee 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index b39a3390bd7d..f9769857d147 100644 +index 037732441f92..d90c90406a49 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1346,14 +1346,25 @@ vdec_mmu: iommu@ff660480 { +@@ -1367,14 +1367,25 @@ vdec_mmu: iommu@ff660480 { #iommu-cells = <0>; }; @@ -1769,11 +1773,11 @@ Signed-off-by: Alex Bee 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 2c1f0a7e0603..afcc4d9ec746 100644 +index 59fba3ac6aae..06545f423de2 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -983,14 +983,25 @@ crypto: cypto-controller@ff8a0000 { - status = "okay"; +@@ -984,14 +984,25 @@ crypto: crypto@ff8a0000 { + reset-names = "crypto-rst"; }; + iep: iep@ff90000 { diff --git a/patch/kernel/archive/media-5.19/070-v91-i2s-mclk.patch b/patch/kernel/archive/media-6.0/070-v91-i2s-mclk.patch similarity index 100% rename from patch/kernel/archive/media-5.19/070-v91-i2s-mclk.patch rename to patch/kernel/archive/media-6.0/070-v91-i2s-mclk.patch diff --git a/patch/kernel/archive/media-5.19/080--v91-irq-gic-v3-its.patch b/patch/kernel/archive/media-6.0/080--v91-irq-gic-v3-its.patch similarity index 100% rename from patch/kernel/archive/media-5.19/080--v91-irq-gic-v3-its.patch rename to patch/kernel/archive/media-6.0/080--v91-irq-gic-v3-its.patch diff --git a/patch/kernel/archive/media-5.19/090-v91-rk356x-vpu.patch b/patch/kernel/archive/media-6.0/090-v91-rk356x-vpu.patch similarity index 100% rename from patch/kernel/archive/media-5.19/090-v91-rk356x-vpu.patch rename to patch/kernel/archive/media-6.0/090-v91-rk356x-vpu.patch diff --git a/patch/kernel/archive/media-6.0/091-rk356x-dtsi.patch b/patch/kernel/archive/media-6.0/091-rk356x-dtsi.patch new file mode 100644 index 000000000..210d1e567 --- /dev/null +++ b/patch/kernel/archive/media-6.0/091-rk356x-dtsi.patch @@ -0,0 +1,38 @@ +--- v6.0-rc3/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ v6.0-rc3/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -287,7 +287,7 @@ + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; +- dr_mode = "otg"; ++ dr_mode = "host"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG0>; +@@ -1031,6 +1031,25 @@ + status = "disabled"; + }; + ++ i2s2_2ch: i2s@fe420000 { ++ compatible = "rockchip,rk3568-i2s-tdm"; ++ reg = <0x0 0xfe420000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac1 4>, <&dmac1 5>; ++ dma-names = "tx", "rx"; ++ rockchip,cru = <&cru>; ++ rockchip,grf = <&grf>; ++ pinctrl-0 = <&i2s2m0_sclktx ++ &i2s2m0_lrcktx ++ &i2s2m0_sdi ++ &i2s2m0_sdo>; ++ pinctrl-names = "default"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s3_2ch: i2s@fe430000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe430000 0x0 0x1000>; + diff --git a/patch/kernel/archive/media-5.19/100-v95-make.patch b/patch/kernel/archive/media-6.0/100-v95-make.patch similarity index 100% rename from patch/kernel/archive/media-5.19/100-v95-make.patch rename to patch/kernel/archive/media-6.0/100-v95-make.patch diff --git a/patch/kernel/archive/station-p2-5.18/0480-v95-rk3566-firefly-roc-pc.patch b/patch/kernel/archive/media-6.0/110-v95-rk3566-firefly-roc-pc.patch similarity index 99% rename from patch/kernel/archive/station-p2-5.18/0480-v95-rk3566-firefly-roc-pc.patch rename to patch/kernel/archive/media-6.0/110-v95-rk3566-firefly-roc-pc.patch index 50fba90da..b1024cbfe 100644 --- a/patch/kernel/archive/station-p2-5.18/0480-v95-rk3566-firefly-roc-pc.patch +++ b/patch/kernel/archive/media-6.0/110-v95-rk3566-firefly-roc-pc.patch @@ -49,7 +49,7 @@ index 000000000..fac2db500 + + hdmi-con { + compatible = "hdmi-connector"; -+ type = "c"; ++ type = "a"; + + port { + hdmi_con_in: endpoint { @@ -682,7 +682,7 @@ index 000000000..fac2db500 +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; -+ status = "okay"; ++ status = "disabled"; +}; + +&uart1 { diff --git a/patch/kernel/archive/station-p2-5.18/0500-v95-rk3568-bpi-r2-pro.patch b/patch/kernel/archive/media-6.0/120-v95-rk3568-bpi-r2pro.patch similarity index 53% rename from patch/kernel/archive/station-p2-5.18/0500-v95-rk3568-bpi-r2-pro.patch rename to patch/kernel/archive/media-6.0/120-v95-rk3568-bpi-r2pro.patch index f99a959c4..bc0a10085 100644 --- a/patch/kernel/archive/station-p2-5.18/0500-v95-rk3568-bpi-r2-pro.patch +++ b/patch/kernel/archive/media-6.0/120-v95-rk3568-bpi-r2pro.patch @@ -23,84 +23,7 @@ }; hdmi-con { -@@ -76,9 +85,75 @@ - vin-supply = <&dc_12v>; - }; - -- vcc5v0_sys: vcc5v0-sys { -+ vcc5v0_sys: vcc5v0_sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ pcie30_avdd0v9: pcie30-avdd0v9 { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ pcie30_avdd1v8: pcie30-avdd1v8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie30_avdd1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ /* pi6c pcie clock generator feeds both ports */ -+ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ startup-delay-us = <200000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ -+ vcc3v3_minipcie: vcc3v3-minipcie-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_minipcie"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc3v3_pi6c_05>; -+ }; -+ -+ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ -+ vcc3v3_ngff: vcc3v3-ngff-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_ngff"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc3v3_pi6c_05>; -+ }; -+ -+ vbus: vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; -@@ -119,6 +194,28 @@ +@@ -119,6 +128,28 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc5v0_usb>; }; @@ -129,7 +52,7 @@ }; &combphy0 { -@@ -134,6 +231,39 @@ +@@ -134,6 +165,39 @@ &combphy2 { /* used for SATA */ status = "okay"; @@ -169,17 +92,10 @@ }; &gmac0 { -@@ -209,18 +339,56 @@ - }; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ +@@ -216,15 +280,49 @@ &i2c0 { status = "okay"; -+ + + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; @@ -198,7 +114,7 @@ + regulator-off-in-suspend; + }; + }; - ++ rk809: pmic@20 { compatible = "rockchip,rk809"; reg = <0x20>; @@ -228,27 +144,21 @@ vcc1-supply = <&vcc3v3_sys>; vcc2-supply = <&vcc3v3_sys>; vcc3-supply = <&vcc3v3_sys>; -@@ -424,12 +592,32 @@ +@@ -427,6 +525,10 @@ + regulator-off-in-suspend; }; }; - }; ++ }; + + codec { + mic-in-differential; -+ }; + }; }; }; +@@ -458,6 +560,18 @@ + status = "okay"; + }; - &i2c5 { - /* pin 3 (SDA) + 4 (SCL) of header con2 */ - status = "disabled"; -+}; -+ -+&i2s0_8ch { -+ /* hdmi sound */ -+ status = "okay"; -+}; -+ +&i2s1_8ch { + /* headphone */ + pinctrl-names = "default"; @@ -257,39 +167,14 @@ + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; -+ status = "okay"; - }; - - &mdio1 { -@@ -439,6 +627,27 @@ - }; - }; - -+&pcie30phy { -+ lane-map = /bits/ 8 <1 2>; + status = "okay"; +}; + -+&pcie3x1 { -+ /* M.2 slot */ -+ num-lanes = <1>; -+ reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_ngff>; -+ status = "okay"; -+}; + -+&pcie3x2 { -+ /* mPCIe slot */ -+ num-lanes = <1>; -+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_minipcie>; -+ status = "okay"; -+}; -+ - &pinctrl { - leds { - blue_led_pin: blue-led-pin { -@@ -463,6 +672,12 @@ + &mdio0 { + #address-cells = <1>; + #size-cells = <0>; +@@ -543,6 +657,12 @@ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -302,24 +187,4 @@ }; }; }; -@@ -628,6 +843,19 @@ - status = "okay"; - }; - -+&usb2phy1 { -+ /* USB for PCIe/M2 */ -+ status = "okay"; -+}; -+ -+&usb2phy1_host { -+ status = "okay"; -+}; -+ -+&usb2phy1_otg { -+ status = "okay"; -+}; -+ - &vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; diff --git a/patch/kernel/archive/station-p2-5.18/0510-v95-rk3568-firefly-roc-pc.patch b/patch/kernel/archive/media-6.0/140-v95-rk3568-firefly-roc-pc.patch similarity index 99% rename from patch/kernel/archive/station-p2-5.18/0510-v95-rk3568-firefly-roc-pc.patch rename to patch/kernel/archive/media-6.0/140-v95-rk3568-firefly-roc-pc.patch index da684a0ca..9877db2fb 100644 --- a/patch/kernel/archive/station-p2-5.18/0510-v95-rk3568-firefly-roc-pc.patch +++ b/patch/kernel/archive/media-6.0/140-v95-rk3568-firefly-roc-pc.patch @@ -51,7 +51,7 @@ index 000000000..fac2db500 + + hdmi-con { + compatible = "hdmi-connector"; -+ type = "c"; ++ type = "a"; + + port { + hdmi_con_in: endpoint { diff --git a/patch/kernel/archive/media-5.18/010-linux-0002-rockchip-from-list.patch b/patch/kernel/archive/media-6.0/210-linux-0002-rockchip-from-list.patch similarity index 100% rename from patch/kernel/archive/media-5.18/010-linux-0002-rockchip-from-list.patch rename to patch/kernel/archive/media-6.0/210-linux-0002-rockchip-from-list.patch diff --git a/patch/kernel/archive/media-5.18/090-linux-90100-add-clock.patch b/patch/kernel/archive/media-6.0/220-linux-90100-add-clock.patch similarity index 100% rename from patch/kernel/archive/media-5.18/090-linux-90100-add-clock.patch rename to patch/kernel/archive/media-6.0/220-linux-90100-add-clock.patch diff --git a/patch/kernel/archive/media-5.18/100-linux-90101-add-rt5651-konf.patch b/patch/kernel/archive/media-6.0/230-linux-90101-add-rt5651-konf.patch similarity index 100% rename from patch/kernel/archive/media-5.18/100-linux-90101-add-rt5651-konf.patch rename to patch/kernel/archive/media-6.0/230-linux-90101-add-rt5651-konf.patch diff --git a/patch/kernel/archive/media-5.18/110-linux-90102-rt5651.patch b/patch/kernel/archive/media-6.0/240-linux-90102-rt5651.patch similarity index 100% rename from patch/kernel/archive/media-5.18/110-linux-90102-rt5651.patch rename to patch/kernel/archive/media-6.0/240-linux-90102-rt5651.patch diff --git a/patch/kernel/archive/media-5.18/120-linux-90103-nanopc-t4-5651.patch b/patch/kernel/archive/media-6.0/250-linux-90103-nanopc-t4-5651.patch similarity index 100% rename from patch/kernel/archive/media-5.18/120-linux-90103-nanopc-t4-5651.patch rename to patch/kernel/archive/media-6.0/250-linux-90103-nanopc-t4-5651.patch diff --git a/patch/kernel/archive/media-5.18/130-linux-90104-all-codec.patch b/patch/kernel/archive/media-6.0/260-linux-90104-all-codec.patch similarity index 100% rename from patch/kernel/archive/media-5.18/130-linux-90104-all-codec.patch rename to patch/kernel/archive/media-6.0/260-linux-90104-all-codec.patch diff --git a/patch/kernel/archive/media-5.18/140-linux-90117-add-rk3399-roc-pc-plus-sound.patch b/patch/kernel/archive/media-6.0/270-linux-90117-add-rk3399-roc-pc-plus-sound.patch similarity index 100% rename from patch/kernel/archive/media-5.18/140-linux-90117-add-rk3399-roc-pc-plus-sound.patch rename to patch/kernel/archive/media-6.0/270-linux-90117-add-rk3399-roc-pc-plus-sound.patch diff --git a/patch/kernel/archive/media-5.18/150-linux-90200-rk3328-roc-pc-wifi-fix.patch b/patch/kernel/archive/media-6.0/280-linux-90200-rk3328-roc-pc-wifi-fix.patch similarity index 100% rename from patch/kernel/archive/media-5.18/150-linux-90200-rk3328-roc-pc-wifi-fix.patch rename to patch/kernel/archive/media-6.0/280-linux-90200-rk3328-roc-pc-wifi-fix.patch diff --git a/patch/kernel/archive/media-5.18/160-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch b/patch/kernel/archive/media-6.0/290-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch similarity index 100% rename from patch/kernel/archive/media-5.18/160-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch rename to patch/kernel/archive/media-6.0/290-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch diff --git a/patch/kernel/archive/media-5.18/170-add-fusb30x-driver.patch b/patch/kernel/archive/media-6.0/300-add-fusb30x-driver.patch similarity index 100% rename from patch/kernel/archive/media-5.18/170-add-fusb30x-driver.patch rename to patch/kernel/archive/media-6.0/300-add-fusb30x-driver.patch diff --git a/patch/kernel/archive/media-6.0/310-add-rk3328-usb3-phy-driver.patch b/patch/kernel/archive/media-6.0/310-add-rk3328-usb3-phy-driver.patch new file mode 100644 index 000000000..1a74d6c25 --- /dev/null +++ b/patch/kernel/archive/media-6.0/310-add-rk3328-usb3-phy-driver.patch @@ -0,0 +1,1456 @@ +Add the rockchip innosilicon usb3 phy driver, supporting devices such as the rk3328. +Pulled from: +https://github.com/FireflyTeam/kernel/blob/roc-rk3328-cc/drivers/phy/rockchip/phy-rockchip-inno-usb3.c + +Signed-off-by: Peter Geis +--- + drivers/phy/rockchip/Kconfig | 9 + + drivers/phy/rockchip/Makefile | 1 + + drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 1107 +++++++++++++++++ + 3 files changed, 1117 insertions(+) + create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c + +diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig +index c454c90cd99e..766407939d4a 100644 +--- a/drivers/phy/rockchip/Kconfig ++++ b/drivers/phy/rockchip/Kconfig +@@ -35,6 +35,15 @@ config PHY_ROCKCHIP_INNO_USB2 + help + Support for Rockchip USB2.0 PHY with Innosilicon IP block. + ++config PHY_ROCKCHIP_INNO_USB3 ++ tristate "Rockchip INNO USB 3.0 PHY Driver" ++ depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF ++ depends on USB_SUPPORT ++ select GENERIC_PHY ++ select USB_PHY ++ help ++ Support for Rockchip USB 3.0 PHY with Innosilicon IP block. ++ + config PHY_ROCKCHIP_PCIE + tristate "Rockchip PCIe PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST +diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile +index fd21cbaf40dd..d7b3d16c19ae 100644 +--- a/drivers/phy/rockchip/Makefile ++++ b/drivers/phy/rockchip/Makefile +@@ -3,6 +3,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o ++obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o + obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o + obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o + obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb3.c b/drivers/phy/rockchip/phy-rockchip-inno-usb3.c +new file mode 100644 +index 000000000000..31fee8f3a705 +--- /dev/null ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb3.c +@@ -0,0 +1,1107 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Rockchip USB 3.0 PHY with Innosilicon IP block driver ++ * ++ * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define U3PHY_PORT_NUM 2 ++#define BIT_WRITEABLE_SHIFT 16 ++#define SCHEDULE_DELAY (60 * HZ) ++ ++#define U3PHY_APB_RST BIT(0) ++#define U3PHY_POR_RST BIT(1) ++#define U3PHY_MAC_RST BIT(2) ++ ++struct rockchip_u3phy; ++struct rockchip_u3phy_port; ++ ++enum rockchip_u3phy_type { ++ U3PHY_TYPE_PIPE, ++ U3PHY_TYPE_UTMI, ++}; ++ ++enum rockchip_u3phy_pipe_pwr { ++ PIPE_PWR_P0 = 0, ++ PIPE_PWR_P1 = 1, ++ PIPE_PWR_P2 = 2, ++ PIPE_PWR_P3 = 3, ++ PIPE_PWR_MAX = 4, ++}; ++ ++enum rockchip_u3phy_rest_req { ++ U3_POR_RSTN = 0, ++ U2_POR_RSTN = 1, ++ PIPE_MAC_RSTN = 2, ++ UTMI_MAC_RSTN = 3, ++ PIPE_APB_RSTN = 4, ++ UTMI_APB_RSTN = 5, ++ U3PHY_RESET_MAX = 6, ++}; ++ ++enum rockchip_u3phy_utmi_state { ++ PHY_UTMI_HS_ONLINE = 0, ++ PHY_UTMI_DISCONNECT = 1, ++ PHY_UTMI_CONNECT = 2, ++ PHY_UTMI_FS_LS_ONLINE = 4, ++}; ++ ++/* ++ * @rvalue: reset value ++ * @dvalue: desired value ++ */ ++struct u3phy_reg { ++ unsigned int offset; ++ unsigned int bitend; ++ unsigned int bitstart; ++ unsigned int rvalue; ++ unsigned int dvalue; ++}; ++ ++struct rockchip_u3phy_grfcfg { ++ struct u3phy_reg um_suspend; ++ struct u3phy_reg ls_det_en; ++ struct u3phy_reg ls_det_st; ++ struct u3phy_reg um_ls; ++ struct u3phy_reg um_hstdct; ++ struct u3phy_reg u2_only_ctrl; ++ struct u3phy_reg u3_disable; ++ struct u3phy_reg pp_pwr_st; ++ struct u3phy_reg pp_pwr_en[PIPE_PWR_MAX]; ++}; ++ ++/** ++ * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration. ++ * @u2_pre_emp: usb2-phy pre-emphasis tuning. ++ * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning. ++ * @u2_odt_tuning: usb2-phy odt 45ohm tuning. ++ */ ++struct rockchip_u3phy_apbcfg { ++ unsigned int u2_pre_emp; ++ unsigned int u2_pre_emp_sth; ++ unsigned int u2_odt_tuning; ++}; ++ ++struct rockchip_u3phy_cfg { ++ unsigned int reg; ++ const struct rockchip_u3phy_grfcfg grfcfg; ++ ++ int (*phy_pipe_power)(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ bool on); ++ int (*phy_tuning)(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ struct device_node *child_np); ++}; ++ ++struct rockchip_u3phy_port { ++ struct phy *phy; ++ void __iomem *base; ++ unsigned int index; ++ unsigned char type; ++ bool suspended; ++ bool refclk_25m_quirk; ++ struct mutex mutex; /* mutex for updating register */ ++ struct delayed_work um_sm_work; ++}; ++ ++struct rockchip_u3phy { ++ struct device *dev; ++ struct regmap *u3phy_grf; ++ struct regmap *grf; ++ int um_ls_irq; ++ struct clk **clks; ++ int num_clocks; ++ struct dentry *root; ++ struct gpio_desc *vbus_drv_gpio; ++ struct reset_control *rsts[U3PHY_RESET_MAX]; ++ struct rockchip_u3phy_apbcfg apbcfg; ++ const struct rockchip_u3phy_cfg *cfgs; ++ struct rockchip_u3phy_port ports[U3PHY_PORT_NUM]; ++ struct usb_phy usb_phy; ++}; ++ ++static inline int param_write(void __iomem *base, ++ const struct u3phy_reg *reg, bool desired) ++{ ++ unsigned int val, mask; ++ unsigned int tmp = desired ? reg->dvalue : reg->rvalue; ++ int ret = 0; ++ ++ mask = GENMASK(reg->bitend, reg->bitstart); ++ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); ++ ret = regmap_write(base, reg->offset, val); ++ ++ return ret; ++} ++ ++static inline bool param_exped(void __iomem *base, ++ const struct u3phy_reg *reg, ++ unsigned int value) ++{ ++ int ret; ++ unsigned int tmp, orig; ++ unsigned int mask = GENMASK(reg->bitend, reg->bitstart); ++ ++ ret = regmap_read(base, reg->offset, &orig); ++ if (ret) ++ return false; ++ ++ tmp = (orig & mask) >> reg->bitstart; ++ return tmp == value; ++} ++ ++static int rockchip_u3phy_usb2_only_show(struct seq_file *s, void *unused) ++{ ++ struct rockchip_u3phy *u3phy = s->private; ++ ++ if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) ++ dev_info(u3phy->dev, "u2\n"); ++ else ++ dev_info(u3phy->dev, "u3\n"); ++ ++ return 0; ++} ++ ++static int rockchip_u3phy_usb2_only_open(struct inode *inode, ++ struct file *file) ++{ ++ return single_open(file, rockchip_u3phy_usb2_only_show, ++ inode->i_private); ++} ++ ++static ssize_t rockchip_u3phy_usb2_only_write(struct file *file, ++ const char __user *ubuf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct rockchip_u3phy *u3phy = s->private; ++ struct rockchip_u3phy_port *u3phy_port; ++ char buf[32]; ++ u8 index; ++ ++ if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) ++ return -EFAULT; ++ ++ if (!strncmp(buf, "u3", 2) && ++ param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) { ++ dev_info(u3phy->dev, "Set usb3.0 and usb2.0 mode successfully\n"); ++ ++ gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 0); ++ ++ param_write(u3phy->grf, ++ &u3phy->cfgs->grfcfg.u3_disable, false); ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.u2_only_ctrl, false); ++ ++ for (index = 0; index < U3PHY_PORT_NUM; index++) { ++ u3phy_port = &u3phy->ports[index]; ++ /* enable u3 rx termimation */ ++ if (u3phy_port->type == U3PHY_TYPE_PIPE) ++ writel(0x30, u3phy_port->base + 0xd8); ++ } ++ ++ atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); ++ ++ gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 1); ++ } else if (!strncmp(buf, "u2", 2) && ++ param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) { ++ dev_info(u3phy->dev, "Set usb2.0 only mode successfully\n"); ++ ++ gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 0); ++ ++ param_write(u3phy->grf, ++ &u3phy->cfgs->grfcfg.u3_disable, true); ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.u2_only_ctrl, true); ++ ++ for (index = 0; index < U3PHY_PORT_NUM; index++) { ++ u3phy_port = &u3phy->ports[index]; ++ /* disable u3 rx termimation */ ++ if (u3phy_port->type == U3PHY_TYPE_PIPE) ++ writel(0x20, u3phy_port->base + 0xd8); ++ } ++ ++ atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); ++ ++ gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 1); ++ } else { ++ dev_info(u3phy->dev, "Same or illegal mode\n"); ++ } ++ ++ return count; ++} ++ ++static const struct file_operations rockchip_u3phy_usb2_only_fops = { ++ .open = rockchip_u3phy_usb2_only_open, ++ .write = rockchip_u3phy_usb2_only_write, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++int rockchip_u3phy_debugfs_init(struct rockchip_u3phy *u3phy) ++{ ++ struct dentry *root; ++ struct dentry *file; ++ int ret; ++ ++ root = debugfs_create_dir(dev_name(u3phy->dev), NULL); ++ if (!root) { ++ ret = -ENOMEM; ++ goto err0; ++ } ++ ++ u3phy->root = root; ++ ++ file = debugfs_create_file("u3phy_mode", 0644, root, ++ u3phy, &rockchip_u3phy_usb2_only_fops); ++ if (!file) { ++ ret = -ENOMEM; ++ goto err1; ++ } ++ return 0; ++ ++err1: ++ debugfs_remove_recursive(root); ++err0: ++ return ret; ++} ++ ++static const char *get_rest_name(enum rockchip_u3phy_rest_req rst) ++{ ++ switch (rst) { ++ case U2_POR_RSTN: ++ return "u3phy-u2-por"; ++ case U3_POR_RSTN: ++ return "u3phy-u3-por"; ++ case PIPE_MAC_RSTN: ++ return "u3phy-pipe-mac"; ++ case UTMI_MAC_RSTN: ++ return "u3phy-utmi-mac"; ++ case UTMI_APB_RSTN: ++ return "u3phy-utmi-apb"; ++ case PIPE_APB_RSTN: ++ return "u3phy-pipe-apb"; ++ default: ++ return "invalid"; ++ } ++} ++ ++static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy, ++ unsigned int flag) ++{ ++ int rst; ++ ++ if (flag & U3PHY_APB_RST) { ++ dev_dbg(u3phy->dev, "deassert APB bus interface reset\n"); ++ for (rst = PIPE_APB_RSTN; rst <= UTMI_APB_RSTN; rst++) { ++ if (u3phy->rsts[rst]) ++ reset_control_deassert(u3phy->rsts[rst]); ++ } ++ } ++ ++ if (flag & U3PHY_POR_RST) { ++ usleep_range(12, 15); ++ dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n"); ++ for (rst = U3_POR_RSTN; rst <= U2_POR_RSTN; rst++) { ++ if (u3phy->rsts[rst]) ++ reset_control_deassert(u3phy->rsts[rst]); ++ } ++ } ++ ++ if (flag & U3PHY_MAC_RST) { ++ usleep_range(1200, 1500); ++ dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n"); ++ for (rst = PIPE_MAC_RSTN; rst <= UTMI_MAC_RSTN; rst++) ++ if (u3phy->rsts[rst]) ++ reset_control_deassert(u3phy->rsts[rst]); ++ } ++} ++ ++static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy) ++{ ++ int rst; ++ ++ dev_dbg(u3phy->dev, "assert u3phy reset\n"); ++ for (rst = 0; rst < U3PHY_RESET_MAX; rst++) ++ if (u3phy->rsts[rst]) ++ reset_control_assert(u3phy->rsts[rst]); ++} ++ ++static int rockchip_u3phy_clk_enable(struct rockchip_u3phy *u3phy) ++{ ++ int ret, clk; ++ ++ for (clk = 0; clk < u3phy->num_clocks && u3phy->clks[clk]; clk++) { ++ ret = clk_prepare_enable(u3phy->clks[clk]); ++ if (ret) ++ goto err_disable_clks; ++ } ++ return 0; ++ ++err_disable_clks: ++ while (--clk >= 0) ++ clk_disable_unprepare(u3phy->clks[clk]); ++ return ret; ++} ++ ++static void rockchip_u3phy_clk_disable(struct rockchip_u3phy *u3phy) ++{ ++ int clk; ++ ++ for (clk = u3phy->num_clocks - 1; clk >= 0; clk--) ++ if (u3phy->clks[clk]) ++ clk_disable_unprepare(u3phy->clks[clk]); ++} ++ ++static int rockchip_u3phy_init(struct phy *phy) ++{ ++ return 0; ++} ++ ++static int rockchip_u3phy_exit(struct phy *phy) ++{ ++ return 0; ++} ++ ++static int rockchip_u3phy_power_on(struct phy *phy) ++{ ++ struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy); ++ struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); ++ int ret; ++ ++ dev_info(&u3phy_port->phy->dev, "u3phy %s power on\n", ++ (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); ++ ++ if (!u3phy_port->suspended) ++ return 0; ++ ++ ret = rockchip_u3phy_clk_enable(u3phy); ++ if (ret) ++ return ret; ++ ++ if (u3phy_port->type == U3PHY_TYPE_UTMI) { ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.um_suspend, false); ++ } else { ++ /* current in p2 ? */ ++ if (param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2)) ++ goto done; ++ ++ if (u3phy->cfgs->phy_pipe_power) { ++ dev_dbg(u3phy->dev, "do pipe power up\n"); ++ u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true); ++ } ++ ++ /* exit to p0 */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); ++ usleep_range(90, 100); ++ ++ /* enter to p2 from p0 */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2], ++ false); ++ udelay(3); ++ } ++ ++done: ++ u3phy_port->suspended = false; ++ return 0; ++} ++ ++static int rockchip_u3phy_power_off(struct phy *phy) ++{ ++ struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy); ++ struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); ++ ++ dev_info(&u3phy_port->phy->dev, "u3phy %s power off\n", ++ (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); ++ ++ if (u3phy_port->suspended) ++ return 0; ++ ++ if (u3phy_port->type == U3PHY_TYPE_UTMI) { ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.um_suspend, true); ++ } else { ++ /* current in p3 ? */ ++ if (param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3)) ++ goto done; ++ ++ /* exit to p0 */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); ++ udelay(2); ++ ++ /* enter to p3 from p0 */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true); ++ udelay(6); ++ ++ if (u3phy->cfgs->phy_pipe_power) { ++ dev_dbg(u3phy->dev, "do pipe power down\n"); ++ u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false); ++ } ++ } ++ ++done: ++ rockchip_u3phy_clk_disable(u3phy); ++ u3phy_port->suspended = true; ++ return 0; ++} ++ ++static __maybe_unused ++struct phy *rockchip_u3phy_xlate(struct device *dev, ++ struct of_phandle_args *args) ++{ ++ struct rockchip_u3phy *u3phy = dev_get_drvdata(dev); ++ struct rockchip_u3phy_port *u3phy_port = NULL; ++ struct device_node *phy_np = args->np; ++ int index; ++ ++ if (args->args_count != 1) { ++ dev_err(dev, "invalid number of cells in 'phy' property\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ for (index = 0; index < U3PHY_PORT_NUM; index++) { ++ if (phy_np == u3phy->ports[index].phy->dev.of_node) { ++ u3phy_port = &u3phy->ports[index]; ++ break; ++ } ++ } ++ ++ if (!u3phy_port) { ++ dev_err(dev, "failed to find appropriate phy\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return u3phy_port->phy; ++} ++ ++static struct phy_ops rockchip_u3phy_ops = { ++ .init = rockchip_u3phy_init, ++ .exit = rockchip_u3phy_exit, ++ .power_on = rockchip_u3phy_power_on, ++ .power_off = rockchip_u3phy_power_off, ++ .owner = THIS_MODULE, ++}; ++ ++/* ++ * The function manage host-phy port state and suspend/resume phy port ++ * to save power automatically. ++ * ++ * we rely on utmi_linestate and utmi_hostdisconnect to identify whether ++ * devices is disconnect or not. Besides, we do not need care it is FS/LS ++ * disconnected or HS disconnected, actually, we just only need get the ++ * device is disconnected at last through rearm the delayed work, ++ * to suspend the phy port in _PHY_STATE_DISCONNECT_ case. ++ */ ++static void rockchip_u3phy_um_sm_work(struct work_struct *work) ++{ ++ struct rockchip_u3phy_port *u3phy_port = ++ container_of(work, struct rockchip_u3phy_port, um_sm_work.work); ++ struct rockchip_u3phy *u3phy = ++ dev_get_drvdata(u3phy_port->phy->dev.parent); ++ unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend - ++ u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1; ++ unsigned int ul, uhd, state; ++ unsigned int ul_mask, uhd_mask; ++ int ret; ++ ++ mutex_lock(&u3phy_port->mutex); ++ ++ ret = regmap_read(u3phy->u3phy_grf, ++ u3phy->cfgs->grfcfg.um_ls.offset, &ul); ++ if (ret < 0) ++ goto next_schedule; ++ ++ ret = regmap_read(u3phy->u3phy_grf, ++ u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd); ++ if (ret < 0) ++ goto next_schedule; ++ ++ uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend, ++ u3phy->cfgs->grfcfg.um_hstdct.bitstart); ++ ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend, ++ u3phy->cfgs->grfcfg.um_ls.bitstart); ++ ++ /* stitch on um_ls and um_hstdct as phy state */ ++ state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) | ++ (((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh); ++ ++ switch (state) { ++ case PHY_UTMI_HS_ONLINE: ++ dev_dbg(&u3phy_port->phy->dev, "HS online\n"); ++ break; ++ case PHY_UTMI_FS_LS_ONLINE: ++ /* ++ * For FS/LS device, the online state share with connect state ++ * from um_ls and um_hstdct register, so we distinguish ++ * them via suspended flag. ++ * ++ * Plus, there are two cases, one is D- Line pull-up, and D+ ++ * line pull-down, the state is 4; another is D+ line pull-up, ++ * and D- line pull-down, the state is 2. ++ */ ++ if (!u3phy_port->suspended) { ++ /* D- line pull-up, D+ line pull-down */ ++ dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); ++ break; ++ } ++ /* fall through */ ++ case PHY_UTMI_CONNECT: ++ if (u3phy_port->suspended) { ++ dev_dbg(&u3phy_port->phy->dev, "Connected\n"); ++ rockchip_u3phy_power_on(u3phy_port->phy); ++ u3phy_port->suspended = false; ++ } else { ++ /* D+ line pull-up, D- line pull-down */ ++ dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); ++ } ++ break; ++ case PHY_UTMI_DISCONNECT: ++ if (!u3phy_port->suspended) { ++ dev_dbg(&u3phy_port->phy->dev, "Disconnected\n"); ++ rockchip_u3phy_power_off(u3phy_port->phy); ++ u3phy_port->suspended = true; ++ } ++ ++ /* ++ * activate the linestate detection to get the next device ++ * plug-in irq. ++ */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.ls_det_st, true); ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.ls_det_en, true); ++ ++ /* ++ * we don't need to rearm the delayed work when the phy port ++ * is suspended. ++ */ ++ mutex_unlock(&u3phy_port->mutex); ++ return; ++ default: ++ dev_dbg(&u3phy_port->phy->dev, "unknown phy state\n"); ++ break; ++ } ++ ++next_schedule: ++ mutex_unlock(&u3phy_port->mutex); ++ schedule_delayed_work(&u3phy_port->um_sm_work, SCHEDULE_DELAY); ++} ++ ++static irqreturn_t rockchip_u3phy_um_ls_irq(int irq, void *data) ++{ ++ struct rockchip_u3phy_port *u3phy_port = data; ++ struct rockchip_u3phy *u3phy = ++ dev_get_drvdata(u3phy_port->phy->dev.parent); ++ ++ if (!param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.ls_det_st, ++ u3phy->cfgs->grfcfg.ls_det_st.dvalue)) ++ return IRQ_NONE; ++ ++ dev_dbg(u3phy->dev, "utmi linestate interrupt\n"); ++ mutex_lock(&u3phy_port->mutex); ++ ++ /* disable linestate detect irq and clear its status */ ++ param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false); ++ param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true); ++ ++ mutex_unlock(&u3phy_port->mutex); ++ ++ /* ++ * In this case for host phy, a new device is plugged in, meanwhile, ++ * if the phy port is suspended, we need rearm the work to resume it ++ * and mange its states; otherwise, we just return irq handled. ++ */ ++ if (u3phy_port->suspended) { ++ dev_dbg(u3phy->dev, "schedule utmi sm work\n"); ++ rockchip_u3phy_um_sm_work(&u3phy_port->um_sm_work.work); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy, ++ struct platform_device *pdev) ++ ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ int ret, i, clk; ++ ++ u3phy->um_ls_irq = platform_get_irq_byname(pdev, "linestate"); ++ if (u3phy->um_ls_irq < 0) { ++ dev_err(dev, "get utmi linestate irq failed\n"); ++ return -ENXIO; ++ } ++ ++ u3phy->vbus_drv_gpio = devm_gpiod_get_optional(dev, "vbus-drv", ++ GPIOD_OUT_HIGH); ++ ++ if (!u3phy->vbus_drv_gpio) { ++ dev_warn(&pdev->dev, "vbus_drv is not assigned\n"); ++ } else if (IS_ERR(u3phy->vbus_drv_gpio)) { ++ dev_err(&pdev->dev, "failed to get vbus_drv\n"); ++ return PTR_ERR(u3phy->vbus_drv_gpio); ++ } ++ ++ u3phy->num_clocks = of_clk_get_parent_count(np); ++ if (u3phy->num_clocks == 0) ++ dev_warn(&pdev->dev, "no clks found in dt\n"); ++ ++ u3phy->clks = devm_kcalloc(dev, u3phy->num_clocks, ++ sizeof(struct clk *), GFP_KERNEL); ++ ++ for (clk = 0; clk < u3phy->num_clocks; clk++) { ++ u3phy->clks[clk] = of_clk_get(np, clk); ++ if (IS_ERR(u3phy->clks[clk])) { ++ ret = PTR_ERR(u3phy->clks[clk]); ++ if (ret == -EPROBE_DEFER) ++ goto err_put_clks; ++ dev_err(&pdev->dev, "failed to get clks, %i\n", ++ ret); ++ u3phy->clks[clk] = NULL; ++ break; ++ } ++ } ++ ++ for (i = 0; i < U3PHY_RESET_MAX; i++) { ++ u3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i)); ++ if (IS_ERR(u3phy->rsts[i])) { ++ dev_info(dev, "no %s reset control specified\n", ++ get_rest_name(i)); ++ u3phy->rsts[i] = NULL; ++ } ++ } ++ ++ return 0; ++ ++err_put_clks: ++ while (--clk >= 0) ++ clk_put(u3phy->clks[clk]); ++ return ret; ++} ++ ++static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ struct device_node *child_np) ++{ ++ struct resource res; ++ struct phy *phy; ++ int ret; ++ ++ dev_dbg(u3phy->dev, "u3phy port initialize\n"); ++ ++ mutex_init(&u3phy_port->mutex); ++ u3phy_port->suspended = true; /* initial status */ ++ ++ phy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops); ++ if (IS_ERR(phy)) { ++ dev_err(u3phy->dev, "failed to create phy\n"); ++ return PTR_ERR(phy); ++ } ++ ++ u3phy_port->phy = phy; ++ ++ ret = of_address_to_resource(child_np, 0, &res); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to get address resource(np-%s)\n", ++ child_np->name); ++ return ret; ++ } ++ ++ u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res); ++ if (IS_ERR(u3phy_port->base)) { ++ dev_err(u3phy->dev, "failed to remap phy regs\n"); ++ return PTR_ERR(u3phy_port->base); ++ } ++ ++ if (!of_node_cmp(child_np->name, "pipe")) { ++ u3phy_port->type = U3PHY_TYPE_PIPE; ++ u3phy_port->refclk_25m_quirk = ++ of_property_read_bool(child_np, ++ "rockchip,refclk-25m-quirk"); ++ } else { ++ u3phy_port->type = U3PHY_TYPE_UTMI; ++ INIT_DELAYED_WORK(&u3phy_port->um_sm_work, ++ rockchip_u3phy_um_sm_work); ++ ++ ret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq, ++ NULL, rockchip_u3phy_um_ls_irq, ++ IRQF_ONESHOT, "rockchip_u3phy", ++ u3phy_port); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to request utmi linestate irq handle\n"); ++ return ret; ++ } ++ } ++ ++ if (u3phy->cfgs->phy_tuning) { ++ dev_dbg(u3phy->dev, "do u3phy tuning\n"); ++ ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np); ++ if (ret) ++ return ret; ++ } ++ ++ phy_set_drvdata(u3phy_port->phy, u3phy_port); ++ return 0; ++} ++ ++static int rockchip_u3phy_on_init(struct usb_phy *usb_phy) ++{ ++ struct rockchip_u3phy *u3phy = ++ container_of(usb_phy, struct rockchip_u3phy, usb_phy); ++ ++ rockchip_u3phy_rest_deassert(u3phy, U3PHY_POR_RST | U3PHY_MAC_RST); ++ return 0; ++} ++ ++static void rockchip_u3phy_on_shutdown(struct usb_phy *usb_phy) ++{ ++ struct rockchip_u3phy *u3phy = ++ container_of(usb_phy, struct rockchip_u3phy, usb_phy); ++ int rst; ++ ++ for (rst = 0; rst < U3PHY_RESET_MAX; rst++) ++ if (u3phy->rsts[rst] && rst != UTMI_APB_RSTN && ++ rst != PIPE_APB_RSTN) ++ reset_control_assert(u3phy->rsts[rst]); ++ udelay(1); ++} ++ ++static int rockchip_u3phy_on_disconnect(struct usb_phy *usb_phy, ++ enum usb_device_speed speed) ++{ ++ struct rockchip_u3phy *u3phy = ++ container_of(usb_phy, struct rockchip_u3phy, usb_phy); ++ ++ dev_info(u3phy->dev, "%s device has disconnected\n", ++ (speed == USB_SPEED_SUPER) ? "U3" : "UW/U2/U1.1/U1"); ++ ++ if (speed == USB_SPEED_SUPER) ++ atomic_notifier_call_chain(&usb_phy->notifier, 0, NULL); ++ ++ return 0; ++} ++ ++static int rockchip_u3phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct device_node *child_np; ++ struct phy_provider *provider; ++ struct rockchip_u3phy *u3phy; ++ const struct rockchip_u3phy_cfg *phy_cfgs; ++ const struct of_device_id *match; ++ unsigned int reg[2]; ++ int index, ret; ++ ++ match = of_match_device(dev->driver->of_match_table, dev); ++ if (!match || !match->data) { ++ dev_err(dev, "phy-cfgs are not assigned!\n"); ++ return -EINVAL; ++ } ++ ++ u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL); ++ if (!u3phy) ++ return -ENOMEM; ++ ++ u3phy->u3phy_grf = ++ syscon_regmap_lookup_by_phandle(np, "rockchip,u3phygrf"); ++ if (IS_ERR(u3phy->u3phy_grf)) ++ return PTR_ERR(u3phy->u3phy_grf); ++ ++ u3phy->grf = ++ syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); ++ if (IS_ERR(u3phy->grf)) { ++ dev_err(dev, "Missing rockchip,grf property\n"); ++ return PTR_ERR(u3phy->grf); ++ } ++ ++ if (of_property_read_u32_array(np, "reg", reg, 2)) { ++ dev_err(dev, "the reg property is not assigned in %s node\n", ++ np->name); ++ return -EINVAL; ++ } ++ ++ u3phy->dev = dev; ++ phy_cfgs = match->data; ++ platform_set_drvdata(pdev, u3phy); ++ ++ /* find out a proper config which can be matched with dt. */ ++ index = 0; ++ while (phy_cfgs[index].reg) { ++ if (phy_cfgs[index].reg == reg[1]) { ++ u3phy->cfgs = &phy_cfgs[index]; ++ break; ++ } ++ ++ ++index; ++ } ++ ++ if (!u3phy->cfgs) { ++ dev_err(dev, "no phy-cfgs can be matched with %s node\n", ++ np->name); ++ return -EINVAL; ++ } ++ ++ ret = rockchip_u3phy_parse_dt(u3phy, pdev); ++ if (ret) { ++ dev_err(dev, "parse dt failed, ret(%d)\n", ret); ++ return ret; ++ } ++ ++ ret = rockchip_u3phy_clk_enable(u3phy); ++ if (ret) { ++ dev_err(dev, "clk enable failed, ret(%d)\n", ret); ++ return ret; ++ } ++ ++ rockchip_u3phy_rest_assert(u3phy); ++ rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST); ++ ++ index = 0; ++ for_each_available_child_of_node(np, child_np) { ++ struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index]; ++ ++ u3phy_port->index = index; ++ ret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np); ++ if (ret) { ++ dev_err(dev, "u3phy port init failed,ret(%d)\n", ret); ++ goto put_child; ++ } ++ ++ /* to prevent out of boundary */ ++ if (++index >= U3PHY_PORT_NUM) ++ break; ++ } ++ ++ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (IS_ERR_OR_NULL(provider)) ++ goto put_child; ++ ++ rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST); ++ rockchip_u3phy_clk_disable(u3phy); ++ ++ u3phy->usb_phy.dev = dev; ++ u3phy->usb_phy.init = rockchip_u3phy_on_init; ++ u3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown; ++ u3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect; ++ usb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3); ++ ATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier); ++ ++ rockchip_u3phy_debugfs_init(u3phy); ++ ++ dev_info(dev, "Rockchip u3phy initialized successfully\n"); ++ return 0; ++ ++put_child: ++ of_node_put(child_np); ++ return ret; ++} ++ ++static int rk3328_u3phy_pipe_power(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ bool on) ++{ ++ unsigned int reg; ++ ++ if (on) { ++ reg = readl(u3phy_port->base + 0x1a8); ++ reg &= ~BIT(4); /* ldo power up */ ++ writel(reg, u3phy_port->base + 0x1a8); ++ ++ reg = readl(u3phy_port->base + 0x044); ++ reg &= ~BIT(4); /* bg power on */ ++ writel(reg, u3phy_port->base + 0x044); ++ ++ reg = readl(u3phy_port->base + 0x150); ++ reg |= BIT(6); /* tx bias enable */ ++ writel(reg, u3phy_port->base + 0x150); ++ ++ reg = readl(u3phy_port->base + 0x080); ++ reg &= ~BIT(2); /* tx cm power up */ ++ writel(reg, u3phy_port->base + 0x080); ++ ++ reg = readl(u3phy_port->base + 0x0c0); ++ /* tx obs enable and rx cm enable */ ++ reg |= (BIT(3) | BIT(4)); ++ writel(reg, u3phy_port->base + 0x0c0); ++ ++ udelay(1); ++ } else { ++ reg = readl(u3phy_port->base + 0x1a8); ++ reg |= BIT(4); /* ldo power down */ ++ writel(reg, u3phy_port->base + 0x1a8); ++ ++ reg = readl(u3phy_port->base + 0x044); ++ reg |= BIT(4); /* bg power down */ ++ writel(reg, u3phy_port->base + 0x044); ++ ++ reg = readl(u3phy_port->base + 0x150); ++ reg &= ~BIT(6); /* tx bias disable */ ++ writel(reg, u3phy_port->base + 0x150); ++ ++ reg = readl(u3phy_port->base + 0x080); ++ reg |= BIT(2); /* tx cm power down */ ++ writel(reg, u3phy_port->base + 0x080); ++ ++ reg = readl(u3phy_port->base + 0x0c0); ++ /* tx obs disable and rx cm disable */ ++ reg &= ~(BIT(3) | BIT(4)); ++ writel(reg, u3phy_port->base + 0x0c0); ++ } ++ ++ return 0; ++} ++ ++static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ struct device_node *child_np) ++{ ++ if (u3phy_port->type == U3PHY_TYPE_UTMI) { ++ /* ++ * For rk3328 SoC, pre-emphasis and pre-emphasis strength must ++ * be written as one fixed value as below. ++ * ++ * Dissimilarly, the odt 45ohm value should be flexibly tuninged ++ * for the different boards to adjust HS eye height, so its ++ * value can be assigned in DT in code design. ++ */ ++ ++ /* {bits[2:0]=111}: always enable pre-emphasis */ ++ u3phy->apbcfg.u2_pre_emp = 0x0f; ++ ++ /* {bits[5:3]=000}: pre-emphasis strength as the weakest */ ++ u3phy->apbcfg.u2_pre_emp_sth = 0x41; ++ ++ /* {bits[4:0]=10101}: odt 45ohm tuning */ ++ u3phy->apbcfg.u2_odt_tuning = 0xb5; ++ /* optional override of the odt 45ohm tuning */ ++ of_property_read_u32(child_np, "rockchip,odt-val-tuning", ++ &u3phy->apbcfg.u2_odt_tuning); ++ ++ writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030); ++ writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040); ++ writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c); ++ } else if (u3phy_port->type == U3PHY_TYPE_PIPE) { ++ if (u3phy_port->refclk_25m_quirk) { ++ dev_dbg(u3phy->dev, "switch to 25m refclk\n"); ++ /* ref clk switch to 25M */ ++ writel(0x64, u3phy_port->base + 0x11c); ++ writel(0x64, u3phy_port->base + 0x028); ++ writel(0x01, u3phy_port->base + 0x020); ++ writel(0x21, u3phy_port->base + 0x030); ++ writel(0x06, u3phy_port->base + 0x108); ++ writel(0x00, u3phy_port->base + 0x118); ++ } else { ++ /* configure for 24M ref clk */ ++ writel(0x80, u3phy_port->base + 0x10c); ++ writel(0x01, u3phy_port->base + 0x118); ++ writel(0x38, u3phy_port->base + 0x11c); ++ writel(0x83, u3phy_port->base + 0x020); ++ writel(0x02, u3phy_port->base + 0x108); ++ } ++ ++ /* Enable SSC */ ++ udelay(3); ++ writel(0x08, u3phy_port->base + 0x000); ++ writel(0x0c, u3phy_port->base + 0x120); ++ ++ /* Tuning Rx for compliance RJTL test */ ++ writel(0x70, u3phy_port->base + 0x150); ++ writel(0x12, u3phy_port->base + 0x0c8); ++ writel(0x05, u3phy_port->base + 0x148); ++ writel(0x08, u3phy_port->base + 0x068); ++ writel(0xf0, u3phy_port->base + 0x1c4); ++ writel(0xff, u3phy_port->base + 0x070); ++ writel(0x0f, u3phy_port->base + 0x06c); ++ writel(0xe0, u3phy_port->base + 0x060); ++ ++ /* ++ * Tuning Tx to increase the bias current ++ * used in TX driver and RX EQ, it can ++ * also increase the voltage of LFPS. ++ */ ++ writel(0x08, u3phy_port->base + 0x180); ++ } else { ++ dev_err(u3phy->dev, "invalid u3phy port type\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct rockchip_u3phy_cfg rk3328_u3phy_cfgs[] = { ++ { ++ .reg = 0xff470000, ++ .grfcfg = { ++ .um_suspend = { 0x0004, 15, 0, 0x1452, 0x15d1 }, ++ .u2_only_ctrl = { 0x0020, 15, 15, 0, 1 }, ++ .um_ls = { 0x0030, 5, 4, 0, 1 }, ++ .um_hstdct = { 0x0030, 7, 7, 0, 1 }, ++ .ls_det_en = { 0x0040, 0, 0, 0, 1 }, ++ .ls_det_st = { 0x0044, 0, 0, 0, 1 }, ++ .pp_pwr_st = { 0x0034, 14, 13, 0, 0}, ++ .pp_pwr_en = { {0x0020, 14, 0, 0x0014, 0x0005}, ++ {0x0020, 14, 0, 0x0014, 0x000d}, ++ {0x0020, 14, 0, 0x0014, 0x0015}, ++ {0x0020, 14, 0, 0x0014, 0x001d} }, ++ .u3_disable = { 0x04c4, 15, 0, 0x1100, 0x101}, ++ }, ++ .phy_pipe_power = rk3328_u3phy_pipe_power, ++ .phy_tuning = rk3328_u3phy_tuning, ++ }, ++ { /* sentinel */ } ++}; ++ ++static const struct of_device_id rockchip_u3phy_dt_match[] = { ++ { .compatible = "rockchip,rk3328-u3phy", .data = &rk3328_u3phy_cfgs }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, rockchip_u3phy_dt_match); ++ ++static struct platform_driver rockchip_u3phy_driver = { ++ .probe = rockchip_u3phy_probe, ++ .driver = { ++ .name = "rockchip-u3phy", ++ .of_match_table = rockchip_u3phy_dt_match, ++ }, ++}; ++module_platform_driver(rockchip_u3phy_driver); ++ ++MODULE_AUTHOR("Frank Wang "); ++MODULE_AUTHOR("William Wu "); ++MODULE_DESCRIPTION("Rockchip USB 3.0 PHY driver"); ++MODULE_LICENSE("GPL v2"); + +diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml +new file mode 100644 +index 000000000000..f4f28625173a +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml +@@ -0,0 +1,157 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: "http://devicetree.org/schemas/phy/phy-rockchip-inno-usb3.yaml#" ++$schema: "http://devicetree.org/meta-schemas/core.yaml#" ++ ++title: ROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK ++ ++maintainers: ++ ++properties: ++ compatible: ++ enum: ++ - rockchip,rk3328-u3phy ++ ++ reg: ++ - description: the base address of the USB 3.0 PHY ++ ++ interrupts: ++ maxItems: 1 ++ ++ interrupt-names: ++ items: ++ - const: linestate ++ description: host/otg linestate interrupt ++ ++ clocks: ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: u3phy-otg ++ description: USB 3.0 PHY UTMI ++ - const: u3phy-pipe ++ description: USB 3.0 PHY Pipe ++ ++ resets: ++ maxItems: 6 ++ ++ reset-names: ++ items: ++ - const: u3phy-u2-por ++ description: USB 2.0 logic of USB 3.0 PHY ++ - const: u3phy-u3-por ++ description: USB 3.0 logic of USB 3.0 PHY ++ - const: u3phy-pipe-mac ++ description: USB 3.0 PHY pipe MAC ++ - const: u3phy-utmi-mac ++ description: USB 3.0 PHY utmi MAC ++ - const: u3phy-utmi-apb ++ description: USB 3.0 PHY utmi apb ++ - const: u3phy-pipe-apb ++ description: USB 3.0 PHY pipe apb ++ ++ "#phy-cells": ++ const: 1 ++ ++ rockchip,u3phygrf: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ type: array ++ - description: phandle to the syscon managing the ++ "USB 3.0 PHY general register files". ++ ++ vbus-drv-gpios: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ type: array ++ - description: phandle for gpio vbus supply ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - interrupt-names ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - "#phy-cells" ++ - rockchip,u3phygrf ++ ++patternProperties: ++ "^u3phy_utmi@[0-9a-f]+$": ++ type: object ++ ++ properties: ++ - description: USB 2.0 utmi phy. ++ ++ rockchip,odt-val-tuning: ++ type: boolean ++ - description: specify 45ohm ODT tuning value. ++ ++ "phy-cells": ++ const: 0 ++ ++ required: ++ - reg ++ - "#phy-cells" ++ ++patternProperties: ++ "^u3phy_pipe@[0-9a-f]+$": ++ type: object ++ ++ properties: ++ - description: USB 3.0 pipe phy. ++ ++ rockchip,refclk-25m-quirk : ++ ++ - description: phy reference clock changed to 25m quirk. ++ ++ "phy-cells": ++ const: 0 ++ ++ required: ++ - reg ++ - "#phy-cells" ++ ++examples: ++ ++usb3phy_grf: syscon@ff460000 { ++ compatible = "rockchip,usb3phy-grf", "syscon"; ++ reg = <0x0 0xff460000 0x0 0x1000>; ++}; ++ ++... ++ ++u3phy: usb3-phy@ff470000 { ++ compatible = "rockchip,rk3328-u3phy"; ++ reg = <0x0 0xff470000 0x0 0x0>; ++ rockchip,u3phygrf = <&usb3phy_grf>; ++ interrupts = ; ++ interrupt-names = "linestate"; ++ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; ++ clock-names = "u3phy-otg", "u3phy-pipe"; ++ resets = <&cru SRST_USB3PHY_U2>, ++ <&cru SRST_USB3PHY_U3>, ++ <&cru SRST_USB3PHY_PIPE>, ++ <&cru SRST_USB3OTG_UTMI>, ++ <&cru SRST_USB3PHY_OTG_P>, ++ <&cru SRST_USB3PHY_PIPE_P>; ++ reset-names = "u3phy-u2-por", "u3phy-u3-por", ++ "u3phy-pipe-mac", "u3phy-utmi-mac", ++ "u3phy-utmi-apb", "u3phy-pipe-apb"; ++ vbus-drv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ u3phy_utmi: utmi@ff470000 { ++ reg = <0x0 0xff470000 0x0 0x8000>; ++ #phy-cells = <0>; ++ }; ++ ++ u3phy_pipe: pipe@ff478000 { ++ reg = <0x0 0xff478000 0x0 0x8000>; ++ #phy-cells = <0>; ++ }; ++}; +diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +index ada5435ce2c3..5f2f19344cc7 100644 +--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml ++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +@@ -34,6 +34,7 @@ + - rockchip,rk3308-usb2phy-grf + - rockchip,rk3328-grf + - rockchip,rk3328-usb2phy-grf ++ - rockchip,rk3328-u3phy-grf + - rockchip,rk3368-grf + - rockchip,rk3368-pmugrf + - rockchip,rk3399-grf +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 31cc1541f1f5..072e988ad655 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -805,6 +805,47 @@ + }; + }; + ++ usb3phy_grf: syscon@ff460000 { ++ compatible = "rockchip,usb3phy-grf", "syscon"; ++ reg = <0x0 0xff460000 0x0 0x1000>; ++ }; ++ ++ u3phy: usb3-phy@ff470000 { ++ compatible = "rockchip,rk3328-u3phy"; ++ reg = <0x0 0xff470000 0x0 0x0>; ++ rockchip,u3phygrf = <&usb3phy_grf>; ++ rockchip,grf = <&grf>; ++ interrupts = ; ++ interrupt-names = "linestate"; ++ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; ++ clock-names = "u3phy-otg", "u3phy-pipe"; ++ resets = <&cru SRST_USB3PHY_U2>, ++ <&cru SRST_USB3PHY_U3>, ++ <&cru SRST_USB3PHY_PIPE>, ++ <&cru SRST_USB3OTG_UTMI>, ++ <&cru SRST_USB3PHY_OTG_P>, ++ <&cru SRST_USB3PHY_PIPE_P>; ++ reset-names = "u3phy-u2-por", "u3phy-u3-por", ++ "u3phy-pipe-mac", "u3phy-utmi-mac", ++ "u3phy-utmi-apb", "u3phy-pipe-apb"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ u3phy_utmi: utmi@ff470000 { ++ reg = <0x0 0xff470000 0x0 0x8000>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ u3phy_pipe: pipe@ff478000 { ++ reg = <0x0 0xff478000 0x0 0x8000>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ + sdmmc: mmc@ff500000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff500000 0x0 0x4000>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +index bb40c163b05d..f300f3d0f02e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -328,6 +328,18 @@ + status = "okay"; + }; + ++&u3phy { ++ status = "okay"; ++}; ++ ++&u3phy_utmi { ++ status = "okay"; ++}; ++ ++&u3phy_pipe { ++ status = "okay"; ++}; ++ + &uart2 { + status = "okay"; + }; +@@ -344,6 +356,11 @@ + status = "okay"; + }; + ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index 62936b432..f97446924 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -383,6 +383,18 @@ + status = "okay"; + }; + ++&u3phy { ++ status = "okay"; ++}; ++ ++&u3phy_utmi { ++ status = "okay"; ++}; ++ ++&u3phy_pipe { ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + }; +@@ -391,6 +403,11 @@ + status = "okay"; + }; + ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; diff --git a/patch/kernel/archive/media-5.19/320-add-rockchip-iep-driver.patch b/patch/kernel/archive/media-6.0/320-add-rockchip-iep-driver.patch similarity index 100% rename from patch/kernel/archive/media-5.19/320-add-rockchip-iep-driver.patch rename to patch/kernel/archive/media-6.0/320-add-rockchip-iep-driver.patch diff --git a/patch/kernel/archive/media-5.18/180-board-roc-rk3399-pc-fix-fusb302-compatible.patch b/patch/kernel/archive/media-6.0/330-board-roc-rk3399-pc-fix-fusb302-compatible.patch similarity index 100% rename from patch/kernel/archive/media-5.18/180-board-roc-rk3399-pc-fix-fusb302-compatible.patch rename to patch/kernel/archive/media-6.0/330-board-roc-rk3399-pc-fix-fusb302-compatible.patch diff --git a/patch/kernel/archive/media-5.18/190-general-add-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/archive/media-6.0/340-general-add-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/media-5.18/190-general-add-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/archive/media-6.0/340-general-add-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/media-6.0/350-general-add-miniDP-dt-doc.patch b/patch/kernel/archive/media-6.0/350-general-add-miniDP-dt-doc.patch new file mode 100644 index 000000000..58b1a9a7a --- /dev/null +++ b/patch/kernel/archive/media-6.0/350-general-add-miniDP-dt-doc.patch @@ -0,0 +1,73 @@ +diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml +new file mode 100644 +index 000000000000..8110fbe2ddc2 +--- /dev/null ++++ b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml +@@ -0,0 +1,66 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/extcon/extcon-usbc-virtual-pd.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Type-C Virtual PD extcon ++ ++maintainers: ++ - Jagan Teki ++ ++description: | ++ USB Type-C protocol supports various modes of operations includes PD, ++ USB3, and Altmode. If the platform design supports a Type-C connector ++ then configuring these modes can be done via enumeration. ++ ++ However, there are some platforms that design these modes as separate ++ protocol connectors like design Display Port from on-chip USB3 controller. ++ So we can access Type-C Altmode Display Port via onboard Display Port ++ connector instead of a Type-C connector. These kinds of platforms require ++ an explicit extcon driver in order to handle Power Delivery and ++ Port Detection. ++ ++properties: ++ compatible: ++ const: linux,extcon-usbc-virtual-pd ++ ++ det-gpios: ++ description: Detect GPIO pin. Pin can be Display Port Detect or USB ID. ++ maxItems: 1 ++ ++ vpd-polarity: ++ description: USB Type-C Polarity. false for Normal and true for Flip. ++ type: boolean ++ ++ vpd-super-speed: ++ description: USB Super Speed. false for USB2 and true for USB3. ++ type: boolean ++ ++ vpd-data-role: ++ description: USB Data roles for Virtual Type-C. ++ $ref: /schemas/types.yaml#definitions/string ++ ++ enum: ++ - host ++ - device ++ - display-port ++ ++required: ++ - compatible ++ - det-gpios ++ - vpd-data-role ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ virtual_pd: virtual-pd { ++ compatible = "linux,extcon-usbc-virtual-pd"; ++ det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; ++ vpd-data-role = "display-port"; ++ vpd-super-speed; ++ }; + diff --git a/patch/kernel/archive/media-6.0/360-general-add-miniDP-virtual-extcon.patch b/patch/kernel/archive/media-6.0/360-general-add-miniDP-virtual-extcon.patch new file mode 100644 index 000000000..07adbb503 --- /dev/null +++ b/patch/kernel/archive/media-6.0/360-general-add-miniDP-virtual-extcon.patch @@ -0,0 +1,337 @@ +diff --git a/MAINTAINERS b/MAINTAINERS +index 68f21d46614c..aeb161b19dae 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -6466,6 +6466,12 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git + F: Documentation/filesystems/ext4/ + F: fs/ext4/ + ++EXTCON DRIVER FOR TYPE-C VIRTUAL PD ++M: Jagan Teki ++S: Maintained ++F: Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml ++F: drivers/extcon/extcon-usbc-virtual-pd.c ++ + Extended Verification Module (EVM) + M: Mimi Zohar + L: linux-integrity@vger.kernel.org +diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig +index aac507bff135..edd6c3c52699 100644 +--- a/drivers/extcon/Kconfig ++++ b/drivers/extcon/Kconfig +@@ -186,4 +186,14 @@ config EXTCON_USBC_CROS_EC + Say Y here to enable USB Type C cable detection extcon support when + using Chrome OS EC based USB Type-C ports. + ++config EXTCON_USBC_VIRTUAL_PD ++ tristate "Virtual Type-C PD EXTCON support" ++ depends on GPIOLIB || COMPILE_TEST ++ help ++ Say Y here to enable Virtual Type-C PD extcon driver support, if ++ hardware platform designed Type-C modes separately. ++ ++ Example, of designing Display Port separately from Type-C Altmode ++ instead of accessing Altmode Display Port in Type-C connector. ++ + endif +diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile +index 52096fd8a216..c35191eef0e1 100644 +--- a/drivers/extcon/Makefile ++++ b/drivers/extcon/Makefile +@@ -25,3 +25,4 @@ obj-$(CONFIG_EXTCON_RT8973A) += extcon-rt8973a.o + obj-$(CONFIG_EXTCON_USB_GPIO) += extcon-usb-gpio.o + obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o + obj-$(CONFIG_EXTCON_USBC_TUSB320) += extcon-usbc-tusb320.o ++obj-$(CONFIG_EXTCON_USBC_VIRTUAL_PD) += extcon-usbc-virtual-pd.o +diff --git a/drivers/extcon/extcon-usbc-virtual-pd.c b/drivers/extcon/extcon-usbc-virtual-pd.c +new file mode 100644 +index 000000000000..e0713670e33d +--- /dev/null ++++ b/drivers/extcon/extcon-usbc-virtual-pd.c +@@ -0,0 +1,285 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Type-C Virtual PD Extcon driver ++ * ++ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2019 Radxa Limited ++ * Copyright (c) 2019 Amarula Solutions(India) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const unsigned int vpd_cable[] = { ++ EXTCON_USB, ++ EXTCON_USB_HOST, ++ EXTCON_DISP_DP, ++ EXTCON_NONE, ++}; ++ ++enum vpd_data_role { ++ DR_NONE, ++ DR_HOST, ++ DR_DEVICE, ++ DR_DISPLAY_PORT, ++}; ++ ++enum vpd_polarity { ++ POLARITY_NORMAL, ++ POLARITY_FLIP, ++}; ++ ++enum vpd_usb_ss { ++ USB_SS_USB2, ++ USB_SS_USB3, ++}; ++ ++struct vpd_extcon { ++ struct device *dev; ++ struct extcon_dev *extcon; ++ struct gpio_desc *det_gpio; ++ ++ u8 polarity; ++ u8 usb_ss; ++ enum vpd_data_role data_role; ++ ++ int irq; ++ bool enable_irq; ++ struct work_struct work; ++ struct delayed_work irq_work; ++}; ++ ++static void vpd_extcon_irq_work(struct work_struct *work) ++{ ++ struct vpd_extcon *vpd = container_of(work, struct vpd_extcon, irq_work.work); ++ bool host_connected = false, device_connected = false, dp_connected = false; ++ union extcon_property_value property; ++ int det; ++ ++ det = vpd->det_gpio ? gpiod_get_raw_value(vpd->det_gpio) : 0; ++ if (det) { ++ device_connected = (vpd->data_role == DR_DEVICE) ? true : false; ++ host_connected = (vpd->data_role == DR_HOST) ? true : false; ++ dp_connected = (vpd->data_role == DR_DISPLAY_PORT) ? true : false; ++ } ++ ++ extcon_set_state(vpd->extcon, EXTCON_USB, host_connected); ++ extcon_set_state(vpd->extcon, EXTCON_USB_HOST, device_connected); ++ extcon_set_state(vpd->extcon, EXTCON_DISP_DP, dp_connected); ++ ++ property.intval = vpd->polarity; ++ extcon_set_property(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ extcon_set_property(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ extcon_set_property(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ ++ property.intval = vpd->usb_ss; ++ extcon_set_property(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS, property); ++ extcon_set_property(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS, property); ++ extcon_set_property(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS, property); ++ ++ extcon_sync(vpd->extcon, EXTCON_USB); ++ extcon_sync(vpd->extcon, EXTCON_USB_HOST); ++ extcon_sync(vpd->extcon, EXTCON_DISP_DP); ++} ++ ++static irqreturn_t vpd_extcon_irq_handler(int irq, void *dev_id) ++{ ++ struct vpd_extcon *vpd = dev_id; ++ ++ schedule_delayed_work(&vpd->irq_work, msecs_to_jiffies(10)); ++ ++ return IRQ_HANDLED; ++} ++ ++static enum vpd_data_role vpd_extcon_data_role(struct vpd_extcon *vpd) ++{ ++ const char *const data_roles[] = { ++ [DR_NONE] = "NONE", ++ [DR_HOST] = "host", ++ [DR_DEVICE] = "device", ++ [DR_DISPLAY_PORT] = "display-port", ++ }; ++ struct device *dev = vpd->dev; ++ int ret; ++ const char *dr; ++ ++ ret = device_property_read_string(dev, "vpd-data-role", &dr); ++ if (ret < 0) ++ return DR_NONE; ++ ++ ret = match_string(data_roles, ARRAY_SIZE(data_roles), dr); ++ ++ return (ret < 0) ? DR_NONE : ret; ++} ++ ++static int vpd_extcon_parse_dts(struct vpd_extcon *vpd) ++{ ++ struct device *dev = vpd->dev; ++ bool val = false; ++ int ret; ++ ++ val = device_property_read_bool(dev, "vpd-polarity"); ++ if (val) ++ vpd->polarity = POLARITY_FLIP; ++ else ++ vpd->polarity = POLARITY_NORMAL; ++ ++ val = device_property_read_bool(dev, "vpd-super-speed"); ++ if (val) ++ vpd->usb_ss = USB_SS_USB3; ++ else ++ vpd->usb_ss = USB_SS_USB2; ++ ++ vpd->data_role = vpd_extcon_data_role(vpd); ++ ++ vpd->det_gpio = devm_gpiod_get_optional(dev, "det", GPIOD_OUT_LOW); ++ if (IS_ERR(vpd->det_gpio)) { ++ ret = PTR_ERR(vpd->det_gpio); ++ dev_warn(dev, "failed to get det gpio: %d\n", ret); ++ return ret; ++ } ++ ++ vpd->irq = gpiod_to_irq(vpd->det_gpio); ++ if (vpd->irq < 0) { ++ dev_err(dev, "failed to get irq for gpio: %d\n", vpd->irq); ++ return vpd->irq; ++ } ++ ++ ret = devm_request_threaded_irq(dev, vpd->irq, NULL, ++ vpd_extcon_irq_handler, ++ IRQF_TRIGGER_FALLING | ++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, ++ NULL, vpd); ++ if (ret) ++ dev_err(dev, "failed to request gpio irq\n"); ++ ++ return ret; ++} ++ ++static int vpd_extcon_probe(struct platform_device *pdev) ++{ ++ struct vpd_extcon *vpd; ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ vpd = devm_kzalloc(dev, sizeof(*vpd), GFP_KERNEL); ++ if (!vpd) ++ return -ENOMEM; ++ ++ vpd->dev = dev; ++ ret = vpd_extcon_parse_dts(vpd); ++ if (ret) ++ return ret; ++ ++ INIT_DELAYED_WORK(&vpd->irq_work, vpd_extcon_irq_work); ++ ++ vpd->extcon = devm_extcon_dev_allocate(dev, vpd_cable); ++ if (IS_ERR(vpd->extcon)) { ++ dev_err(dev, "allocat extcon failed\n"); ++ return PTR_ERR(vpd->extcon); ++ } ++ ++ ret = devm_extcon_dev_register(dev, vpd->extcon); ++ if (ret) { ++ dev_err(dev, "register extcon failed: %d\n", ret); ++ return ret; ++ } ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_VBUS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_VBUS); ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS); ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ ++ platform_set_drvdata(pdev, vpd); ++ ++ vpd_extcon_irq_work(&vpd->irq_work.work); ++ ++ return 0; ++} ++ ++static int vpd_extcon_remove(struct platform_device *pdev) ++{ ++ struct vpd_extcon *vpd = platform_get_drvdata(pdev); ++ ++ cancel_delayed_work_sync(&vpd->irq_work); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int vpd_extcon_suspend(struct device *dev) ++{ ++ struct vpd_extcon *vpd = dev_get_drvdata(dev); ++ ++ if (!vpd->enable_irq) { ++ disable_irq_nosync(vpd->irq); ++ vpd->enable_irq = true; ++ } ++ ++ return 0; ++} ++ ++static int vpd_extcon_resume(struct device *dev) ++{ ++ struct vpd_extcon *vpd = dev_get_drvdata(dev); ++ ++ if (vpd->enable_irq) { ++ enable_irq(vpd->irq); ++ vpd->enable_irq = false; ++ } ++ ++ return 0; ++} ++#endif ++ ++static SIMPLE_DEV_PM_OPS(vpd_extcon_pm_ops, ++ vpd_extcon_suspend, vpd_extcon_resume); ++ ++static const struct of_device_id vpd_extcon_dt_match[] = { ++ { .compatible = "linux,extcon-usbc-virtual-pd", }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver vpd_extcon_driver = { ++ .probe = vpd_extcon_probe, ++ .remove = vpd_extcon_remove, ++ .driver = { ++ .name = "extcon-usbc-virtual-pd", ++ .pm = &vpd_extcon_pm_ops, ++ .of_match_table = vpd_extcon_dt_match, ++ }, ++}; ++ ++module_platform_driver(vpd_extcon_driver); ++ ++MODULE_AUTHOR("Jagan Teki "); ++MODULE_DESCRIPTION("Type-C Virtual PD extcon driver"); ++MODULE_LICENSE("GPL v2"); + diff --git a/patch/kernel/archive/media-5.18/200-general-add-overlay-compilation-support.patch b/patch/kernel/archive/media-6.0/370-general-add-overlay-compilation-support.patch similarity index 100% rename from patch/kernel/archive/media-5.18/200-general-add-overlay-compilation-support.patch rename to patch/kernel/archive/media-6.0/370-general-add-overlay-compilation-support.patch diff --git a/patch/kernel/archive/media-5.18/210-general-add-overlay-configfs.patch b/patch/kernel/archive/media-6.0/380-general-add-overlay-configfs.patch similarity index 100% rename from patch/kernel/archive/media-5.18/210-general-add-overlay-configfs.patch rename to patch/kernel/archive/media-6.0/380-general-add-overlay-configfs.patch diff --git a/patch/kernel/archive/media-5.19/390-general-add-pll-hdmi-timings.patch b/patch/kernel/archive/media-6.0/390-general-add-pll-hdmi-timings.patch similarity index 100% rename from patch/kernel/archive/media-5.19/390-general-add-pll-hdmi-timings.patch rename to patch/kernel/archive/media-6.0/390-general-add-pll-hdmi-timings.patch diff --git a/patch/kernel/archive/media-6.0/400-general-bluetooth-02-add-support-for-RTL8723CS.patch b/patch/kernel/archive/media-6.0/400-general-bluetooth-02-add-support-for-RTL8723CS.patch new file mode 100644 index 000000000..afe31fb10 --- /dev/null +++ b/patch/kernel/archive/media-6.0/400-general-bluetooth-02-add-support-for-RTL8723CS.patch @@ -0,0 +1,266 @@ +From 26e61cffb09c1f5519a4eeb9d9e99239d58b6c2d Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Thu, 1 Jul 2021 11:22:23 +0200 +Subject: [PATCH 302/467] Bluetooth: btrtl: add support for the RTL8723CS + +The Realtek RTL8723CS is SDIO WiFi chip. It also contains a Bluetooth +module which is connected via UART to the host. + +It shares lmp subversion with 8703B, so Realtek's userspace +initialization tool (rtk_hciattach) differentiates varieties of RTL8723CS +(CG, VF, XX) with RTL8703B using vendor's command to read chip type. + +Also this chip declares support for some features it doesn't support +so add a quirk to indicate that these features are broken. + +Signed-off-by: Vasily Khoruzhick +Signed-off-by: Ondrej Jirman +--- + drivers/bluetooth/btrtl.c | 119 +++++++++++++++++++++++++++++++++++++- + drivers/bluetooth/btrtl.h | 5 ++ + 2 files changed, 121 insertions(+), 3 deletions(-) + +diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c +index 1f8afa024..fd293a9c4 100644 +--- a/drivers/bluetooth/btrtl.c ++++ b/drivers/bluetooth/btrtl.c +@@ -17,7 +17,12 @@ + + #define VERSION "0.1" + ++#define RTL_CHIP_8723CS_CG 3 ++#define RTL_CHIP_8723CS_VF 4 ++#define RTL_CHIP_8723CS_XX 5 + #define RTL_EPATCH_SIGNATURE "Realtech" ++#define RTL_ROM_LMP_3499 0x3499 ++#define RTL_ROM_LMP_8703B 0x8703 + #define RTL_ROM_LMP_8723A 0x1200 + #define RTL_ROM_LMP_8723B 0x8723 + #define RTL_ROM_LMP_8821A 0x8821 +@@ -30,6 +35,7 @@ + #define IC_MATCH_FL_HCIREV (1 << 1) + #define IC_MATCH_FL_HCIVER (1 << 2) + #define IC_MATCH_FL_HCIBUS (1 << 3) ++#define IC_MATCH_FL_CHIP_TYPE (1 << 4) + #define IC_INFO(lmps, hcir, hciv, bus) \ + .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV | \ + IC_MATCH_FL_HCIVER | IC_MATCH_FL_HCIBUS, \ +@@ -57,6 +63,7 @@ struct id_table { + __u16 hci_rev; + __u8 hci_ver; + __u8 hci_bus; ++ __u8 chip_type; + bool config_needed; + bool has_rom_version; + char *fw_name; +@@ -96,6 +103,39 @@ static const struct id_table ic_id_table[] = { + .fw_name = "rtl_bt/rtl8723b_fw.bin", + .cfg_name = "rtl_bt/rtl8723b_config" }, + ++ /* 8723CS-CG */ ++ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | ++ IC_MATCH_FL_HCIBUS, ++ .lmp_subver = RTL_ROM_LMP_8703B, ++ .chip_type = RTL_CHIP_8723CS_CG, ++ .hci_bus = HCI_UART, ++ .config_needed = true, ++ .has_rom_version = true, ++ .fw_name = "rtl_bt/rtl8723cs_cg_fw.bin", ++ .cfg_name = "rtl_bt/rtl8723cs_cg_config" }, ++ ++ /* 8723CS-VF */ ++ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | ++ IC_MATCH_FL_HCIBUS, ++ .lmp_subver = RTL_ROM_LMP_8703B, ++ .chip_type = RTL_CHIP_8723CS_VF, ++ .hci_bus = HCI_UART, ++ .config_needed = true, ++ .has_rom_version = true, ++ .fw_name = "rtl_bt/rtl8723cs_vf_fw.bin", ++ .cfg_name = "rtl_bt/rtl8723cs_vf_config" }, ++ ++ /* 8723CS-XX */ ++ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | ++ IC_MATCH_FL_HCIBUS, ++ .lmp_subver = RTL_ROM_LMP_8703B, ++ .chip_type = RTL_CHIP_8723CS_XX, ++ .hci_bus = HCI_UART, ++ .config_needed = true, ++ .has_rom_version = true, ++ .fw_name = "rtl_bt/rtl8723cs_xx_fw.bin", ++ .cfg_name = "rtl_bt/rtl8723cs_xx_config" }, ++ + /* 8723D */ + { IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_USB), + .config_needed = true, +@@ -175,7 +215,8 @@ static const struct id_table ic_id_table[] = { + }; + + static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev, +- u8 hci_ver, u8 hci_bus) ++ u8 hci_ver, u8 hci_bus, ++ u8 chip_type) + { + int i; + +@@ -192,6 +233,9 @@ static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev, + if ((ic_id_table[i].match_flags & IC_MATCH_FL_HCIBUS) && + (ic_id_table[i].hci_bus != hci_bus)) + continue; ++ if ((ic_id_table[i].match_flags & IC_MATCH_FL_CHIP_TYPE) && ++ (ic_id_table[i].chip_type != chip_type)) ++ continue; + + break; + } +@@ -274,6 +318,7 @@ static int rtlbt_parse_firmware(struct hci_dev *hdev, + { RTL_ROM_LMP_8723B, 1 }, + { RTL_ROM_LMP_8821A, 2 }, + { RTL_ROM_LMP_8761A, 3 }, ++ { RTL_ROM_LMP_8703B, 7 }, + { RTL_ROM_LMP_8822B, 8 }, + { RTL_ROM_LMP_8723B, 9 }, /* 8723D */ + { RTL_ROM_LMP_8821A, 10 }, /* 8821C */ +@@ -552,6 +597,48 @@ static int btrtl_setup_rtl8723b(struct hci_dev *hdev, + return ret; + } + ++static bool rtl_has_chip_type(u16 lmp_subver) ++{ ++ switch (lmp_subver) { ++ case RTL_ROM_LMP_8703B: ++ return true; ++ default: ++ break; ++ } ++ ++ return false; ++} ++ ++static int rtl_read_chip_type(struct hci_dev *hdev, u8 *type) ++{ ++ struct rtl_chip_type_evt *chip_type; ++ struct sk_buff *skb; ++ const unsigned char cmd_buf[] = {0x00, 0x94, 0xa0, 0x00, 0xb0}; ++ ++ /* Read RTL chip type command */ ++ skb = __hci_cmd_sync(hdev, 0xfc61, 5, cmd_buf, HCI_INIT_TIMEOUT); ++ if (IS_ERR(skb)) { ++ rtl_dev_err(hdev, "Read chip type failed (%ld)", ++ PTR_ERR(skb)); ++ return PTR_ERR(skb); ++ } ++ ++ if (skb->len != sizeof(*chip_type)) { ++ rtl_dev_err(hdev, "RTL chip type event length mismatch"); ++ kfree_skb(skb); ++ return -EIO; ++ } ++ ++ chip_type = (struct rtl_chip_type_evt *)skb->data; ++ rtl_dev_info(hdev, "chip_type status=%x type=%x", ++ chip_type->status, chip_type->type); ++ ++ *type = chip_type->type & 0x0f; ++ ++ kfree_skb(skb); ++ return 0; ++} ++ + void btrtl_free(struct btrtl_device_info *btrtl_dev) + { + kvfree(btrtl_dev->fw_data); +@@ -568,7 +655,7 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev, + struct hci_rp_read_local_version *resp; + char cfg_name[40]; + u16 hci_rev, lmp_subver; +- u8 hci_ver; ++ u8 hci_ver, chip_type = 0; + int ret; + u16 opcode; + u8 cmd[2]; +@@ -638,8 +725,14 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev, + out_free: + kfree_skb(skb); + ++ if (rtl_has_chip_type(lmp_subver)) { ++ ret = rtl_read_chip_type(hdev, &chip_type); ++ if (ret) ++ goto err_free; ++ } ++ + btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver, +- hdev->bus); ++ hdev->bus, chip_type); + + if (!btrtl_dev->ic_info) { + rtl_dev_info(hdev, "unknown IC info, lmp subver %04x, hci rev %04x, hci ver %04x", +@@ -757,7 +757,7 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev, + lmp_subver = le16_to_cpu(resp->lmp_subver); + + btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver, +- hdev->bus); ++ hdev->bus, chip_type); + } + out_free: + kfree_skb(skb); +@@ -722,6 +815,7 @@ int btrtl_download_firmware(struct hci_dev *hdev, + case RTL_ROM_LMP_8761A: + case RTL_ROM_LMP_8822B: + case RTL_ROM_LMP_8852A: ++ case RTL_ROM_LMP_8703B: + return btrtl_setup_rtl8723b(hdev, btrtl_dev); + default: + rtl_dev_info(hdev, "assuming no firmware upload needed"); +@@ -752,6 +846,19 @@ void btrtl_set_quirks(struct hci_dev *hdev, struct btrtl_device_info *btrtl_dev) + rtl_dev_dbg(hdev, "WBS supported not enabled."); + break; + } ++ ++ switch (btrtl_dev->ic_info->lmp_subver) { ++ case RTL_ROM_LMP_8703B: ++ /* 8723CS reports two pages for local ext features, ++ * but it doesn't support any features from page 2 - ++ * it either responds with garbage or with error status ++ */ ++ set_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE, ++ &hdev->quirks); ++ break; ++ default: ++ break; ++ } + } + EXPORT_SYMBOL_GPL(btrtl_set_quirks); + +@@ -910,6 +1017,12 @@ MODULE_FIRMWARE("rtl_bt/rtl8723b_fw.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723b_config.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723bs_fw.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723bs_config.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_fw.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_config.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_fw.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_config.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_fw.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_config.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723ds_fw.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723ds_config.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8761a_fw.bin"); +diff --git a/drivers/bluetooth/btrtl.h b/drivers/bluetooth/btrtl.h +index 2c441bda3..1c6282241 100644 +--- a/drivers/bluetooth/btrtl.h ++++ b/drivers/bluetooth/btrtl.h +@@ -14,6 +14,11 @@ + + struct btrtl_device_info; + ++struct rtl_chip_type_evt { ++ __u8 status; ++ __u8 type; ++} __packed; ++ + struct rtl_download_cmd { + __u8 index; + __u8 data[RTL_FRAG_LEN]; +-- +2.34.0 + diff --git a/patch/kernel/archive/media-6.0/410-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch b/patch/kernel/archive/media-6.0/410-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch new file mode 100644 index 000000000..058ea2c39 --- /dev/null +++ b/patch/kernel/archive/media-6.0/410-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch @@ -0,0 +1,31 @@ +From 8fc0422773dc5274fa32e2a5a6ce2e1f0a96d78c Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Wed, 31 Oct 2018 20:07:41 -0700 +Subject: [PATCH 304/467] Bluetooth: hci_h5: Add support for binding RTL8723CS + with device tree + +RTL8723CS is often used in ARM boards, so add ability to bind it +using device tree. + +Signed-off-by: Vasily Khoruzhick +Signed-off-by: Ondrej Jirman +--- + drivers/bluetooth/hci_h5.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c +index d49a39d17..c9b54335a 100644 +--- a/drivers/bluetooth/hci_h5.c ++++ b/drivers/bluetooth/hci_h5.c +@@ -1100,6 +1100,8 @@ static const struct of_device_id rtl_bluetooth_of_match[] = { + .data = (const void *)&h5_data_rtl8723bs }, + { .compatible = "realtek,rtl8723ds-bt", + .data = (const void *)&h5_data_rtl8723bs }, ++ { .compatible = "realtek,rtl8723cs-bt", ++ .data = (const void *)&h5_data_rtl8723bs }, + #endif + { }, + }; +-- +2.34.0 + diff --git a/patch/kernel/archive/media-6.0/420-general-bluetooth-04-add-rtl8703bs.patch b/patch/kernel/archive/media-6.0/420-general-bluetooth-04-add-rtl8703bs.patch new file mode 100644 index 000000000..474db44ec --- /dev/null +++ b/patch/kernel/archive/media-6.0/420-general-bluetooth-04-add-rtl8703bs.patch @@ -0,0 +1,42 @@ +From f0c05140b92cca447cd55a93ad4de141d0f117f1 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Thu, 9 Dec 2021 22:47:36 +0000 +Subject: [PATCH] rtl8703bs: add chip type to list and info block + +--- + drivers/bluetooth/btrtl.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c +index ad4085eede4..2c227bf4e00 100644 +--- a/drivers/bluetooth/btrtl.c ++++ b/drivers/bluetooth/btrtl.c +@@ -20,6 +20,7 @@ + #define RTL_CHIP_8723CS_CG 3 + #define RTL_CHIP_8723CS_VF 4 + #define RTL_CHIP_8723CS_XX 5 ++#define RTL_CHIP_8703BS 7 + #define RTL_EPATCH_SIGNATURE "Realtech" + #define RTL_ROM_LMP_3499 0x3499 + #define RTL_ROM_LMP_8703B 0x8703 +@@ -136,6 +137,17 @@ static const struct id_table ic_id_table[] = { + .fw_name = "rtl_bt/rtl8723cs_xx_fw.bin", + .cfg_name = "rtl_bt/rtl8723cs_xx_config" }, + ++ /* 8703BS */ ++ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | ++ IC_MATCH_FL_HCIBUS, ++ .lmp_subver = RTL_ROM_LMP_8703B, ++ .chip_type = RTL_CHIP_8703BS, ++ .hci_bus = HCI_UART, ++ .config_needed = true, ++ .has_rom_version = true, ++ .fw_name = "rtl_bt/rtl8723cs_xx_fw.bin", ++ .cfg_name = "rtl_bt/rtl8723cs_xx_config" }, ++ + /* 8723D */ + { IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_USB), + .config_needed = true, +-- +2.30.2 + diff --git a/patch/kernel/archive/media-6.0/430-general-bluetooth-add-new-quirk.patch b/patch/kernel/archive/media-6.0/430-general-bluetooth-add-new-quirk.patch new file mode 100644 index 000000000..a4614e12b --- /dev/null +++ b/patch/kernel/archive/media-6.0/430-general-bluetooth-add-new-quirk.patch @@ -0,0 +1,53 @@ +From f60f1605f5056d543e49fc625ffeeb05621f2ad3 Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Wed, 31 Oct 2018 19:40:18 -0700 +Subject: Bluetooth: Add new quirk for broken local ext features max_page + +Some adapters (e.g. RTL8723CS) advertise that they have more than +2 pages for local ext features, but they don't support any features +declared in these pages. RTL8723CS reports max_page = 2 and declares +support for sync train and secure connection, but it responds with +either garbage or with error in status on corresponding commands. + +Signed-off-by: Vasily Khoruzhick +--- + include/net/bluetooth/hci.h | 7 +++++++ + net/bluetooth/hci_event.c | 4 +++- + 2 files changed, 10 insertions(+), 1 deletion(-) + +diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h +index 16ab6ce87883..8e4c16210d18 100644 +--- a/include/net/bluetooth/hci.h ++++ b/include/net/bluetooth/hci.h +@@ -238,6 +238,13 @@ enum { + * HCI after resume. + */ + HCI_QUIRK_NO_SUSPEND_NOTIFIER, ++ ++ /* When this quirk is set, max_page for local extended features ++ * is set to 1, even if controller reports higher number. Some ++ * controllers (e.g. RTL8723CS) report more pages, but they ++ * don't actually support features declared there. ++ */ ++ HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE, + + /* + * When this quirk is set, LE tx power is not queried on startup +diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c +index cfeaee347db3..df3232828978 100644 +--- a/net/bluetooth/hci_event.c ++++ b/net/bluetooth/hci_event.c +@@ -700,7 +700,9 @@ static void hci_cc_read_local_ext_features(struct hci_dev *hdev, + if (rp->status) + return; + +- if (hdev->max_page < rp->max_page) ++ if (!test_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE, ++ &hdev->quirks) && ++ hdev->max_page < rp->max_page) + hdev->max_page = rp->max_page; + + if (rp->page < HCI_MAX_PAGES) +-- +cgit v1.2.3 + diff --git a/patch/kernel/archive/media-5.18/230-general-fix-es8316-kernel-panic.patch b/patch/kernel/archive/media-6.0/450-general-fix-es8316-kernel-panic.patch similarity index 100% rename from patch/kernel/archive/media-5.18/230-general-fix-es8316-kernel-panic.patch rename to patch/kernel/archive/media-6.0/450-general-fix-es8316-kernel-panic.patch diff --git a/patch/kernel/archive/media-5.18/240-general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/archive/media-6.0/470-general-increasing_DMA_block_memory_allocation_to_2048.patch similarity index 100% rename from patch/kernel/archive/media-5.18/240-general-increasing_DMA_block_memory_allocation_to_2048.patch rename to patch/kernel/archive/media-6.0/470-general-increasing_DMA_block_memory_allocation_to_2048.patch diff --git a/patch/kernel/archive/media-5.18/250-general-possibility-of-disabling-rk808-rtc.patch b/patch/kernel/archive/media-6.0/480-general-possibility-of-disabling-rk808-rtc.patch similarity index 100% rename from patch/kernel/archive/media-5.18/250-general-possibility-of-disabling-rk808-rtc.patch rename to patch/kernel/archive/media-6.0/480-general-possibility-of-disabling-rk808-rtc.patch diff --git a/patch/kernel/archive/media-5.18/260-general-rk808-configurable-switch-voltage-steps.patch b/patch/kernel/archive/media-6.0/490-general-rk808-configurable-switch-voltage-steps.patch similarity index 100% rename from patch/kernel/archive/media-5.18/260-general-rk808-configurable-switch-voltage-steps.patch rename to patch/kernel/archive/media-6.0/490-general-rk808-configurable-switch-voltage-steps.patch diff --git a/patch/kernel/archive/media-5.18/270-general-workaround-broadcom-bt-serdev.patch b/patch/kernel/archive/media-6.0/500-general-workaround-broadcom-bt-serdev.patch similarity index 100% rename from patch/kernel/archive/media-5.18/270-general-workaround-broadcom-bt-serdev.patch rename to patch/kernel/archive/media-6.0/500-general-workaround-broadcom-bt-serdev.patch diff --git a/patch/kernel/archive/media-5.18/280-rk3328-dtsi-usb3-reset-properties.patch b/patch/kernel/archive/media-6.0/510-rk3328-dtsi-usb3-reset-properties.patch similarity index 100% rename from patch/kernel/archive/media-5.18/280-rk3328-dtsi-usb3-reset-properties.patch rename to patch/kernel/archive/media-6.0/510-rk3328-dtsi-usb3-reset-properties.patch diff --git a/patch/kernel/archive/media-5.18/290-rk3328-roc-pc-bt.patch b/patch/kernel/archive/media-6.0/520-rk3328-roc-pc-bt.patch similarity index 100% rename from patch/kernel/archive/media-5.18/290-rk3328-roc-pc-bt.patch rename to patch/kernel/archive/media-6.0/520-rk3328-roc-pc-bt.patch diff --git a/patch/kernel/archive/media-5.18/300-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/archive/media-6.0/530-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/media-5.18/300-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/archive/media-6.0/530-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/media-5.18/310-rk3399-nanopc-t4-emmc.patch b/patch/kernel/archive/media-6.0/540-rk3399-nanopc-t4-emmc.patch similarity index 100% rename from patch/kernel/archive/media-5.18/310-rk3399-nanopc-t4-emmc.patch rename to patch/kernel/archive/media-6.0/540-rk3399-nanopc-t4-emmc.patch diff --git a/patch/kernel/archive/media-5.18/320-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch b/patch/kernel/archive/media-6.0/550-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch similarity index 100% rename from patch/kernel/archive/media-5.18/320-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch rename to patch/kernel/archive/media-6.0/550-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch diff --git a/patch/kernel/archive/media-5.18/330-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch b/patch/kernel/archive/media-6.0/560-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch similarity index 100% rename from patch/kernel/archive/media-5.18/330-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch rename to patch/kernel/archive/media-6.0/560-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch diff --git a/patch/kernel/archive/media-5.18/340-rk3399-sd-drive-level-8ma.patch b/patch/kernel/archive/media-6.0/570-rk3399-sd-drive-level-8ma.patch similarity index 100% rename from patch/kernel/archive/media-5.18/340-rk3399-sd-drive-level-8ma.patch rename to patch/kernel/archive/media-6.0/570-rk3399-sd-drive-level-8ma.patch diff --git a/patch/kernel/archive/media-5.18/350-rk3399-unlock-temperature.patch b/patch/kernel/archive/media-6.0/580-rk3399-unlock-temperature.patch similarity index 100% rename from patch/kernel/archive/media-5.18/350-rk3399-unlock-temperature.patch rename to patch/kernel/archive/media-6.0/580-rk3399-unlock-temperature.patch diff --git a/patch/kernel/archive/media-6.0/600-usb-fix.patch b/patch/kernel/archive/media-6.0/600-usb-fix.patch new file mode 100644 index 000000000..c4b775d41 --- /dev/null +++ b/patch/kernel/archive/media-6.0/600-usb-fix.patch @@ -0,0 +1,31 @@ +--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +@@ -1124,7 +1124,7 @@ + struct rockchip_usb2phy_port *rport, + struct device_node *child_np) + { +- int ret; ++ int ret, id; + + rport->port_id = USB2PHY_PORT_OTG; + rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; +@@ -1162,13 +1162,15 @@ + + ret = devm_extcon_register_notifier(rphy->dev, rphy->edev, + EXTCON_USB_HOST, &rport->event_nb); +- if (ret) ++ if (ret) { + dev_err(rphy->dev, "register USB HOST notifier failed\n"); ++ goto out; ++ } + + if (!of_property_read_bool(rphy->dev->of_node, "extcon")) { + /* do initial sync of usb state */ +- ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); +- extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret); ++ id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); ++ extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); + } + } + + diff --git a/patch/kernel/archive/media-5.18/980-builddeb.patch b/patch/kernel/archive/media-6.0/980-builddeb.patch similarity index 100% rename from patch/kernel/archive/media-5.18/980-builddeb.patch rename to patch/kernel/archive/media-6.0/980-builddeb.patch diff --git a/patch/kernel/archive/media-5.18/981-mkdebian.patch b/patch/kernel/archive/media-6.0/981-mkdebian.patch similarity index 100% rename from patch/kernel/archive/media-5.18/981-mkdebian.patch rename to patch/kernel/archive/media-6.0/981-mkdebian.patch diff --git a/patch/kernel/archive/station-p2-5.18/0010-v11-01-24-clk-rk3568-Mark-hclk_vo-as-critical.patch b/patch/kernel/archive/station-p2-5.18/0010-v11-01-24-clk-rk3568-Mark-hclk_vo-as-critical.patch deleted file mode 100755 index e5ca4b9ed..000000000 --- a/patch/kernel/archive/station-p2-5.18/0010-v11-01-24-clk-rk3568-Mark-hclk_vo-as-critical.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c -index 606ae6cd918b2..f85902e2590c7 100644 ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -1591,6 +1591,7 @@ static const char *const rk3568_cru_critical_clocks[] __initconst = { - "hclk_php", - "pclk_php", - "hclk_usb", -+ "hclk_vo", - }; - - static const char *const rk3568_pmucru_critical_clocks[] __initconst = { diff --git a/patch/kernel/archive/station-p2-5.18/0020-v11-02-24-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch b/patch/kernel/archive/station-p2-5.18/0020-v11-02-24-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch deleted file mode 100755 index 7c89ee1c2..000000000 --- a/patch/kernel/archive/station-p2-5.18/0020-v11-02-24-drm-rockchip-Embed-drm_encoder-into-rockchip_decoder.patch +++ /dev/null @@ -1,586 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c -index c82901d9a9ccd..28fcc8efa33db 100644 ---- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c -+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c -@@ -40,8 +40,6 @@ - - #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 - --#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm) -- - /** - * struct rockchip_dp_chip_data - splite the grf setting of kind of chips - * @lcdsel_grf_reg: grf register offset of lcdc select -@@ -59,7 +57,7 @@ struct rockchip_dp_chip_data { - struct rockchip_dp_device { - struct drm_device *drm_dev; - struct device *dev; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - struct drm_display_mode mode; - - struct clk *pclk; -@@ -73,6 +71,18 @@ struct rockchip_dp_device { - struct analogix_dp_plat_data plat_data; - }; - -+static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_dp_device, encoder); -+} -+ -+static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data) -+{ -+ return container_of(plat_data, struct rockchip_dp_device, plat_data); -+} -+ - static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) - { - reset_control_assert(dp->rst); -@@ -84,7 +94,7 @@ static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) - - static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data) - { -- struct rockchip_dp_device *dp = to_dp(plat_data); -+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); - int ret; - - ret = clk_prepare_enable(dp->pclk); -@@ -105,7 +115,7 @@ static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data) - - static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) - { -- struct rockchip_dp_device *dp = to_dp(plat_data); -+ struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); - - clk_disable_unprepare(dp->pclk); - -@@ -166,7 +176,7 @@ struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder, - static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) - { -- struct rockchip_dp_device *dp = to_dp(encoder); -+ struct rockchip_dp_device *dp = encoder_to_dp(encoder); - struct drm_crtc *crtc; - struct drm_crtc_state *old_crtc_state; - int ret; -@@ -208,7 +218,7 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, - static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) - { -- struct rockchip_dp_device *dp = to_dp(encoder); -+ struct rockchip_dp_device *dp = encoder_to_dp(encoder); - struct drm_crtc *crtc; - struct drm_crtc_state *new_crtc_state = NULL; - int ret; -@@ -297,7 +307,7 @@ static int rockchip_dp_of_probe(struct rockchip_dp_device *dp) - - static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp) - { -- struct drm_encoder *encoder = &dp->encoder; -+ struct drm_encoder *encoder = &dp->encoder.encoder; - struct drm_device *drm_dev = dp->drm_dev; - struct device *dev = dp->dev; - int ret; -@@ -333,7 +343,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master, - return ret; - } - -- dp->plat_data.encoder = &dp->encoder; -+ dp->plat_data.encoder = &dp->encoder.encoder; - - ret = analogix_dp_bind(dp->adp, drm_dev); - if (ret) -@@ -341,7 +351,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master, - - return 0; - err_cleanup_encoder: -- dp->encoder.funcs->destroy(&dp->encoder); -+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); - return ret; - } - -@@ -351,7 +361,7 @@ static void rockchip_dp_unbind(struct device *dev, struct device *master, - struct rockchip_dp_device *dp = dev_get_drvdata(dev); - - analogix_dp_unbind(dp->adp); -- dp->encoder.funcs->destroy(&dp->encoder); -+ dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); - } - - static const struct component_ops rockchip_dp_component_ops = { -diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c -index d3e6c93739bf6..8584e19792be2 100644 ---- a/drivers/gpu/drm/rockchip/cdn-dp-core.c -+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c -@@ -26,11 +26,17 @@ - #include "cdn-dp-reg.h" - #include "rockchip_drm_vop.h" - --#define connector_to_dp(c) \ -- container_of(c, struct cdn_dp_device, connector) -+static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector) -+{ -+ return container_of(connector, struct cdn_dp_device, connector); -+} - --#define encoder_to_dp(c) \ -- container_of(c, struct cdn_dp_device, encoder) -+static inline struct cdn_dp_device *encoder_to_dp(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct cdn_dp_device, encoder); -+} - - #define GRF_SOC_CON9 0x6224 - #define DP_SEL_VOP_LIT BIT(12) -@@ -1050,7 +1056,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data) - - INIT_WORK(&dp->event_work, cdn_dp_pd_event_work); - -- encoder = &dp->encoder; -+ encoder = &dp->encoder.encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, - dev->of_node); -@@ -1115,7 +1121,7 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data) - static void cdn_dp_unbind(struct device *dev, struct device *master, void *data) - { - struct cdn_dp_device *dp = dev_get_drvdata(dev); -- struct drm_encoder *encoder = &dp->encoder; -+ struct drm_encoder *encoder = &dp->encoder.encoder; - struct drm_connector *connector = &dp->connector; - - cancel_work_sync(&dp->event_work); -diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h b/drivers/gpu/drm/rockchip/cdn-dp-core.h -index 6d0c5032ef3ad..f7d4cecb46ba4 100644 ---- a/drivers/gpu/drm/rockchip/cdn-dp-core.h -+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h -@@ -66,7 +66,7 @@ struct cdn_dp_device { - struct device *dev; - struct drm_device *drm_dev; - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - struct drm_display_mode mode; - struct platform_device *audio_pdev; - struct work_struct event_work; -diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -index 4ed7a68681978..110e83aad9bb4 100644 ---- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c -@@ -181,8 +181,6 @@ - - #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) - --#define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm) -- - enum { - DW_DSI_USAGE_IDLE, - DW_DSI_USAGE_DSI, -@@ -236,7 +234,7 @@ struct rockchip_dw_dsi_chip_data { - - struct dw_mipi_dsi_rockchip { - struct device *dev; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - void __iomem *base; - - struct regmap *grf_regmap; -@@ -271,6 +269,13 @@ struct dw_mipi_dsi_rockchip { - bool dsi_bound; - }; - -+static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); -+} -+ - struct dphy_pll_parameter_map { - unsigned int max_mbps; - u8 hsfreqrange; -@@ -770,7 +775,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) - int ret, mux; - - mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, -- &dsi->encoder); -+ &dsi->encoder.encoder); - if (mux < 0) - return; - -@@ -801,7 +806,7 @@ dw_mipi_dsi_encoder_helper_funcs = { - static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, - struct drm_device *drm_dev) - { -- struct drm_encoder *encoder = &dsi->encoder; -+ struct drm_encoder *encoder = &dsi->encoder.encoder; - int ret; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, -@@ -959,7 +964,7 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev, - goto out_pll_clk; - } - -- ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); -+ ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); - if (ret) { - DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); - goto out_pll_clk; -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 8677c82716784..06c9ddef6f362 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -67,7 +67,7 @@ struct rockchip_hdmi_chip_data { - struct rockchip_hdmi { - struct device *dev; - struct regmap *regmap; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; - struct clk *vpll_clk; - struct clk *grf_clk; -@@ -75,7 +75,12 @@ struct rockchip_hdmi { - struct phy *phy; - }; - --#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) -+static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_hdmi, encoder); -+} - - static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - { -@@ -511,7 +516,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - hdmi->dev = &pdev->dev; - hdmi->chip_data = plat_data->phy_data; - plat_data->phy_data = hdmi; -- encoder = &hdmi->encoder; -+ encoder = &hdmi->encoder.encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); - /* -diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c -index 046e8ec2a71c5..0a4f72021d6af 100644 ---- a/drivers/gpu/drm/rockchip/inno_hdmi.c -+++ b/drivers/gpu/drm/rockchip/inno_hdmi.c -@@ -26,8 +26,6 @@ - - #include "inno_hdmi.h" - --#define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x) -- - struct hdmi_data_info { - int vic; - bool sink_is_hdmi; -@@ -56,7 +54,7 @@ struct inno_hdmi { - void __iomem *regs; - - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - - struct inno_hdmi_i2c *i2c; - struct i2c_adapter *ddc; -@@ -67,6 +65,18 @@ struct inno_hdmi { - struct drm_display_mode previous_mode; - }; - -+static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct inno_hdmi, encoder); -+} -+ -+static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector) -+{ -+ return container_of(connector, struct inno_hdmi, connector); -+} -+ - enum { - CSC_ITU601_16_235_TO_RGB_0_255_8BIT, - CSC_ITU601_0_255_TO_RGB_0_255_8BIT, -@@ -483,7 +493,7 @@ static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); -+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_setup(hdmi, adj_mode); - -@@ -493,14 +503,14 @@ static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder, - - static void inno_hdmi_encoder_enable(struct drm_encoder *encoder) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); -+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_set_pwr_mode(hdmi, NORMAL); - } - - static void inno_hdmi_encoder_disable(struct drm_encoder *encoder) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(encoder); -+ struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR); - } -@@ -536,7 +546,7 @@ static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = { - static enum drm_connector_status - inno_hdmi_connector_detect(struct drm_connector *connector, bool force) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(connector); -+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); - - return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? - connector_status_connected : connector_status_disconnected; -@@ -544,7 +554,7 @@ inno_hdmi_connector_detect(struct drm_connector *connector, bool force) - - static int inno_hdmi_connector_get_modes(struct drm_connector *connector) - { -- struct inno_hdmi *hdmi = to_inno_hdmi(connector); -+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); - struct edid *edid; - int ret = 0; - -@@ -599,7 +609,7 @@ static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = { - - static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) - { -- struct drm_encoder *encoder = &hdmi->encoder; -+ struct drm_encoder *encoder = &hdmi->encoder.encoder; - struct device *dev = hdmi->dev; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -@@ -879,7 +889,7 @@ static int inno_hdmi_bind(struct device *dev, struct device *master, - return 0; - err_cleanup_hdmi: - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - err_put_adapter: - i2c_put_adapter(hdmi->ddc); - err_disable_clk: -@@ -893,7 +903,7 @@ static void inno_hdmi_unbind(struct device *dev, struct device *master, - struct inno_hdmi *hdmi = dev_get_drvdata(dev); - - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - - i2c_put_adapter(hdmi->ddc); - clk_disable_unprepare(hdmi->pclk); -diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c -index 1c546c3a89984..319240c33dcc0 100644 ---- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c -+++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c -@@ -47,7 +47,7 @@ struct rk3066_hdmi { - void __iomem *regs; - - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - - struct rk3066_hdmi_i2c *i2c; - struct i2c_adapter *ddc; -@@ -58,7 +58,17 @@ struct rk3066_hdmi { - struct drm_display_mode previous_mode; - }; - --#define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x) -+static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rk3066_hdmi, encoder); -+} -+ -+static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector) -+{ -+ return container_of(connector, struct rk3066_hdmi, connector); -+} - - static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) - { -@@ -380,7 +390,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); -+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); - - /* Store the display mode for plugin/DPMS poweron events. */ - memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode)); -@@ -388,7 +398,7 @@ rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder, - - static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); -+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); - int mux, val; - - mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); -@@ -407,7 +417,7 @@ static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder) - - static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder); -+ struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder); - - DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); - -@@ -455,7 +465,7 @@ struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = { - static enum drm_connector_status - rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); -+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); - - return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? - connector_status_connected : connector_status_disconnected; -@@ -463,7 +473,7 @@ rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force) - - static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); -+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); - struct edid *edid; - int ret = 0; - -@@ -496,9 +506,9 @@ rk3066_hdmi_connector_mode_valid(struct drm_connector *connector, - static struct drm_encoder * - rk3066_hdmi_connector_best_encoder(struct drm_connector *connector) - { -- struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector); -+ struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector); - -- return &hdmi->encoder; -+ return &hdmi->encoder.encoder; - } - - static int -@@ -538,7 +548,7 @@ struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = { - static int - rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) - { -- struct drm_encoder *encoder = &hdmi->encoder; -+ struct drm_encoder *encoder = &hdmi->encoder.encoder; - struct device *dev = hdmi->dev; - - encoder->possible_crtcs = -@@ -816,7 +826,7 @@ static int rk3066_hdmi_bind(struct device *dev, struct device *master, - - err_cleanup_hdmi: - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - err_disable_i2c: - i2c_put_adapter(hdmi->ddc); - err_disable_hclk: -@@ -831,7 +841,7 @@ static void rk3066_hdmi_unbind(struct device *dev, struct device *master, - struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); - - hdmi->connector.funcs->destroy(&hdmi->connector); -- hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - - i2c_put_adapter(hdmi->ddc); - clk_disable_unprepare(hdmi->hclk); -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -index 008c44aef4001..048ab277de653 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -49,6 +49,10 @@ struct rockchip_drm_private { - struct drm_mm mm; - }; - -+struct rockchip_encoder { -+ struct drm_encoder encoder; -+}; -+ - int rockchip_drm_dma_attach_device(struct drm_device *drm_dev, - struct device *dev); - void rockchip_drm_dma_detach_device(struct drm_device *drm_dev, -@@ -66,4 +70,10 @@ extern struct platform_driver rockchip_dp_driver; - extern struct platform_driver rockchip_lvds_driver; - extern struct platform_driver vop_platform_driver; - extern struct platform_driver rk3066_hdmi_driver; -+ -+static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder) -+{ -+ return container_of(encoder, struct rockchip_encoder, encoder); -+} -+ - #endif /* _ROCKCHIP_DRM_DRV_H_ */ -diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c -index 0b972418067e8..25d8c24ef7729 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_lvds.c -+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c -@@ -36,12 +36,6 @@ - - struct rockchip_lvds; - --#define connector_to_lvds(c) \ -- container_of(c, struct rockchip_lvds, connector) -- --#define encoder_to_lvds(c) \ -- container_of(c, struct rockchip_lvds, encoder) -- - /** - * struct rockchip_lvds_soc_data - rockchip lvds Soc private data - * @probe: LVDS platform probe function -@@ -65,10 +59,22 @@ struct rockchip_lvds { - struct drm_panel *panel; - struct drm_bridge *bridge; - struct drm_connector connector; -- struct drm_encoder encoder; -+ struct rockchip_encoder encoder; - struct dev_pin_info *pins; - }; - -+static inline struct rockchip_lvds *connector_to_lvds(struct drm_connector *connector) -+{ -+ return container_of(connector, struct rockchip_lvds, connector); -+} -+ -+static inline struct rockchip_lvds *encoder_to_lvds(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_lvds, encoder); -+} -+ - static inline void rk3288_writel(struct rockchip_lvds *lvds, u32 offset, - u32 val) - { -@@ -599,7 +605,7 @@ static int rockchip_lvds_bind(struct device *dev, struct device *master, - goto err_put_remote; - } - -- encoder = &lvds->encoder; -+ encoder = &lvds->encoder.encoder; - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, - dev->of_node); - -@@ -674,10 +680,10 @@ static void rockchip_lvds_unbind(struct device *dev, struct device *master, - const struct drm_encoder_helper_funcs *encoder_funcs; - - encoder_funcs = lvds->soc_data->helper_funcs; -- encoder_funcs->disable(&lvds->encoder); -+ encoder_funcs->disable(&lvds->encoder.encoder); - pm_runtime_disable(dev); - drm_connector_cleanup(&lvds->connector); -- drm_encoder_cleanup(&lvds->encoder); -+ drm_encoder_cleanup(&lvds->encoder.encoder); - } - - static const struct component_ops rockchip_lvds_component_ops = { diff --git a/patch/kernel/archive/station-p2-5.18/0030-v11-03-24-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch b/patch/kernel/archive/station-p2-5.18/0030-v11-03-24-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch deleted file mode 100755 index 061cb5dc3..000000000 --- a/patch/kernel/archive/station-p2-5.18/0030-v11-03-24-drm-rockchip-Add-crtc_endpoint_id-to-rockchip_encoder.patch +++ /dev/null @@ -1,66 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 7efd12312354b..0dc09d92d92d6 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -244,6 +244,39 @@ static const struct dev_pm_ops rockchip_drm_pm_ops = { - static struct platform_driver *rockchip_sub_drivers[MAX_ROCKCHIP_SUB_DRIVERS]; - static int num_rockchip_sub_drivers; - -+/* -+ * Get the endpoint id of the remote endpoint of the given encoder. This -+ * information is used by the VOP2 driver to identify the encoder. -+ * -+ * @rkencoder: The encoder to get the remote endpoint id from -+ * @np: The encoder device node -+ * @port: The number of the port leading to the VOP2 -+ * @reg: The endpoint number leading to the VOP2 -+ */ -+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rkencoder, -+ struct device_node *np, int port, int reg) -+{ -+ struct of_endpoint ep; -+ struct device_node *en, *ren; -+ int ret; -+ -+ en = of_graph_get_endpoint_by_regs(np, port, reg); -+ if (!en) -+ return -ENOENT; -+ -+ ren = of_graph_get_remote_endpoint(en); -+ if (!ren) -+ return -ENOENT; -+ -+ ret = of_graph_parse_endpoint(ren, &ep); -+ if (ret) -+ return ret; -+ -+ rkencoder->crtc_endpoint_id = ep.id; -+ -+ return 0; -+} -+ - /* - * Check if a vop endpoint is leading to a rockchip subdriver or bridge. - * Should be called from the component bind stage of the drivers -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -index 048ab277de653..a27ab928e1d2f 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -50,6 +50,7 @@ struct rockchip_drm_private { - }; - - struct rockchip_encoder { -+ int crtc_endpoint_id; - struct drm_encoder encoder; - }; - -@@ -60,7 +61,8 @@ void rockchip_drm_dma_detach_device(struct drm_device *drm_dev, - void rockchip_drm_dma_init_device(struct drm_device *drm_dev, - struct device *dev); - int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout); -- -+int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder, -+ struct device_node *np, int port, int reg); - int rockchip_drm_endpoint_is_subdriver(struct device_node *ep); - extern struct platform_driver cdn_dp_driver; - extern struct platform_driver dw_hdmi_rockchip_pltfm_driver; diff --git a/patch/kernel/archive/station-p2-5.18/0040-v11-04-24-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch b/patch/kernel/archive/station-p2-5.18/0040-v11-04-24-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch deleted file mode 100755 index dfdee44c9..000000000 --- a/patch/kernel/archive/station-p2-5.18/0040-v11-04-24-drm-rockchip-dw_hdmi-rename-vpll-clock-to-reference-clock.patch +++ /dev/null @@ -1,75 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 06c9ddef6f362..912181429880a 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -69,7 +69,7 @@ struct rockchip_hdmi { - struct regmap *regmap; - struct rockchip_encoder encoder; - const struct rockchip_hdmi_chip_data *chip_data; -- struct clk *vpll_clk; -+ struct clk *ref_clk; - struct clk *grf_clk; - struct dw_hdmi *hdmi; - struct phy *phy; -@@ -201,14 +201,15 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) - return PTR_ERR(hdmi->regmap); - } - -- hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll"); -- if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) { -- hdmi->vpll_clk = NULL; -- } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) { -+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref"); -+ if (!hdmi->ref_clk) -+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll"); -+ -+ if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) { - return -EPROBE_DEFER; -- } else if (IS_ERR(hdmi->vpll_clk)) { -- DRM_DEV_ERROR(hdmi->dev, "failed to get vpll clock\n"); -- return PTR_ERR(hdmi->vpll_clk); -+ } else if (IS_ERR(hdmi->ref_clk)) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n"); -+ return PTR_ERR(hdmi->ref_clk); - } - - hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); -@@ -262,7 +263,7 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, - { - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); - -- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000); -+ clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); - } - - static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) -@@ -542,9 +543,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -- ret = clk_prepare_enable(hdmi->vpll_clk); -+ ret = clk_prepare_enable(hdmi->ref_clk); - if (ret) { -- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", -+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", - ret); - return ret; - } -@@ -563,7 +564,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - if (IS_ERR(hdmi->hdmi)) { - ret = PTR_ERR(hdmi->hdmi); - drm_encoder_cleanup(encoder); -- clk_disable_unprepare(hdmi->vpll_clk); -+ clk_disable_unprepare(hdmi->ref_clk); - } - - return ret; -@@ -575,7 +576,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, - struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); - - dw_hdmi_unbind(hdmi->hdmi); -- clk_disable_unprepare(hdmi->vpll_clk); -+ clk_disable_unprepare(hdmi->ref_clk); - } - - static const struct component_ops dw_hdmi_rockchip_ops = { diff --git a/patch/kernel/archive/station-p2-5.18/0050-v11-05-24-dt-bindings-display-rockchip-dw-hdmi-use-ref-as-clock-name.patch b/patch/kernel/archive/station-p2-5.18/0050-v11-05-24-dt-bindings-display-rockchip-dw-hdmi-use-ref-as-clock-name.patch deleted file mode 100755 index e12a58148..000000000 --- a/patch/kernel/archive/station-p2-5.18/0050-v11-05-24-dt-bindings-display-rockchip-dw-hdmi-use-ref-as-clock-name.patch +++ /dev/null @@ -1,30 +0,0 @@ -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index da3b889ad8fcd..0400f67e5f2c9 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -36,7 +36,8 @@ properties: - # order when present. - - description: The HDMI CEC controller main clock - - description: Power for GRF IO -- - description: External clock for some HDMI PHY -+ - description: External clock for some HDMI PHY (old clock name, deprecated) -+ - description: External clock for some HDMI PHY (new name) - - clock-names: - minItems: 2 -@@ -47,10 +48,14 @@ properties: - - cec - - grf - - vpll -+ - ref - - enum: - - grf - - vpll -- - const: vpll -+ - ref -+ - enum: -+ - vpll -+ - ref - - ddc-i2c-bus: - $ref: /schemas/types.yaml#/definitions/phandle diff --git a/patch/kernel/archive/station-p2-5.18/0060-v11-06-24-arm64-dts-rockchip-rk3399-rename-HDMI-ref-clock-to-ref.patch b/patch/kernel/archive/station-p2-5.18/0060-v11-06-24-arm64-dts-rockchip-rk3399-rename-HDMI-ref-clock-to-ref.patch deleted file mode 100755 index d0e18fac9..000000000 --- a/patch/kernel/archive/station-p2-5.18/0060-v11-06-24-arm64-dts-rockchip-rk3399-rename-HDMI-ref-clock-to-ref.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 080457a68e3c7..d0add619b0d22 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1884,7 +1884,7 @@ hdmi: hdmi@ff940000 { - <&cru SCLK_HDMI_CEC>, - <&cru PCLK_VIO_GRF>, - <&cru PLL_VPLL>; -- clock-names = "iahb", "isfr", "cec", "grf", "vpll"; -+ clock-names = "iahb", "isfr", "cec", "grf", "ref"; - power-domains = <&power RK3399_PD_HDCP>; - reg-io-width = <4>; - rockchip,grf = <&grf>; diff --git a/patch/kernel/archive/station-p2-5.18/0070-v11-07-24-drm-rockchip-dw_hdmi-add-rk3568-support.patch b/patch/kernel/archive/station-p2-5.18/0070-v11-07-24-drm-rockchip-dw_hdmi-add-rk3568-support.patch deleted file mode 100755 index 0ee6d28a0..000000000 --- a/patch/kernel/archive/station-p2-5.18/0070-v11-07-24-drm-rockchip-dw_hdmi-add-rk3568-support.patch +++ /dev/null @@ -1,70 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 912181429880a..b64cc62c7b5af 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -50,6 +50,10 @@ - #define RK3399_GRF_SOC_CON20 0x6250 - #define RK3399_HDMI_LCDC_SEL BIT(6) - -+#define RK3568_GRF_VO_CON1 0x0364 -+#define RK3568_HDMI_SDAIN_MSK BIT(15) -+#define RK3568_HDMI_SCLIN_MSK BIT(14) -+ - #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) - - /** -@@ -473,6 +477,19 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { - .use_drm_infoframe = true, - }; - -+static struct rockchip_hdmi_chip_data rk3568_chip_data = { -+ .lcdsel_grf_reg = -1, -+}; -+ -+static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { -+ .mode_valid = dw_hdmi_rockchip_mode_valid, -+ .mpll_cfg = rockchip_mpll_cfg, -+ .cur_ctr = rockchip_cur_ctr, -+ .phy_config = rockchip_phy_config, -+ .phy_data = &rk3568_chip_data, -+ .use_drm_infoframe = true, -+}; -+ - static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { - { .compatible = "rockchip,rk3228-dw-hdmi", - .data = &rk3228_hdmi_drv_data -@@ -486,6 +503,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { - { .compatible = "rockchip,rk3399-dw-hdmi", - .data = &rk3399_hdmi_drv_data - }, -+ { .compatible = "rockchip,rk3568-dw-hdmi", -+ .data = &rk3568_hdmi_drv_data -+ }, - {}, - }; - MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); -@@ -520,6 +540,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - encoder = &hdmi->encoder.encoder; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -+ rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, -+ dev->of_node, 0, 0); -+ - /* - * If we failed to find the CRTC(s) which this encoder is - * supposed to be connected to, it's because the CRTC has -@@ -550,6 +573,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -+ if (hdmi->chip_data == &rk3568_chip_data) { -+ regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, -+ HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | -+ RK3568_HDMI_SCLIN_MSK, -+ RK3568_HDMI_SDAIN_MSK | -+ RK3568_HDMI_SCLIN_MSK)); -+ } -+ - drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - diff --git a/patch/kernel/archive/station-p2-5.18/0080-v11-08-24-dt-bindings-display-rockchip-dw-hdmi-Add-compatible-for-rk3568-HDMI.patch b/patch/kernel/archive/station-p2-5.18/0080-v11-08-24-dt-bindings-display-rockchip-dw-hdmi-Add-compatible-for-rk3568-HDMI.patch deleted file mode 100755 index 06e6cd929..000000000 --- a/patch/kernel/archive/station-p2-5.18/0080-v11-08-24-dt-bindings-display-rockchip-dw-hdmi-Add-compatible-for-rk3568-HDMI.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index 0400f67e5f2c9..e6b8437a1e2d1 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -23,6 +23,7 @@ properties: - - rockchip,rk3288-dw-hdmi - - rockchip,rk3328-dw-hdmi - - rockchip,rk3399-dw-hdmi -+ - rockchip,rk3568-dw-hdmi - - reg-io-width: - const: 4 diff --git a/patch/kernel/archive/station-p2-5.18/0090-v11-09-24-drm-rockchip-dw_hdmi-add-regulator-support.patch b/patch/kernel/archive/station-p2-5.18/0090-v11-09-24-drm-rockchip-dw_hdmi-add-regulator-support.patch deleted file mode 100755 index 322b0b2a8..000000000 --- a/patch/kernel/archive/station-p2-5.18/0090-v11-09-24-drm-rockchip-dw_hdmi-add-regulator-support.patch +++ /dev/null @@ -1,93 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index b64cc62c7b5af..fe4f9556239ac 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -76,6 +77,8 @@ struct rockchip_hdmi { - struct clk *ref_clk; - struct clk *grf_clk; - struct dw_hdmi *hdmi; -+ struct regulator *avdd_0v9; -+ struct regulator *avdd_1v8; - struct phy *phy; - }; - -@@ -226,6 +229,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) - return PTR_ERR(hdmi->grf_clk); - } - -+ hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); -+ if (IS_ERR(hdmi->avdd_0v9)) -+ return PTR_ERR(hdmi->avdd_0v9); -+ -+ hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8"); -+ if (IS_ERR(hdmi->avdd_1v8)) -+ return PTR_ERR(hdmi->avdd_1v8); -+ - return 0; - } - -@@ -566,11 +577,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - return ret; - } - -+ ret = regulator_enable(hdmi->avdd_0v9); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); -+ goto err_avdd_0v9; -+ } -+ -+ ret = regulator_enable(hdmi->avdd_1v8); -+ if (ret) { -+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); -+ goto err_avdd_1v8; -+ } -+ - ret = clk_prepare_enable(hdmi->ref_clk); - if (ret) { - DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", - ret); -- return ret; -+ goto err_clk; - } - - if (hdmi->chip_data == &rk3568_chip_data) { -@@ -594,10 +617,19 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, - */ - if (IS_ERR(hdmi->hdmi)) { - ret = PTR_ERR(hdmi->hdmi); -- drm_encoder_cleanup(encoder); -- clk_disable_unprepare(hdmi->ref_clk); -+ goto err_bind; - } - -+ return 0; -+ -+err_bind: -+ clk_disable_unprepare(hdmi->ref_clk); -+ drm_encoder_cleanup(encoder); -+err_clk: -+ regulator_disable(hdmi->avdd_1v8); -+err_avdd_1v8: -+ regulator_disable(hdmi->avdd_0v9); -+err_avdd_0v9: - return ret; - } - -@@ -608,6 +640,9 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, - - dw_hdmi_unbind(hdmi->hdmi); - clk_disable_unprepare(hdmi->ref_clk); -+ -+ regulator_disable(hdmi->avdd_1v8); -+ regulator_disable(hdmi->avdd_0v9); - } - - static const struct component_ops dw_hdmi_rockchip_ops = { diff --git a/patch/kernel/archive/station-p2-5.18/0100-v11-10-24-dt-bindings-display-rockchip-dw-hdmi-Add-regulator-support.patch b/patch/kernel/archive/station-p2-5.18/0100-v11-10-24-dt-bindings-display-rockchip-dw-hdmi-Add-regulator-support.patch deleted file mode 100755 index 3bc22b037..000000000 --- a/patch/kernel/archive/station-p2-5.18/0100-v11-10-24-dt-bindings-display-rockchip-dw-hdmi-Add-regulator-support.patch +++ /dev/null @@ -1,22 +0,0 @@ -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index e6b8437a1e2d1..38ebb69830287 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -28,6 +28,17 @@ properties: - reg-io-width: - const: 4 - -+ avdd-0v9-supply: -+ description: -+ A 0.9V supply that powers up the SoC internal circuitry. The actual pin name -+ varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes -+ HDMI_AVDD_1V0. -+ -+ avdd-1v8-supply: -+ description: -+ A 1.8V supply that powers up the SoC internal circuitry. The pin name on the -+ SoC usually is HDMI_TX_AVDD_1V8. -+ - clocks: - minItems: 2 - items: diff --git a/patch/kernel/archive/station-p2-5.18/0110-v11-11-24-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch b/patch/kernel/archive/station-p2-5.18/0110-v11-11-24-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch deleted file mode 100755 index d740d4bef..000000000 --- a/patch/kernel/archive/station-p2-5.18/0110-v11-11-24-drm-rockchip-dw_hdmi-Use-auto-generated-tables.patch +++ /dev/null @@ -1,154 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index fe4f9556239ac..cb43e7b47157d 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -91,80 +91,88 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) - - static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - { -- 27000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -+ 30666000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2153, 0x0000 }, -+ { 0x40f3, 0x0000 }, - }, -- }, { -- 36000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -+ }, { -+ 36800000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2153, 0x0000 }, -+ { 0x40a2, 0x0001 }, - }, -- }, { -- 40000000, { -- { 0x00b3, 0x0000}, -- { 0x2153, 0x0000}, -- { 0x40f3, 0x0000} -+ }, { -+ 46000000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2142, 0x0001 }, -+ { 0x40a2, 0x0001 }, - }, -- }, { -- 54000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -+ }, { -+ 61333000, { -+ { 0x0072, 0x0001 }, -+ { 0x2142, 0x0001 }, -+ { 0x40a2, 0x0001 }, - }, -- }, { -- 65000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -+ }, { -+ 73600000, { -+ { 0x0072, 0x0001 }, -+ { 0x2142, 0x0001 }, -+ { 0x4061, 0x0002 }, - }, -- }, { -- 66000000, { -- { 0x013e, 0x0003}, -- { 0x217e, 0x0002}, -- { 0x4061, 0x0002} -+ }, { -+ 92000000, { -+ { 0x0072, 0x0001 }, -+ { 0x2145, 0x0002 }, -+ { 0x4061, 0x0002 }, - }, -- }, { -- 74250000, { -- { 0x0072, 0x0001}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -+ }, { -+ 122666000, { -+ { 0x0051, 0x0002 }, -+ { 0x2145, 0x0002 }, -+ { 0x4061, 0x0002 }, - }, -- }, { -- 83500000, { -- { 0x0072, 0x0001}, -+ }, { -+ 147200000, { -+ { 0x0051, 0x0002 }, -+ { 0x2145, 0x0002 }, -+ { 0x4064, 0x0003 }, - }, -- }, { -- 108000000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -+ }, { -+ 184000000, { -+ { 0x0051, 0x0002 }, -+ { 0x214c, 0x0003 }, -+ { 0x4064, 0x0003 }, - }, -- }, { -- 106500000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -+ }, { -+ 226666000, { -+ { 0x0040, 0x0003 }, -+ { 0x214c, 0x0003 }, -+ { 0x4064, 0x0003 }, - }, -- }, { -- 146250000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -+ }, { -+ 272000000, { -+ { 0x0040, 0x0003 }, -+ { 0x214c, 0x0003 }, -+ { 0x5a64, 0x0003 }, - }, -- }, { -- 148500000, { -- { 0x0051, 0x0003}, -- { 0x214c, 0x0003}, -- { 0x4064, 0x0003} -+ }, { -+ 340000000, { -+ { 0x0040, 0x0003 }, -+ { 0x3b4c, 0x0003 }, -+ { 0x5a64, 0x0003 }, - }, -- }, { -+ }, { -+ 600000000, { -+ { 0x1a40, 0x0003 }, -+ { 0x3b4c, 0x0003 }, -+ { 0x5a64, 0x0003 }, -+ }, -+ }, { - ~0UL, { -- { 0x00a0, 0x000a }, -- { 0x2001, 0x000f }, -- { 0x4002, 0x000f }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, -+ { 0x0000, 0x0000 }, - }, - } - }; diff --git a/patch/kernel/archive/station-p2-5.18/0120-v11-12-24-drm-rockchip-dw_hdmi-relax-mode_valid-hook.patch b/patch/kernel/archive/station-p2-5.18/0120-v11-12-24-drm-rockchip-dw_hdmi-relax-mode_valid-hook.patch deleted file mode 100755 index 13e4980e1..000000000 --- a/patch/kernel/archive/station-p2-5.18/0120-v11-12-24-drm-rockchip-dw_hdmi-relax-mode_valid-hook.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index cb43e7b47157d..a77a46a709809 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -259,7 +259,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, - int i; - - for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { -- if (pclk == mpll_cfg[i].mpixelclock) { -+ if (pclk <= mpll_cfg[i].mpixelclock) { - valid = true; - break; - } diff --git a/patch/kernel/archive/station-p2-5.18/0130-v11-13-24-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch b/patch/kernel/archive/station-p2-5.18/0130-v11-13-24-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch deleted file mode 100755 index 80d2ef524..000000000 --- a/patch/kernel/archive/station-p2-5.18/0130-v11-13-24-drm-rockchip-dw_hdmi-Set-cur_ctr-to-0-always.patch +++ /dev/null @@ -1,27 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index a77a46a709809..ed480f6548f0e 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -180,20 +180,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { - static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { - /* pixelclk bpp8 bpp10 bpp12 */ - { -- 40000000, { 0x0018, 0x0018, 0x0018 }, -- }, { -- 65000000, { 0x0028, 0x0028, 0x0028 }, -- }, { -- 66000000, { 0x0038, 0x0038, 0x0038 }, -- }, { -- 74250000, { 0x0028, 0x0038, 0x0038 }, -- }, { -- 83500000, { 0x0028, 0x0038, 0x0038 }, -- }, { -- 146250000, { 0x0038, 0x0038, 0x0038 }, -- }, { -- 148500000, { 0x0000, 0x0038, 0x0038 }, -- }, { -+ 600000000, { 0x0000, 0x0000, 0x0000 }, -+ }, { - ~0UL, { 0x0000, 0x0000, 0x0000}, - } - }; diff --git a/patch/kernel/archive/station-p2-5.18/0140-v11-14-24-drm-rockchip-dw_hdmi-add-default-594Mhz-clk-for-4K-60hz.patch b/patch/kernel/archive/station-p2-5.18/0140-v11-14-24-drm-rockchip-dw_hdmi-add-default-594Mhz-clk-for-4K-60hz.patch deleted file mode 100755 index 7e779ea3a..000000000 --- a/patch/kernel/archive/station-p2-5.18/0140-v11-14-24-drm-rockchip-dw_hdmi-add-default-594Mhz-clk-for-4K-60hz.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index ed480f6548f0e..de8720fd7d5d6 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -191,6 +191,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { - { 74250000, 0x8009, 0x0004, 0x0272}, - { 148500000, 0x802b, 0x0004, 0x028d}, - { 297000000, 0x8039, 0x0005, 0x028d}, -+ { 594000000, 0x8039, 0x0000, 0x019d}, - { ~0UL, 0x0000, 0x0000, 0x0000} - }; - diff --git a/patch/kernel/archive/station-p2-5.18/0150-v11-15-24-dt-bindings-display-rockchip-dw-hdmi-Make-unwedge-pinctrl-optional.patch b/patch/kernel/archive/station-p2-5.18/0150-v11-15-24-dt-bindings-display-rockchip-dw-hdmi-Make-unwedge-pinctrl-optional.patch deleted file mode 100755 index 5e75852e8..000000000 --- a/patch/kernel/archive/station-p2-5.18/0150-v11-15-24-dt-bindings-display-rockchip-dw-hdmi-Make-unwedge-pinctrl-optional.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index 38ebb69830287..d7cb2b2be60e8 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -89,6 +89,7 @@ properties: - The unwedge pinctrl entry shall drive the DDC SDA line low. This is - intended to work around a hardware errata that can cause the DDC I2C - bus to be wedged. -+ minItems: 1 - items: - - const: default - - const: unwedge diff --git a/patch/kernel/archive/station-p2-5.18/0160-v11-16-24-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch b/patch/kernel/archive/station-p2-5.18/0160-v11-16-24-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch deleted file mode 100755 index 1abc00699..000000000 --- a/patch/kernel/archive/station-p2-5.18/0160-v11-16-24-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch +++ /dev/null @@ -1,113 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi -index 3839eef5e4f76..595fa2562cb8e 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi -@@ -18,3 +18,7 @@ power-domain@RK3568_PD_PIPE { - #power-domain-cells = <0>; - }; - }; -+ -+&vop { -+ compatible = "rockchip,rk3566-vop"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -index 5b0f528d68180..4deab90e83834 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -114,3 +114,7 @@ power-domain@RK3568_PD_PIPE { - #power-domain-cells = <0>; - }; - }; -+ -+&vop { -+ compatible = "rockchip,rk3568-vop"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index 7cdef800cb3ce..fdb7a9a6ca743 100644 ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -129,6 +129,11 @@ opp-1800000000 { - }; - }; - -+ display_subsystem: display-subsystem { -+ compatible = "rockchip,display-subsystem"; -+ ports = <&vop_out>; -+ }; -+ - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; -@@ -569,6 +574,52 @@ gmac1_mtl_tx_setup: tx-queues-config { - }; - }; - -+ vop: vop@fe040000 { -+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; -+ reg-names = "regs", "gamma_lut"; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; -+ clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; -+ iommus = <&vop_mmu>; -+ power-domains = <&power RK3568_PD_VO>; -+ rockchip,grf = <&grf>; -+ status = "disabled"; -+ -+ vop_out: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ vp0: port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ vp1: port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ vp2: port@2 { -+ reg = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ -+ vop_mmu: iommu@fe043e00 { -+ compatible = "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; -+ clock-names = "aclk", "iface"; -+ #iommu-cells = <0>; -+ status = "disabled"; -+ }; -+ - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; -diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h -new file mode 100644 -index 0000000000000..6e66a802b96a5 ---- /dev/null -+++ b/include/dt-bindings/soc/rockchip,vop2.h -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ -+ -+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H -+#define __DT_BINDINGS_ROCKCHIP_VOP2_H -+ -+#define ROCKCHIP_VOP2_EP_RGB0 1 -+#define ROCKCHIP_VOP2_EP_HDMI0 2 -+#define ROCKCHIP_VOP2_EP_EDP0 3 -+#define ROCKCHIP_VOP2_EP_MIPI0 4 -+#define ROCKCHIP_VOP2_EP_LVDS0 5 -+#define ROCKCHIP_VOP2_EP_MIPI1 6 -+#define ROCKCHIP_VOP2_EP_LVDS1 7 -+ -+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ diff --git a/patch/kernel/archive/station-p2-5.18/0170-v11-17-24-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch b/patch/kernel/archive/station-p2-5.18/0170-v11-17-24-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch deleted file mode 100755 index 5ff391880..000000000 --- a/patch/kernel/archive/station-p2-5.18/0170-v11-17-24-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch +++ /dev/null @@ -1,43 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index fdb7a9a6ca743..1a359bbf65300 100644 ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -620,6 +620,38 @@ vop_mmu: iommu@fe043e00 { - status = "disabled"; - }; - -+ hdmi: hdmi@fe0a0000 { -+ compatible = "rockchip,rk3568-dw-hdmi"; -+ reg = <0x0 0xfe0a0000 0x0 0x20000>; -+ interrupts = ; -+ clocks = <&cru PCLK_HDMI_HOST>, -+ <&cru CLK_HDMI_SFR>, -+ <&cru CLK_HDMI_CEC>, -+ <&pmucru CLK_HDMI_REF>, -+ <&cru HCLK_VO>; -+ clock-names = "iahb", "isfr", "cec", "ref"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; -+ power-domains = <&power RK3568_PD_VO>; -+ reg-io-width = <4>; -+ rockchip,grf = <&grf>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hdmi_in: port@0 { -+ reg = <0>; -+ }; -+ -+ hdmi_out: port@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; diff --git a/patch/kernel/archive/station-p2-5.18/0180-v11-18-24-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch b/patch/kernel/archive/station-p2-5.18/0180-v11-18-24-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch deleted file mode 100755 index 45d2723a5..000000000 --- a/patch/kernel/archive/station-p2-5.18/0180-v11-18-24-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch +++ /dev/null @@ -1,76 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -index a794a0ea5c701..096b66d7697e2 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include "rk3568.dtsi" - - / { -@@ -34,6 +35,17 @@ dc_12v: dc-12v { - regulator-max-microvolt = <12000000>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -189,6 +201,24 @@ &gpu { - status = "okay"; - }; - -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -589,3 +619,20 @@ &usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; - }; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/patch/kernel/archive/station-p2-5.18/0190-v11-19-24-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz64a.patch b/patch/kernel/archive/station-p2-5.18/0190-v11-19-24-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz64a.patch deleted file mode 100755 index cb43aa187..000000000 --- a/patch/kernel/archive/station-p2-5.18/0190-v11-19-24-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz64a.patch +++ /dev/null @@ -1,76 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -index dd7f4b9b686b8..6504f7ab3ea77 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3566.dtsi" - - / { -@@ -35,6 +36,17 @@ fan: gpio_fan { - #cooling-cells = <2>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -248,6 +260,24 @@ &gpu { - status = "okay"; - }; - -+&hdmi { -+ avdd-0v9-supply = <&vdda_0v9>; -+ avdd-1v8-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -685,3 +715,20 @@ &usb2phy1_otg { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; - }; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/patch/kernel/archive/station-p2-5.18/0200-v11-21-24-drm-rockchip-Make-VOP-driver-optional.patch b/patch/kernel/archive/station-p2-5.18/0200-v11-21-24-drm-rockchip-Make-VOP-driver-optional.patch deleted file mode 100755 index e0d14518b..000000000 --- a/patch/kernel/archive/station-p2-5.18/0200-v11-21-24-drm-rockchip-Make-VOP-driver-optional.patch +++ /dev/null @@ -1,49 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig -index fa5cfda4e90e3..22cf6c8402c89 100644 ---- a/drivers/gpu/drm/rockchip/Kconfig -+++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -23,8 +23,16 @@ config DRM_ROCKCHIP - - if DRM_ROCKCHIP - -+config ROCKCHIP_VOP -+ bool "Rockchip VOP driver" -+ default y -+ help -+ This selects support for the VOP driver. You should enable it -+ on older SoCs. -+ - config ROCKCHIP_ANALOGIX_DP - bool "Rockchip specific extensions for Analogix DP driver" -+ depends on ROCKCHIP_VOP - help - This selects support for Rockchip SoC specific extensions - for the Analogix Core DP driver. If you want to enable DP -diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile -index 1a56f696558ca..dfc5512fdb9f1 100644 ---- a/drivers/gpu/drm/rockchip/Makefile -+++ b/drivers/gpu/drm/rockchip/Makefile -@@ -4,8 +4,9 @@ - # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. - - rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ -- rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o -+ rockchip_drm_gem.o - -+rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 0dc09d92d92d6..6ab0460819467 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -481,7 +481,7 @@ static int __init rockchip_drm_init(void) - return -ENODEV; - - num_rockchip_sub_drivers = 0; -- ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP); -+ ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver, - CONFIG_ROCKCHIP_LVDS); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver, diff --git a/patch/kernel/archive/station-p2-5.18/0210-v11-22-24-drm-rockchip-Add-VOP2-driver.patch b/patch/kernel/archive/station-p2-5.18/0210-v11-22-24-drm-rockchip-Add-VOP2-driver.patch deleted file mode 100755 index 09420f56d..000000000 --- a/patch/kernel/archive/station-p2-5.18/0210-v11-22-24-drm-rockchip-Add-VOP2-driver.patch +++ /dev/null @@ -1,3599 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig -index 22cf6c8402c89..6c24e817b22d2 100644 ---- a/drivers/gpu/drm/rockchip/Kconfig -+++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -30,6 +30,12 @@ config ROCKCHIP_VOP - This selects support for the VOP driver. You should enable it - on older SoCs. - -+config ROCKCHIP_VOP2 -+ bool "Rockchip VOP2 driver" -+ help -+ This selects support for the VOP2 driver. The VOP2 hardware is -+ first found on the RK3568. -+ - config ROCKCHIP_ANALOGIX_DP - bool "Rockchip specific extensions for Analogix DP driver" - depends on ROCKCHIP_VOP -diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile -index dfc5512fdb9f1..3ff7b21c04149 100644 ---- a/drivers/gpu/drm/rockchip/Makefile -+++ b/drivers/gpu/drm/rockchip/Makefile -@@ -6,6 +6,7 @@ - rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ - rockchip_drm_gem.o - -+rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 6ab0460819467..67d38f53d3e50 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -482,6 +482,7 @@ static int __init rockchip_drm_init(void) - - num_rockchip_sub_drivers = 0; - ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP); -+ ADD_ROCKCHIP_SUB_DRIVER(vop2_platform_driver, CONFIG_ROCKCHIP_VOP2); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver, - CONFIG_ROCKCHIP_LVDS); - ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver, -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -index a27ab928e1d2f..1641440837af5 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -18,7 +18,7 @@ - - #define ROCKCHIP_MAX_FB_BUFFER 3 - #define ROCKCHIP_MAX_CONNECTOR 2 --#define ROCKCHIP_MAX_CRTC 2 -+#define ROCKCHIP_MAX_CRTC 4 - - struct drm_device; - struct drm_connector; -@@ -31,6 +31,9 @@ struct rockchip_crtc_state { - int output_bpc; - int output_flags; - bool enable_afbc; -+ u32 bus_format; -+ u32 bus_flags; -+ int color_space; - }; - #define to_rockchip_crtc_state(s) \ - container_of(s, struct rockchip_crtc_state, base) -@@ -72,6 +75,7 @@ extern struct platform_driver rockchip_dp_driver; - extern struct platform_driver rockchip_lvds_driver; - extern struct platform_driver vop_platform_driver; - extern struct platform_driver rk3066_hdmi_driver; -+extern struct platform_driver vop2_platform_driver; - - static inline struct rockchip_encoder *to_rockchip_encoder(struct drm_encoder *encoder) - { -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -index 3aa37e177667e..0d2cb4f3922b8 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -@@ -134,4 +134,6 @@ void rockchip_drm_mode_config_init(struct drm_device *dev) - - dev->mode_config.funcs = &rockchip_drm_mode_config_funcs; - dev->mode_config.helper_private = &rockchip_mode_config_helpers; -+ -+ dev->mode_config.normalize_zpos = true; - } -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 857d97cdc67c6..1e364d7b50e69 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -54,9 +54,23 @@ struct vop_afbc { - struct vop_reg enable; - struct vop_reg win_sel; - struct vop_reg format; -+ struct vop_reg rb_swap; -+ struct vop_reg uv_swap; -+ struct vop_reg auto_gating_en; -+ struct vop_reg block_split_en; -+ struct vop_reg pic_vir_width; -+ struct vop_reg tile_num; - struct vop_reg hreg_block_split; -+ struct vop_reg pic_offset; - struct vop_reg pic_size; -+ struct vop_reg dsp_offset; -+ struct vop_reg transform_offset; - struct vop_reg hdr_ptr; -+ struct vop_reg half_block_en; -+ struct vop_reg xmirror; -+ struct vop_reg ymirror; -+ struct vop_reg rotate_270; -+ struct vop_reg rotate_90; - struct vop_reg rstn; - }; - -@@ -410,4 +424,5 @@ static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) - } - - extern const struct component_ops vop_component_ops; -+ - #endif /* _ROCKCHIP_DRM_VOP_H */ -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -new file mode 100644 -index 0000000000000..8d1323a47f822 ---- /dev/null -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c -@@ -0,0 +1,2706 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd. -+ * Author: Andy Yan -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "rockchip_drm_drv.h" -+#include "rockchip_drm_gem.h" -+#include "rockchip_drm_fb.h" -+#include "rockchip_drm_vop2.h" -+ -+/* -+ * VOP2 architecture -+ * -+ +----------+ +-------------+ +-----------+ -+ | Cluster | | Sel 1 from 6| | 1 from 3 | -+ | window0 | | Layer0 | | RGB | -+ +----------+ +-------------+ +---------------+ +-------------+ +-----------+ -+ +----------+ +-------------+ |N from 6 layers| | | -+ | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+ -+ | window1 | | Layer1 | | | | | | 1 from 3 | -+ +----------+ +-------------+ +---------------+ +-------------+ | LVDS | -+ +----------+ +-------------+ +-----------+ -+ | Esmart | | Sel 1 from 6| -+ | window0 | | Layer2 | +---------------+ +-------------+ +-----------+ -+ +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 | -+ +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI | -+ | Esmart | | Sel 1 from 6| --------> | | | | +-----------+ -+ | Window1 | | Layer3 | +---------------+ +-------------+ -+ +----------+ +-------------+ +-----------+ -+ +----------+ +-------------+ | 1 from 3 | -+ | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI | -+ | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+ -+ +----------+ +-------------+ | Overlay2 +--->| Video Port2 | -+ +----------+ +-------------+ | | | | +-----------+ -+ | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 | -+ | Window1 | | Layer5 | | eDP | -+ +----------+ +-------------+ +-----------+ -+ * -+ */ -+ -+enum vop2_data_format { -+ VOP2_FMT_ARGB8888 = 0, -+ VOP2_FMT_RGB888, -+ VOP2_FMT_RGB565, -+ VOP2_FMT_XRGB101010, -+ VOP2_FMT_YUV420SP, -+ VOP2_FMT_YUV422SP, -+ VOP2_FMT_YUV444SP, -+ VOP2_FMT_YUYV422 = 8, -+ VOP2_FMT_YUYV420, -+ VOP2_FMT_VYUY422, -+ VOP2_FMT_VYUY420, -+ VOP2_FMT_YUV420SP_TILE_8x4 = 0x10, -+ VOP2_FMT_YUV420SP_TILE_16x2, -+ VOP2_FMT_YUV422SP_TILE_8x4, -+ VOP2_FMT_YUV422SP_TILE_16x2, -+ VOP2_FMT_YUV420SP_10, -+ VOP2_FMT_YUV422SP_10, -+ VOP2_FMT_YUV444SP_10, -+}; -+ -+enum vop2_afbc_format { -+ VOP2_AFBC_FMT_RGB565, -+ VOP2_AFBC_FMT_ARGB2101010 = 2, -+ VOP2_AFBC_FMT_YUV420_10BIT, -+ VOP2_AFBC_FMT_RGB888, -+ VOP2_AFBC_FMT_ARGB8888, -+ VOP2_AFBC_FMT_YUV420 = 9, -+ VOP2_AFBC_FMT_YUV422 = 0xb, -+ VOP2_AFBC_FMT_YUV422_10BIT = 0xe, -+ VOP2_AFBC_FMT_INVALID = -1, -+}; -+ -+union vop2_alpha_ctrl { -+ u32 val; -+ struct { -+ /* [0:1] */ -+ u32 color_mode:1; -+ u32 alpha_mode:1; -+ /* [2:3] */ -+ u32 blend_mode:2; -+ u32 alpha_cal_mode:1; -+ /* [5:7] */ -+ u32 factor_mode:3; -+ /* [8:9] */ -+ u32 alpha_en:1; -+ u32 src_dst_swap:1; -+ u32 reserved:6; -+ /* [16:23] */ -+ u32 glb_alpha:8; -+ } bits; -+}; -+ -+struct vop2_alpha { -+ union vop2_alpha_ctrl src_color_ctrl; -+ union vop2_alpha_ctrl dst_color_ctrl; -+ union vop2_alpha_ctrl src_alpha_ctrl; -+ union vop2_alpha_ctrl dst_alpha_ctrl; -+}; -+ -+struct vop2_alpha_config { -+ bool src_premulti_en; -+ bool dst_premulti_en; -+ bool src_pixel_alpha_en; -+ bool dst_pixel_alpha_en; -+ u16 src_glb_alpha_value; -+ u16 dst_glb_alpha_value; -+}; -+ -+struct vop2_win { -+ struct vop2 *vop2; -+ struct drm_plane base; -+ const struct vop2_win_data *data; -+ struct regmap_field *reg[VOP2_WIN_MAX_REG]; -+ -+ /** -+ * @win_id: graphic window id, a cluster may be split into two -+ * graphics windows. -+ */ -+ u8 win_id; -+ u8 delay; -+ u32 offset; -+ -+ enum drm_plane_type type; -+}; -+ -+struct vop2_video_port { -+ struct drm_crtc crtc; -+ struct vop2 *vop2; -+ struct clk *dclk; -+ unsigned int id; -+ const struct vop2_video_port_regs *regs; -+ const struct vop2_video_port_data *data; -+ -+ struct completion dsp_hold_completion; -+ -+ /** -+ * @win_mask: Bitmask of windows attached to the video port; -+ */ -+ u32 win_mask; -+ -+ struct vop2_win *primary_plane; -+ struct drm_pending_vblank_event *event; -+ -+ unsigned int nlayers; -+}; -+ -+struct vop2 { -+ struct device *dev; -+ struct drm_device *drm; -+ struct vop2_video_port vps[ROCKCHIP_MAX_CRTC]; -+ -+ const struct vop2_data *data; -+ /* -+ * Number of windows that are registered as plane, may be less than the -+ * total number of hardware windows. -+ */ -+ u32 registered_num_wins; -+ -+ void __iomem *regs; -+ struct regmap *map; -+ -+ struct regmap *grf; -+ -+ /* physical map length of vop2 register */ -+ u32 len; -+ -+ void __iomem *lut_regs; -+ -+ /* protects crtc enable/disable */ -+ struct mutex vop2_lock; -+ -+ int irq; -+ -+ /* -+ * Some global resources are shared between all video ports(crtcs), so -+ * we need a ref counter here. -+ */ -+ unsigned int enable_count; -+ struct clk *hclk; -+ struct clk *aclk; -+ -+ /* must be put at the end of the struct */ -+ struct vop2_win win[]; -+}; -+ -+static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) -+{ -+ return container_of(crtc, struct vop2_video_port, crtc); -+} -+ -+static struct vop2_win *to_vop2_win(struct drm_plane *p) -+{ -+ return container_of(p, struct vop2_win, base); -+} -+ -+static void vop2_lock(struct vop2 *vop2) -+{ -+ mutex_lock(&vop2->vop2_lock); -+} -+ -+static void vop2_unlock(struct vop2 *vop2) -+{ -+ mutex_unlock(&vop2->vop2_lock); -+} -+ -+static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) -+{ -+ regmap_write(vop2->map, offset, v); -+} -+ -+static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v) -+{ -+ regmap_write(vp->vop2->map, vp->data->offset + offset, v); -+} -+ -+static u32 vop2_readl(struct vop2 *vop2, u32 offset) -+{ -+ u32 val; -+ -+ regmap_read(vop2->map, offset, &val); -+ -+ return val; -+} -+ -+static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v) -+{ -+ regmap_field_write(win->reg[reg], v); -+} -+ -+static bool vop2_cluster_window(const struct vop2_win *win) -+{ -+ return win->data->feature & WIN_FEATURE_CLUSTER; -+} -+ -+static void vop2_cfg_done(struct vop2_video_port *vp) -+{ -+ struct vop2 *vop2 = vp->vop2; -+ -+ regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, -+ BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); -+} -+ -+static void vop2_win_disable(struct vop2_win *win) -+{ -+ vop2_win_write(win, VOP2_WIN_ENABLE, 0); -+ -+ if (vop2_cluster_window(win)) -+ vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0); -+} -+ -+static enum vop2_data_format vop2_convert_format(u32 format) -+{ -+ switch (format) { -+ case DRM_FORMAT_XRGB8888: -+ case DRM_FORMAT_ARGB8888: -+ case DRM_FORMAT_XBGR8888: -+ case DRM_FORMAT_ABGR8888: -+ return VOP2_FMT_ARGB8888; -+ case DRM_FORMAT_RGB888: -+ case DRM_FORMAT_BGR888: -+ return VOP2_FMT_RGB888; -+ case DRM_FORMAT_RGB565: -+ case DRM_FORMAT_BGR565: -+ return VOP2_FMT_RGB565; -+ case DRM_FORMAT_NV12: -+ return VOP2_FMT_YUV420SP; -+ case DRM_FORMAT_NV16: -+ return VOP2_FMT_YUV422SP; -+ case DRM_FORMAT_NV24: -+ return VOP2_FMT_YUV444SP; -+ case DRM_FORMAT_YUYV: -+ case DRM_FORMAT_YVYU: -+ return VOP2_FMT_VYUY422; -+ case DRM_FORMAT_VYUY: -+ case DRM_FORMAT_UYVY: -+ return VOP2_FMT_YUYV422; -+ default: -+ DRM_ERROR("unsupported format[%08x]\n", format); -+ return -EINVAL; -+ } -+} -+ -+static enum vop2_afbc_format vop2_convert_afbc_format(u32 format) -+{ -+ switch (format) { -+ case DRM_FORMAT_XRGB8888: -+ case DRM_FORMAT_ARGB8888: -+ case DRM_FORMAT_XBGR8888: -+ case DRM_FORMAT_ABGR8888: -+ return VOP2_AFBC_FMT_ARGB8888; -+ case DRM_FORMAT_RGB888: -+ case DRM_FORMAT_BGR888: -+ return VOP2_AFBC_FMT_RGB888; -+ case DRM_FORMAT_RGB565: -+ case DRM_FORMAT_BGR565: -+ return VOP2_AFBC_FMT_RGB565; -+ case DRM_FORMAT_NV12: -+ return VOP2_AFBC_FMT_YUV420; -+ case DRM_FORMAT_NV16: -+ return VOP2_AFBC_FMT_YUV422; -+ default: -+ return VOP2_AFBC_FMT_INVALID; -+ } -+ -+ return VOP2_AFBC_FMT_INVALID; -+} -+ -+static bool vop2_win_rb_swap(u32 format) -+{ -+ switch (format) { -+ case DRM_FORMAT_XBGR8888: -+ case DRM_FORMAT_ABGR8888: -+ case DRM_FORMAT_BGR888: -+ case DRM_FORMAT_BGR565: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool vop2_afbc_rb_swap(u32 format) -+{ -+ switch (format) { -+ case DRM_FORMAT_NV24: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool vop2_afbc_uv_swap(u32 format) -+{ -+ switch (format) { -+ case DRM_FORMAT_NV12: -+ case DRM_FORMAT_NV16: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool vop2_win_uv_swap(u32 format) -+{ -+ switch (format) { -+ case DRM_FORMAT_NV12: -+ case DRM_FORMAT_NV16: -+ case DRM_FORMAT_NV24: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool vop2_win_dither_up(u32 format) -+{ -+ switch (format) { -+ case DRM_FORMAT_BGR565: -+ case DRM_FORMAT_RGB565: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode) -+{ -+ /* -+ * FIXME: -+ * -+ * There is no media type for YUV444 output, -+ * so when out_mode is AAAA or P888, assume output is YUV444 on -+ * yuv format. -+ * -+ * From H/W testing, YUV444 mode need a rb swap. -+ */ -+ if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || -+ bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || -+ bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || -+ bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || -+ ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || -+ bus_format == MEDIA_BUS_FMT_YUV10_1X30) && -+ (output_mode == ROCKCHIP_OUT_MODE_AAAA || -+ output_mode == ROCKCHIP_OUT_MODE_P888))) -+ return true; -+ else -+ return false; -+} -+ -+static bool is_yuv_output(u32 bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: -+ case MEDIA_BUS_FMT_YUYV8_2X8: -+ case MEDIA_BUS_FMT_YVYU8_2X8: -+ case MEDIA_BUS_FMT_UYVY8_2X8: -+ case MEDIA_BUS_FMT_VYUY8_2X8: -+ case MEDIA_BUS_FMT_YUYV8_1X16: -+ case MEDIA_BUS_FMT_YVYU8_1X16: -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ case MEDIA_BUS_FMT_VYUY8_1X16: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static bool rockchip_afbc(struct drm_plane *plane, u64 modifier) -+{ -+ int i; -+ -+ if (modifier == DRM_FORMAT_MOD_LINEAR) -+ return false; -+ -+ for (i = 0 ; i < plane->modifier_count; i++) -+ if (plane->modifiers[i] == modifier) -+ return true; -+ -+ return false; -+ -+} -+ -+static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, -+ u64 modifier) -+{ -+ struct vop2_win *win = to_vop2_win(plane); -+ struct vop2 *vop2 = win->vop2; -+ -+ if (modifier == DRM_FORMAT_MOD_INVALID) -+ return false; -+ -+ if (modifier == DRM_FORMAT_MOD_LINEAR) -+ return true; -+ -+ if (!rockchip_afbc(plane, modifier)) { -+ drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n", -+ modifier); -+ -+ return false; -+ } -+ -+ return vop2_convert_afbc_format(format) >= 0; -+} -+ -+static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate, -+ bool afbc_half_block_en) -+{ -+ struct drm_rect *src = &pstate->src; -+ struct drm_framebuffer *fb = pstate->fb; -+ u32 bpp = fb->format->cpp[0] * 8; -+ u32 vir_width = (fb->pitches[0] << 3) / bpp; -+ u32 width = drm_rect_width(src) >> 16; -+ u32 height = drm_rect_height(src) >> 16; -+ u32 act_xoffset = src->x1 >> 16; -+ u32 act_yoffset = src->y1 >> 16; -+ u32 align16_crop = 0; -+ u32 align64_crop = 0; -+ u32 height_tmp; -+ u8 tx, ty; -+ u8 bottom_crop_line_num = 0; -+ -+ /* 16 pixel align */ -+ if (height & 0xf) -+ align16_crop = 16 - (height & 0xf); -+ -+ height_tmp = height + align16_crop; -+ -+ /* 64 pixel align */ -+ if (height_tmp & 0x3f) -+ align64_crop = 64 - (height_tmp & 0x3f); -+ -+ bottom_crop_line_num = align16_crop + align64_crop; -+ -+ switch (pstate->rotation & -+ (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | -+ DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) { -+ case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y: -+ tx = 16 - ((act_xoffset + width) & 0xf); -+ ty = bottom_crop_line_num - act_yoffset; -+ break; -+ case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90: -+ tx = bottom_crop_line_num - act_yoffset; -+ ty = vir_width - width - act_xoffset; -+ break; -+ case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270: -+ tx = act_yoffset; -+ ty = act_xoffset; -+ break; -+ case DRM_MODE_REFLECT_X: -+ tx = 16 - ((act_xoffset + width) & 0xf); -+ ty = act_yoffset; -+ break; -+ case DRM_MODE_REFLECT_Y: -+ tx = act_xoffset; -+ ty = bottom_crop_line_num - act_yoffset; -+ break; -+ case DRM_MODE_ROTATE_90: -+ tx = bottom_crop_line_num - act_yoffset; -+ ty = act_xoffset; -+ break; -+ case DRM_MODE_ROTATE_270: -+ tx = act_yoffset; -+ ty = vir_width - width - act_xoffset; -+ break; -+ case 0: -+ tx = act_xoffset; -+ ty = act_yoffset; -+ break; -+ } -+ -+ if (afbc_half_block_en) -+ ty &= 0x7f; -+ -+#define TRANSFORM_XOFFSET GENMASK(7, 0) -+#define TRANSFORM_YOFFSET GENMASK(23, 16) -+ return FIELD_PREP(TRANSFORM_XOFFSET, tx) | -+ FIELD_PREP(TRANSFORM_YOFFSET, ty); -+} -+ -+/* -+ * A Cluster window has 2048 x 16 line buffer, which can -+ * works at 2048 x 16(Full) or 4096 x 8 (Half) mode. -+ * for Cluster_lb_mode register: -+ * 0: half mode, for plane input width range 2048 ~ 4096 -+ * 1: half mode, for cluster work at 2 * 2048 plane mode -+ * 2: half mode, for rotate_90/270 mode -+ * -+ */ -+static int vop2_get_cluster_lb_mode(struct vop2_win *win, -+ struct drm_plane_state *pstate) -+{ -+ if ((pstate->rotation & DRM_MODE_ROTATE_270) || -+ (pstate->rotation & DRM_MODE_ROTATE_90)) -+ return 2; -+ else -+ return 0; -+} -+ -+static u16 vop2_scale_factor(u32 src, u32 dst) -+{ -+ u32 fac; -+ int shift; -+ -+ if (src == dst) -+ return 0; -+ -+ if (dst < 2) -+ return U16_MAX; -+ -+ if (src < 2) -+ return 0; -+ -+ if (src > dst) -+ shift = 12; -+ else -+ shift = 16; -+ -+ src--; -+ dst--; -+ -+ fac = DIV_ROUND_UP(src << shift, dst) - 1; -+ -+ if (fac > U16_MAX) -+ return U16_MAX; -+ -+ return fac; -+} -+ -+static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win, -+ u32 src_w, u32 src_h, u32 dst_w, -+ u32 dst_h, u32 pixel_format) -+{ -+ const struct drm_format_info *info; -+ u16 hor_scl_mode, ver_scl_mode; -+ u16 hscl_filter_mode, vscl_filter_mode; -+ u8 gt2 = 0; -+ u8 gt4 = 0; -+ u32 val; -+ -+ info = drm_format_info(pixel_format); -+ -+ if (src_h >= (4 * dst_h)) { -+ gt4 = 1; -+ src_h >>= 2; -+ } else if (src_h >= (2 * dst_h)) { -+ gt2 = 1; -+ src_h >>= 1; -+ } -+ -+ hor_scl_mode = scl_get_scl_mode(src_w, dst_w); -+ ver_scl_mode = scl_get_scl_mode(src_h, dst_h); -+ -+ if (hor_scl_mode == SCALE_UP) -+ hscl_filter_mode = VOP2_SCALE_UP_BIC; -+ else -+ hscl_filter_mode = VOP2_SCALE_DOWN_BIL; -+ -+ if (ver_scl_mode == SCALE_UP) -+ vscl_filter_mode = VOP2_SCALE_UP_BIL; -+ else -+ vscl_filter_mode = VOP2_SCALE_DOWN_BIL; -+ -+ /* -+ * RK3568 VOP Esmart/Smart dsp_w should be even pixel -+ * at scale down mode -+ */ -+ if (!(win->data->feature & WIN_FEATURE_AFBDC)) { -+ if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { -+ drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n", -+ win->data->name, dst_w); -+ dst_w++; -+ } -+ } -+ -+ val = vop2_scale_factor(src_w, dst_w); -+ vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val); -+ val = vop2_scale_factor(src_h, dst_h); -+ vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val); -+ -+ vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4); -+ vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2); -+ -+ vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode); -+ vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode); -+ -+ if (vop2_cluster_window(win)) -+ return; -+ -+ vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode); -+ vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode); -+ -+ if (info->is_yuv) { -+ src_w /= info->hsub; -+ src_h /= info->vsub; -+ -+ gt4 = gt2 = 0; -+ -+ if (src_h >= (4 * dst_h)) { -+ gt4 = 1; -+ src_h >>= 2; -+ } else if (src_h >= (2 * dst_h)) { -+ gt2 = 1; -+ src_h >>= 1; -+ } -+ -+ hor_scl_mode = scl_get_scl_mode(src_w, dst_w); -+ ver_scl_mode = scl_get_scl_mode(src_h, dst_h); -+ -+ val = vop2_scale_factor(src_w, dst_w); -+ vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val); -+ -+ val = vop2_scale_factor(src_h, dst_h); -+ vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val); -+ -+ vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4); -+ vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2); -+ vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode); -+ vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode); -+ vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode); -+ vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode); -+ } -+} -+ -+static int vop2_convert_csc_mode(int csc_mode) -+{ -+ switch (csc_mode) { -+ case V4L2_COLORSPACE_SMPTE170M: -+ case V4L2_COLORSPACE_470_SYSTEM_M: -+ case V4L2_COLORSPACE_470_SYSTEM_BG: -+ return CSC_BT601L; -+ case V4L2_COLORSPACE_REC709: -+ case V4L2_COLORSPACE_SMPTE240M: -+ case V4L2_COLORSPACE_DEFAULT: -+ return CSC_BT709L; -+ case V4L2_COLORSPACE_JPEG: -+ return CSC_BT601F; -+ case V4L2_COLORSPACE_BT2020: -+ return CSC_BT2020; -+ default: -+ return CSC_BT709L; -+ } -+} -+ -+/* -+ * colorspace path: -+ * Input Win csc Output -+ * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709) -+ * RGB --> R2Y __/ -+ * -+ * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020) -+ * RGB --> 709To2020->R2Y __/ -+ * -+ * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709) -+ * RGB --> R2Y __/ -+ * -+ * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020) -+ * RGB --> 709To2020->R2Y __/ -+ * -+ * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709) -+ * RGB --> R2Y __/ -+ * -+ * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601) -+ * RGB --> R2Y(601) __/ -+ * -+ * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709) -+ * RGB --> bypass __/ -+ * -+ * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020) -+ * -+ * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709) -+ * -+ * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601) -+ * -+ * 11. RGB --> bypass --> RGB_OUTPUT(709) -+ */ -+ -+static void vop2_setup_csc_mode(struct vop2_video_port *vp, -+ struct vop2_win *win, -+ struct drm_plane_state *pstate) -+{ -+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); -+ int is_input_yuv = pstate->fb->format->is_yuv; -+ int is_output_yuv = is_yuv_output(vcstate->bus_format); -+ int input_csc = V4L2_COLORSPACE_DEFAULT; -+ int output_csc = vcstate->color_space; -+ bool r2y_en, y2r_en; -+ int csc_mode; -+ -+ if (is_input_yuv && !is_output_yuv) { -+ y2r_en = true; -+ r2y_en = false; -+ csc_mode = vop2_convert_csc_mode(input_csc); -+ } else if (!is_input_yuv && is_output_yuv) { -+ y2r_en = false; -+ r2y_en = true; -+ csc_mode = vop2_convert_csc_mode(output_csc); -+ } else { -+ y2r_en = false; -+ r2y_en = false; -+ csc_mode = false; -+ } -+ -+ vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en); -+ vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en); -+ vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode); -+} -+ -+static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) -+{ -+ struct vop2 *vop2 = vp->vop2; -+ -+ vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); -+ vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); -+} -+ -+static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) -+{ -+ struct vop2 *vop2 = vp->vop2; -+ -+ vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); -+} -+ -+static int vop2_core_clks_prepare_enable(struct vop2 *vop2) -+{ -+ int ret; -+ -+ ret = clk_prepare_enable(vop2->hclk); -+ if (ret < 0) { -+ drm_err(vop2->drm, "failed to enable hclk - %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(vop2->aclk); -+ if (ret < 0) { -+ drm_err(vop2->drm, "failed to enable aclk - %d\n", ret); -+ goto err; -+ } -+ -+ return 0; -+err: -+ clk_disable_unprepare(vop2->hclk); -+ -+ return ret; -+} -+ -+static void vop2_enable(struct vop2 *vop2) -+{ -+ int ret; -+ -+ ret = pm_runtime_get_sync(vop2->dev); -+ if (ret < 0) { -+ drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret); -+ return; -+ } -+ -+ ret = vop2_core_clks_prepare_enable(vop2); -+ if (ret) { -+ pm_runtime_put_sync(vop2->dev); -+ return; -+ } -+ -+ ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev); -+ if (ret) { -+ drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret); -+ return; -+ } -+ -+ if (vop2->data->soc_id == 3566) -+ vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); -+ -+ vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); -+ -+ /* -+ * Disable auto gating, this is a workaround to -+ * avoid display image shift when a window enabled. -+ */ -+ regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL, -+ RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN); -+ -+ vop2_writel(vop2, RK3568_SYS0_INT_CLR, -+ VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); -+ vop2_writel(vop2, RK3568_SYS0_INT_EN, -+ VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); -+ vop2_writel(vop2, RK3568_SYS1_INT_CLR, -+ VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); -+ vop2_writel(vop2, RK3568_SYS1_INT_EN, -+ VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR); -+} -+ -+static void vop2_disable(struct vop2 *vop2) -+{ -+ rockchip_drm_dma_detach_device(vop2->drm, vop2->dev); -+ -+ pm_runtime_put_sync(vop2->dev); -+ -+ clk_disable_unprepare(vop2->aclk); -+ clk_disable_unprepare(vop2->hclk); -+} -+ -+static void vop2_crtc_atomic_disable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct vop2 *vop2 = vp->vop2; -+ int ret; -+ -+ vop2_lock(vop2); -+ -+ drm_crtc_vblank_off(crtc); -+ -+ /* -+ * Vop standby will take effect at end of current frame, -+ * if dsp hold valid irq happen, it means standby complete. -+ * -+ * we must wait standby complete when we want to disable aclk, -+ * if not, memory bus maybe dead. -+ */ -+ reinit_completion(&vp->dsp_hold_completion); -+ -+ vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); -+ -+ vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); -+ -+ ret = wait_for_completion_timeout(&vp->dsp_hold_completion, -+ msecs_to_jiffies(50)); -+ if (!ret) -+ drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); -+ -+ vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); -+ -+ clk_disable_unprepare(vp->dclk); -+ -+ vop2->enable_count--; -+ -+ if (!vop2->enable_count) -+ vop2_disable(vop2); -+ -+ vop2_unlock(vop2); -+ -+ if (crtc->state->event && !crtc->state->active) { -+ spin_lock_irq(&crtc->dev->event_lock); -+ drm_crtc_send_vblank_event(crtc, crtc->state->event); -+ spin_unlock_irq(&crtc->dev->event_lock); -+ -+ crtc->state->event = NULL; -+ } -+} -+ -+static int vop2_plane_atomic_check(struct drm_plane *plane, -+ struct drm_atomic_state *astate) -+{ -+ struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane); -+ struct drm_framebuffer *fb = pstate->fb; -+ struct drm_crtc *crtc = pstate->crtc; -+ struct drm_crtc_state *cstate; -+ struct vop2_video_port *vp; -+ struct vop2 *vop2; -+ const struct vop2_data *vop2_data; -+ struct drm_rect *dest = &pstate->dst; -+ struct drm_rect *src = &pstate->src; -+ int min_scale = FRAC_16_16(1, 8); -+ int max_scale = FRAC_16_16(8, 1); -+ int format; -+ int ret; -+ -+ if (!crtc) -+ return 0; -+ -+ vp = to_vop2_video_port(crtc); -+ vop2 = vp->vop2; -+ vop2_data = vop2->data; -+ -+ cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc); -+ if (WARN_ON(!cstate)) -+ return -EINVAL; -+ -+ ret = drm_atomic_helper_check_plane_state(pstate, cstate, -+ min_scale, max_scale, -+ true, true); -+ if (ret) -+ return ret; -+ -+ if (!pstate->visible) -+ return 0; -+ -+ format = vop2_convert_format(fb->format->format); -+ if (format < 0) -+ return format; -+ -+ if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 || -+ drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) { -+ drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n", -+ drm_rect_width(src) >> 16, drm_rect_height(src) >> 16, -+ drm_rect_width(dest), drm_rect_height(dest)); -+ pstate->visible = false; -+ return 0; -+ } -+ -+ if (drm_rect_width(src) >> 16 > vop2_data->max_input.width || -+ drm_rect_height(src) >> 16 > vop2_data->max_input.height) { -+ drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n", -+ drm_rect_width(src) >> 16, -+ drm_rect_height(src) >> 16, -+ vop2_data->max_input.width, -+ vop2_data->max_input.height); -+ return -EINVAL; -+ } -+ -+ /* -+ * Src.x1 can be odd when do clip, but yuv plane start point -+ * need align with 2 pixel. -+ */ -+ if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) { -+ drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static void vop2_plane_atomic_disable(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *old_pstate = drm_atomic_get_old_plane_state(state, plane); -+ struct vop2_win *win = to_vop2_win(plane); -+ struct vop2 *vop2 = win->vop2; -+ -+ drm_dbg(vop2->drm, "%s disable\n", win->data->name); -+ -+ if (!old_pstate->crtc) -+ return; -+ -+ vop2_win_disable(win); -+ vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0); -+} -+ -+/* -+ * The color key is 10 bit, so all format should -+ * convert to 10 bit here. -+ */ -+static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key) -+{ -+ struct drm_plane_state *pstate = plane->state; -+ struct drm_framebuffer *fb = pstate->fb; -+ struct vop2_win *win = to_vop2_win(plane); -+ u32 color_key_en = 0; -+ u32 r = 0; -+ u32 g = 0; -+ u32 b = 0; -+ -+ if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) { -+ vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0); -+ return; -+ } -+ -+ switch (fb->format->format) { -+ case DRM_FORMAT_RGB565: -+ case DRM_FORMAT_BGR565: -+ r = (color_key & 0xf800) >> 11; -+ g = (color_key & 0x7e0) >> 5; -+ b = (color_key & 0x1f); -+ r <<= 5; -+ g <<= 4; -+ b <<= 5; -+ color_key_en = 1; -+ break; -+ case DRM_FORMAT_XRGB8888: -+ case DRM_FORMAT_ARGB8888: -+ case DRM_FORMAT_XBGR8888: -+ case DRM_FORMAT_ABGR8888: -+ case DRM_FORMAT_RGB888: -+ case DRM_FORMAT_BGR888: -+ r = (color_key & 0xff0000) >> 16; -+ g = (color_key & 0xff00) >> 8; -+ b = (color_key & 0xff); -+ r <<= 2; -+ g <<= 2; -+ b <<= 2; -+ color_key_en = 1; -+ break; -+ } -+ -+ vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en); -+ vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b); -+} -+ -+static void vop2_plane_atomic_update(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *pstate = plane->state; -+ struct drm_crtc *crtc = pstate->crtc; -+ struct vop2_win *win = to_vop2_win(plane); -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; -+ struct vop2 *vop2 = win->vop2; -+ struct drm_framebuffer *fb = pstate->fb; -+ u32 bpp = fb->format->cpp[0] * 8; -+ u32 actual_w, actual_h, dsp_w, dsp_h; -+ u32 act_info, dsp_info; -+ u32 format; -+ u32 afbc_format; -+ u32 rb_swap; -+ u32 uv_swap; -+ struct drm_rect *src = &pstate->src; -+ struct drm_rect *dest = &pstate->dst; -+ u32 afbc_tile_num; -+ u32 transform_offset; -+ bool dither_up; -+ bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; -+ bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; -+ bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; -+ bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; -+ struct rockchip_gem_object *rk_obj; -+ unsigned long offset; -+ bool afbc_en; -+ dma_addr_t yrgb_mst; -+ dma_addr_t uv_mst; -+ -+ /* -+ * can't update plane when vop2 is disabled. -+ */ -+ if (WARN_ON(!crtc)) -+ return; -+ -+ if (!pstate->visible) { -+ vop2_plane_atomic_disable(plane, state); -+ return; -+ } -+ -+ afbc_en = rockchip_afbc(plane, fb->modifier); -+ -+ offset = (src->x1 >> 16) * fb->format->cpp[0]; -+ -+ /* -+ * AFBC HDR_PTR must set to the zero offset of the framebuffer. -+ */ -+ if (afbc_en) -+ offset = 0; -+ else if (pstate->rotation & DRM_MODE_REFLECT_Y) -+ offset += ((src->y2 >> 16) - 1) * fb->pitches[0]; -+ else -+ offset += (src->y1 >> 16) * fb->pitches[0]; -+ -+ rk_obj = to_rockchip_obj(fb->obj[0]); -+ -+ yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; -+ if (fb->format->is_yuv) { -+ int hsub = fb->format->hsub; -+ int vsub = fb->format->vsub; -+ -+ offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub; -+ offset += (src->y1 >> 16) * fb->pitches[1] / vsub; -+ -+ if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en) -+ offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub; -+ -+ rk_obj = to_rockchip_obj(fb->obj[0]); -+ uv_mst = rk_obj->dma_addr + offset + fb->offsets[1]; -+ } -+ -+ actual_w = drm_rect_width(src) >> 16; -+ actual_h = drm_rect_height(src) >> 16; -+ dsp_w = drm_rect_width(dest); -+ -+ if (dest->x1 + dsp_w > adjusted_mode->hdisplay) { -+ drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n", -+ vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay); -+ dsp_w = adjusted_mode->hdisplay - dest->x1; -+ if (dsp_w < 4) -+ dsp_w = 4; -+ actual_w = dsp_w * actual_w / drm_rect_width(dest); -+ } -+ -+ dsp_h = drm_rect_height(dest); -+ -+ if (dest->y1 + dsp_h > adjusted_mode->vdisplay) { -+ drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n", -+ vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay); -+ dsp_h = adjusted_mode->vdisplay - dest->y1; -+ if (dsp_h < 4) -+ dsp_h = 4; -+ actual_h = dsp_h * actual_h / drm_rect_height(dest); -+ } -+ -+ /* -+ * This is workaround solution for IC design: -+ * esmart can't support scale down when actual_w % 16 == 1. -+ */ -+ if (!(win->data->feature & WIN_FEATURE_AFBDC)) { -+ if (actual_w > dsp_w && (actual_w & 0xf) == 1) { -+ drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", -+ vp->id, win->data->name, actual_w); -+ actual_w -= 1; -+ } -+ } -+ -+ if (afbc_en && actual_w % 4) { -+ drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n", -+ vp->id, win->data->name, actual_w); -+ actual_w = ALIGN_DOWN(actual_w, 4); -+ } -+ -+ act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); -+ dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff); -+ -+ format = vop2_convert_format(fb->format->format); -+ -+ drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", -+ vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, -+ dest->x1, dest->y1, -+ &fb->format->format, -+ afbc_en ? "AFBC" : "", &yrgb_mst); -+ -+ if (afbc_en) { -+ u32 stride; -+ -+ /* the afbc superblock is 16 x 16 */ -+ afbc_format = vop2_convert_afbc_format(fb->format->format); -+ -+ /* Enable color transform for YTR */ -+ if (fb->modifier & AFBC_FORMAT_MOD_YTR) -+ afbc_format |= (1 << 4); -+ -+ afbc_tile_num = ALIGN(actual_w, 16) >> 4; -+ -+ /* -+ * AFBC pic_vir_width is count by pixel, this is different -+ * with WIN_VIR_STRIDE. -+ */ -+ stride = (fb->pitches[0] << 3) / bpp; -+ if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270)) -+ drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligened\n", -+ vp->id, win->data->name, stride); -+ -+ rb_swap = vop2_afbc_rb_swap(fb->format->format); -+ uv_swap = vop2_afbc_uv_swap(fb->format->format); -+ /* -+ * This is a workaround for crazy IC design, Cluster -+ * and Esmart/Smart use different format configuration map: -+ * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart. -+ * -+ * This is one thing we can make the convert simple: -+ * AFBCD decode all the YUV data to YUV444. So we just -+ * set all the yuv 10 bit to YUV444_10. -+ */ -+ if (fb->format->is_yuv && (bpp == 10)) -+ format = VOP2_CLUSTER_YUV444_10; -+ -+ if (vop2_cluster_window(win)) -+ vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); -+ vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); -+ vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap); -+ vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); -+ vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); -+ vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); -+ if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) { -+ vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0); -+ transform_offset = vop2_afbc_transform_offset(pstate, false); -+ } else { -+ vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1); -+ transform_offset = vop2_afbc_transform_offset(pstate, true); -+ } -+ vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); -+ vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); -+ vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset); -+ vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1)); -+ vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16))); -+ vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride); -+ vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num); -+ vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror); -+ vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270); -+ vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90); -+ } else { -+ vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); -+ } -+ -+ vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror); -+ -+ if (rotate_90 || rotate_270) { -+ act_info = swahw32(act_info); -+ actual_w = drm_rect_height(src) >> 16; -+ actual_h = drm_rect_width(src) >> 16; -+ } -+ -+ vop2_win_write(win, VOP2_WIN_FORMAT, format); -+ vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst); -+ -+ rb_swap = vop2_win_rb_swap(fb->format->format); -+ vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap); -+ if (!vop2_cluster_window(win)) { -+ uv_swap = vop2_win_uv_swap(fb->format->format); -+ vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap); -+ } -+ -+ if (fb->format->is_yuv) { -+ vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4)); -+ vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst); -+ } -+ -+ vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format); -+ if (!vop2_cluster_window(win)) -+ vop2_plane_setup_color_key(plane, 0); -+ vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info); -+ vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info); -+ vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff)); -+ -+ vop2_setup_csc_mode(vp, win, pstate); -+ -+ dither_up = vop2_win_dither_up(fb->format->format); -+ vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up); -+ -+ vop2_win_write(win, VOP2_WIN_ENABLE, 1); -+ -+ if (vop2_cluster_window(win)) { -+ int lb_mode = vop2_get_cluster_lb_mode(win, pstate); -+ -+ vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode); -+ vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1); -+ } -+} -+ -+static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = { -+ .atomic_check = vop2_plane_atomic_check, -+ .atomic_update = vop2_plane_atomic_update, -+ .atomic_disable = vop2_plane_atomic_disable, -+}; -+ -+static const struct drm_plane_funcs vop2_plane_funcs = { -+ .update_plane = drm_atomic_helper_update_plane, -+ .disable_plane = drm_atomic_helper_disable_plane, -+ .destroy = drm_plane_cleanup, -+ .reset = drm_atomic_helper_plane_reset, -+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, -+ .format_mod_supported = rockchip_vop2_mod_supported, -+}; -+ -+static int vop2_crtc_enable_vblank(struct drm_crtc *crtc) -+{ -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ -+ vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD); -+ -+ return 0; -+} -+ -+static void vop2_crtc_disable_vblank(struct drm_crtc *crtc) -+{ -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ -+ vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD); -+} -+ -+static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, -+ const struct drm_display_mode *mode, -+ struct drm_display_mode *adj_mode) -+{ -+ drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V | -+ CRTC_STEREO_DOUBLE); -+ -+ return true; -+} -+ -+static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl) -+{ -+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); -+ -+ switch (vcstate->bus_format) { -+ case MEDIA_BUS_FMT_RGB565_1X16: -+ *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; -+ break; -+ case MEDIA_BUS_FMT_RGB666_1X18: -+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: -+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: -+ *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN; -+ *dsp_ctrl |= RGB888_TO_RGB666; -+ break; -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: -+ *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; -+ break; -+ default: -+ break; -+ } -+ -+ if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA) -+ *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN; -+ -+ *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL, -+ DITHER_DOWN_ALLEGRO); -+} -+ -+static void vop2_post_config(struct drm_crtc *crtc) -+{ -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct drm_display_mode *mode = &crtc->state->adjusted_mode; -+ u16 vtotal = mode->crtc_vtotal; -+ u16 hdisplay = mode->crtc_hdisplay; -+ u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; -+ u16 vdisplay = mode->crtc_vdisplay; -+ u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; -+ u32 left_margin = 100, right_margin = 100; -+ u32 top_margin = 100, bottom_margin = 100; -+ u16 hsize = hdisplay * (left_margin + right_margin) / 200; -+ u16 vsize = vdisplay * (top_margin + bottom_margin) / 200; -+ u16 hact_end, vact_end; -+ u32 val; -+ -+ vsize = rounddown(vsize, 2); -+ hsize = rounddown(hsize, 2); -+ hact_st += hdisplay * (100 - left_margin) / 200; -+ hact_end = hact_st + hsize; -+ val = hact_st << 16; -+ val |= hact_end; -+ vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val); -+ vact_st += vdisplay * (100 - top_margin) / 200; -+ vact_end = vact_st + vsize; -+ val = vact_st << 16; -+ val |= vact_end; -+ vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val); -+ val = scl_cal_scale2(vdisplay, vsize) << 16; -+ val |= scl_cal_scale2(hdisplay, hsize); -+ vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val); -+ -+ val = 0; -+ if (hdisplay != hsize) -+ val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN; -+ if (vdisplay != vsize) -+ val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN; -+ vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); -+ -+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) { -+ u16 vact_st_f1 = vtotal + vact_st + 1; -+ u16 vact_end_f1 = vact_st_f1 + vsize; -+ -+ val = vact_st_f1 << 16 | vact_end_f1; -+ vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); -+ } -+ -+ vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); -+} -+ -+static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, -+ u32 polflags) -+{ -+ struct vop2 *vop2 = vp->vop2; -+ u32 die, dip; -+ -+ die = vop2_readl(vop2, RK3568_DSP_IF_EN); -+ dip = vop2_readl(vop2, RK3568_DSP_IF_POL); -+ -+ switch (id) { -+ case ROCKCHIP_VOP2_EP_RGB0: -+ die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX; -+ die |= RK3568_SYS_DSP_INFACE_EN_RGB | -+ FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id); -+ if (polflags & POLFLAG_DCLK_INV) -+ regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); -+ else -+ regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); -+ break; -+ case ROCKCHIP_VOP2_EP_HDMI0: -+ die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; -+ die |= RK3568_SYS_DSP_INFACE_EN_HDMI | -+ FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id); -+ break; -+ case ROCKCHIP_VOP2_EP_EDP0: -+ die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX; -+ die |= RK3568_SYS_DSP_INFACE_EN_EDP | -+ FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id); -+ break; -+ case ROCKCHIP_VOP2_EP_MIPI0: -+ die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX; -+ die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 | -+ FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id); -+ dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; -+ dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); -+ break; -+ case ROCKCHIP_VOP2_EP_MIPI1: -+ die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX; -+ die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 | -+ FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); -+ dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL; -+ dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); -+ break; -+ case ROCKCHIP_VOP2_EP_LVDS0: -+ die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX; -+ die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 | -+ FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id); -+ dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; -+ dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); -+ break; -+ case ROCKCHIP_VOP2_EP_LVDS1: -+ die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX; -+ die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 | -+ FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id); -+ dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; -+ dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); -+ break; -+ default: -+ drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); -+ return; -+ }; -+ -+ dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; -+ -+ vop2_writel(vop2, RK3568_DSP_IF_EN, die); -+ vop2_writel(vop2, RK3568_DSP_IF_POL, dip); -+} -+ -+static int us_to_vertical_line(struct drm_display_mode *mode, int us) -+{ -+ return us * mode->clock / mode->htotal / 1000; -+} -+ -+static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct vop2 *vop2 = vp->vop2; -+ const struct vop2_data *vop2_data = vop2->data; -+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); -+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); -+ struct drm_display_mode *mode = &crtc->state->adjusted_mode; -+ unsigned long clock = mode->crtc_clock * 1000; -+ u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; -+ u16 hdisplay = mode->crtc_hdisplay; -+ u16 htotal = mode->crtc_htotal; -+ u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; -+ u16 hact_end = hact_st + hdisplay; -+ u16 vdisplay = mode->crtc_vdisplay; -+ u16 vtotal = mode->crtc_vtotal; -+ u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; -+ u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; -+ u16 vact_end = vact_st + vdisplay; -+ u8 out_mode; -+ u32 dsp_ctrl = 0; -+ int act_end; -+ u32 val, polflags; -+ int ret; -+ struct drm_encoder *encoder; -+ -+ drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", -+ hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", -+ drm_mode_vrefresh(mode), vcstate->output_type, vp->id); -+ -+ vop2_lock(vop2); -+ -+ ret = clk_prepare_enable(vp->dclk); -+ if (ret < 0) { -+ drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n", -+ vp->id, ret); -+ return; -+ } -+ -+ if (!vop2->enable_count) -+ vop2_enable(vop2); -+ -+ vop2->enable_count++; -+ -+ vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); -+ -+ polflags = 0; -+ if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) -+ polflags |= POLFLAG_DCLK_INV; -+ if (mode->flags & DRM_MODE_FLAG_PHSYNC) -+ polflags |= BIT(HSYNC_POSITIVE); -+ if (mode->flags & DRM_MODE_FLAG_PVSYNC) -+ polflags |= BIT(VSYNC_POSITIVE); -+ -+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); -+ } -+ -+ if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && -+ !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) -+ out_mode = ROCKCHIP_OUT_MODE_P888; -+ else -+ out_mode = vcstate->output_mode; -+ -+ dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode); -+ -+ if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) -+ dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; -+ -+ if (is_yuv_output(vcstate->bus_format)) -+ dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; -+ -+ vop2_dither_setup(crtc, &dsp_ctrl); -+ -+ vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len); -+ val = hact_st << 16; -+ val |= hact_end; -+ vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val); -+ -+ val = vact_st << 16; -+ val |= vact_end; -+ vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); -+ -+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) { -+ u16 vact_st_f1 = vtotal + vact_st + 1; -+ u16 vact_end_f1 = vact_st_f1 + vdisplay; -+ -+ val = vact_st_f1 << 16 | vact_end_f1; -+ vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); -+ -+ val = vtotal << 16 | (vtotal + vsync_len); -+ vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val); -+ dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE; -+ dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL; -+ dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN; -+ vtotal += vtotal + 1; -+ act_end = vact_end_f1; -+ } else { -+ act_end = vact_end; -+ } -+ -+ vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), -+ (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end); -+ -+ vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len); -+ -+ if (mode->flags & DRM_MODE_FLAG_DBLCLK) { -+ dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV; -+ clock *= 2; -+ } -+ -+ vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); -+ -+ clk_set_rate(vp->dclk, clock); -+ -+ vop2_post_config(crtc); -+ -+ vop2_cfg_done(vp); -+ -+ vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); -+ -+ drm_crtc_vblank_on(crtc); -+ -+ vop2_unlock(vop2); -+} -+ -+static int vop2_crtc_atomic_check(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct drm_plane *plane; -+ int nplanes = 0; -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); -+ -+ drm_atomic_crtc_state_for_each_plane(plane, crtc_state) -+ nplanes++; -+ -+ if (nplanes > vp->nlayers) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static bool is_opaque(u16 alpha) -+{ -+ return (alpha >> 8) == 0xff; -+} -+ -+static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config, -+ struct vop2_alpha *alpha) -+{ -+ int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1; -+ int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1; -+ int src_color_mode = alpha_config->src_premulti_en ? -+ ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; -+ int dst_color_mode = alpha_config->dst_premulti_en ? -+ ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL; -+ -+ alpha->src_color_ctrl.val = 0; -+ alpha->dst_color_ctrl.val = 0; -+ alpha->src_alpha_ctrl.val = 0; -+ alpha->dst_alpha_ctrl.val = 0; -+ -+ if (!alpha_config->src_pixel_alpha_en) -+ alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; -+ else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en) -+ alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX; -+ else -+ alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; -+ -+ alpha->src_color_ctrl.bits.alpha_en = 1; -+ -+ if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) { -+ alpha->src_color_ctrl.bits.color_mode = src_color_mode; -+ alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; -+ } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) { -+ alpha->src_color_ctrl.bits.color_mode = src_color_mode; -+ alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE; -+ } else { -+ alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL; -+ alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL; -+ } -+ alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8; -+ alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; -+ alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; -+ -+ alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; -+ alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; -+ alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL; -+ alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8; -+ alpha->dst_color_ctrl.bits.color_mode = dst_color_mode; -+ alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; -+ -+ alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; -+ alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode; -+ alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION; -+ alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE; -+ -+ alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT; -+ if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en) -+ alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX; -+ else -+ alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL; -+ alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION; -+ alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE; -+} -+ -+static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id) -+{ -+ struct vop2_video_port *vp; -+ int used_layer = 0; -+ int i; -+ -+ for (i = 0; i < port_id; i++) { -+ vp = &vop2->vps[i]; -+ used_layer += hweight32(vp->win_mask); -+ } -+ -+ return used_layer; -+} -+ -+static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win) -+{ -+ u32 offset = (main_win->data->phys_id * 0x10); -+ struct vop2_alpha_config alpha_config; -+ struct vop2_alpha alpha; -+ struct drm_plane_state *bottom_win_pstate; -+ bool src_pixel_alpha_en = false; -+ u16 src_glb_alpha_val, dst_glb_alpha_val; -+ bool premulti_en = false; -+ bool swap = false; -+ -+ /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */ -+ bottom_win_pstate = main_win->base.state; -+ src_glb_alpha_val = 0; -+ dst_glb_alpha_val = main_win->base.state->alpha; -+ -+ if (!bottom_win_pstate->fb) -+ return; -+ -+ alpha_config.src_premulti_en = premulti_en; -+ alpha_config.dst_premulti_en = false; -+ alpha_config.src_pixel_alpha_en = src_pixel_alpha_en; -+ alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ -+ alpha_config.src_glb_alpha_value = src_glb_alpha_val; -+ alpha_config.dst_glb_alpha_value = dst_glb_alpha_val; -+ vop2_parse_alpha(&alpha_config, &alpha); -+ -+ alpha.src_color_ctrl.bits.src_dst_swap = swap; -+ vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset, -+ alpha.src_color_ctrl.val); -+ vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset, -+ alpha.dst_color_ctrl.val); -+ vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset, -+ alpha.src_alpha_ctrl.val); -+ vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset, -+ alpha.dst_alpha_ctrl.val); -+} -+ -+static void vop2_setup_alpha(struct vop2_video_port *vp) -+{ -+ struct vop2 *vop2 = vp->vop2; -+ struct drm_framebuffer *fb; -+ struct vop2_alpha_config alpha_config; -+ struct vop2_alpha alpha; -+ struct drm_plane *plane; -+ int pixel_alpha_en; -+ int premulti_en, gpremulti_en = 0; -+ int mixer_id; -+ u32 offset; -+ bool bottom_layer_alpha_en = false; -+ u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE; -+ -+ mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id); -+ alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */ -+ -+ drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { -+ struct vop2_win *win = to_vop2_win(plane); -+ -+ if (plane->state->normalized_zpos == 0 && -+ !is_opaque(plane->state->alpha) && -+ !vop2_cluster_window(win)) { -+ /* -+ * If bottom layer have global alpha effect [except cluster layer, -+ * because cluster have deal with bottom layer global alpha value -+ * at cluster mix], bottom layer mix need deal with global alpha. -+ */ -+ bottom_layer_alpha_en = true; -+ dst_global_alpha = plane->state->alpha; -+ } -+ } -+ -+ drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { -+ struct vop2_win *win = to_vop2_win(plane); -+ int zpos = plane->state->normalized_zpos; -+ -+ if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) -+ premulti_en = 1; -+ else -+ premulti_en = 0; -+ -+ plane = &win->base; -+ fb = plane->state->fb; -+ -+ pixel_alpha_en = fb->format->has_alpha; -+ -+ alpha_config.src_premulti_en = premulti_en; -+ -+ if (bottom_layer_alpha_en && zpos == 1) { -+ gpremulti_en = premulti_en; -+ /* Cd = Cs + (1 - As) * Cd * Agd */ -+ alpha_config.dst_premulti_en = false; -+ alpha_config.src_pixel_alpha_en = pixel_alpha_en; -+ alpha_config.src_glb_alpha_value = plane->state->alpha; -+ alpha_config.dst_glb_alpha_value = dst_global_alpha; -+ } else if (vop2_cluster_window(win)) { -+ /* Mix output data only have pixel alpha */ -+ alpha_config.dst_premulti_en = true; -+ alpha_config.src_pixel_alpha_en = true; -+ alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; -+ alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; -+ } else { -+ /* Cd = Cs + (1 - As) * Cd */ -+ alpha_config.dst_premulti_en = true; -+ alpha_config.src_pixel_alpha_en = pixel_alpha_en; -+ alpha_config.src_glb_alpha_value = plane->state->alpha; -+ alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; -+ } -+ -+ vop2_parse_alpha(&alpha_config, &alpha); -+ -+ offset = (mixer_id + zpos - 1) * 0x10; -+ vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset, -+ alpha.src_color_ctrl.val); -+ vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset, -+ alpha.dst_color_ctrl.val); -+ vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset, -+ alpha.src_alpha_ctrl.val); -+ vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset, -+ alpha.dst_alpha_ctrl.val); -+ } -+ -+ if (vp->id == 0) { -+ if (bottom_layer_alpha_en) { -+ /* Transfer pixel alpha to hdr mix */ -+ alpha_config.src_premulti_en = gpremulti_en; -+ alpha_config.dst_premulti_en = true; -+ alpha_config.src_pixel_alpha_en = true; -+ alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; -+ alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE; -+ vop2_parse_alpha(&alpha_config, &alpha); -+ -+ vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, -+ alpha.src_color_ctrl.val); -+ vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL, -+ alpha.dst_color_ctrl.val); -+ vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL, -+ alpha.src_alpha_ctrl.val); -+ vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL, -+ alpha.dst_alpha_ctrl.val); -+ } else { -+ vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0); -+ } -+ } -+} -+ -+static void vop2_setup_layer_mixer(struct vop2_video_port *vp) -+{ -+ struct vop2 *vop2 = vp->vop2; -+ struct drm_plane *plane; -+ u32 layer_sel = 0; -+ u32 port_sel; -+ unsigned int nlayer, ofs; -+ struct drm_display_mode *adjusted_mode; -+ u16 hsync_len; -+ u16 hdisplay; -+ u32 bg_dly; -+ u32 pre_scan_dly; -+ int i; -+ struct vop2_video_port *vp0 = &vop2->vps[0]; -+ struct vop2_video_port *vp1 = &vop2->vps[1]; -+ struct vop2_video_port *vp2 = &vop2->vps[2]; -+ -+ adjusted_mode = &vp->crtc.state->adjusted_mode; -+ hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; -+ hdisplay = adjusted_mode->crtc_hdisplay; -+ -+ bg_dly = vp->data->pre_scan_max_dly[3]; -+ vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id), -+ FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly)); -+ -+ pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; -+ vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); -+ -+ vop2_writel(vop2, RK3568_OVL_CTRL, 0); -+ port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); -+ port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT; -+ -+ if (vp0->nlayers) -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, -+ vp0->nlayers - 1); -+ else -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8); -+ -+ if (vp1->nlayers) -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, -+ (vp0->nlayers + vp1->nlayers - 1)); -+ else -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); -+ -+ if (vp2->nlayers) -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, -+ (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1)); -+ else -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8); -+ -+ layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL); -+ -+ ofs = 0; -+ for (i = 0; i < vp->id; i++) -+ ofs += vop2->vps[i].nlayers; -+ -+ nlayer = 0; -+ drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { -+ struct vop2_win *win = to_vop2_win(plane); -+ -+ switch (win->data->phys_id) { -+ case ROCKCHIP_VOP2_CLUSTER0: -+ port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0; -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id); -+ break; -+ case ROCKCHIP_VOP2_CLUSTER1: -+ port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1; -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id); -+ break; -+ case ROCKCHIP_VOP2_ESMART0: -+ port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0; -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id); -+ break; -+ case ROCKCHIP_VOP2_ESMART1: -+ port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1; -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id); -+ break; -+ case ROCKCHIP_VOP2_SMART0: -+ port_sel &= ~RK3568_OVL_PORT_SEL__SMART0; -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id); -+ break; -+ case ROCKCHIP_VOP2_SMART1: -+ port_sel &= ~RK3568_OVL_PORT_SEL__SMART1; -+ port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id); -+ break; -+ } -+ -+ layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, -+ 0x7); -+ layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs, -+ win->data->layer_sel_id); -+ nlayer++; -+ } -+ -+ /* configure unused layers to 0x5 (reserved) */ -+ for (; nlayer < vp->nlayers; nlayer++) { -+ layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7); -+ layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5); -+ } -+ -+ vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); -+ vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); -+ vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD); -+} -+ -+static void vop2_setup_dly_for_windows(struct vop2 *vop2) -+{ -+ struct vop2_win *win; -+ int i = 0; -+ u32 cdly = 0, sdly = 0; -+ -+ for (i = 0; i < vop2->data->win_size; i++) { -+ u32 dly; -+ -+ win = &vop2->win[i]; -+ dly = win->delay; -+ -+ switch (win->data->phys_id) { -+ case ROCKCHIP_VOP2_CLUSTER0: -+ cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly); -+ cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly); -+ break; -+ case ROCKCHIP_VOP2_CLUSTER1: -+ cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly); -+ cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly); -+ break; -+ case ROCKCHIP_VOP2_ESMART0: -+ sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly); -+ break; -+ case ROCKCHIP_VOP2_ESMART1: -+ sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly); -+ break; -+ case ROCKCHIP_VOP2_SMART0: -+ sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly); -+ break; -+ case ROCKCHIP_VOP2_SMART1: -+ sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly); -+ break; -+ } -+ } -+ -+ vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly); -+ vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly); -+} -+ -+static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ struct vop2 *vop2 = vp->vop2; -+ struct drm_plane *plane; -+ -+ vp->win_mask = 0; -+ -+ drm_atomic_crtc_for_each_plane(plane, crtc) { -+ struct vop2_win *win = to_vop2_win(plane); -+ -+ win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT]; -+ -+ vp->win_mask |= BIT(win->data->phys_id); -+ -+ if (vop2_cluster_window(win)) -+ vop2_setup_cluster_alpha(vop2, win); -+ } -+ -+ if (!vp->win_mask) -+ return; -+ -+ vop2_setup_layer_mixer(vp); -+ vop2_setup_alpha(vp); -+ vop2_setup_dly_for_windows(vop2); -+} -+ -+static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vop2_video_port *vp = to_vop2_video_port(crtc); -+ -+ vop2_post_config(crtc); -+ -+ vop2_cfg_done(vp); -+ -+ spin_lock_irq(&crtc->dev->event_lock); -+ -+ if (crtc->state->event) { -+ WARN_ON(drm_crtc_vblank_get(crtc)); -+ vp->event = crtc->state->event; -+ crtc->state->event = NULL; -+ } -+ -+ spin_unlock_irq(&crtc->dev->event_lock); -+} -+ -+static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { -+ .mode_fixup = vop2_crtc_mode_fixup, -+ .atomic_check = vop2_crtc_atomic_check, -+ .atomic_begin = vop2_crtc_atomic_begin, -+ .atomic_flush = vop2_crtc_atomic_flush, -+ .atomic_enable = vop2_crtc_atomic_enable, -+ .atomic_disable = vop2_crtc_atomic_disable, -+}; -+ -+static void vop2_crtc_reset(struct drm_crtc *crtc) -+{ -+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); -+ -+ if (crtc->state) { -+ __drm_atomic_helper_crtc_destroy_state(crtc->state); -+ kfree(vcstate); -+ } -+ -+ vcstate = kzalloc(sizeof(*vcstate), GFP_KERNEL); -+ if (!vcstate) -+ return; -+ -+ crtc->state = &vcstate->base; -+ crtc->state->crtc = crtc; -+} -+ -+static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc) -+{ -+ struct rockchip_crtc_state *vcstate, *old_vcstate; -+ -+ old_vcstate = to_rockchip_crtc_state(crtc->state); -+ -+ vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL); -+ if (!vcstate) -+ return NULL; -+ -+ __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base); -+ -+ return &vcstate->base; -+} -+ -+static void vop2_crtc_destroy_state(struct drm_crtc *crtc, -+ struct drm_crtc_state *state) -+{ -+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state); -+ -+ __drm_atomic_helper_crtc_destroy_state(&vcstate->base); -+ kfree(vcstate); -+} -+ -+static const struct drm_crtc_funcs vop2_crtc_funcs = { -+ .set_config = drm_atomic_helper_set_config, -+ .page_flip = drm_atomic_helper_page_flip, -+ .destroy = drm_crtc_cleanup, -+ .reset = vop2_crtc_reset, -+ .atomic_duplicate_state = vop2_crtc_duplicate_state, -+ .atomic_destroy_state = vop2_crtc_destroy_state, -+ .enable_vblank = vop2_crtc_enable_vblank, -+ .disable_vblank = vop2_crtc_disable_vblank, -+}; -+ -+static irqreturn_t vop2_isr(int irq, void *data) -+{ -+ struct vop2 *vop2 = data; -+ const struct vop2_data *vop2_data = vop2->data; -+ u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM]; -+ int ret = IRQ_NONE; -+ int i; -+ -+ /* -+ * The irq is shared with the iommu. If the runtime-pm state of the -+ * vop2-device is disabled the irq has to be targeted at the iommu. -+ */ -+ if (!pm_runtime_get_if_in_use(vop2->dev)) -+ return IRQ_NONE; -+ -+ for (i = 0; i < vop2_data->nr_vps; i++) { -+ struct vop2_video_port *vp = &vop2->vps[i]; -+ struct drm_crtc *crtc = &vp->crtc; -+ u32 irqs; -+ -+ irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); -+ vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); -+ -+ if (irqs & VP_INT_DSP_HOLD_VALID) { -+ complete(&vp->dsp_hold_completion); -+ ret = IRQ_HANDLED; -+ } -+ -+ if (irqs & VP_INT_FS_FIELD) { -+ drm_crtc_handle_vblank(crtc); -+ spin_lock(&crtc->dev->event_lock); -+ if (vp->event) { -+ u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE); -+ -+ if (!(val & BIT(vp->id))) { -+ drm_crtc_send_vblank_event(crtc, vp->event); -+ vp->event = NULL; -+ drm_crtc_vblank_put(crtc); -+ } -+ } -+ spin_unlock(&crtc->dev->event_lock); -+ -+ ret = IRQ_HANDLED; -+ } -+ -+ if (irqs & VP_INT_POST_BUF_EMPTY) { -+ drm_err_ratelimited(vop2->drm, -+ "POST_BUF_EMPTY irq err at vp%d\n", -+ vp->id); -+ ret = IRQ_HANDLED; -+ } -+ } -+ -+ axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS); -+ vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]); -+ axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS); -+ vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]); -+ -+ for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) { -+ if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) { -+ drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n"); -+ ret = IRQ_HANDLED; -+ } -+ } -+ -+ pm_runtime_put(vop2->dev); -+ -+ return ret; -+} -+ -+static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, -+ unsigned long possible_crtcs) -+{ -+ const struct vop2_win_data *win_data = win->data; -+ unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | -+ BIT(DRM_MODE_BLEND_PREMULTI) | -+ BIT(DRM_MODE_BLEND_COVERAGE); -+ int ret; -+ -+ ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs, -+ &vop2_plane_funcs, win_data->formats, -+ win_data->nformats, -+ win_data->format_modifiers, -+ win->type, win_data->name); -+ if (ret) { -+ drm_err(vop2->drm, "failed to initialize plane %d\n", ret); -+ return ret; -+ } -+ -+ drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs); -+ -+ if (win->data->supported_rotations) -+ drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0, -+ DRM_MODE_ROTATE_0 | -+ win->data->supported_rotations); -+ drm_plane_create_alpha_property(&win->base); -+ drm_plane_create_blend_mode_property(&win->base, blend_caps); -+ drm_plane_create_zpos_property(&win->base, win->win_id, 0, -+ vop2->registered_num_wins - 1); -+ -+ return 0; -+} -+ -+static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2) -+{ -+ int i; -+ -+ for (i = 0; i < vop2->data->nr_vps; i++) { -+ struct vop2_video_port *vp = &vop2->vps[i]; -+ -+ if (!vp->crtc.port) -+ continue; -+ if (vp->primary_plane) -+ continue; -+ -+ return vp; -+ } -+ -+ return NULL; -+} -+ -+#define NR_LAYERS 6 -+ -+static int vop2_create_crtc(struct vop2 *vop2) -+{ -+ const struct vop2_data *vop2_data = vop2->data; -+ struct drm_device *drm = vop2->drm; -+ struct device *dev = vop2->dev; -+ struct drm_plane *plane; -+ struct device_node *port; -+ struct vop2_video_port *vp; -+ int i, nvp, nvps = 0; -+ int ret; -+ -+ for (i = 0; i < vop2_data->nr_vps; i++) { -+ const struct vop2_video_port_data *vp_data; -+ struct device_node *np; -+ char dclk_name[9]; -+ -+ vp_data = &vop2_data->vp[i]; -+ vp = &vop2->vps[i]; -+ vp->vop2 = vop2; -+ vp->id = vp_data->id; -+ vp->regs = vp_data->regs; -+ vp->data = vp_data; -+ -+ snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); -+ vp->dclk = devm_clk_get(vop2->dev, dclk_name); -+ if (IS_ERR(vp->dclk)) { -+ drm_err(vop2->drm, "failed to get %s\n", dclk_name); -+ return PTR_ERR(vp->dclk); -+ } -+ -+ np = of_graph_get_remote_node(dev->of_node, i, -1); -+ if (!np) { -+ drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); -+ continue; -+ } -+ of_node_put(np); -+ -+ port = of_graph_get_port_by_id(dev->of_node, i); -+ if (!port) { -+ drm_err(vop2->drm, "no port node found for video_port%d\n", i); -+ return -ENOENT; -+ } -+ -+ vp->crtc.port = port; -+ nvps++; -+ } -+ -+ nvp = 0; -+ for (i = 0; i < vop2->registered_num_wins; i++) { -+ struct vop2_win *win = &vop2->win[i]; -+ u32 possible_crtcs; -+ -+ if (vop2->data->soc_id == 3566) { -+ /* -+ * On RK3566 these windows don't have an independent -+ * framebuffer. They share the framebuffer with smart0, -+ * esmart0 and cluster0 respectively. -+ */ -+ switch (win->data->phys_id) { -+ case ROCKCHIP_VOP2_SMART1: -+ case ROCKCHIP_VOP2_ESMART1: -+ case ROCKCHIP_VOP2_CLUSTER1: -+ continue; -+ } -+ } -+ -+ if (win->type == DRM_PLANE_TYPE_PRIMARY) { -+ vp = find_vp_without_primary(vop2); -+ if (vp) { -+ possible_crtcs = BIT(nvp); -+ vp->primary_plane = win; -+ nvp++; -+ } else { -+ /* change the unused primary window to overlay window */ -+ win->type = DRM_PLANE_TYPE_OVERLAY; -+ } -+ } -+ -+ if (win->type == DRM_PLANE_TYPE_OVERLAY) -+ possible_crtcs = (1 << nvps) - 1; -+ -+ ret = vop2_plane_init(vop2, win, possible_crtcs); -+ if (ret) { -+ drm_err(vop2->drm, "failed to init plane %s: %d\n", -+ win->data->name, ret); -+ return ret; -+ } -+ } -+ -+ for (i = 0; i < vop2_data->nr_vps; i++) { -+ vp = &vop2->vps[i]; -+ -+ if (!vp->crtc.port) -+ continue; -+ -+ plane = &vp->primary_plane->base; -+ -+ ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, -+ &vop2_crtc_funcs, -+ "video_port%d", vp->id); -+ if (ret) { -+ drm_err(vop2->drm, "crtc init for video_port%d failed\n", i); -+ return ret; -+ } -+ -+ drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); -+ -+ init_completion(&vp->dsp_hold_completion); -+ } -+ -+ /* -+ * On the VOP2 it's very hard to change the number of layers on a VP -+ * during runtime, so we distribute the layers equally over the used -+ * VPs -+ */ -+ for (i = 0; i < vop2->data->nr_vps; i++) { -+ struct vop2_video_port *vp = &vop2->vps[i]; -+ -+ if (vp->crtc.port) -+ vp->nlayers = NR_LAYERS / nvps; -+ } -+ -+ return 0; -+} -+ -+static void vop2_destroy_crtc(struct drm_crtc *crtc) -+{ -+ of_node_put(crtc->port); -+ -+ /* -+ * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane() -+ * references the CRTC. -+ */ -+ drm_crtc_cleanup(crtc); -+} -+ -+static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = { -+ [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), -+ [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), -+ [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14), -+ [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18), -+ [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31), -+ [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31), -+ [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31), -+ [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31), -+ [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31), -+ [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19), -+ [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15), -+ [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31), -+ [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8), -+ [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9), -+ [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11), -+ -+ /* Scale */ -+ [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15), -+ [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31), -+ [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15), -+ [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13), -+ [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3), -+ [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28), -+ [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29), -+ -+ /* cluster regs */ -+ [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1), -+ [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0), -+ [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7), -+ -+ /* afbc regs */ -+ [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6), -+ [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9), -+ [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10), -+ [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4), -+ [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7), -+ [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8), -+ [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31), -+ [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31), -+ [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15), -+ [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31), -+ [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31), -+ [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31), -+ [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31), -+ [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0), -+ [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1), -+ [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2), -+ [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3), -+ [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff }, -+ [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff }, -+ [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff }, -+ [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff }, -+ [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff }, -+ [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff }, -+ [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff }, -+}; -+ -+static int vop2_cluster_init(struct vop2_win *win) -+{ -+ struct vop2 *vop2 = win->vop2; -+ struct reg_field *cluster_regs; -+ int ret, i; -+ -+ cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs), -+ GFP_KERNEL); -+ if (!cluster_regs) -+ return -ENOMEM; -+ -+ for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++) -+ if (cluster_regs[i].reg != 0xffffffff) -+ cluster_regs[i].reg += win->offset; -+ -+ ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, -+ cluster_regs, -+ ARRAY_SIZE(vop2_cluster_regs)); -+ -+ kfree(cluster_regs); -+ -+ return ret; -+}; -+ -+static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = { -+ [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0), -+ [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5), -+ [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12), -+ [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14), -+ [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16), -+ [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31), -+ [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31), -+ [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28), -+ [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31), -+ [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31), -+ [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17), -+ [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15), -+ [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31), -+ [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0), -+ [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1), -+ [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3), -+ [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31), -+ [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29), -+ [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31), -+ -+ /* Scale */ -+ [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15), -+ [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31), -+ [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15), -+ [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31), -+ [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1), -+ [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3), -+ [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5), -+ [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7), -+ [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9), -+ [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11), -+ [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13), -+ [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15), -+ [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17), -+ [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8), -+ [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9), -+ [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10), -+ [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11), -+ [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff }, -+ [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff }, -+}; -+ -+static int vop2_esmart_init(struct vop2_win *win) -+{ -+ struct vop2 *vop2 = win->vop2; -+ struct reg_field *esmart_regs; -+ int ret, i; -+ -+ esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs), -+ GFP_KERNEL); -+ if (!esmart_regs) -+ return -ENOMEM; -+ -+ for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++) -+ if (esmart_regs[i].reg != 0xffffffff) -+ esmart_regs[i].reg += win->offset; -+ -+ ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg, -+ esmart_regs, -+ ARRAY_SIZE(vop2_esmart_regs)); -+ -+ kfree(esmart_regs); -+ -+ return ret; -+}; -+ -+static int vop2_win_init(struct vop2 *vop2) -+{ -+ const struct vop2_data *vop2_data = vop2->data; -+ struct vop2_win *win; -+ int i, ret; -+ -+ for (i = 0; i < vop2_data->win_size; i++) { -+ const struct vop2_win_data *win_data = &vop2_data->win[i]; -+ -+ win = &vop2->win[i]; -+ win->data = win_data; -+ win->type = win_data->type; -+ win->offset = win_data->base; -+ win->win_id = i; -+ win->vop2 = vop2; -+ if (vop2_cluster_window(win)) -+ ret = vop2_cluster_init(win); -+ else -+ ret = vop2_esmart_init(win); -+ if (ret) -+ return ret; -+ } -+ -+ vop2->registered_num_wins = vop2_data->win_size; -+ -+ return 0; -+} -+ -+/* -+ * The window registers are only updated when config done is written. -+ * Until that they read back the old value. As we read-modify-write -+ * these registers mark them as non-volatile. This makes sure we read -+ * the new values from the regmap register cache. -+ */ -+static const struct regmap_range vop2_nonvolatile_range[] = { -+ regmap_reg_range(0x1000, 0x23ff), -+}; -+ -+static const struct regmap_access_table vop2_volatile_table = { -+ .no_ranges = vop2_nonvolatile_range, -+ .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range), -+}; -+ -+static const struct regmap_config vop2_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = 0x3000, -+ .name = "vop2", -+ .volatile_table = &vop2_volatile_table, -+ .cache_type = REGCACHE_RBTREE, -+}; -+ -+static int vop2_bind(struct device *dev, struct device *master, void *data) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ const struct vop2_data *vop2_data; -+ struct drm_device *drm = data; -+ struct vop2 *vop2; -+ struct resource *res; -+ size_t alloc_size; -+ int ret; -+ -+ vop2_data = of_device_get_match_data(dev); -+ if (!vop2_data) -+ return -ENODEV; -+ -+ /* Allocate vop2 struct and its vop2_win array */ -+ alloc_size = sizeof(*vop2) + sizeof(*vop2->win) * vop2_data->win_size; -+ vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL); -+ if (!vop2) -+ return -ENOMEM; -+ -+ vop2->dev = dev; -+ vop2->data = vop2_data; -+ vop2->drm = drm; -+ -+ dev_set_drvdata(dev, vop2); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); -+ if (!res) { -+ drm_err(vop2->drm, "failed to get vop2 register byname\n"); -+ return -EINVAL; -+ } -+ -+ vop2->regs = devm_ioremap_resource(dev, res); -+ if (IS_ERR(vop2->regs)) -+ return PTR_ERR(vop2->regs); -+ vop2->len = resource_size(res); -+ -+ vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config); -+ -+ ret = vop2_win_init(vop2); -+ if (ret) -+ return ret; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut"); -+ if (res) { -+ vop2->lut_regs = devm_ioremap_resource(dev, res); -+ if (IS_ERR(vop2->lut_regs)) -+ return PTR_ERR(vop2->lut_regs); -+ } -+ -+ vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); -+ -+ vop2->hclk = devm_clk_get(vop2->dev, "hclk"); -+ if (IS_ERR(vop2->hclk)) { -+ drm_err(vop2->drm, "failed to get hclk source\n"); -+ return PTR_ERR(vop2->hclk); -+ } -+ -+ vop2->aclk = devm_clk_get(vop2->dev, "aclk"); -+ if (IS_ERR(vop2->aclk)) { -+ drm_err(vop2->drm, "failed to get aclk source\n"); -+ return PTR_ERR(vop2->aclk); -+ } -+ -+ vop2->irq = platform_get_irq(pdev, 0); -+ if (vop2->irq < 0) { -+ drm_err(vop2->drm, "cannot find irq for vop2\n"); -+ return vop2->irq; -+ } -+ -+ mutex_init(&vop2->vop2_lock); -+ -+ ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2); -+ if (ret) -+ return ret; -+ -+ ret = vop2_create_crtc(vop2); -+ if (ret) -+ return ret; -+ -+ rockchip_drm_dma_init_device(vop2->drm, vop2->dev); -+ -+ pm_runtime_enable(&pdev->dev); -+ -+ return 0; -+} -+ -+static void vop2_unbind(struct device *dev, struct device *master, void *data) -+{ -+ struct vop2 *vop2 = dev_get_drvdata(dev); -+ struct drm_device *drm = vop2->drm; -+ struct list_head *plane_list = &drm->mode_config.plane_list; -+ struct list_head *crtc_list = &drm->mode_config.crtc_list; -+ struct drm_crtc *crtc, *tmpc; -+ struct drm_plane *plane, *tmpp; -+ -+ pm_runtime_disable(dev); -+ -+ list_for_each_entry_safe(plane, tmpp, plane_list, head) -+ drm_plane_cleanup(plane); -+ -+ list_for_each_entry_safe(crtc, tmpc, crtc_list, head) -+ vop2_destroy_crtc(crtc); -+} -+ -+const struct component_ops vop2_component_ops = { -+ .bind = vop2_bind, -+ .unbind = vop2_unbind, -+}; -+EXPORT_SYMBOL_GPL(vop2_component_ops); -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h -new file mode 100644 -index 0000000000000..c727093a06d68 ---- /dev/null -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h -@@ -0,0 +1,477 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd -+ * Author:Mark Yao -+ */ -+ -+#ifndef _ROCKCHIP_DRM_VOP2_H -+#define _ROCKCHIP_DRM_VOP2_H -+ -+#include "rockchip_drm_vop.h" -+ -+#include -+#include -+ -+#define VOP_FEATURE_OUTPUT_10BIT BIT(0) -+ -+#define WIN_FEATURE_AFBDC BIT(0) -+#define WIN_FEATURE_CLUSTER BIT(1) -+ -+/* -+ * the delay number of a window in different mode. -+ */ -+enum win_dly_mode { -+ VOP2_DLY_MODE_DEFAULT, /**< default mode */ -+ VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */ -+ VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */ -+ VOP2_DLY_MODE_MAX, -+}; -+ -+struct vop_rect { -+ int width; -+ int height; -+}; -+ -+enum vop2_scale_up_mode { -+ VOP2_SCALE_UP_NRST_NBOR, -+ VOP2_SCALE_UP_BIL, -+ VOP2_SCALE_UP_BIC, -+}; -+ -+enum vop2_scale_down_mode { -+ VOP2_SCALE_DOWN_NRST_NBOR, -+ VOP2_SCALE_DOWN_BIL, -+ VOP2_SCALE_DOWN_AVG, -+}; -+ -+enum vop2_win_regs { -+ VOP2_WIN_ENABLE, -+ VOP2_WIN_FORMAT, -+ VOP2_WIN_CSC_MODE, -+ VOP2_WIN_XMIRROR, -+ VOP2_WIN_YMIRROR, -+ VOP2_WIN_RB_SWAP, -+ VOP2_WIN_UV_SWAP, -+ VOP2_WIN_ACT_INFO, -+ VOP2_WIN_DSP_INFO, -+ VOP2_WIN_DSP_ST, -+ VOP2_WIN_YRGB_MST, -+ VOP2_WIN_UV_MST, -+ VOP2_WIN_YRGB_VIR, -+ VOP2_WIN_UV_VIR, -+ VOP2_WIN_YUV_CLIP, -+ VOP2_WIN_Y2R_EN, -+ VOP2_WIN_R2Y_EN, -+ VOP2_WIN_COLOR_KEY, -+ VOP2_WIN_COLOR_KEY_EN, -+ VOP2_WIN_DITHER_UP, -+ -+ /* scale regs */ -+ VOP2_WIN_SCALE_YRGB_X, -+ VOP2_WIN_SCALE_YRGB_Y, -+ VOP2_WIN_SCALE_CBCR_X, -+ VOP2_WIN_SCALE_CBCR_Y, -+ VOP2_WIN_YRGB_HOR_SCL_MODE, -+ VOP2_WIN_YRGB_HSCL_FILTER_MODE, -+ VOP2_WIN_YRGB_VER_SCL_MODE, -+ VOP2_WIN_YRGB_VSCL_FILTER_MODE, -+ VOP2_WIN_CBCR_VER_SCL_MODE, -+ VOP2_WIN_CBCR_HSCL_FILTER_MODE, -+ VOP2_WIN_CBCR_HOR_SCL_MODE, -+ VOP2_WIN_CBCR_VSCL_FILTER_MODE, -+ VOP2_WIN_VSD_CBCR_GT2, -+ VOP2_WIN_VSD_CBCR_GT4, -+ VOP2_WIN_VSD_YRGB_GT2, -+ VOP2_WIN_VSD_YRGB_GT4, -+ VOP2_WIN_BIC_COE_SEL, -+ -+ /* cluster regs */ -+ VOP2_WIN_CLUSTER_ENABLE, -+ VOP2_WIN_AFBC_ENABLE, -+ VOP2_WIN_CLUSTER_LB_MODE, -+ -+ /* afbc regs */ -+ VOP2_WIN_AFBC_FORMAT, -+ VOP2_WIN_AFBC_RB_SWAP, -+ VOP2_WIN_AFBC_UV_SWAP, -+ VOP2_WIN_AFBC_AUTO_GATING_EN, -+ VOP2_WIN_AFBC_BLOCK_SPLIT_EN, -+ VOP2_WIN_AFBC_PIC_VIR_WIDTH, -+ VOP2_WIN_AFBC_TILE_NUM, -+ VOP2_WIN_AFBC_PIC_OFFSET, -+ VOP2_WIN_AFBC_PIC_SIZE, -+ VOP2_WIN_AFBC_DSP_OFFSET, -+ VOP2_WIN_AFBC_TRANSFORM_OFFSET, -+ VOP2_WIN_AFBC_HDR_PTR, -+ VOP2_WIN_AFBC_HALF_BLOCK_EN, -+ VOP2_WIN_AFBC_ROTATE_270, -+ VOP2_WIN_AFBC_ROTATE_90, -+ VOP2_WIN_MAX_REG, -+}; -+ -+struct vop2_win_data { -+ const char *name; -+ unsigned int phys_id; -+ -+ u32 base; -+ enum drm_plane_type type; -+ -+ u32 nformats; -+ const u32 *formats; -+ const uint64_t *format_modifiers; -+ const unsigned int supported_rotations; -+ -+ /** -+ * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2 -+ */ -+ unsigned int layer_sel_id; -+ uint64_t feature; -+ -+ unsigned int max_upscale_factor; -+ unsigned int max_downscale_factor; -+ const u8 dly[VOP2_DLY_MODE_MAX]; -+}; -+ -+struct vop2_video_port_data { -+ unsigned int id; -+ u32 feature; -+ u16 gamma_lut_len; -+ u16 cubic_lut_len; -+ struct vop_rect max_output; -+ const u8 pre_scan_max_dly[4]; -+ const struct vop2_video_port_regs *regs; -+ unsigned int offset; -+}; -+ -+struct vop2_data { -+ u8 nr_vps; -+ const struct vop2_ctrl *ctrl; -+ const struct vop2_win_data *win; -+ const struct vop2_video_port_data *vp; -+ const struct vop_csc_table *csc_table; -+ struct vop_rect max_input; -+ struct vop_rect max_output; -+ -+ unsigned int win_size; -+ unsigned int soc_id; -+}; -+ -+/* interrupt define */ -+#define FS_NEW_INTR BIT(4) -+#define ADDR_SAME_INTR BIT(5) -+#define LINE_FLAG1_INTR BIT(6) -+#define WIN0_EMPTY_INTR BIT(7) -+#define WIN1_EMPTY_INTR BIT(8) -+#define WIN2_EMPTY_INTR BIT(9) -+#define WIN3_EMPTY_INTR BIT(10) -+#define HWC_EMPTY_INTR BIT(11) -+#define POST_BUF_EMPTY_INTR BIT(12) -+#define PWM_GEN_INTR BIT(13) -+#define DMA_FINISH_INTR BIT(14) -+#define FS_FIELD_INTR BIT(15) -+#define FE_INTR BIT(16) -+#define WB_UV_FIFO_FULL_INTR BIT(17) -+#define WB_YRGB_FIFO_FULL_INTR BIT(18) -+#define WB_COMPLETE_INTR BIT(19) -+ -+/* -+ * display output interface supported by rockchip lcdc -+ */ -+#define ROCKCHIP_OUT_MODE_P888 0 -+#define ROCKCHIP_OUT_MODE_BT1120 0 -+#define ROCKCHIP_OUT_MODE_P666 1 -+#define ROCKCHIP_OUT_MODE_P565 2 -+#define ROCKCHIP_OUT_MODE_BT656 5 -+#define ROCKCHIP_OUT_MODE_S888 8 -+#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 -+#define ROCKCHIP_OUT_MODE_YUV420 14 -+/* for use special outface */ -+#define ROCKCHIP_OUT_MODE_AAAA 15 -+ -+enum vop_csc_format { -+ CSC_BT601L, -+ CSC_BT709L, -+ CSC_BT601F, -+ CSC_BT2020, -+}; -+ -+enum src_factor_mode { -+ SRC_FAC_ALPHA_ZERO, -+ SRC_FAC_ALPHA_ONE, -+ SRC_FAC_ALPHA_DST, -+ SRC_FAC_ALPHA_DST_INVERSE, -+ SRC_FAC_ALPHA_SRC, -+ SRC_FAC_ALPHA_SRC_GLOBAL, -+}; -+ -+enum dst_factor_mode { -+ DST_FAC_ALPHA_ZERO, -+ DST_FAC_ALPHA_ONE, -+ DST_FAC_ALPHA_SRC, -+ DST_FAC_ALPHA_SRC_INVERSE, -+ DST_FAC_ALPHA_DST, -+ DST_FAC_ALPHA_DST_GLOBAL, -+}; -+ -+#define RK3568_GRF_VO_CON1 0x0364 -+/* System registers definition */ -+#define RK3568_REG_CFG_DONE 0x000 -+#define RK3568_VERSION_INFO 0x004 -+#define RK3568_SYS_AUTO_GATING_CTRL 0x008 -+#define RK3568_SYS_AXI_LUT_CTRL 0x024 -+#define RK3568_DSP_IF_EN 0x028 -+#define RK3568_DSP_IF_CTRL 0x02c -+#define RK3568_DSP_IF_POL 0x030 -+#define RK3568_WB_CTRL 0x40 -+#define RK3568_WB_XSCAL_FACTOR 0x44 -+#define RK3568_WB_YRGB_MST 0x48 -+#define RK3568_WB_CBR_MST 0x4C -+#define RK3568_OTP_WIN_EN 0x050 -+#define RK3568_LUT_PORT_SEL 0x058 -+#define RK3568_SYS_STATUS0 0x060 -+#define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4) -+#define RK3568_SYS0_INT_EN 0x80 -+#define RK3568_SYS0_INT_CLR 0x84 -+#define RK3568_SYS0_INT_STATUS 0x88 -+#define RK3568_SYS1_INT_EN 0x90 -+#define RK3568_SYS1_INT_CLR 0x94 -+#define RK3568_SYS1_INT_STATUS 0x98 -+#define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10) -+#define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10) -+#define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10) -+#define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) -+ -+/* Video Port registers definition */ -+#define RK3568_VP_DSP_CTRL 0x00 -+#define RK3568_VP_MIPI_CTRL 0x04 -+#define RK3568_VP_COLOR_BAR_CTRL 0x08 -+#define RK3568_VP_3D_LUT_CTRL 0x10 -+#define RK3568_VP_3D_LUT_MST 0x20 -+#define RK3568_VP_DSP_BG 0x2C -+#define RK3568_VP_PRE_SCAN_HTIMING 0x30 -+#define RK3568_VP_POST_DSP_HACT_INFO 0x34 -+#define RK3568_VP_POST_DSP_VACT_INFO 0x38 -+#define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C -+#define RK3568_VP_POST_SCL_CTRL 0x40 -+#define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44 -+#define RK3568_VP_DSP_HTOTAL_HS_END 0x48 -+#define RK3568_VP_DSP_HACT_ST_END 0x4C -+#define RK3568_VP_DSP_VTOTAL_VS_END 0x50 -+#define RK3568_VP_DSP_VACT_ST_END 0x54 -+#define RK3568_VP_DSP_VS_ST_END_F1 0x58 -+#define RK3568_VP_DSP_VACT_ST_END_F1 0x5C -+#define RK3568_VP_BCSH_CTRL 0x60 -+#define RK3568_VP_BCSH_BCS 0x64 -+#define RK3568_VP_BCSH_H 0x68 -+#define RK3568_VP_BCSH_COLOR_BAR 0x6C -+ -+/* Overlay registers definition */ -+#define RK3568_OVL_CTRL 0x600 -+#define RK3568_OVL_LAYER_SEL 0x604 -+#define RK3568_OVL_PORT_SEL 0x608 -+#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 -+#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 -+#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 -+#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C -+#define RK3568_MIX0_SRC_COLOR_CTRL 0x650 -+#define RK3568_MIX0_DST_COLOR_CTRL 0x654 -+#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 -+#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C -+#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 -+#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 -+#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 -+#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC -+#define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4) -+#define RK3568_CLUSTER_DLY_NUM 0x6F0 -+#define RK3568_SMART_DLY_NUM 0x6F8 -+ -+/* Cluster register definition, offset relative to window base */ -+#define RK3568_CLUSTER_WIN_CTRL0 0x00 -+#define RK3568_CLUSTER_WIN_CTRL1 0x04 -+#define RK3568_CLUSTER_WIN_YRGB_MST 0x10 -+#define RK3568_CLUSTER_WIN_CBR_MST 0x14 -+#define RK3568_CLUSTER_WIN_VIR 0x18 -+#define RK3568_CLUSTER_WIN_ACT_INFO 0x20 -+#define RK3568_CLUSTER_WIN_DSP_INFO 0x24 -+#define RK3568_CLUSTER_WIN_DSP_ST 0x28 -+#define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30 -+#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C -+#define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50 -+#define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54 -+#define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58 -+#define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C -+#define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60 -+#define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64 -+#define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68 -+#define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C -+ -+#define RK3568_CLUSTER_CTRL 0x100 -+ -+/* (E)smart register definition, offset relative to window base */ -+#define RK3568_SMART_CTRL0 0x00 -+#define RK3568_SMART_CTRL1 0x04 -+#define RK3568_SMART_REGION0_CTRL 0x10 -+#define RK3568_SMART_REGION0_YRGB_MST 0x14 -+#define RK3568_SMART_REGION0_CBR_MST 0x18 -+#define RK3568_SMART_REGION0_VIR 0x1C -+#define RK3568_SMART_REGION0_ACT_INFO 0x20 -+#define RK3568_SMART_REGION0_DSP_INFO 0x24 -+#define RK3568_SMART_REGION0_DSP_ST 0x28 -+#define RK3568_SMART_REGION0_SCL_CTRL 0x30 -+#define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34 -+#define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38 -+#define RK3568_SMART_REGION0_SCL_OFFSET 0x3C -+#define RK3568_SMART_REGION1_CTRL 0x40 -+#define RK3568_SMART_REGION1_YRGB_MST 0x44 -+#define RK3568_SMART_REGION1_CBR_MST 0x48 -+#define RK3568_SMART_REGION1_VIR 0x4C -+#define RK3568_SMART_REGION1_ACT_INFO 0x50 -+#define RK3568_SMART_REGION1_DSP_INFO 0x54 -+#define RK3568_SMART_REGION1_DSP_ST 0x58 -+#define RK3568_SMART_REGION1_SCL_CTRL 0x60 -+#define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64 -+#define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68 -+#define RK3568_SMART_REGION1_SCL_OFFSET 0x6C -+#define RK3568_SMART_REGION2_CTRL 0x70 -+#define RK3568_SMART_REGION2_YRGB_MST 0x74 -+#define RK3568_SMART_REGION2_CBR_MST 0x78 -+#define RK3568_SMART_REGION2_VIR 0x7C -+#define RK3568_SMART_REGION2_ACT_INFO 0x80 -+#define RK3568_SMART_REGION2_DSP_INFO 0x84 -+#define RK3568_SMART_REGION2_DSP_ST 0x88 -+#define RK3568_SMART_REGION2_SCL_CTRL 0x90 -+#define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94 -+#define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98 -+#define RK3568_SMART_REGION2_SCL_OFFSET 0x9C -+#define RK3568_SMART_REGION3_CTRL 0xA0 -+#define RK3568_SMART_REGION3_YRGB_MST 0xA4 -+#define RK3568_SMART_REGION3_CBR_MST 0xA8 -+#define RK3568_SMART_REGION3_VIR 0xAC -+#define RK3568_SMART_REGION3_ACT_INFO 0xB0 -+#define RK3568_SMART_REGION3_DSP_INFO 0xB4 -+#define RK3568_SMART_REGION3_DSP_ST 0xB8 -+#define RK3568_SMART_REGION3_SCL_CTRL 0xC0 -+#define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4 -+#define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8 -+#define RK3568_SMART_REGION3_SCL_OFFSET 0xCC -+#define RK3568_SMART_COLOR_KEY_CTRL 0xD0 -+ -+/* HDR register definition */ -+#define RK3568_HDR_LUT_CTRL 0x2000 -+#define RK3568_HDR_LUT_MST 0x2004 -+#define RK3568_SDR2HDR_CTRL 0x2010 -+#define RK3568_HDR2SDR_CTRL 0x2020 -+#define RK3568_HDR2SDR_SRC_RANGE 0x2024 -+#define RK3568_HDR2SDR_NORMFACEETF 0x2028 -+#define RK3568_HDR2SDR_DST_RANGE 0x202C -+#define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030 -+#define RK3568_HDR_EETF_OETF_Y0 0x203C -+#define RK3568_HDR_SAT_Y0 0x20C0 -+#define RK3568_HDR_EOTF_OETF_Y0 0x20F0 -+#define RK3568_HDR_OETF_DX_POW1 0x2200 -+#define RK3568_HDR_OETF_XN1 0x2300 -+ -+#define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15) -+ -+#define RK3568_VP_DSP_CTRL__STANDBY BIT(31) -+#define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20) -+#define RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL GENMASK(19, 18) -+#define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17) -+#define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16) -+#define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15) -+#define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9) -+#define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7) -+#define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6) -+#define RK3568_VP_DSP_CTRL__P2I_EN BIT(5) -+#define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4) -+#define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0) -+ -+#define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) -+#define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) -+ -+#define RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX GENMASK(26, 25) -+#define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24) -+#define RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) -+#define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20) -+#define RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX GENMASK(19, 18) -+#define RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(17, 16) -+#define RK3568_SYS_DSP_INFACE_EN_EDP_MUX GENMASK(15, 14) -+#define RK3568_SYS_DSP_INFACE_EN_HDMI_MUX GENMASK(11, 10) -+#define RK3568_SYS_DSP_INFACE_EN_RGB_MUX GENMASK(9, 8) -+#define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5) -+#define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4) -+#define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3) -+#define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1) -+#define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0) -+ -+#define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16) -+#define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12) -+#define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4) -+#define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0) -+ -+#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5) -+#define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4) -+ -+#define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31) -+ -+#define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28) -+ -+#define VOP2_SYS_AXI_BUS_NUM 2 -+ -+#define VOP2_CLUSTER_YUV444_10 0x12 -+ -+#define VOP2_COLOR_KEY_MASK BIT(31) -+ -+#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28) -+ -+#define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) -+ -+#define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16) -+#define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30) -+#define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28) -+#define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26) -+#define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24) -+#define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18) -+#define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16) -+#define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8) -+#define RK3568_OVL_PORT_SET__PORT1_MUX GENMASK(7, 4) -+#define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0) -+#define RK3568_OVL_LAYER_SEL__LAYER(layer, x) ((x) << ((layer) * 4)) -+ -+#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_1 GENMASK(31, 24) -+#define RK3568_CLUSTER_DLY_NUM__CLUSTER1_0 GENMASK(23, 16) -+#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8) -+#define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0) -+ -+#define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24) -+#define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16) -+#define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8) -+#define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0) -+ -+#define VP_INT_DSP_HOLD_VALID BIT(6) -+#define VP_INT_FS_FIELD BIT(5) -+#define VP_INT_POST_BUF_EMPTY BIT(4) -+#define VP_INT_LINE_FLAG1 BIT(3) -+#define VP_INT_LINE_FLAG0 BIT(2) -+#define VOP2_INT_BUS_ERRPR BIT(1) -+#define VP_INT_FS BIT(0) -+ -+#define POLFLAG_DCLK_INV BIT(3) -+ -+enum vop2_layer_phy_id { -+ ROCKCHIP_VOP2_CLUSTER0 = 0, -+ ROCKCHIP_VOP2_CLUSTER1, -+ ROCKCHIP_VOP2_ESMART0, -+ ROCKCHIP_VOP2_ESMART1, -+ ROCKCHIP_VOP2_SMART0, -+ ROCKCHIP_VOP2_SMART1, -+ ROCKCHIP_VOP2_CLUSTER2, -+ ROCKCHIP_VOP2_CLUSTER3, -+ ROCKCHIP_VOP2_ESMART2, -+ ROCKCHIP_VOP2_ESMART3, -+ ROCKCHIP_VOP2_PHY_ID_INVALID = -1, -+}; -+ -+extern const struct component_ops vop2_component_ops; -+ -+#endif /* _ROCKCHIP_DRM_VOP2_H */ -diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c -new file mode 100644 -index 0000000000000..9bf0637bf8e26 ---- /dev/null -+++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c -@@ -0,0 +1,281 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) Rockchip Electronics Co.Ltd -+ * Author: Andy Yan -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "rockchip_drm_vop2.h" -+ -+static const uint32_t formats_win_full_10bit[] = { -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_RGB888, -+ DRM_FORMAT_BGR888, -+ DRM_FORMAT_RGB565, -+ DRM_FORMAT_BGR565, -+ DRM_FORMAT_NV12, -+ DRM_FORMAT_NV16, -+ DRM_FORMAT_NV24, -+}; -+ -+static const uint32_t formats_win_full_10bit_yuyv[] = { -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_RGB888, -+ DRM_FORMAT_BGR888, -+ DRM_FORMAT_RGB565, -+ DRM_FORMAT_BGR565, -+ DRM_FORMAT_NV12, -+ DRM_FORMAT_NV16, -+ DRM_FORMAT_NV24, -+ DRM_FORMAT_YVYU, -+ DRM_FORMAT_VYUY, -+}; -+ -+static const uint32_t formats_win_lite[] = { -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_RGB888, -+ DRM_FORMAT_BGR888, -+ DRM_FORMAT_RGB565, -+ DRM_FORMAT_BGR565, -+}; -+ -+static const uint64_t format_modifiers[] = { -+ DRM_FORMAT_MOD_LINEAR, -+ DRM_FORMAT_MOD_INVALID, -+}; -+ -+static const uint64_t format_modifiers_afbc[] = { -+ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16), -+ -+ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | -+ AFBC_FORMAT_MOD_SPARSE), -+ -+ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | -+ AFBC_FORMAT_MOD_YTR), -+ -+ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | -+ AFBC_FORMAT_MOD_CBR), -+ -+ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | -+ AFBC_FORMAT_MOD_YTR | -+ AFBC_FORMAT_MOD_SPARSE), -+ -+ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | -+ AFBC_FORMAT_MOD_CBR | -+ AFBC_FORMAT_MOD_SPARSE), -+ -+ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | -+ AFBC_FORMAT_MOD_YTR | -+ AFBC_FORMAT_MOD_CBR), -+ -+ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | -+ AFBC_FORMAT_MOD_YTR | -+ AFBC_FORMAT_MOD_CBR | -+ AFBC_FORMAT_MOD_SPARSE), -+ -+ /* SPLIT mandates SPARSE, RGB modes mandates YTR */ -+ DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | -+ AFBC_FORMAT_MOD_YTR | -+ AFBC_FORMAT_MOD_SPARSE | -+ AFBC_FORMAT_MOD_SPLIT), -+ DRM_FORMAT_MOD_INVALID, -+}; -+ -+static const struct vop2_video_port_data rk3568_vop_video_ports[] = { -+ { -+ .id = 0, -+ .feature = VOP_FEATURE_OUTPUT_10BIT, -+ .gamma_lut_len = 1024, -+ .cubic_lut_len = 9 * 9 * 9, -+ .max_output = { 4096, 2304 }, -+ .pre_scan_max_dly = { 69, 53, 53, 42 }, -+ .offset = 0xc00, -+ }, { -+ .id = 1, -+ .gamma_lut_len = 1024, -+ .max_output = { 2048, 1536 }, -+ .pre_scan_max_dly = { 40, 40, 40, 40 }, -+ .offset = 0xd00, -+ }, { -+ .id = 2, -+ .gamma_lut_len = 1024, -+ .max_output = { 1920, 1080 }, -+ .pre_scan_max_dly = { 40, 40, 40, 40 }, -+ .offset = 0xe00, -+ }, -+}; -+ -+/* -+ * rk3568 vop with 2 cluster, 2 esmart win, 2 smart win. -+ * Every cluster can work as 4K win or split into two win. -+ * All win in cluster support AFBCD. -+ * -+ * Every esmart win and smart win support 4 Multi-region. -+ * -+ * Scale filter mode: -+ * -+ * * Cluster: bicubic for horizontal scale up, others use bilinear -+ * * ESmart: -+ * * nearest-neighbor/bilinear/bicubic for scale up -+ * * nearest-neighbor/bilinear/average for scale down -+ * -+ * -+ * @TODO describe the wind like cpu-map dt nodes; -+ */ -+static const struct vop2_win_data rk3568_vop_win_data[] = { -+ { -+ .name = "Smart0-win0", -+ .phys_id = ROCKCHIP_VOP2_SMART0, -+ .base = 0x1c00, -+ .formats = formats_win_lite, -+ .nformats = ARRAY_SIZE(formats_win_lite), -+ .format_modifiers = format_modifiers, -+ .layer_sel_id = 3, -+ .supported_rotations = DRM_MODE_REFLECT_Y, -+ .type = DRM_PLANE_TYPE_PRIMARY, -+ .max_upscale_factor = 8, -+ .max_downscale_factor = 8, -+ .dly = { 20, 47, 41 }, -+ }, { -+ .name = "Smart1-win0", -+ .phys_id = ROCKCHIP_VOP2_SMART1, -+ .formats = formats_win_lite, -+ .nformats = ARRAY_SIZE(formats_win_lite), -+ .format_modifiers = format_modifiers, -+ .base = 0x1e00, -+ .layer_sel_id = 7, -+ .supported_rotations = DRM_MODE_REFLECT_Y, -+ .type = DRM_PLANE_TYPE_PRIMARY, -+ .max_upscale_factor = 8, -+ .max_downscale_factor = 8, -+ .dly = { 20, 47, 41 }, -+ }, { -+ .name = "Esmart1-win0", -+ .phys_id = ROCKCHIP_VOP2_ESMART1, -+ .formats = formats_win_full_10bit_yuyv, -+ .nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv), -+ .format_modifiers = format_modifiers, -+ .base = 0x1a00, -+ .layer_sel_id = 6, -+ .supported_rotations = DRM_MODE_REFLECT_Y, -+ .type = DRM_PLANE_TYPE_PRIMARY, -+ .max_upscale_factor = 8, -+ .max_downscale_factor = 8, -+ .dly = { 20, 47, 41 }, -+ }, { -+ .name = "Esmart0-win0", -+ .phys_id = ROCKCHIP_VOP2_ESMART0, -+ .formats = formats_win_full_10bit_yuyv, -+ .nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv), -+ .format_modifiers = format_modifiers, -+ .base = 0x1800, -+ .layer_sel_id = 2, -+ .supported_rotations = DRM_MODE_REFLECT_Y, -+ .type = DRM_PLANE_TYPE_OVERLAY, -+ .max_upscale_factor = 8, -+ .max_downscale_factor = 8, -+ .dly = { 20, 47, 41 }, -+ }, { -+ .name = "Cluster0-win0", -+ .phys_id = ROCKCHIP_VOP2_CLUSTER0, -+ .base = 0x1000, -+ .formats = formats_win_full_10bit, -+ .nformats = ARRAY_SIZE(formats_win_full_10bit), -+ .format_modifiers = format_modifiers_afbc, -+ .layer_sel_id = 0, -+ .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | -+ DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, -+ .max_upscale_factor = 4, -+ .max_downscale_factor = 4, -+ .dly = { 0, 27, 21 }, -+ .type = DRM_PLANE_TYPE_OVERLAY, -+ .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, -+ }, { -+ .name = "Cluster1-win0", -+ .phys_id = ROCKCHIP_VOP2_CLUSTER1, -+ .base = 0x1200, -+ .formats = formats_win_full_10bit, -+ .nformats = ARRAY_SIZE(formats_win_full_10bit), -+ .format_modifiers = format_modifiers_afbc, -+ .layer_sel_id = 1, -+ .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | -+ DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, -+ .type = DRM_PLANE_TYPE_OVERLAY, -+ .max_upscale_factor = 4, -+ .max_downscale_factor = 4, -+ .dly = { 0, 27, 21 }, -+ .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, -+ }, -+}; -+ -+static const struct vop2_data rk3566_vop = { -+ .nr_vps = 3, -+ .max_input = { 4096, 2304 }, -+ .max_output = { 4096, 2304 }, -+ .vp = rk3568_vop_video_ports, -+ .win = rk3568_vop_win_data, -+ .win_size = ARRAY_SIZE(rk3568_vop_win_data), -+ .soc_id = 3566, -+}; -+ -+static const struct vop2_data rk3568_vop = { -+ .nr_vps = 3, -+ .max_input = { 4096, 2304 }, -+ .max_output = { 4096, 2304 }, -+ .vp = rk3568_vop_video_ports, -+ .win = rk3568_vop_win_data, -+ .win_size = ARRAY_SIZE(rk3568_vop_win_data), -+ .soc_id = 3568, -+}; -+ -+static const struct of_device_id vop2_dt_match[] = { -+ { -+ .compatible = "rockchip,rk3566-vop", -+ .data = &rk3566_vop, -+ }, { -+ .compatible = "rockchip,rk3568-vop", -+ .data = &rk3568_vop, -+ }, { -+ }, -+}; -+MODULE_DEVICE_TABLE(of, vop2_dt_match); -+ -+static int vop2_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ -+ return component_add(dev, &vop2_component_ops); -+} -+ -+static int vop2_remove(struct platform_device *pdev) -+{ -+ component_del(&pdev->dev, &vop2_component_ops); -+ -+ return 0; -+} -+ -+struct platform_driver vop2_platform_driver = { -+ .probe = vop2_probe, -+ .remove = vop2_remove, -+ .driver = { -+ .name = "rockchip-vop2", -+ .of_match_table = of_match_ptr(vop2_dt_match), -+ }, -+}; diff --git a/patch/kernel/archive/station-p2-5.18/0220-v11-23-24-dt-bindings-display-rockchip-Add-binding-for-VOP2.patch b/patch/kernel/archive/station-p2-5.18/0220-v11-23-24-dt-bindings-display-rockchip-Add-binding-for-VOP2.patch deleted file mode 100755 index 27932fdeb..000000000 --- a/patch/kernel/archive/station-p2-5.18/0220-v11-23-24-dt-bindings-display-rockchip-Add-binding-for-VOP2.patch +++ /dev/null @@ -1,146 +0,0 @@ -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -new file mode 100644 -index 0000000000000..655d9b327f7d3 ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml -@@ -0,0 +1,140 @@ -+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip SoC display controller (VOP2) -+ -+description: -+ VOP2 (Video Output Processor v2) is the display controller for the Rockchip -+ series of SoCs which transfers the image data from a video memory -+ buffer to an external LCD interface. -+ -+maintainers: -+ - Sandy Huang -+ - Heiko Stuebner -+ -+properties: -+ compatible: -+ enum: -+ - rockchip,rk3566-vop -+ - rockchip,rk3568-vop -+ -+ reg: -+ minItems: 1 -+ items: -+ - description: -+ Must contain one entry corresponding to the base address and length -+ of the register space. -+ - description: -+ Can optionally contain a second entry corresponding to -+ the CRTC gamma LUT address. -+ -+ interrupts: -+ maxItems: 1 -+ description: -+ The VOP interrupt is shared by several interrupt sources, such as -+ frame start (VSYNC), line flag and other status interrupts. -+ -+ clocks: -+ items: -+ - description: Clock for ddr buffer transfer. -+ - description: Clock for the ahb bus to R/W the phy regs. -+ - description: Pixel clock for video port 0. -+ - description: Pixel clock for video port 1. -+ - description: Pixel clock for video port 2. -+ -+ clock-names: -+ items: -+ - const: aclk -+ - const: hclk -+ - const: dclk_vp0 -+ - const: dclk_vp1 -+ - const: dclk_vp2 -+ -+ rockchip,grf: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ Phandle to GRF regs used for misc control -+ -+ ports: -+ $ref: /schemas/graph.yaml#/properties/ports -+ -+ properties: -+ port@0: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: -+ Output endpoint of VP0 -+ -+ port@1: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: -+ Output endpoint of VP1 -+ -+ port@2: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: -+ Output endpoint of VP2 -+ -+ iommus: -+ maxItems: 1 -+ -+ power-domains: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ - ports -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ bus { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ vop: vop@fe040000 { -+ compatible = "rockchip,rk3568-vop"; -+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, -+ <&cru HCLK_VOP>, -+ <&cru DCLK_VOP0>, -+ <&cru DCLK_VOP1>, -+ <&cru DCLK_VOP2>; -+ clock-names = "aclk", -+ "hclk", -+ "dclk_vp0", -+ "dclk_vp1", -+ "dclk_vp2"; -+ power-domains = <&power RK3568_PD_VO>; -+ iommus = <&vop_mmu>; -+ vop_out: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ vp0: port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ vp1: port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ vp2: port@2 { -+ reg = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ }; diff --git a/patch/kernel/archive/station-p2-5.18/0230-v11-24-24-dt-bindings-display-rockchip-dw-hdmi-fix-ports-description.patch b/patch/kernel/archive/station-p2-5.18/0230-v11-24-24-dt-bindings-display-rockchip-dw-hdmi-fix-ports-description.patch deleted file mode 100755 index 78cc51fcb..000000000 --- a/patch/kernel/archive/station-p2-5.18/0230-v11-24-24-dt-bindings-display-rockchip-dw-hdmi-fix-ports-description.patch +++ /dev/null @@ -1,41 +0,0 @@ -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -index d7cb2b2be60e8..7e59dee15a5f4 100644 ---- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml -@@ -97,27 +97,21 @@ properties: - ports: - $ref: /schemas/graph.yaml#/properties/ports - -- properties: -- port: -- $ref: /schemas/graph.yaml#/$defs/port-base -- unevaluatedProperties: false -+ patternProperties: -+ "^port(@0)?$": -+ $ref: /schemas/graph.yaml#/properties/port - description: Input of the DWC HDMI TX -- - properties: -+ endpoint: -+ description: Connection to the VOP - endpoint@0: -- $ref: /schemas/graph.yaml#/properties/endpoint - description: Connection to the VOPB -- - endpoint@1: -- $ref: /schemas/graph.yaml#/properties/endpoint - description: Connection to the VOPL -- -- required: -- - endpoint@0 -- - endpoint@1 -- -- required: -- - port -+ properties: -+ port@1: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: Output of the DWC HDMI TX - - rockchip,grf: - $ref: /schemas/types.yaml#/definitions/phandle diff --git a/patch/kernel/archive/station-p2-5.18/0240-v5-1-5-dt-bindings-soc-grf-add-rk3566-pipe-grf-compatible.patch b/patch/kernel/archive/station-p2-5.18/0240-v5-1-5-dt-bindings-soc-grf-add-rk3566-pipe-grf-compatible.patch deleted file mode 100755 index a017a5c54..000000000 --- a/patch/kernel/archive/station-p2-5.18/0240-v5-1-5-dt-bindings-soc-grf-add-rk3566-pipe-grf-compatible.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -index b2ba7bed89b2..3be3cfd52f7b 100644 ---- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -@@ -15,6 +15,7 @@ properties: - - items: - - enum: - - rockchip,rk3288-sgrf -+ - rockchip,rk3566-pipe-grf - - rockchip,rk3568-usb2phy-grf - - rockchip,rv1108-usbgrf - - const: syscon diff --git a/patch/kernel/archive/station-p2-5.18/0250-v5-2-5-soc-rockchip-set-dwc3-clock-for-rk3566.patch b/patch/kernel/archive/station-p2-5.18/0250-v5-2-5-soc-rockchip-set-dwc3-clock-for-rk3566.patch deleted file mode 100755 index f63946377..000000000 --- a/patch/kernel/archive/station-p2-5.18/0250-v5-2-5-soc-rockchip-set-dwc3-clock-for-rk3566.patch +++ /dev/null @@ -1,35 +0,0 @@ -diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c -index 494cf2b5bf7b..384461b70684 100644 ---- a/drivers/soc/rockchip/grf.c -+++ b/drivers/soc/rockchip/grf.c -@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk3399_grf __initconst = { - .num_values = ARRAY_SIZE(rk3399_defaults), - }; - -+#define RK3566_GRF_USB3OTG0_CON1 0x0104 -+ -+static const struct rockchip_grf_value rk3566_defaults[] __initconst = { -+ { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) }, -+ { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) }, -+ { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) }, -+}; -+ -+static const struct rockchip_grf_info rk3566_pipegrf __initconst = { -+ .values = rk3566_defaults, -+ .num_values = ARRAY_SIZE(rk3566_defaults), -+}; -+ -+ - static const struct of_device_id rockchip_grf_dt_match[] __initconst = { - { - .compatible = "rockchip,rk3036-grf", -@@ -130,6 +144,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = { - }, { - .compatible = "rockchip,rk3399-grf", - .data = (void *)&rk3399_grf, -+ }, { -+ .compatible = "rockchip,rk3566-pipe-grf", -+ .data = (void *)&rk3566_pipegrf, - }, - { /* sentinel */ }, - }; diff --git a/patch/kernel/archive/station-p2-5.18/0260-v5-3-5-arm64-dts-rockchip-add-rk356x-dwc3-usb3-nodes.patch b/patch/kernel/archive/station-p2-5.18/0260-v5-3-5-arm64-dts-rockchip-add-rk356x-dwc3-usb3-nodes.patch deleted file mode 100755 index 238c4defe..000000000 --- a/patch/kernel/archive/station-p2-5.18/0260-v5-3-5-arm64-dts-rockchip-add-rk356x-dwc3-usb3-nodes.patch +++ /dev/null @@ -1,103 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi -index 3839eef5e4f7..0b957068ff89 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi -@@ -6,6 +6,10 @@ / { - compatible = "rockchip,rk3566"; - }; - -+&pipegrf { -+ compatible = "rockchip,rk3566-pipe-grf", "syscon"; -+}; -+ - &power { - power-domain@RK3568_PD_PIPE { - reg = ; -@@ -18,3 +22,10 @@ power-domain@RK3568_PD_PIPE { - #power-domain-cells = <0>; - }; - }; -+ -+&usb_host0_xhci { -+ phys = <&usb2phy0_otg>; -+ phy-names = "usb2-phy"; -+ extcon = <&usb2phy0>; -+ maximum-speed = "high-speed"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -index 5b0f528d6818..8ba9334f9753 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -99,6 +99,10 @@ opp-1992000000 { - }; - }; - -+&pipegrf { -+ compatible = "rockchip,rk3568-pipe-grf", "syscon"; -+}; -+ - &power { - power-domain@RK3568_PD_PIPE { - reg = ; -@@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE { - #power-domain-cells = <0>; - }; - }; -+ -+&usb_host0_xhci { -+ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index 7cdef800cb3c..ca20d7b91fe5 100644 ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -230,6 +230,40 @@ scmi_shmem: sram@0 { - }; - }; - -+ usb_host0_xhci: usb@fcc00000 { -+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfcc00000 0x0 0x400000>; -+ interrupts = ; -+ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, -+ <&cru ACLK_USB3OTG0>; -+ clock-names = "ref_clk", "suspend_clk", -+ "bus_clk"; -+ dr_mode = "host"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ resets = <&cru SRST_USB3OTG0>; -+ snps,dis_u2_susphy_quirk; -+ status = "disabled"; -+ }; -+ -+ usb_host1_xhci: usb@fd000000 { -+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfd000000 0x0 0x400000>; -+ interrupts = ; -+ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, -+ <&cru ACLK_USB3OTG1>; -+ clock-names = "ref_clk", "suspend_clk", -+ "bus_clk"; -+ dr_mode = "host"; -+ phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ resets = <&cru SRST_USB3OTG1>; -+ snps,dis_u2_susphy_quirk; -+ status = "disabled"; -+ }; -+ - gic: interrupt-controller@fd400000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ -@@ -297,7 +331,6 @@ pmu_io_domains: io-domains { - }; - - pipegrf: syscon@fdc50000 { -- compatible = "rockchip,rk3568-pipe-grf", "syscon"; - reg = <0x0 0xfdc50000 0x0 0x1000>; - }; - diff --git a/patch/kernel/archive/station-p2-5.18/0270-v5-4-5-arm64-dts-rockchip-enable-dwc3-on-quartz64-a.patch b/patch/kernel/archive/station-p2-5.18/0270-v5-4-5-arm64-dts-rockchip-enable-dwc3-on-quartz64-a.patch deleted file mode 100755 index 8c0eee8fb..000000000 --- a/patch/kernel/archive/station-p2-5.18/0270-v5-4-5-arm64-dts-rockchip-enable-dwc3-on-quartz64-a.patch +++ /dev/null @@ -1,62 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -index dd7f4b9b686b..141a433429b5 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -151,6 +151,16 @@ vcc5v0_usb20_host: vcc5v0_usb20_host { - vin-supply = <&vcc5v0_usb>; - }; - -+ vcc5v0_usb20_otg: vcc5v0_usb20_otg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc5v0_usb20_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&dcdc_boost>; -+ }; -+ - vcc3v3_sd: vcc3v3_sd { - compatible = "regulator-fixed"; - enable-active-low; -@@ -187,6 +197,10 @@ vcc_wl: vcc_wl { - }; - }; - -+&combphy1 { -+ status = "okay"; -+}; -+ - &cpu0 { - cpu-supply = <&vdd_cpu>; - }; -@@ -672,6 +686,29 @@ &usb_host1_ohci { - status = "okay"; - }; - -+&usb_host0_xhci { -+ status = "okay"; -+}; -+ -+/* usb3 controller is muxed with sata1 */ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb20_host>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ phy-supply = <&vcc5v0_usb20_otg>; -+ status = "okay"; -+}; -+ - &usb2phy1 { - status = "okay"; - }; diff --git a/patch/kernel/archive/station-p2-5.18/0280-v5-5-5-arm64-dts-rockchip-add-usb3-support-to-rk3568-evb1-v10.patch b/patch/kernel/archive/station-p2-5.18/0280-v5-5-5-arm64-dts-rockchip-add-usb3-support-to-rk3568-evb1-v10.patch deleted file mode 100755 index fb66f3a27..000000000 --- a/patch/kernel/archive/station-p2-5.18/0280-v5-5-5-arm64-dts-rockchip-add-usb3-support-to-rk3568-evb1-v10.patch +++ /dev/null @@ -1,85 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -index a794a0ea5c70..622be8be9813 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts -@@ -103,6 +103,18 @@ vcc5v0_usb_host: vcc5v0-usb-host { - vin-supply = <&vcc5v0_usb>; - }; - -+ vcc5v0_usb_otg: vcc5v0-usb-otg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_otg_en>; -+ regulator-name = "vcc5v0_usb_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ - vcc3v3_lcd0_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; -@@ -136,6 +148,14 @@ regulator-state-mem { - }; - }; - -+&combphy0 { -+ status = "okay"; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ - &cpu0 { - cpu-supply = <&vdd_cpu>; - }; -@@ -507,6 +527,9 @@ usb { - vcc5v0_usb_host_en: vcc5v0_usb_host_en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; -+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; - }; - }; - -@@ -568,6 +591,11 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usb_host0_xhci { -+ extcon = <&usb2phy0>; -+ status = "okay"; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; -@@ -576,6 +604,24 @@ &usb_host1_ohci { - status = "okay"; - }; - -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb_host>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ vbus-supply = <&vcc5v0_usb_otg>; -+ status = "okay"; -+}; -+ - &usb2phy1 { - status = "okay"; - }; diff --git a/patch/kernel/archive/station-p2-5.18/0290-1-2-arm64-dts-rockchip-Add-USB-nodes-for-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.18/0290-1-2-arm64-dts-rockchip-Add-USB-nodes-for-BPI-R2-Pro.patch deleted file mode 100755 index ded00f486..000000000 --- a/patch/kernel/archive/station-p2-5.18/0290-1-2-arm64-dts-rockchip-Add-USB-nodes-for-BPI-R2-Pro.patch +++ /dev/null @@ -1,115 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -index 067fe4a6b178..879557595a64 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -73,6 +73,50 @@ vcc5v0_sys: vcc5v0-sys { - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; -+ -+ vcc5v0_usb: vcc5v0_usb { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ vcc5v0_usb_host: vcc5v0-usb-host { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_host_en>; -+ regulator-name = "vcc5v0_usb_host"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_usb_otg: vcc5v0-usb-otg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_otg_en>; -+ regulator-name = "vcc5v0_usb_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+}; -+ -+&combphy0 { -+ /* used for USB3 */ -+ status = "okay"; -+}; -+ -+&combphy1 { -+ /* used for USB3 */ -+ status = "okay"; - }; - - &gmac0 { -@@ -368,6 +412,16 @@ pmic_int: pmic_int { - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -+ -+ usb { -+ vcc5v0_usb_host_en: vcc5v0_usb_host_en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; - }; - - &pmu_io_domains { -@@ -485,3 +539,42 @@ &uart9 { - pinctrl-0 = <&uart9m1_xfer>; - status = "disabled"; - }; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host0_xhci { -+ extcon = <&usb2phy0>; -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb_host>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ phy-supply = <&vcc5v0_usb_otg>; -+ status = "okay"; -+}; diff --git a/patch/kernel/archive/station-p2-5.18/0300-2-2-arm64-dts-rockchip-Add-SATA-support-to-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.18/0300-2-2-arm64-dts-rockchip-Add-SATA-support-to-BPI-R2-Pro.patch deleted file mode 100755 index 24fbf8f63..000000000 --- a/patch/kernel/archive/station-p2-5.18/0300-2-2-arm64-dts-rockchip-Add-SATA-support-to-BPI-R2-Pro.patch +++ /dev/null @@ -1,27 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -index 879557595a64..40cf2236c0b6 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -119,6 +119,11 @@ &combphy1 { - status = "okay"; - }; - -+&combphy2 { -+ /* used for SATA */ -+ status = "okay"; -+}; -+ - &gmac0 { - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; -@@ -484,6 +489,10 @@ &saradc { - status = "okay"; - }; - -+&sata2 { -+ status = "okay"; -+}; -+ - &sdhci { - bus-width = <8>; - max-frequency = <200000000>; diff --git a/patch/kernel/archive/station-p2-5.18/0310-drm-rockchip-Refactor-IOMMU-initialisation.patch b/patch/kernel/archive/station-p2-5.18/0310-drm-rockchip-Refactor-IOMMU-initialisation.patch deleted file mode 100755 index 3b8bae939..000000000 --- a/patch/kernel/archive/station-p2-5.18/0310-drm-rockchip-Refactor-IOMMU-initialisation.patch +++ /dev/null @@ -1,187 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 4eaeb430c83a..7efd12312354 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -7,7 +7,6 @@ - */ - - #include --#include - #include - #include - #include -@@ -34,7 +33,6 @@ - #define DRIVER_MAJOR 1 - #define DRIVER_MINOR 0 - --static bool is_support_iommu = true; - static const struct drm_driver rockchip_drm_driver; - - /* -@@ -48,7 +46,7 @@ int rockchip_drm_dma_attach_device(struct drm_device *drm_dev, - struct rockchip_drm_private *private = drm_dev->dev_private; - int ret; - -- if (!is_support_iommu) -+ if (!private->domain) - return 0; - - ret = iommu_attach_device(private->domain, dev); -@@ -64,12 +62,22 @@ void rockchip_drm_dma_detach_device(struct drm_device *drm_dev, - struct device *dev) - { - struct rockchip_drm_private *private = drm_dev->dev_private; -- struct iommu_domain *domain = private->domain; - -- if (!is_support_iommu) -+ if (!private->domain) - return; - -- iommu_detach_device(domain, dev); -+ iommu_detach_device(private->domain, dev); -+} -+ -+void rockchip_drm_dma_init_device(struct drm_device *drm_dev, -+ struct device *dev) -+{ -+ struct rockchip_drm_private *private = drm_dev->dev_private; -+ -+ if (!device_iommu_mapped(dev)) -+ private->iommu_dev = ERR_PTR(-ENODEV); -+ else if (!private->iommu_dev) -+ private->iommu_dev = dev; - } - - static int rockchip_drm_init_iommu(struct drm_device *drm_dev) -@@ -78,10 +86,10 @@ static int rockchip_drm_init_iommu(struct drm_device *drm_dev) - struct iommu_domain_geometry *geometry; - u64 start, end; - -- if (!is_support_iommu) -+ if (IS_ERR_OR_NULL(private->iommu_dev)) - return 0; - -- private->domain = iommu_domain_alloc(&platform_bus_type); -+ private->domain = iommu_domain_alloc(private->iommu_dev->bus); - if (!private->domain) - return -ENOMEM; - -@@ -101,7 +109,7 @@ static void rockchip_iommu_cleanup(struct drm_device *drm_dev) - { - struct rockchip_drm_private *private = drm_dev->dev_private; - -- if (!is_support_iommu) -+ if (!private->domain) - return; - - drm_mm_takedown(&private->mm); -@@ -137,24 +145,24 @@ static int rockchip_drm_bind(struct device *dev) - - drm_dev->dev_private = private; - -- ret = rockchip_drm_init_iommu(drm_dev); -- if (ret) -- goto err_free; -- - ret = drmm_mode_config_init(drm_dev); - if (ret) -- goto err_iommu_cleanup; -+ goto err_free; - - rockchip_drm_mode_config_init(drm_dev); - - /* Try to bind all sub drivers. */ - ret = component_bind_all(dev, drm_dev); - if (ret) -- goto err_iommu_cleanup; -+ goto err_free; -+ -+ ret = rockchip_drm_init_iommu(drm_dev); -+ if (ret) -+ goto err_unbind_all; - - ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc); - if (ret) -- goto err_unbind_all; -+ goto err_iommu_cleanup; - - drm_mode_config_reset(drm_dev); - -@@ -170,10 +178,10 @@ static int rockchip_drm_bind(struct device *dev) - return 0; - err_kms_helper_poll_fini: - drm_kms_helper_poll_fini(drm_dev); --err_unbind_all: -- component_unbind_all(dev, drm_dev); - err_iommu_cleanup: - rockchip_iommu_cleanup(drm_dev); -+err_unbind_all: -+ component_unbind_all(dev, drm_dev); - err_free: - drm_dev_put(drm_dev); - return ret; -@@ -342,8 +350,6 @@ static int rockchip_drm_platform_of_probe(struct device *dev) - return -ENODEV; - - for (i = 0;; i++) { -- struct device_node *iommu; -- - port = of_parse_phandle(np, "ports", i); - if (!port) - break; -@@ -353,21 +359,7 @@ static int rockchip_drm_platform_of_probe(struct device *dev) - continue; - } - -- iommu = of_parse_phandle(port->parent, "iommus", 0); -- if (!iommu || !of_device_is_available(iommu)) { -- DRM_DEV_DEBUG(dev, -- "no iommu attached for %pOF, using non-iommu buffers\n", -- port->parent); -- /* -- * if there is a crtc not support iommu, force set all -- * crtc use non-iommu buffer. -- */ -- is_support_iommu = false; -- } -- - found = true; -- -- of_node_put(iommu); - of_node_put(port); - } - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -index 143a48330f84..008c44aef400 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -44,6 +44,7 @@ struct rockchip_crtc_state { - */ - struct rockchip_drm_private { - struct iommu_domain *domain; -+ struct device *iommu_dev; - struct mutex mm_lock; - struct drm_mm mm; - }; -@@ -52,6 +53,8 @@ int rockchip_drm_dma_attach_device(struct drm_device *drm_dev, - struct device *dev); - void rockchip_drm_dma_detach_device(struct drm_device *drm_dev, - struct device *dev); -+void rockchip_drm_dma_init_device(struct drm_device *drm_dev, -+ struct device *dev); - int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout); - - int rockchip_drm_endpoint_is_subdriver(struct device_node *ep); -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 3e8d9e2d1b67..4c38c53e9f65 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -2175,6 +2175,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data) - } - } - -+ rockchip_drm_dma_init_device(drm_dev, dev); -+ - return 0; - - err_disable_pm_runtime: diff --git a/patch/kernel/archive/station-p2-5.18/0320-RFC-v2-1-4-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch b/patch/kernel/archive/station-p2-5.18/0320-RFC-v2-1-4-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch deleted file mode 100755 index 6aa687e97..000000000 --- a/patch/kernel/archive/station-p2-5.18/0320-RFC-v2-1-4-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch +++ /dev/null @@ -1,63 +0,0 @@ -diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c -index 19f0035d4410..46dee0714382 100644 ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1522,11 +1522,11 @@ static void - mt7530_hw_vlan_add(struct mt7530_priv *priv, - struct mt7530_hw_vlan_entry *entry) - { -+ struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); - u8 new_members; - u32 val; - -- new_members = entry->old_members | BIT(entry->port) | -- BIT(MT7530_CPU_PORT); -+ new_members = entry->old_members | BIT(entry->port); - - /* Validate the entry with independent learning, create egress tag per - * VLAN and joining the port as one of the port members. -@@ -1537,22 +1537,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *priv, - - /* Decide whether adding tag or not for those outgoing packets from the - * port inside the VLAN. -- */ -- val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : -- MT7530_VLAN_EGRESS_TAG; -- mt7530_rmw(priv, MT7530_VAWD2, -- ETAG_CTRL_P_MASK(entry->port), -- ETAG_CTRL_P(entry->port, val)); -- -- /* CPU port is always taken as a tagged port for serving more than one -+ * CPU port is always taken as a tagged port for serving more than one - * VLANs across and also being applied with egress type stack mode for - * that VLAN tags would be appended after hardware special tag used as - * DSA tag. - */ -+ if (dsa_port_is_cpu(dp)) -+ val = MT7530_VLAN_EGRESS_STACK; -+ else if (entry->untagged) -+ val = MT7530_VLAN_EGRESS_UNTAG; -+ else -+ val = MT7530_VLAN_EGRESS_TAG; - mt7530_rmw(priv, MT7530_VAWD2, -- ETAG_CTRL_P_MASK(MT7530_CPU_PORT), -- ETAG_CTRL_P(MT7530_CPU_PORT, -- MT7530_VLAN_EGRESS_STACK)); -+ ETAG_CTRL_P_MASK(entry->port), -+ ETAG_CTRL_P(entry->port, val)); - } - - static void -@@ -1571,11 +1569,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *priv, - return; - } - -- /* If certain member apart from CPU port is still alive in the VLAN, -- * the entry would be kept valid. Otherwise, the entry is got to be -- * disabled. -- */ -- if (new_members && new_members != BIT(MT7530_CPU_PORT)) { -+ if (new_members) { - val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | - VLAN_VALID; - mt7530_write(priv, MT7530_VAWD1, val); diff --git a/patch/kernel/archive/station-p2-5.18/0330-RFC-v2-2-4-net-dsa-mt7530-rework-mt753-01-_setup.patch b/patch/kernel/archive/station-p2-5.18/0330-RFC-v2-2-4-net-dsa-mt7530-rework-mt753-01-_setup.patch deleted file mode 100755 index 310b39534..000000000 --- a/patch/kernel/archive/station-p2-5.18/0330-RFC-v2-2-4-net-dsa-mt7530-rework-mt753-01-_setup.patch +++ /dev/null @@ -1,61 +0,0 @@ -diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c -index 46dee0714382..144c29f8fefc 100644 ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2087,11 +2087,12 @@ static int - mt7530_setup(struct dsa_switch *ds) - { - struct mt7530_priv *priv = ds->priv; -+ struct device_node *dn = NULL; - struct device_node *phy_node; - struct device_node *mac_np; - struct mt7530_dummy_poll p; - phy_interface_t interface; -- struct device_node *dn; -+ struct dsa_port *cpu_dp; - u32 id, val; - int ret, i; - -@@ -2099,7 +2100,19 @@ mt7530_setup(struct dsa_switch *ds) - * controller also is the container for two GMACs nodes representing - * as two netdev instances. - */ -- dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; -+ dsa_switch_for_each_cpu_port(cpu_dp, ds) { -+ dn = cpu_dp->master->dev.of_node->parent; -+ /* It doesn't matter which CPU port is found first, -+ * their masters should share the same parent OF node -+ */ -+ break; -+ } -+ -+ if (!dn) { -+ dev_err(ds->dev, "parent OF node of DSA master not found"); -+ return -EINVAL; -+ } -+ - ds->assisted_learning_on_cpu_port = true; - ds->mtu_enforcement_ingress = true; - -@@ -2260,6 +2273,7 @@ mt7531_setup(struct dsa_switch *ds) - { - struct mt7530_priv *priv = ds->priv; - struct mt7530_dummy_poll p; -+ struct dsa_port *cpu_dp; - u32 val, id; - int ret, i; - -@@ -2332,8 +2346,11 @@ mt7531_setup(struct dsa_switch *ds) - CORE_PLL_GROUP4, val); - - /* BPDU to CPU port */ -- mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, -- BIT(MT7530_CPU_PORT)); -+ dsa_switch_for_each_cpu_port(cpu_dp, ds) { -+ mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, -+ BIT(cpu_dp->index)); -+ break; -+ } - mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); - diff --git a/patch/kernel/archive/station-p2-5.18/0340-RFC-v2-3-4-net-dsa-mt7530-get-cpu-port-via-dp--cpu_dp-instead-of-constant.patch b/patch/kernel/archive/station-p2-5.18/0340-RFC-v2-3-4-net-dsa-mt7530-get-cpu-port-via-dp--cpu_dp-instead-of-constant.patch deleted file mode 100755 index 07757164f..000000000 --- a/patch/kernel/archive/station-p2-5.18/0340-RFC-v2-3-4-net-dsa-mt7530-get-cpu-port-via-dp--cpu_dp-instead-of-constant.patch +++ /dev/null @@ -1,100 +0,0 @@ -diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c -index 144c29f8fefc..8bf27937e577 100644 ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1033,6 +1033,7 @@ static int - mt7530_port_enable(struct dsa_switch *ds, int port, - struct phy_device *phy) - { -+ struct dsa_port *dp = dsa_to_port(ds, port); - struct mt7530_priv *priv = ds->priv; - - mutex_lock(&priv->reg_mutex); -@@ -1041,7 +1042,11 @@ mt7530_port_enable(struct dsa_switch *ds, int port, - * restore the port matrix if the port is the member of a certain - * bridge. - */ -- priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); -+ if (dsa_port_is_user(dp)) { -+ struct dsa_port *cpu_dp = dp->cpu_dp; -+ -+ priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); -+ } - priv->ports[port].enable = true; - mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, - priv->ports[port].pm); -@@ -1190,7 +1195,8 @@ mt7530_port_bridge_join(struct dsa_switch *ds, int port, - struct netlink_ext_ack *extack) - { - struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; -- u32 port_bitmap = BIT(MT7530_CPU_PORT); -+ struct dsa_port *cpu_dp = dp->cpu_dp; -+ u32 port_bitmap = BIT(cpu_dp->index); - struct mt7530_priv *priv = ds->priv; - - mutex_lock(&priv->reg_mutex); -@@ -1267,9 +1273,12 @@ mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) - * the CPU port get out of VLAN filtering mode. - */ - if (all_user_ports_removed) { -- mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), -+ struct dsa_port *dp = dsa_to_port(ds, port); -+ struct dsa_port *cpu_dp = dp->cpu_dp; -+ -+ mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), - PCR_MATRIX(dsa_user_ports(priv->ds))); -- mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG -+ mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG - | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); - } - } -@@ -1307,6 +1316,7 @@ mt7530_port_bridge_leave(struct dsa_switch *ds, int port, - struct dsa_bridge bridge) - { - struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; -+ struct dsa_port *cpu_dp = dp->cpu_dp; - struct mt7530_priv *priv = ds->priv; - - mutex_lock(&priv->reg_mutex); -@@ -1335,8 +1345,8 @@ mt7530_port_bridge_leave(struct dsa_switch *ds, int port, - */ - if (priv->ports[port].enable) - mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, -- PCR_MATRIX(BIT(MT7530_CPU_PORT))); -- priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); -+ PCR_MATRIX(BIT(cpu_dp->index))); -+ priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); - - /* When a port is removed from the bridge, the port would be set up - * back to the default as is at initial boot which is a VLAN-unaware -@@ -1503,6 +1513,9 @@ static int - mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, - struct netlink_ext_ack *extack) - { -+ struct dsa_port *dp = dsa_to_port(ds, port); -+ struct dsa_port *cpu_dp = dp->cpu_dp; -+ - if (vlan_filtering) { - /* The port is being kept as VLAN-unaware port when bridge is - * set up with vlan_filtering not being set, Otherwise, the -@@ -1510,7 +1523,7 @@ mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, - * for becoming a VLAN-aware port. - */ - mt7530_port_set_vlan_aware(ds, port); -- mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); -+ mt7530_port_set_vlan_aware(ds, cpu_dp->index); - } else { - mt7530_port_set_vlan_unaware(ds, port); - } -diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h -index 91508e2feef9..5895bcfc0f7d 100644 ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -8,7 +8,6 @@ - - #define MT7530_NUM_PORTS 7 - #define MT7530_NUM_PHYS 5 --#define MT7530_CPU_PORT 6 - #define MT7530_NUM_FDB_RECORDS 2048 - #define MT7530_ALL_MEMBERS 0xff - diff --git a/patch/kernel/archive/station-p2-5.18/0350-1-3-arm64-dts-rockchip-set-display-regulators-to-always-on-on-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.18/0350-1-3-arm64-dts-rockchip-set-display-regulators-to-always-on-on-BPI-R2-Pro.patch deleted file mode 100755 index 93c8a564a..000000000 --- a/patch/kernel/archive/station-p2-5.18/0350-1-3-arm64-dts-rockchip-set-display-regulators-to-always-on-on-BPI-R2-Pro.patch +++ /dev/null @@ -1,28 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -index 2700fb18a3bc..0950f9659bb4 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -225,6 +225,7 @@ regulator-state-mem { - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; -+ regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; -@@ -274,6 +275,7 @@ regulator-state-mem { - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; -+ regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - -@@ -369,6 +371,7 @@ regulator-state-mem { - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; -+ regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - diff --git a/patch/kernel/archive/station-p2-5.18/0360-2-3-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.18/0360-2-3-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2-Pro.patch deleted file mode 100755 index 93393df8c..000000000 --- a/patch/kernel/archive/station-p2-5.18/0360-2-3-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2-Pro.patch +++ /dev/null @@ -1,76 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -index 0950f9659bb4..cc3591251bab 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include "rk3568.dtsi" - - / { -@@ -54,6 +55,17 @@ dc_12v: dc-12v { - regulator-max-microvolt = <12000000>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; -@@ -184,6 +196,24 @@ &gmac1m1_rgmii_clk - status = "okay"; - }; - -+&hdmi { -+ avdd-0v9-supply = <&vdda0v9_image>; -+ avdd-1v8-supply = <&vcca1v8_image>; -+ status = "okay"; -+}; -+ -+&hdmi_in { -+ hdmi_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -600,3 +630,20 @@ &usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; - }; -+ -+&vop { -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0 { -+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; diff --git a/patch/kernel/archive/station-p2-5.18/0370-3-3-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.18/0370-3-3-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch deleted file mode 100755 index f9ee28f41..000000000 --- a/patch/kernel/archive/station-p2-5.18/0370-3-3-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch +++ /dev/null @@ -1,25 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -index cc3591251bab..10f68d054f76 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts -@@ -196,6 +196,11 @@ &gmac1m1_rgmii_clk - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ - &hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; -@@ -566,6 +571,8 @@ &spi3 { - }; - - &tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; - status = "okay"; - }; - diff --git a/patch/kernel/archive/station-p2-5.18/0380-RFC-v3-1-5-dt-bindings-phy-rockchip-add-PCIe-v3-phy.patch b/patch/kernel/archive/station-p2-5.18/0380-RFC-v3-1-5-dt-bindings-phy-rockchip-add-PCIe-v3-phy.patch deleted file mode 100755 index d07f52cb0..000000000 --- a/patch/kernel/archive/station-p2-5.18/0380-RFC-v3-1-5-dt-bindings-phy-rockchip-add-PCIe-v3-phy.patch +++ /dev/null @@ -1,88 +0,0 @@ -diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml -new file mode 100644 -index 000000000000..ac82f551bbfb ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml -@@ -0,0 +1,82 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip PCIe v3 phy -+ -+maintainers: -+ - Heiko Stuebner -+ -+properties: -+ compatible: -+ enum: -+ - rockchip,rk3568-pcie3-phy -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 3 -+ maxItems: 3 -+ -+ clock-names: -+ items: -+ - const: refclk_m -+ - const: refclk_n -+ - const: pclk -+ -+ minItems: 3 -+ -+ lane-map: -+ description: which lanes (by position) should be mapped to which -+ controller (value). 0 means lane unused, higher value means used. -+ (controller-number +1 ) -+ $ref: /schemas/types.yaml#/definitions/uint32-array -+ minItems: 2 -+ maxItems: 16 -+ items: -+ minimum: 0 -+ maximum: 16 -+ -+ "#phy-cells": -+ const: 0 -+ -+ resets: -+ maxItems: 1 -+ -+ reset-names: -+ const: phy -+ -+ rockchip,phy-grf: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: phandle to the syscon managing the phy "general register files" -+ -+ rockchip,pipe-grf: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: phandle to the syscon managing the pipe "general register files" -+ -+required: -+ - compatible -+ - reg -+ - rockchip,phy-grf -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ pcie30phy: phy@fe8c0000 { -+ compatible = "rockchip,rk3568-pcie3-phy"; -+ reg = <0x0 0xfe8c0000 0x0 0x20000>; -+ #phy-cells = <0>; -+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, -+ <&pmucru CLK_PCIE30PHY_REF_N>, -+ <&cru PCLK_PCIE30PHY>; -+ clock-names = "refclk_m", "refclk_n", "pclk"; -+ resets = <&cru SRST_PCIE30PHY>; -+ reset-names = "phy"; -+ rockchip,phy-grf = <&pcie30_phy_grf>; -+ }; diff --git a/patch/kernel/archive/station-p2-5.18/0390-RFC-v3-2-5-dt-bindings-soc-grf-add-pcie30--phy-pipe--grf.patch b/patch/kernel/archive/station-p2-5.18/0390-RFC-v3-2-5-dt-bindings-soc-grf-add-pcie30--phy-pipe--grf.patch deleted file mode 100755 index 30455e97a..000000000 --- a/patch/kernel/archive/station-p2-5.18/0390-RFC-v3-2-5-dt-bindings-soc-grf-add-pcie30--phy-pipe--grf.patch +++ /dev/null @@ -1,15 +0,0 @@ -diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -index 3be3cfd52f7b..a854e1f10d63 100644 ---- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -@@ -16,7 +16,10 @@ properties: - - enum: - - rockchip,rk3288-sgrf - - rockchip,rk3566-pipe-grf -+ - rockchip,rk3568-pcie3-phy-grf - - rockchip,rk3568-usb2phy-grf -+ - rockchip,rk3588-pcie3-phy-grf -+ - rockchip,rk3588-pcie3-pipe-grf - - rockchip,rv1108-usbgrf - - const: syscon - - items: diff --git a/patch/kernel/archive/station-p2-5.18/0400-RFC-v3-3-5-phy-rockchip-Support-PCIe-v3.patch b/patch/kernel/archive/station-p2-5.18/0400-RFC-v3-3-5-phy-rockchip-Support-PCIe-v3.patch deleted file mode 100755 index 49fc47506..000000000 --- a/patch/kernel/archive/station-p2-5.18/0400-RFC-v3-3-5-phy-rockchip-Support-PCIe-v3.patch +++ /dev/null @@ -1,372 +0,0 @@ -diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig -index 9022e395c056..94360fc96a6f 100644 ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE - help - Enable this to support the Rockchip PCIe PHY. - -+config PHY_ROCKCHIP_SNPS_PCIE3 -+ tristate "Rockchip Snps PCIe3 PHY Driver" -+ depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST -+ depends on HAS_IOMEM -+ select GENERIC_PHY -+ select MFD_SYSCON -+ help -+ Enable this to support the Rockchip snps PCIe3 PHY. -+ - config PHY_ROCKCHIP_TYPEC - tristate "Rockchip TYPEC PHY Driver" - depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) -diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile -index a5041efb5b8f..7eab129230d1 100644 ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o - obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o -+obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o -diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -new file mode 100644 -index 000000000000..9d8fadff8a04 ---- /dev/null -+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -0,0 +1,317 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip PCIE3.0 phy driver -+ * -+ * Copyright (C) 2020 Rockchip Electronics Co., Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Register for RK3568 */ -+#define GRF_PCIE30PHY_CON1 0x4 -+#define GRF_PCIE30PHY_CON6 0x18 -+#define GRF_PCIE30PHY_CON9 0x24 -+#define GRF_PCIE30PHY_STATUS0 0x80 -+#define SRAM_INIT_DONE(reg) (reg & BIT(14)) -+ -+#define RK3568_BIFURCATION_LANE_0_1 BIT(0) -+ -+/* Register for RK3588 */ -+#define PHP_GRF_PCIESEL_CON 0x100 -+#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 -+#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 -+#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 -+#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) -+ -+#define RK3588_BIFURCATION_LANE_0_1 BIT(0) -+#define RK3588_BIFURCATION_LANE_2_3 BIT(1) -+#define RK3588_LANE_AGGREGATION BIT(2) -+ -+struct rockchip_p3phy_ops; -+ -+struct rockchip_p3phy_priv { -+ const struct rockchip_p3phy_ops *ops; -+ void __iomem *mmio; -+ /* mode: RC, EP */ -+ int mode; -+ /* pcie30_phymode: Aggregation, Bifurcation */ -+ int pcie30_phymode; -+ struct regmap *phy_grf; -+ struct regmap *pipe_grf; -+ struct reset_control *p30phy; -+ struct phy *phy; -+ struct clk_bulk_data *clks; -+ int num_clks; -+ int num_lanes; -+ u8 lanes[4]; -+}; -+ -+struct rockchip_p3phy_ops { -+ int (*phy_init)(struct rockchip_p3phy_priv *priv); -+}; -+ -+static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) -+{ -+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); -+ -+ /* Actually We don't care EP/RC mode, but just record it */ -+ switch (submode) { -+ case PHY_MODE_PCIE_RC: -+ priv->mode = PHY_MODE_PCIE_RC; -+ break; -+ case PHY_MODE_PCIE_EP: -+ priv->mode = PHY_MODE_PCIE_EP; -+ break; -+ default: -+ dev_err(&phy->dev, "%s, invalid mode\n", __func__); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) -+{ -+ struct phy *phy = priv->phy; -+ bool bifurcation = false; -+ int ret; -+ u32 reg; -+ -+ /* Deassert PCIe PMA output clamp mode */ -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31)); -+ -+ for (int i = 0; i < priv->num_lanes; i++) { -+ dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); -+ if (priv->lanes[i] > 1) -+ bifurcation = true; -+ } -+ -+ /* Set bifurcation if needed, and it doesn't care RC/EP */ -+ if (bifurcation) { -+ dev_info(&phy->dev, "bifurcation enabled\n"); -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, -+ (0xf << 16) | RK3568_BIFURCATION_LANE_0_1); -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, -+ BIT(15) | BIT(31)); -+ } else { -+ dev_info(&phy->dev, "bifurcation disabled\n"); -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, -+ (0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1); -+ } -+ -+ reset_control_deassert(priv->p30phy); -+ -+ ret = regmap_read_poll_timeout(priv->phy_grf, -+ GRF_PCIE30PHY_STATUS0, -+ reg, SRAM_INIT_DONE(reg), -+ 0, 500); -+ if (ret) -+ dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", -+ __func__, reg); -+ return ret; -+} -+ -+static const struct rockchip_p3phy_ops rk3568_ops = { -+ .phy_init = rockchip_p3phy_rk3568_init, -+}; -+ -+static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) -+{ -+ u32 reg = 0; -+ u8 mode = 0; -+ int ret; -+ -+ /* Deassert PCIe PMA output clamp mode */ -+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); -+ -+ /* Set bifurcation if needed */ -+ for (int i = 0; i < priv->num_lanes; i++) { -+ if (!priv->lanes[i]) -+ mode |= (BIT(i) << 3); -+ -+ if (priv->lanes[i] > 1) -+ mode |= (BIT(i) >> 1); -+ } -+ -+ if (!mode) -+ reg = RK3588_LANE_AGGREGATION; -+ else { -+ if (mode & (BIT(0) | BIT(1))) -+ reg |= RK3588_BIFURCATION_LANE_0_1; -+ -+ if (mode & (BIT(2) | BIT(3))) -+ reg |= RK3588_BIFURCATION_LANE_2_3; -+ } -+ -+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); -+ -+ /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ -+ if (!IS_ERR(priv->pipe_grf)) { -+ reg = (mode & (BIT(6) | BIT(7))) >> 6; -+ if (reg) -+ regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, -+ (reg << 16) | reg); -+ } -+ -+ reset_control_deassert(priv->p30phy); -+ -+ ret = regmap_read_poll_timeout(priv->phy_grf, -+ RK3588_PCIE3PHY_GRF_PHY0_STATUS1, -+ reg, RK3588_SRAM_INIT_DONE(reg), -+ 0, 500); -+ ret |= regmap_read_poll_timeout(priv->phy_grf, -+ RK3588_PCIE3PHY_GRF_PHY1_STATUS1, -+ reg, RK3588_SRAM_INIT_DONE(reg), -+ 0, 500); -+ if (ret) -+ pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", -+ __func__, reg); -+ return ret; -+} -+ -+static const struct rockchip_p3phy_ops rk3588_ops = { -+ .phy_init = rockchip_p3phy_rk3588_init, -+}; -+ -+static int rochchip_p3phy_init(struct phy *phy) -+{ -+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); -+ int ret; -+ -+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); -+ if (ret) { -+ pr_err("failed to enable PCIe bulk clks %d\n", ret); -+ return ret; -+ } -+ -+ reset_control_assert(priv->p30phy); -+ udelay(1); -+ -+ if (priv->ops->phy_init) { -+ ret = priv->ops->phy_init(priv); -+ if (ret) -+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks); -+ } -+ -+ return ret; -+} -+ -+static int rochchip_p3phy_exit(struct phy *phy) -+{ -+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); -+ -+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks); -+ reset_control_assert(priv->p30phy); -+ return 0; -+} -+ -+static const struct phy_ops rochchip_p3phy_ops = { -+ .init = rochchip_p3phy_init, -+ .exit = rochchip_p3phy_exit, -+ .set_mode = rockchip_p3phy_set_mode, -+ .owner = THIS_MODULE, -+}; -+ -+static int rockchip_p3phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct rockchip_p3phy_priv *priv; -+ struct device_node *np = dev->of_node; -+ struct resource *res; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ priv->mmio = devm_ioremap_resource(dev, res); -+ if (IS_ERR(priv->mmio)) { -+ ret = PTR_ERR(priv->mmio); -+ return ret; -+ } -+ -+ priv->ops = of_device_get_match_data(&pdev->dev); -+ if (!priv->ops) { -+ dev_err(&pdev->dev, "no of match data provided\n"); -+ return -EINVAL; -+ } -+ -+ priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); -+ if (IS_ERR(priv->phy_grf)) { -+ dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); -+ return PTR_ERR(priv->phy_grf); -+ } -+ -+ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "rockchip,pipe-grf"); -+ if (IS_ERR(priv->pipe_grf)) -+ dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); -+ -+ priv->num_lanes = of_property_read_variable_u8_array(dev->of_node, "lane-map", -+ priv->lanes, 2, -+ ARRAY_SIZE(priv->lanes)); -+ -+ /* if no lane-map assume aggregation */ -+ if (priv->num_lanes == -EINVAL) { -+ dev_dbg(dev, "no lane-map property found\n"); -+ priv->num_lanes = 1; -+ priv->lanes[0] = 1; -+ } else if (priv->num_lanes < 0) { -+ dev_err(dev, "failed to read lane-map property %d\n", priv->num_lanes); -+ return priv->num_lanes; -+ } -+ -+ priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); -+ if (IS_ERR(priv->phy)) { -+ dev_err(dev, "failed to create combphy\n"); -+ return PTR_ERR(priv->phy); -+ } -+ -+ priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); -+ if (IS_ERR(priv->p30phy)) { -+ return dev_err_probe(dev, PTR_ERR(priv->p30phy), -+ "failed to get phy reset control\n"); -+ } -+ if (!priv->p30phy) -+ dev_info(dev, "no phy reset control specified\n"); -+ -+ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); -+ if (priv->num_clks < 1) -+ return -ENODEV; -+ -+ dev_set_drvdata(dev, priv); -+ phy_set_drvdata(priv->phy, priv); -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id rockchip_p3phy_of_match[] = { -+ { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops }, -+ { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match); -+ -+static struct platform_driver rockchip_p3phy_driver = { -+ .probe = rockchip_p3phy_probe, -+ .driver = { -+ .name = "rockchip-snps-pcie3-phy", -+ .of_match_table = rockchip_p3phy_of_match, -+ }, -+}; -+module_platform_driver(rockchip_p3phy_driver); -+MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver"); -+MODULE_LICENSE("GPL"); -diff --git a/include/linux/phy/pcie.h b/include/linux/phy/pcie.h -new file mode 100644 -index 000000000000..93c997f520fe ---- /dev/null -+++ b/include/linux/phy/pcie.h -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ */ -+#ifndef __PHY_PCIE_H -+#define __PHY_PCIE_H -+ -+#define PHY_MODE_PCIE_RC 20 -+#define PHY_MODE_PCIE_EP 21 -+#define PHY_MODE_PCIE_BIFURCATION 22 -+ -+#endif diff --git a/patch/kernel/archive/station-p2-5.18/0410-RFC-v3-4-5-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch b/patch/kernel/archive/station-p2-5.18/0410-RFC-v3-4-5-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch deleted file mode 100755 index 32999f14a..000000000 --- a/patch/kernel/archive/station-p2-5.18/0410-RFC-v3-4-5-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch +++ /dev/null @@ -1,133 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -index 5eafddf62edc..6dbe73c9cddf 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { - reg = <0x0 0xfe190200 0x0 0x20>; - }; - -+ pcie30_phy_grf: syscon@fdcb8000 { -+ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; -+ reg = <0x0 0xfdcb8000 0x0 0x10000>; -+ }; -+ -+ pcie30phy: phy@fe8c0000 { -+ compatible = "rockchip,rk3568-pcie3-phy"; -+ reg = <0x0 0xfe8c0000 0x0 0x20000>; -+ #phy-cells = <0>; -+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, -+ <&cru PCLK_PCIE30PHY>; -+ clock-names = "refclk_m", "refclk_n", "pclk"; -+ resets = <&cru SRST_PCIE30PHY>; -+ reset-names = "phy"; -+ rockchip,phy-grf = <&pcie30_phy_grf>; -+ status = "disabled"; -+ }; -+ -+ pcie3x1: pcie@fe270000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, -+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, -+ <&cru CLK_PCIE30X1_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, -+ <0 0 0 2 &pcie3x1_intc 1>, -+ <0 0 0 3 &pcie3x1_intc 2>, -+ <0 0 0 4 &pcie3x1_intc 3>; -+ linux,pci-domain = <1>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x1000 0x1000>; -+ num-lanes = <1>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0400000 0x0 0x00400000>, -+ <0x0 0xfe270000 0x0 0x00010000>, -+ <0x3 0x40000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x01000000 0x3 0x41000000 0x0 0x00100000>, -+ <0x02000000 0x0 0x02000000 0x3 0x41100000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X1_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane1 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x1_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ -+ pcie3x2: pcie@fe280000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, -+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, -+ <&cru CLK_PCIE30X2_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, -+ <0 0 0 2 &pcie3x2_intc 1>, -+ <0 0 0 3 &pcie3x2_intc 2>, -+ <0 0 0 4 &pcie3x2_intc 3>; -+ linux,pci-domain = <2>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <3>; -+ msi-map = <0x0 &gic 0x2000 0x1000>; -+ num-lanes = <2>; -+ phys = <&pcie30phy>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0800000 0x0 0x00400000>, -+ <0x0 0xfe280000 0x0 0x00010000>, -+ <0x3 0x80000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x01000000 0x3 0x81000000 0x0 0x00100000>, -+ <0x02000000 0x0 0x02000000 0x3 0x81100000 0x0 0x3ef00000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE30X2_POWERUP>; -+ reset-names = "pipe"; -+ /* bifurcation; lane0 when using 1+1 */ -+ status = "disabled"; -+ -+ pcie3x2_intc: legacy-interrupt-controller { -+ interrupt-controller; -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ }; -+ - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; diff --git a/patch/kernel/archive/station-p2-5.18/0440-v91-pcie-dw-rockchip.patch b/patch/kernel/archive/station-p2-5.18/0440-v91-pcie-dw-rockchip.patch deleted file mode 100644 index 49b73a940..000000000 --- a/patch/kernel/archive/station-p2-5.18/0440-v91-pcie-dw-rockchip.patch +++ /dev/null @@ -1,137 +0,0 @@ ---- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c -+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c -@@ -10,9 +10,12 @@ - - #include - #include -+#include -+#include - #include - #include - #include -+#include - #include - #include - #include -@@ -36,10 +39,12 @@ - #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) - #define PCIE_L0S_ENTRY 0x11 - #define PCIE_CLIENT_GENERAL_CONTROL 0x0 -+#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c - #define PCIE_CLIENT_GENERAL_DEBUG 0x104 --#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 -+#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 - #define PCIE_CLIENT_LTSSM_STATUS 0x300 --#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) -+#define PCIE_LEGACY_INT_ENABLE GENMASK(7, 0) -+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) - #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) - - struct rockchip_pcie { -@@ -51,6 +56,7 @@ - struct reset_control *rst; - struct gpio_desc *rst_gpio; - struct regulator *vpcie3v3; -+ struct irq_domain *irq_domain; - }; - - static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, -@@ -63,6 +69,68 @@ - u32 val, u32 reg) - { - writel_relaxed(val, rockchip->apb_base + reg); -+} -+ -+static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) -+{ -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); -+ struct device *dev = rockchip->pci.dev; -+ u32 reg; -+ u32 hwirq; -+ u32 virq; -+ -+ chained_irq_enter(chip, desc); -+ -+ reg = rockchip_pcie_readl_apb(rockchip, 0x8); -+ -+ while (reg) { -+ hwirq = ffs(reg) - 1; -+ reg &= ~BIT(hwirq); -+ -+ virq = irq_find_mapping(rockchip->irq_domain, hwirq); -+ if (virq) -+ generic_handle_irq(virq); -+ else -+ dev_err(dev, "unexpected IRQ, INT%d\n", hwirq); -+ } -+ -+ chained_irq_exit(chip, desc); -+} -+ -+static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, -+ irq_hw_number_t hwirq) -+{ -+ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); -+ irq_set_chip_data(irq, domain->host_data); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops intx_domain_ops = { -+ .map = rockchip_pcie_intx_map, -+}; -+ -+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) -+{ -+ struct device *dev = rockchip->pci.dev; -+ struct device_node *intc; -+ -+ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"); -+ if (!intc) { -+ dev_err(dev, "missing child interrupt-controller node\n"); -+ return -EINVAL; -+ } -+ -+ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, -+ &intx_domain_ops, rockchip); -+ of_node_put(intc); -+ if (!rockchip->irq_domain) { -+ dev_err(dev, "failed to get a INTx IRQ domain\n"); -+ return -EINVAL; -+ } -+ -+ return 0; - } - - static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) -@@ -111,9 +179,27 @@ - { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); -- u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); -+ struct device *dev = rockchip->pci.dev; -+ int irq, ret; -+ u32 val; -+ -+ irq = of_irq_get_byname(dev->of_node, "legacy"); -+ if (irq < 0) -+ return irq; -+ -+ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, rockchip); -+ -+ ret = rockchip_pcie_init_irq_domain(rockchip); -+ if (ret < 0) -+ dev_err(dev, "failed to init irq domain\n"); -+ -+ /* enable legacy interrupts */ -+ val = HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); -+ val &= ~PCIE_LEGACY_INT_ENABLE; -+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); - - /* LTSSM enable control mode */ -+ val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); - - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, - diff --git a/patch/kernel/archive/station-p2-5.18/0490-v95-rk3566-quartz64-a.patch b/patch/kernel/archive/station-p2-5.18/0490-v95-rk3566-quartz64-a.patch deleted file mode 100644 index fd1afa015..000000000 --- a/patch/kernel/archive/station-p2-5.18/0490-v95-rk3566-quartz64-a.patch +++ /dev/null @@ -1,478 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts -@@ -19,6 +19,24 @@ - - chosen: chosen { - stdout-path = "serial2:1500000n8"; -+ }; -+ -+ battery_cell: battery-cell { -+ compatible = "simple-battery"; -+ charge-full-design-microamp-hours = <2500000>; -+ charge-term-current-microamp = <300000>; -+ constant-charge-current-max-microamp = <2000000>; -+ constant-charge-voltage-max-microvolt = <4200000>; -+ factory-internal-resistance-micro-ohms = <180000>; -+ voltage-max-design-microvolt = <4106000>; -+ voltage-min-design-microvolt = <3625000>; -+ -+ ocv-capacity-celsius = <20>; -+ ocv-capacity-table-0 = <4106000 100>, <4071000 95>, <4018000 90>, <3975000 85>, -+ <3946000 80>, <3908000 75>, <3877000 70>, <3853000 65>, -+ <3834000 60>, <3816000 55>, <3802000 50>, <3788000 45>, -+ <3774000 40>, <3760000 35>, <3748000 30>, <3735000 25>, -+ <3718000 20>, <3697000 15>, <3685000 10>, <3625000 0>; - }; - - gmac1_clkin: external-gmac1-clock { -@@ -33,6 +51,8 @@ - gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 4500 1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fan_en_h>; - #cooling-cells = <2>; - }; - -@@ -173,6 +193,28 @@ - vin-supply = <&dcdc_boost>; - }; - -+ vcc3v3_pcie_p: vcc3v3_pcie_p { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_enable_h>; -+ regulator-name = "vcc3v3_pcie_p"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3>; -+ }; -+ -+ vcc5v0_usb20_otg: vcc5v0_usb20_otg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc5v0_usb20_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&dcdc_boost>; -+ }; -+ - vcc3v3_sd: vcc3v3_sd { - compatible = "regulator-fixed"; - enable-active-low; -@@ -197,6 +239,19 @@ - vin-supply = <&vbus>; - }; - -+ vcc_sys_ebc: vcc_sys_ebc { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_sys_ebc_h>; -+ regulator-boot-on; -+ regulator-name = "vcc_sys_ebc"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sys>; -+ }; -+ - /* sourced from vcc_sys, sdio module operates internally at 3.3v */ - vcc_wl: vcc_wl { - compatible = "regulator-fixed"; -@@ -207,9 +262,30 @@ - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; -+ -+ vcc_lcd_en: vcc_lcd_en { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_lcd_en_h>; -+ regulator-name = "vcc_lcd_en"; -+ vin-supply = <&vcc_3v3>; -+ }; -+ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm14 0 1000000 0>; -+ brightness-levels = <0 4 8 16 32 64 128 255>; -+ default-brightness-level = <6>; -+ }; - }; - - &combphy1 { -+ status = "okay"; -+}; -+ -+&combphy2 { - status = "okay"; - }; - -@@ -244,6 +320,39 @@ - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -+}; -+ -+&ebc { -+ panel,width = <1872>; -+ panel,height = <1404>; -+ panel,vir_width = <1872>; -+ panel,vir_height = <1404>; -+ panel,sdck = <33300000>; -+ panel,lsl = <11>; -+ panel,lbl = <8>; -+ panel,ldl = <234>; -+ panel,lel = <23>; -+ panel,gdck-sta = <10>; -+ panel,lgonl = <215>; -+ panel,fsl = <1>; -+ panel,fbl = <4>; -+ panel,fdl = <1404>; -+ panel,fel = <12>; -+ panel,mirror = <1>; -+ panel,panel_16bit = <1>; -+ panel,panel_color = <0>; -+ panel,width-mm = <157>; -+ panel,height-mm = <210>; -+ -+ io-channels = <&ebc_pmic 0>; -+ panel-supply = <&v3p3>; -+ vcom-supply = <&vcom>; -+ vdrive-supply = <&vdrive>; -+ status = "disabled"; -+}; -+ -+&eink { -+ status = "disabled"; - }; - - &gmac1 { -@@ -292,6 +401,10 @@ - }; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &i2c0 { - status = "okay"; - -@@ -511,6 +624,58 @@ - }; - }; - }; -+ -+ rk817_battery: battery { -+ monitored-battery = <&battery_cell>; -+ rockchip,resistor-sense-micro-ohms = <10000>; -+ rockchip,sleep-enter-current-microamp = <300000>; -+ rockchip,sleep-filter-current-microamp = <100000>; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ ebc_pmic: pmic@68 { -+ compatible = "ti,tps65185"; -+ reg = <0x68>; -+ interrupt-parent = <&gpio4>; -+ interrupts = ; -+ #io-channel-cells = <1>; -+ pinctrl-0 = <&ebc_pmic_pins>; -+ pinctrl-names = "default"; -+ powerup-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; -+ pwr_good-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; -+ vcom_ctrl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; -+ vin-supply = <&vcc_sys_ebc>; -+ vin3p3-supply = <&vcc_sys_ebc>; -+ wakeup-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; -+ ti,up-sequence = <1>, <0>, <2>, <3>; -+ ti,up-delay-ms = <3>, <3>, <3>, <3>; -+ ti,down-sequence = <2>, <3>, <1>, <0>; -+ ti,down-delay-ms = <3>, <6>, <6>, <6>; -+ -+ regulators { -+ v3p3: v3p3 { -+ regulator-name = "v3p3"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ vcom: vcom { -+ regulator-name = "vcom"; -+ regulator-min-microvolt = <1450000>; -+ regulator-max-microvolt = <1450000>; -+ }; -+ -+ vdrive: vdrive { -+ regulator-name = "vdrive"; -+ regulator-min-microvolt = <15000000>; -+ regulator-max-microvolt = <15000000>; -+ }; -+ }; - }; - }; - -@@ -519,6 +684,10 @@ - * pin 5 - i2c3_scl_m0, pullup to vcc_3v3 - */ - &i2c3 { -+ status = "okay"; -+}; -+ -+&i2s0_8ch { - status = "okay"; - }; - -@@ -539,6 +708,14 @@ - }; - }; - -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ vpcie3v3-supply = <&vcc3v3_pcie_p>; -+}; -+ - &pinctrl { - bt { - bt_enable_h: bt-enable-h { -@@ -554,6 +731,27 @@ - }; - }; - -+ ebc_pmic { -+ ebc_pmic_pins: ebc-pmic-pins { -+ rockchip,pins = /* wakeup */ -+ <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, -+ /* int */ -+ <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, -+ /* pwr_good */ -+ <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, -+ /* pwrup */ -+ <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, -+ /* vcom_ctrl */ -+ <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ fan { -+ fan_en_h: fan-en-h { -+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - leds { - work_led_enable_h: work-led-enable-h { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -564,6 +762,16 @@ - }; - }; - -+ pcie { -+ pcie_enable_h: pcie-enable-h { -+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -@@ -582,9 +790,21 @@ - }; - }; - -+ vcc_lcd_en { -+ vcc_lcd_en_h: vcc-lcd-en-h { -+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - vcc_sd { - vcc_sd_h: vcc-sd-h { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ vcc_sys_ebc { -+ vcc_sys_ebc_h: vcc-sys-ebc-h { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - }; -@@ -602,10 +822,23 @@ - status = "okay"; - }; - -+/* sata1 is muxed with the usb3 port */ -+&sata1 { -+ status = "disabled"; -+}; -+ -+/* sata2 is muxed with the pcie2 slot*/ -+&sata2 { -+ target-supply = <&vcc3v3_pcie_p>; -+ status = "disabled"; -+}; -+ - &sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -@@ -618,6 +851,7 @@ - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -@@ -627,6 +861,7 @@ - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; -+ disable-wp; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; -@@ -636,6 +871,21 @@ - vmmc-supply = <&vcc_wl>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -+}; -+ -+&sfc { -+ pinctrl-0 = <&fspi_pins>; -+ pinctrl-names = "default"; -+ rockchip,sfc-no-dma; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <50000000>; -+ spi-rx-bus-width = <1>; -+ spi-tx-bus-width = <1>; -+ }; - }; - - /* spdif is exposed on con40 pin 18 */ -@@ -739,6 +989,29 @@ - status = "okay"; - }; - -+&usb_host0_xhci { -+ status = "okay"; -+}; -+ -+/* usb3 controller is muxed with sata1 */ -+&usb_host1_xhci { -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb20_host>; -+ status = "okay"; -+}; -+ -+&usb2phy0_otg { -+ phy-supply = <&vcc5v0_usb20_otg>; -+ status = "okay"; -+}; -+ - &usb2phy1 { - status = "okay"; - }; -@@ -769,3 +1042,65 @@ - remote-endpoint = <&hdmi_in_vp0>; - }; - }; -+ -+ -+&dsi0 { -+ status = "disabled"; -+ clock-master; -+ -+ mipi_panel: panel@0 { -+ compatible = "feiyang,fy07024di26a30d"; -+ reg = <0>; -+ backlight = <&backlight>; -+ width-mm = <154>; -+ height-mm = <86>; -+ rotation = <0>; -+ dvdd-supply = <&vcc_lcd_en>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ panel_in_dsi: endpoint { -+ remote-endpoint = <&dsi_out_panel>; -+ }; -+ }; -+ }; -+ }; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ dsi_out_panel: endpoint { -+ remote-endpoint = <&panel_in_dsi>; -+ }; -+ }; -+ }; -+}; -+ -+&dsi0_in { -+ dsi0_in_vp1: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&vp1_out_dsi0>; -+ }; -+}; -+ -+&video_phy0 { -+ status = "okay"; -+}; -+ -+&vp1 { -+ vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { -+ reg = ; -+ remote-endpoint = <&dsi0_in_vp1>; -+ }; -+}; -+ -+&pwm14 { -+ status = "okay"; -+ pinctrl-0 = <&pwm14m1_pins>; -+ pinctrl-names = "default"; -+}; - diff --git a/patch/kernel/archive/station-p2-5.18/0520-v96-rk356x.patch b/patch/kernel/archive/station-p2-5.18/0520-v96-rk356x.patch deleted file mode 100644 index b94f70767..000000000 --- a/patch/kernel/archive/station-p2-5.18/0520-v96-rk356x.patch +++ /dev/null @@ -1,422 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -183,6 +183,22 @@ - }; - }; - -+ hdmi_sound: hdmi-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "HDMI"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ status = "disabled"; -+ -+ simple-audio-card,codec { -+ sound-dai = <&hdmi>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s0_8ch>; -+ }; -+ }; -+ - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = , -@@ -233,6 +249,36 @@ - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; -+ }; -+ -+ sata1: sata@fc400000 { -+ compatible = "snps,dwc-ahci"; -+ reg = <0 0xfc400000 0 0x1000>; -+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, -+ <&cru CLK_SATA1_RXOOB>; -+ clock-names = "sata", "pmalive", "rxoob"; -+ interrupts = ; -+ interrupt-names = "hostc"; -+ phys = <&combphy1 PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ ports-implemented = <0x1>; -+ power-domains = <&power RK3568_PD_PIPE>; -+ status = "disabled"; -+ }; -+ -+ sata2: sata@fc800000 { -+ compatible = "snps,dwc-ahci"; -+ reg = <0 0xfc800000 0 0x1000>; -+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, -+ <&cru CLK_SATA2_RXOOB>; -+ clock-names = "sata", "pmalive", "rxoob"; -+ interrupts = ; -+ interrupt-names = "hostc"; -+ phys = <&combphy2 PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ ports-implemented = <0x1>; -+ power-domains = <&power RK3568_PD_PIPE>; -+ status = "disabled"; - }; - - usb_host0_xhci: usb@fcc00000 { -@@ -275,10 +321,17 @@ - <0x0 0xfd460000 0 0x80000>; /* GICR */ - interrupts = ; - interrupt-controller; -+ ranges; - #interrupt-cells = <3>; -- mbi-alias = <0x0 0xfd410000>; -- mbi-ranges = <296 24>; -- msi-controller; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ its: interrupt-controller@fd440000 { -+ compatible = "arm,gic-v3-its"; -+ reg = <0x0 0xfd440000 0x0 0x20000>; -+ msi-controller; -+ #msi-cells = <1>; -+ }; - }; - - usb_host0_ehci: usb@fd800000 { -@@ -401,6 +454,7 @@ - clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 0>, <&dmac0 1>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; -@@ -566,6 +620,28 @@ - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - power-domains = <&power RK3568_PD_VPU>; - #iommu-cells = <0>; -+ }; -+ -+ ebc: ebc@fdec0000 { -+ compatible = "rockchip,rk3568-ebc-tcon"; -+ reg = <0x0 0xfdec0000 0x0 0x5000>; -+ interrupts = ; -+ clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>; -+ clock-names = "hclk", "dclk"; -+ pinctrl-0 = <&ebc_pins>; -+ pinctrl-names = "default"; -+ power-domains = <&power RK3568_PD_RGA>; -+ rockchip,grf = <&grf>; -+ status = "disabled"; -+ }; -+ -+ eink: eink@fdf00000 { -+ compatible = "rockchip,rk3568-eink-tcon"; -+ reg = <0x0 0xfdf00000 0x0 0x74>; -+ clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>; -+ clock-names = "pclk", "hclk"; -+ interrupts = ; -+ status = "disabled"; - }; - - sdmmc2: mmc@fe000000 { -@@ -675,6 +751,62 @@ - status = "disabled"; - }; - -+ dsi0: dsi@fe060000 { -+ compatible = "rockchip,rk3568-mipi-dsi"; -+ reg = <0x0 0xfe060000 0x0 0x10000>; -+ interrupts = ; -+ clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&video_phy0>; -+ clock-names = "pclk", "hclk", "hs_clk"; -+ phys = <&video_phy0>; -+ phy-names = "dphy"; -+ power-domains = <&power RK3568_PD_VO>; -+ resets = <&cru SRST_P_DSITX_0>; -+ reset-names = "apb"; -+ rockchip,grf = <&grf>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dsi0_in: port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ -+ dsi1: dsi@fe070000 { -+ compatible = "rockchip,rk3568-mipi-dsi"; -+ reg = <0x0 0xfe070000 0x0 0x10000>; -+ interrupts = ; -+ clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&video_phy1>; -+ clock-names = "pclk", "hclk", "hs_clk"; -+ phys = <&video_phy1>; -+ phy-names = "dphy"; -+ power-domains = <&power RK3568_PD_VO>; -+ resets = <&cru SRST_P_DSITX_1>; -+ reset-names = "apb"; -+ rockchip,grf = <&grf>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dsi1_in: port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ - hdmi: hdmi@fe0a0000 { - compatible = "rockchip,rk3568-dw-hdmi"; - reg = <0x0 0xfe0a0000 0x0 0x20000>; -@@ -825,6 +957,61 @@ - qos_vop_m1: qos@fe1a8100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8100 0x0 0x20>; -+ }; -+ -+ pcie2x1: pcie@fe260000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, -+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, -+ <&cru CLK_PCIE20_AUX_NDFT>; -+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, -+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, -+ <&cru CLK_PCIE20_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msi", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc 0>, -+ <0 0 0 2 &pcie_intc 1>, -+ <0 0 0 3 &pcie_intc 2>, -+ <0 0 0 4 &pcie_intc 3>; -+ linux,pci-domain = <0>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <2>; -+ msi-map = <0x0 &its 0x0 0x1000>; -+ num-lanes = <1>; -+ phys = <&combphy2 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0000000 0x0 0x00400000>, -+ <0x0 0xfe260000 0x0 0x00010000>, -+ <0x3 0x00000000 0x0 0x01000000>; -+ ranges = <0x01000000 0x0 0x01000000 0x3 0x01000000 0x0 0x00100000 -+ 0x02000000 0x0 0x02000000 0x3 0x02000000 0x0 0x3e000000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE20_POWERUP>; -+ reset-names = "pipe"; -+ status = "disabled"; -+ -+ pcie_intc: legacy-interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ - }; - - sdmmc0: mmc@fe2b0000 { -@@ -855,6 +1042,19 @@ - status = "disabled"; - }; - -+ sfc: spi@fe300000 { -+ compatible = "rockchip,sfc"; -+ reg = <0x0 0xfe300000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; -+ clock-names = "clk_sfc", "hclk_sfc"; -+ assigned-clocks = <&cru SCLK_SFC>; -+ assigned-clock-rates = <100000000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - sdhci: mmc@fe310000 { - compatible = "rockchip,rk3568-dwcmshc"; - reg = <0x0 0xfe310000 0x0 0x10000>; -@@ -878,6 +1078,23 @@ - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdifm0_tx>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s0_8ch: i2s@fe400000 { -+ compatible = "rockchip,rk3568-i2s-tdm"; -+ reg = <0x0 0xfe400000 0x0 0x1000>; -+ interrupts = ; -+ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; -+ assigned-clock-rates = <1188000000>, <1188000000>; -+ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ dmas = <&dmac1 0>; -+ dma-names = "tx"; -+ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; -+ reset-names = "tx-m", "rx-m"; -+ rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; -@@ -907,6 +1124,25 @@ - status = "disabled"; - }; - -+ i2s2_2ch: i2s@fe420000 { -+ compatible = "rockchip,rk3568-i2s-tdm"; -+ reg = <0x0 0xfe420000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ dmas = <&dmac1 4>, <&dmac1 5>; -+ dma-names = "tx", "rx"; -+ rockchip,cru = <&cru>; -+ rockchip,grf = <&grf>; -+ pinctrl-0 = <&i2s2m0_sclktx -+ &i2s2m0_lrcktx -+ &i2s2m0_sdi -+ &i2s2m0_sdo>; -+ pinctrl-names = "default"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ - i2s3_2ch: i2s@fe430000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe430000 0x0 0x1000>; -@@ -1106,6 +1342,7 @@ - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 2>, <&dmac0 3>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart1m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; -@@ -1120,6 +1357,7 @@ - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 4>, <&dmac0 5>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart2m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; -@@ -1134,6 +1372,7 @@ - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart3m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; -@@ -1148,6 +1387,7 @@ - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart4m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; -@@ -1162,6 +1402,7 @@ - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart5m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; -@@ -1176,6 +1417,7 @@ - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart6m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; -@@ -1190,6 +1432,7 @@ - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart7m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; -@@ -1204,6 +1447,7 @@ - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart8m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; -@@ -1218,10 +1462,41 @@ - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 18>, <&dmac0 19>; -+ dma-names = "tx", "rx"; - pinctrl-0 = <&uart9m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ video_phy0: video-phy@fe850000 { -+ compatible = "rockchip,rk3568-video-phy"; -+ reg = <0x0 0xfe850000 0x0 0x10000>, -+ <0x0 0xfe060000 0x0 0x10000>; -+ clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, -+ <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>; -+ clock-names = "ref", "pclk_phy", "pclk_host"; -+ #clock-cells = <0>; -+ resets = <&cru SRST_P_MIPIDSIPHY0>; -+ reset-names = "rst"; -+ power-domains = <&power RK3568_PD_VO>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ video_phy1: video-phy@fe860000 { -+ compatible = "rockchip,rk3568-video-phy"; -+ reg = <0x0 0xfe860000 0x0 0x10000>, -+ <0x0 0xfe070000 0x0 0x10000>; -+ clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, -+ <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>; -+ clock-names = "ref", "pclk_phy", "pclk_host"; -+ #clock-cells = <0>; -+ resets = <&cru SRST_P_MIPIDSIPHY1>; -+ reset-names = "rst"; -+ power-domains = <&power RK3568_PD_VO>; -+ #phy-cells = <0>; - status = "disabled"; - }; - - diff --git a/patch/kernel/archive/station-p2-5.18/0530-v96-rk3568.patch b/patch/kernel/archive/station-p2-5.18/0530-v96-rk3568.patch deleted file mode 100644 index 9f9e12c69..000000000 --- a/patch/kernel/archive/station-p2-5.18/0530-v96-rk3568.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -7,6 +7,21 @@ - - / { - compatible = "rockchip,rk3568"; -+ -+ sata0: sata@fc000000 { -+ compatible = "snps,dwc-ahci"; -+ reg = <0 0xfc000000 0 0x1000>; -+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, -+ <&cru CLK_SATA0_RXOOB>; -+ clock-names = "sata", "pmalive", "rxoob"; -+ interrupts = ; -+ interrupt-names = "hostc"; -+ phys = <&combphy0 PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ ports-implemented = <0x1>; -+ power-domains = <&power RK3568_PD_PIPE>; -+ status = "disabled"; -+ }; - - pipe_phy_grf0: syscon@fdc70000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; diff --git a/patch/kernel/archive/station-p2-5.18/0540-usb-dwc3-fix.patch b/patch/kernel/archive/station-p2-5.18/0540-usb-dwc3-fix.patch deleted file mode 100755 index d4d441742..000000000 --- a/patch/kernel/archive/station-p2-5.18/0540-usb-dwc3-fix.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/usb/dwc3/core.c -+++ b/drivers/usb/dwc3/core.c -@@ -274,8 +274,7 @@ - - reg = dwc3_readl(dwc->regs, DWC3_DCTL); - reg |= DWC3_DCTL_CSFTRST; -- reg &= ~DWC3_DCTL_RUN_STOP; -- dwc3_gadget_dctl_write_safe(dwc, reg); -+ dwc3_writel(dwc->regs, DWC3_DCTL, reg); - - /* - * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit -@@ -1378,10 +1377,10 @@ - u8 lpm_nyet_threshold; - u8 tx_de_emphasis; - u8 hird_threshold; -- u8 rx_thr_num_pkt_prd = 0; -- u8 rx_max_burst_prd = 0; -- u8 tx_thr_num_pkt_prd = 0; -- u8 tx_max_burst_prd = 0; -+ u8 rx_thr_num_pkt_prd; -+ u8 rx_max_burst_prd; -+ u8 tx_thr_num_pkt_prd; -+ u8 tx_max_burst_prd; - u8 tx_fifo_resize_max_num; - const char *usb_psy_name; - int ret; - diff --git a/patch/kernel/archive/station-p2-5.18/0690-general-disable-mtu-validation.patch b/patch/kernel/archive/station-p2-5.18/0690-general-disable-mtu-validation.patch deleted file mode 100644 index 17134c1fa..000000000 --- a/patch/kernel/archive/station-p2-5.18/0690-general-disable-mtu-validation.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bf80eaa34a1b9f503a779b13deed2fda642a1e87 Mon Sep 17 00:00:00 2001 -From: Igor Pecovnik -Date: Wed, 21 Jul 2021 20:59:39 +0000 -Subject: [PATCH] Disable MTU validation - -This patch reverts: https://github.com/torvalds/linux/commit/eaf4fac478077d4ed57cbca2c044c4b58a96bd98 - -It works around following issues: - - no way to change MTU (tx_fifo_size is reported as 0 for Rockchip's dwmac) - -Signed-off-by: Piotr Szczepanik -Signed-off-by: Igor Pecovnik ---- - drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 12 ------------ - 1 file changed, 12 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index 91cd5073d..b409a7598 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5435,14 +5435,8 @@ static void stmmac_set_rx_mode(struct net_device *dev) - static int stmmac_change_mtu(struct net_device *dev, int new_mtu) - { - struct stmmac_priv *priv = netdev_priv(dev); -- int txfifosz = priv->plat->tx_fifo_size; - const int mtu = new_mtu; - -- if (txfifosz == 0) -- txfifosz = priv->dma_cap.tx_fifo_size; -- -- txfifosz /= priv->plat->tx_queues_to_use; -- - if (netif_running(dev)) { - netdev_err(priv->dev, "must be stopped to change its MTU\n"); - return -EBUSY; -@@ -5453,12 +5447,6 @@ static int stmmac_change_mtu(struct net_device *dev, int new_mtu) - return -EINVAL; - } - -- new_mtu = STMMAC_ALIGN(new_mtu); -- -- /* If condition true, FIFO is too small or MTU too large */ -- if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) -- return -EINVAL; -- - dev->mtu = mtu; - - netdev_update_features(dev); --- -Created with Armbian build tools https://github.com/armbian/build - diff --git a/patch/kernel/archive/media-5.19/010-v2-1-5-arm64-dts-rockchip-set-display-regulators-to-always-on-on-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.19/010-v2-1-5-arm64-dts-rockchip-set-display-regulators-to-always-on-on-BPI-R2-Pro.patch similarity index 100% rename from patch/kernel/archive/media-5.19/010-v2-1-5-arm64-dts-rockchip-set-display-regulators-to-always-on-on-BPI-R2-Pro.patch rename to patch/kernel/archive/station-p2-5.19/010-v2-1-5-arm64-dts-rockchip-set-display-regulators-to-always-on-on-BPI-R2-Pro.patch diff --git a/patch/kernel/archive/media-5.19/020-v2-2-5-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.19/020-v2-2-5-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2-Pro.patch similarity index 100% rename from patch/kernel/archive/media-5.19/020-v2-2-5-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2-Pro.patch rename to patch/kernel/archive/station-p2-5.19/020-v2-2-5-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2-Pro.patch diff --git a/patch/kernel/archive/media-5.19/030-v2-3-5-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.19/030-v2-3-5-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch similarity index 100% rename from patch/kernel/archive/media-5.19/030-v2-3-5-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch rename to patch/kernel/archive/station-p2-5.19/030-v2-3-5-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch diff --git a/patch/kernel/archive/media-5.19/040-v2-4-5-arm64-dts-rockchip-configure-thermal-shutdown-for-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.19/040-v2-4-5-arm64-dts-rockchip-configure-thermal-shutdown-for-BPI-R2-Pro.patch similarity index 100% rename from patch/kernel/archive/media-5.19/040-v2-4-5-arm64-dts-rockchip-configure-thermal-shutdown-for-BPI-R2-Pro.patch rename to patch/kernel/archive/station-p2-5.19/040-v2-4-5-arm64-dts-rockchip-configure-thermal-shutdown-for-BPI-R2-Pro.patch diff --git a/patch/kernel/archive/media-5.19/050-v2-5-5-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch b/patch/kernel/archive/station-p2-5.19/050-v2-5-5-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch similarity index 100% rename from patch/kernel/archive/media-5.19/050-v2-5-5-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch rename to patch/kernel/archive/station-p2-5.19/050-v2-5-5-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch diff --git a/patch/kernel/archive/media-5.19/060-v91-dw_hdmi-rockchip.patch b/patch/kernel/archive/station-p2-5.19/060-v91-dw_hdmi-rockchip.patch similarity index 100% rename from patch/kernel/archive/media-5.19/060-v91-dw_hdmi-rockchip.patch rename to patch/kernel/archive/station-p2-5.19/060-v91-dw_hdmi-rockchip.patch diff --git a/patch/kernel/archive/station-p2-5.18/0420-v91-i2s-mclk.patch b/patch/kernel/archive/station-p2-5.19/070-v91-i2s-mclk.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0420-v91-i2s-mclk.patch rename to patch/kernel/archive/station-p2-5.19/070-v91-i2s-mclk.patch diff --git a/patch/kernel/archive/station-p2-5.18/0430-v91-irq-gic-v3-its.patch b/patch/kernel/archive/station-p2-5.19/080--v91-irq-gic-v3-its.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0430-v91-irq-gic-v3-its.patch rename to patch/kernel/archive/station-p2-5.19/080--v91-irq-gic-v3-its.patch diff --git a/patch/kernel/archive/station-p2-5.18/0460-v91-rk356x-vpu.patch b/patch/kernel/archive/station-p2-5.19/090-v91-rk356x-vpu.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0460-v91-rk356x-vpu.patch rename to patch/kernel/archive/station-p2-5.19/090-v91-rk356x-vpu.patch diff --git a/patch/kernel/archive/station-p2-5.18/0980-builddeb.patch b/patch/kernel/archive/station-p2-5.19/0980-builddeb.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0980-builddeb.patch rename to patch/kernel/archive/station-p2-5.19/0980-builddeb.patch diff --git a/patch/kernel/archive/station-p2-5.18/0981-mkdebian.patch b/patch/kernel/archive/station-p2-5.19/0981-mkdebian.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0981-mkdebian.patch rename to patch/kernel/archive/station-p2-5.19/0981-mkdebian.patch diff --git a/patch/kernel/archive/station-p2-5.18/0470-v95-make.patch b/patch/kernel/archive/station-p2-5.19/100-v95-make.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0470-v95-make.patch rename to patch/kernel/archive/station-p2-5.19/100-v95-make.patch diff --git a/patch/kernel/archive/media-5.19/110-v95-rk3566-firefly-roc-pc.patch b/patch/kernel/archive/station-p2-5.19/110-v95-rk3566-firefly-roc-pc.patch similarity index 100% rename from patch/kernel/archive/media-5.19/110-v95-rk3566-firefly-roc-pc.patch rename to patch/kernel/archive/station-p2-5.19/110-v95-rk3566-firefly-roc-pc.patch diff --git a/patch/kernel/archive/media-5.19/120-v95-rk3566-quartz64-a.patch b/patch/kernel/archive/station-p2-5.19/120-v95-rk3566-quartz64-a.patch similarity index 100% rename from patch/kernel/archive/media-5.19/120-v95-rk3566-quartz64-a.patch rename to patch/kernel/archive/station-p2-5.19/120-v95-rk3566-quartz64-a.patch diff --git a/patch/kernel/archive/media-5.19/130-v95-rk3568-bpi-r2-pro.patch b/patch/kernel/archive/station-p2-5.19/130-v95-rk3568-bpi-r2-pro.patch similarity index 100% rename from patch/kernel/archive/media-5.19/130-v95-rk3568-bpi-r2-pro.patch rename to patch/kernel/archive/station-p2-5.19/130-v95-rk3568-bpi-r2-pro.patch diff --git a/patch/kernel/archive/media-5.19/140-v95-rk3568-firefly-roc-pc.patch b/patch/kernel/archive/station-p2-5.19/140-v95-rk3568-firefly-roc-pc.patch similarity index 100% rename from patch/kernel/archive/media-5.19/140-v95-rk3568-firefly-roc-pc.patch rename to patch/kernel/archive/station-p2-5.19/140-v95-rk3568-firefly-roc-pc.patch diff --git a/patch/kernel/archive/media-5.19/150-v96-rk356x.patch b/patch/kernel/archive/station-p2-5.19/150-v96-rk356x.patch similarity index 100% rename from patch/kernel/archive/media-5.19/150-v96-rk356x.patch rename to patch/kernel/archive/station-p2-5.19/150-v96-rk356x.patch diff --git a/patch/kernel/archive/media-5.19/160-v96-rk3566.patch b/patch/kernel/archive/station-p2-5.19/160-v96-rk3566.patch similarity index 100% rename from patch/kernel/archive/media-5.19/160-v96-rk3566.patch rename to patch/kernel/archive/station-p2-5.19/160-v96-rk3566.patch diff --git a/patch/kernel/archive/media-5.19/170-v96-rk3568.patch b/patch/kernel/archive/station-p2-5.19/170-v96-rk3568.patch similarity index 100% rename from patch/kernel/archive/media-5.19/170-v96-rk3568.patch rename to patch/kernel/archive/station-p2-5.19/170-v96-rk3568.patch diff --git a/patch/kernel/archive/media-5.19/180-v97-rk356x.patch b/patch/kernel/archive/station-p2-5.19/180-v97-rk356x.patch similarity index 100% rename from patch/kernel/archive/media-5.19/180-v97-rk356x.patch rename to patch/kernel/archive/station-p2-5.19/180-v97-rk356x.patch diff --git a/patch/kernel/archive/media-5.19/181-v97-rk356x.patch b/patch/kernel/archive/station-p2-5.19/181-v97-rk356x.patch similarity index 100% rename from patch/kernel/archive/media-5.19/181-v97-rk356x.patch rename to patch/kernel/archive/station-p2-5.19/181-v97-rk356x.patch diff --git a/patch/kernel/archive/media-5.19/190-v97-rk3568.patch b/patch/kernel/archive/station-p2-5.19/190-v97-rk3568.patch similarity index 100% rename from patch/kernel/archive/media-5.19/190-v97-rk3568.patch rename to patch/kernel/archive/station-p2-5.19/190-v97-rk3568.patch diff --git a/patch/kernel/archive/media-5.19/200-usb-dwc3-fix.patch b/patch/kernel/archive/station-p2-5.19/200-usb-dwc3-fix.patch similarity index 100% rename from patch/kernel/archive/media-5.19/200-usb-dwc3-fix.patch rename to patch/kernel/archive/station-p2-5.19/200-usb-dwc3-fix.patch diff --git a/patch/kernel/archive/station-p2-5.18/0550-linux-0002-rockchip-from-list.patch b/patch/kernel/archive/station-p2-5.19/210-linux-0002-rockchip-from-list.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0550-linux-0002-rockchip-from-list.patch rename to patch/kernel/archive/station-p2-5.19/210-linux-0002-rockchip-from-list.patch diff --git a/patch/kernel/archive/station-p2-5.18/0560-linux-90100-add-clock.patch b/patch/kernel/archive/station-p2-5.19/220-linux-90100-add-clock.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0560-linux-90100-add-clock.patch rename to patch/kernel/archive/station-p2-5.19/220-linux-90100-add-clock.patch diff --git a/patch/kernel/archive/station-p2-5.18/0570-linux-90101-add-rt5651-konf.patch b/patch/kernel/archive/station-p2-5.19/230-linux-90101-add-rt5651-konf.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0570-linux-90101-add-rt5651-konf.patch rename to patch/kernel/archive/station-p2-5.19/230-linux-90101-add-rt5651-konf.patch diff --git a/patch/kernel/archive/station-p2-5.18/0580-linux-90102-rt5651.patch b/patch/kernel/archive/station-p2-5.19/240-linux-90102-rt5651.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0580-linux-90102-rt5651.patch rename to patch/kernel/archive/station-p2-5.19/240-linux-90102-rt5651.patch diff --git a/patch/kernel/archive/station-p2-5.18/0590-linux-90103-nanopc-t4-5651.patch b/patch/kernel/archive/station-p2-5.19/250-linux-90103-nanopc-t4-5651.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0590-linux-90103-nanopc-t4-5651.patch rename to patch/kernel/archive/station-p2-5.19/250-linux-90103-nanopc-t4-5651.patch diff --git a/patch/kernel/archive/station-p2-5.18/0600-linux-90104-all-codec.patch b/patch/kernel/archive/station-p2-5.19/260-linux-90104-all-codec.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0600-linux-90104-all-codec.patch rename to patch/kernel/archive/station-p2-5.19/260-linux-90104-all-codec.patch diff --git a/patch/kernel/archive/station-p2-5.18/0610-linux-90117-add-rk3399-roc-pc-plus-sound.patch b/patch/kernel/archive/station-p2-5.19/270-linux-90117-add-rk3399-roc-pc-plus-sound.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0610-linux-90117-add-rk3399-roc-pc-plus-sound.patch rename to patch/kernel/archive/station-p2-5.19/270-linux-90117-add-rk3399-roc-pc-plus-sound.patch diff --git a/patch/kernel/archive/station-p2-5.18/0620-linux-90200-rk3328-roc-pc-wifi-fix.patch b/patch/kernel/archive/station-p2-5.19/280-linux-90200-rk3328-roc-pc-wifi-fix.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0620-linux-90200-rk3328-roc-pc-wifi-fix.patch rename to patch/kernel/archive/station-p2-5.19/280-linux-90200-rk3328-roc-pc-wifi-fix.patch diff --git a/patch/kernel/archive/station-p2-5.18/0630-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch b/patch/kernel/archive/station-p2-5.19/290-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0630-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch rename to patch/kernel/archive/station-p2-5.19/290-Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch diff --git a/patch/kernel/archive/station-p2-5.18/0640-add-fusb30x-driver.patch b/patch/kernel/archive/station-p2-5.19/300-add-fusb30x-driver.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0640-add-fusb30x-driver.patch rename to patch/kernel/archive/station-p2-5.19/300-add-fusb30x-driver.patch diff --git a/patch/kernel/archive/station-p2-5.19/310-add-rk3328-usb3-phy-driver.patch b/patch/kernel/archive/station-p2-5.19/310-add-rk3328-usb3-phy-driver.patch new file mode 100644 index 000000000..1a74d6c25 --- /dev/null +++ b/patch/kernel/archive/station-p2-5.19/310-add-rk3328-usb3-phy-driver.patch @@ -0,0 +1,1456 @@ +Add the rockchip innosilicon usb3 phy driver, supporting devices such as the rk3328. +Pulled from: +https://github.com/FireflyTeam/kernel/blob/roc-rk3328-cc/drivers/phy/rockchip/phy-rockchip-inno-usb3.c + +Signed-off-by: Peter Geis +--- + drivers/phy/rockchip/Kconfig | 9 + + drivers/phy/rockchip/Makefile | 1 + + drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 1107 +++++++++++++++++ + 3 files changed, 1117 insertions(+) + create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c + +diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig +index c454c90cd99e..766407939d4a 100644 +--- a/drivers/phy/rockchip/Kconfig ++++ b/drivers/phy/rockchip/Kconfig +@@ -35,6 +35,15 @@ config PHY_ROCKCHIP_INNO_USB2 + help + Support for Rockchip USB2.0 PHY with Innosilicon IP block. + ++config PHY_ROCKCHIP_INNO_USB3 ++ tristate "Rockchip INNO USB 3.0 PHY Driver" ++ depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF ++ depends on USB_SUPPORT ++ select GENERIC_PHY ++ select USB_PHY ++ help ++ Support for Rockchip USB 3.0 PHY with Innosilicon IP block. ++ + config PHY_ROCKCHIP_PCIE + tristate "Rockchip PCIe PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST +diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile +index fd21cbaf40dd..d7b3d16c19ae 100644 +--- a/drivers/phy/rockchip/Makefile ++++ b/drivers/phy/rockchip/Makefile +@@ -3,6 +3,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o ++obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o + obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o + obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o + obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb3.c b/drivers/phy/rockchip/phy-rockchip-inno-usb3.c +new file mode 100644 +index 000000000000..31fee8f3a705 +--- /dev/null ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb3.c +@@ -0,0 +1,1107 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Rockchip USB 3.0 PHY with Innosilicon IP block driver ++ * ++ * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define U3PHY_PORT_NUM 2 ++#define BIT_WRITEABLE_SHIFT 16 ++#define SCHEDULE_DELAY (60 * HZ) ++ ++#define U3PHY_APB_RST BIT(0) ++#define U3PHY_POR_RST BIT(1) ++#define U3PHY_MAC_RST BIT(2) ++ ++struct rockchip_u3phy; ++struct rockchip_u3phy_port; ++ ++enum rockchip_u3phy_type { ++ U3PHY_TYPE_PIPE, ++ U3PHY_TYPE_UTMI, ++}; ++ ++enum rockchip_u3phy_pipe_pwr { ++ PIPE_PWR_P0 = 0, ++ PIPE_PWR_P1 = 1, ++ PIPE_PWR_P2 = 2, ++ PIPE_PWR_P3 = 3, ++ PIPE_PWR_MAX = 4, ++}; ++ ++enum rockchip_u3phy_rest_req { ++ U3_POR_RSTN = 0, ++ U2_POR_RSTN = 1, ++ PIPE_MAC_RSTN = 2, ++ UTMI_MAC_RSTN = 3, ++ PIPE_APB_RSTN = 4, ++ UTMI_APB_RSTN = 5, ++ U3PHY_RESET_MAX = 6, ++}; ++ ++enum rockchip_u3phy_utmi_state { ++ PHY_UTMI_HS_ONLINE = 0, ++ PHY_UTMI_DISCONNECT = 1, ++ PHY_UTMI_CONNECT = 2, ++ PHY_UTMI_FS_LS_ONLINE = 4, ++}; ++ ++/* ++ * @rvalue: reset value ++ * @dvalue: desired value ++ */ ++struct u3phy_reg { ++ unsigned int offset; ++ unsigned int bitend; ++ unsigned int bitstart; ++ unsigned int rvalue; ++ unsigned int dvalue; ++}; ++ ++struct rockchip_u3phy_grfcfg { ++ struct u3phy_reg um_suspend; ++ struct u3phy_reg ls_det_en; ++ struct u3phy_reg ls_det_st; ++ struct u3phy_reg um_ls; ++ struct u3phy_reg um_hstdct; ++ struct u3phy_reg u2_only_ctrl; ++ struct u3phy_reg u3_disable; ++ struct u3phy_reg pp_pwr_st; ++ struct u3phy_reg pp_pwr_en[PIPE_PWR_MAX]; ++}; ++ ++/** ++ * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration. ++ * @u2_pre_emp: usb2-phy pre-emphasis tuning. ++ * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning. ++ * @u2_odt_tuning: usb2-phy odt 45ohm tuning. ++ */ ++struct rockchip_u3phy_apbcfg { ++ unsigned int u2_pre_emp; ++ unsigned int u2_pre_emp_sth; ++ unsigned int u2_odt_tuning; ++}; ++ ++struct rockchip_u3phy_cfg { ++ unsigned int reg; ++ const struct rockchip_u3phy_grfcfg grfcfg; ++ ++ int (*phy_pipe_power)(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ bool on); ++ int (*phy_tuning)(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ struct device_node *child_np); ++}; ++ ++struct rockchip_u3phy_port { ++ struct phy *phy; ++ void __iomem *base; ++ unsigned int index; ++ unsigned char type; ++ bool suspended; ++ bool refclk_25m_quirk; ++ struct mutex mutex; /* mutex for updating register */ ++ struct delayed_work um_sm_work; ++}; ++ ++struct rockchip_u3phy { ++ struct device *dev; ++ struct regmap *u3phy_grf; ++ struct regmap *grf; ++ int um_ls_irq; ++ struct clk **clks; ++ int num_clocks; ++ struct dentry *root; ++ struct gpio_desc *vbus_drv_gpio; ++ struct reset_control *rsts[U3PHY_RESET_MAX]; ++ struct rockchip_u3phy_apbcfg apbcfg; ++ const struct rockchip_u3phy_cfg *cfgs; ++ struct rockchip_u3phy_port ports[U3PHY_PORT_NUM]; ++ struct usb_phy usb_phy; ++}; ++ ++static inline int param_write(void __iomem *base, ++ const struct u3phy_reg *reg, bool desired) ++{ ++ unsigned int val, mask; ++ unsigned int tmp = desired ? reg->dvalue : reg->rvalue; ++ int ret = 0; ++ ++ mask = GENMASK(reg->bitend, reg->bitstart); ++ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); ++ ret = regmap_write(base, reg->offset, val); ++ ++ return ret; ++} ++ ++static inline bool param_exped(void __iomem *base, ++ const struct u3phy_reg *reg, ++ unsigned int value) ++{ ++ int ret; ++ unsigned int tmp, orig; ++ unsigned int mask = GENMASK(reg->bitend, reg->bitstart); ++ ++ ret = regmap_read(base, reg->offset, &orig); ++ if (ret) ++ return false; ++ ++ tmp = (orig & mask) >> reg->bitstart; ++ return tmp == value; ++} ++ ++static int rockchip_u3phy_usb2_only_show(struct seq_file *s, void *unused) ++{ ++ struct rockchip_u3phy *u3phy = s->private; ++ ++ if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) ++ dev_info(u3phy->dev, "u2\n"); ++ else ++ dev_info(u3phy->dev, "u3\n"); ++ ++ return 0; ++} ++ ++static int rockchip_u3phy_usb2_only_open(struct inode *inode, ++ struct file *file) ++{ ++ return single_open(file, rockchip_u3phy_usb2_only_show, ++ inode->i_private); ++} ++ ++static ssize_t rockchip_u3phy_usb2_only_write(struct file *file, ++ const char __user *ubuf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *s = file->private_data; ++ struct rockchip_u3phy *u3phy = s->private; ++ struct rockchip_u3phy_port *u3phy_port; ++ char buf[32]; ++ u8 index; ++ ++ if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) ++ return -EFAULT; ++ ++ if (!strncmp(buf, "u3", 2) && ++ param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) { ++ dev_info(u3phy->dev, "Set usb3.0 and usb2.0 mode successfully\n"); ++ ++ gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 0); ++ ++ param_write(u3phy->grf, ++ &u3phy->cfgs->grfcfg.u3_disable, false); ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.u2_only_ctrl, false); ++ ++ for (index = 0; index < U3PHY_PORT_NUM; index++) { ++ u3phy_port = &u3phy->ports[index]; ++ /* enable u3 rx termimation */ ++ if (u3phy_port->type == U3PHY_TYPE_PIPE) ++ writel(0x30, u3phy_port->base + 0xd8); ++ } ++ ++ atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); ++ ++ gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 1); ++ } else if (!strncmp(buf, "u2", 2) && ++ param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) { ++ dev_info(u3phy->dev, "Set usb2.0 only mode successfully\n"); ++ ++ gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 0); ++ ++ param_write(u3phy->grf, ++ &u3phy->cfgs->grfcfg.u3_disable, true); ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.u2_only_ctrl, true); ++ ++ for (index = 0; index < U3PHY_PORT_NUM; index++) { ++ u3phy_port = &u3phy->ports[index]; ++ /* disable u3 rx termimation */ ++ if (u3phy_port->type == U3PHY_TYPE_PIPE) ++ writel(0x20, u3phy_port->base + 0xd8); ++ } ++ ++ atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); ++ ++ gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 1); ++ } else { ++ dev_info(u3phy->dev, "Same or illegal mode\n"); ++ } ++ ++ return count; ++} ++ ++static const struct file_operations rockchip_u3phy_usb2_only_fops = { ++ .open = rockchip_u3phy_usb2_only_open, ++ .write = rockchip_u3phy_usb2_only_write, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++int rockchip_u3phy_debugfs_init(struct rockchip_u3phy *u3phy) ++{ ++ struct dentry *root; ++ struct dentry *file; ++ int ret; ++ ++ root = debugfs_create_dir(dev_name(u3phy->dev), NULL); ++ if (!root) { ++ ret = -ENOMEM; ++ goto err0; ++ } ++ ++ u3phy->root = root; ++ ++ file = debugfs_create_file("u3phy_mode", 0644, root, ++ u3phy, &rockchip_u3phy_usb2_only_fops); ++ if (!file) { ++ ret = -ENOMEM; ++ goto err1; ++ } ++ return 0; ++ ++err1: ++ debugfs_remove_recursive(root); ++err0: ++ return ret; ++} ++ ++static const char *get_rest_name(enum rockchip_u3phy_rest_req rst) ++{ ++ switch (rst) { ++ case U2_POR_RSTN: ++ return "u3phy-u2-por"; ++ case U3_POR_RSTN: ++ return "u3phy-u3-por"; ++ case PIPE_MAC_RSTN: ++ return "u3phy-pipe-mac"; ++ case UTMI_MAC_RSTN: ++ return "u3phy-utmi-mac"; ++ case UTMI_APB_RSTN: ++ return "u3phy-utmi-apb"; ++ case PIPE_APB_RSTN: ++ return "u3phy-pipe-apb"; ++ default: ++ return "invalid"; ++ } ++} ++ ++static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy, ++ unsigned int flag) ++{ ++ int rst; ++ ++ if (flag & U3PHY_APB_RST) { ++ dev_dbg(u3phy->dev, "deassert APB bus interface reset\n"); ++ for (rst = PIPE_APB_RSTN; rst <= UTMI_APB_RSTN; rst++) { ++ if (u3phy->rsts[rst]) ++ reset_control_deassert(u3phy->rsts[rst]); ++ } ++ } ++ ++ if (flag & U3PHY_POR_RST) { ++ usleep_range(12, 15); ++ dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n"); ++ for (rst = U3_POR_RSTN; rst <= U2_POR_RSTN; rst++) { ++ if (u3phy->rsts[rst]) ++ reset_control_deassert(u3phy->rsts[rst]); ++ } ++ } ++ ++ if (flag & U3PHY_MAC_RST) { ++ usleep_range(1200, 1500); ++ dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n"); ++ for (rst = PIPE_MAC_RSTN; rst <= UTMI_MAC_RSTN; rst++) ++ if (u3phy->rsts[rst]) ++ reset_control_deassert(u3phy->rsts[rst]); ++ } ++} ++ ++static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy) ++{ ++ int rst; ++ ++ dev_dbg(u3phy->dev, "assert u3phy reset\n"); ++ for (rst = 0; rst < U3PHY_RESET_MAX; rst++) ++ if (u3phy->rsts[rst]) ++ reset_control_assert(u3phy->rsts[rst]); ++} ++ ++static int rockchip_u3phy_clk_enable(struct rockchip_u3phy *u3phy) ++{ ++ int ret, clk; ++ ++ for (clk = 0; clk < u3phy->num_clocks && u3phy->clks[clk]; clk++) { ++ ret = clk_prepare_enable(u3phy->clks[clk]); ++ if (ret) ++ goto err_disable_clks; ++ } ++ return 0; ++ ++err_disable_clks: ++ while (--clk >= 0) ++ clk_disable_unprepare(u3phy->clks[clk]); ++ return ret; ++} ++ ++static void rockchip_u3phy_clk_disable(struct rockchip_u3phy *u3phy) ++{ ++ int clk; ++ ++ for (clk = u3phy->num_clocks - 1; clk >= 0; clk--) ++ if (u3phy->clks[clk]) ++ clk_disable_unprepare(u3phy->clks[clk]); ++} ++ ++static int rockchip_u3phy_init(struct phy *phy) ++{ ++ return 0; ++} ++ ++static int rockchip_u3phy_exit(struct phy *phy) ++{ ++ return 0; ++} ++ ++static int rockchip_u3phy_power_on(struct phy *phy) ++{ ++ struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy); ++ struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); ++ int ret; ++ ++ dev_info(&u3phy_port->phy->dev, "u3phy %s power on\n", ++ (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); ++ ++ if (!u3phy_port->suspended) ++ return 0; ++ ++ ret = rockchip_u3phy_clk_enable(u3phy); ++ if (ret) ++ return ret; ++ ++ if (u3phy_port->type == U3PHY_TYPE_UTMI) { ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.um_suspend, false); ++ } else { ++ /* current in p2 ? */ ++ if (param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2)) ++ goto done; ++ ++ if (u3phy->cfgs->phy_pipe_power) { ++ dev_dbg(u3phy->dev, "do pipe power up\n"); ++ u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true); ++ } ++ ++ /* exit to p0 */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); ++ usleep_range(90, 100); ++ ++ /* enter to p2 from p0 */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2], ++ false); ++ udelay(3); ++ } ++ ++done: ++ u3phy_port->suspended = false; ++ return 0; ++} ++ ++static int rockchip_u3phy_power_off(struct phy *phy) ++{ ++ struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy); ++ struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); ++ ++ dev_info(&u3phy_port->phy->dev, "u3phy %s power off\n", ++ (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); ++ ++ if (u3phy_port->suspended) ++ return 0; ++ ++ if (u3phy_port->type == U3PHY_TYPE_UTMI) { ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.um_suspend, true); ++ } else { ++ /* current in p3 ? */ ++ if (param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3)) ++ goto done; ++ ++ /* exit to p0 */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); ++ udelay(2); ++ ++ /* enter to p3 from p0 */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true); ++ udelay(6); ++ ++ if (u3phy->cfgs->phy_pipe_power) { ++ dev_dbg(u3phy->dev, "do pipe power down\n"); ++ u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false); ++ } ++ } ++ ++done: ++ rockchip_u3phy_clk_disable(u3phy); ++ u3phy_port->suspended = true; ++ return 0; ++} ++ ++static __maybe_unused ++struct phy *rockchip_u3phy_xlate(struct device *dev, ++ struct of_phandle_args *args) ++{ ++ struct rockchip_u3phy *u3phy = dev_get_drvdata(dev); ++ struct rockchip_u3phy_port *u3phy_port = NULL; ++ struct device_node *phy_np = args->np; ++ int index; ++ ++ if (args->args_count != 1) { ++ dev_err(dev, "invalid number of cells in 'phy' property\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ for (index = 0; index < U3PHY_PORT_NUM; index++) { ++ if (phy_np == u3phy->ports[index].phy->dev.of_node) { ++ u3phy_port = &u3phy->ports[index]; ++ break; ++ } ++ } ++ ++ if (!u3phy_port) { ++ dev_err(dev, "failed to find appropriate phy\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return u3phy_port->phy; ++} ++ ++static struct phy_ops rockchip_u3phy_ops = { ++ .init = rockchip_u3phy_init, ++ .exit = rockchip_u3phy_exit, ++ .power_on = rockchip_u3phy_power_on, ++ .power_off = rockchip_u3phy_power_off, ++ .owner = THIS_MODULE, ++}; ++ ++/* ++ * The function manage host-phy port state and suspend/resume phy port ++ * to save power automatically. ++ * ++ * we rely on utmi_linestate and utmi_hostdisconnect to identify whether ++ * devices is disconnect or not. Besides, we do not need care it is FS/LS ++ * disconnected or HS disconnected, actually, we just only need get the ++ * device is disconnected at last through rearm the delayed work, ++ * to suspend the phy port in _PHY_STATE_DISCONNECT_ case. ++ */ ++static void rockchip_u3phy_um_sm_work(struct work_struct *work) ++{ ++ struct rockchip_u3phy_port *u3phy_port = ++ container_of(work, struct rockchip_u3phy_port, um_sm_work.work); ++ struct rockchip_u3phy *u3phy = ++ dev_get_drvdata(u3phy_port->phy->dev.parent); ++ unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend - ++ u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1; ++ unsigned int ul, uhd, state; ++ unsigned int ul_mask, uhd_mask; ++ int ret; ++ ++ mutex_lock(&u3phy_port->mutex); ++ ++ ret = regmap_read(u3phy->u3phy_grf, ++ u3phy->cfgs->grfcfg.um_ls.offset, &ul); ++ if (ret < 0) ++ goto next_schedule; ++ ++ ret = regmap_read(u3phy->u3phy_grf, ++ u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd); ++ if (ret < 0) ++ goto next_schedule; ++ ++ uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend, ++ u3phy->cfgs->grfcfg.um_hstdct.bitstart); ++ ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend, ++ u3phy->cfgs->grfcfg.um_ls.bitstart); ++ ++ /* stitch on um_ls and um_hstdct as phy state */ ++ state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) | ++ (((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh); ++ ++ switch (state) { ++ case PHY_UTMI_HS_ONLINE: ++ dev_dbg(&u3phy_port->phy->dev, "HS online\n"); ++ break; ++ case PHY_UTMI_FS_LS_ONLINE: ++ /* ++ * For FS/LS device, the online state share with connect state ++ * from um_ls and um_hstdct register, so we distinguish ++ * them via suspended flag. ++ * ++ * Plus, there are two cases, one is D- Line pull-up, and D+ ++ * line pull-down, the state is 4; another is D+ line pull-up, ++ * and D- line pull-down, the state is 2. ++ */ ++ if (!u3phy_port->suspended) { ++ /* D- line pull-up, D+ line pull-down */ ++ dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); ++ break; ++ } ++ /* fall through */ ++ case PHY_UTMI_CONNECT: ++ if (u3phy_port->suspended) { ++ dev_dbg(&u3phy_port->phy->dev, "Connected\n"); ++ rockchip_u3phy_power_on(u3phy_port->phy); ++ u3phy_port->suspended = false; ++ } else { ++ /* D+ line pull-up, D- line pull-down */ ++ dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); ++ } ++ break; ++ case PHY_UTMI_DISCONNECT: ++ if (!u3phy_port->suspended) { ++ dev_dbg(&u3phy_port->phy->dev, "Disconnected\n"); ++ rockchip_u3phy_power_off(u3phy_port->phy); ++ u3phy_port->suspended = true; ++ } ++ ++ /* ++ * activate the linestate detection to get the next device ++ * plug-in irq. ++ */ ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.ls_det_st, true); ++ param_write(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.ls_det_en, true); ++ ++ /* ++ * we don't need to rearm the delayed work when the phy port ++ * is suspended. ++ */ ++ mutex_unlock(&u3phy_port->mutex); ++ return; ++ default: ++ dev_dbg(&u3phy_port->phy->dev, "unknown phy state\n"); ++ break; ++ } ++ ++next_schedule: ++ mutex_unlock(&u3phy_port->mutex); ++ schedule_delayed_work(&u3phy_port->um_sm_work, SCHEDULE_DELAY); ++} ++ ++static irqreturn_t rockchip_u3phy_um_ls_irq(int irq, void *data) ++{ ++ struct rockchip_u3phy_port *u3phy_port = data; ++ struct rockchip_u3phy *u3phy = ++ dev_get_drvdata(u3phy_port->phy->dev.parent); ++ ++ if (!param_exped(u3phy->u3phy_grf, ++ &u3phy->cfgs->grfcfg.ls_det_st, ++ u3phy->cfgs->grfcfg.ls_det_st.dvalue)) ++ return IRQ_NONE; ++ ++ dev_dbg(u3phy->dev, "utmi linestate interrupt\n"); ++ mutex_lock(&u3phy_port->mutex); ++ ++ /* disable linestate detect irq and clear its status */ ++ param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false); ++ param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true); ++ ++ mutex_unlock(&u3phy_port->mutex); ++ ++ /* ++ * In this case for host phy, a new device is plugged in, meanwhile, ++ * if the phy port is suspended, we need rearm the work to resume it ++ * and mange its states; otherwise, we just return irq handled. ++ */ ++ if (u3phy_port->suspended) { ++ dev_dbg(u3phy->dev, "schedule utmi sm work\n"); ++ rockchip_u3phy_um_sm_work(&u3phy_port->um_sm_work.work); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy, ++ struct platform_device *pdev) ++ ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ int ret, i, clk; ++ ++ u3phy->um_ls_irq = platform_get_irq_byname(pdev, "linestate"); ++ if (u3phy->um_ls_irq < 0) { ++ dev_err(dev, "get utmi linestate irq failed\n"); ++ return -ENXIO; ++ } ++ ++ u3phy->vbus_drv_gpio = devm_gpiod_get_optional(dev, "vbus-drv", ++ GPIOD_OUT_HIGH); ++ ++ if (!u3phy->vbus_drv_gpio) { ++ dev_warn(&pdev->dev, "vbus_drv is not assigned\n"); ++ } else if (IS_ERR(u3phy->vbus_drv_gpio)) { ++ dev_err(&pdev->dev, "failed to get vbus_drv\n"); ++ return PTR_ERR(u3phy->vbus_drv_gpio); ++ } ++ ++ u3phy->num_clocks = of_clk_get_parent_count(np); ++ if (u3phy->num_clocks == 0) ++ dev_warn(&pdev->dev, "no clks found in dt\n"); ++ ++ u3phy->clks = devm_kcalloc(dev, u3phy->num_clocks, ++ sizeof(struct clk *), GFP_KERNEL); ++ ++ for (clk = 0; clk < u3phy->num_clocks; clk++) { ++ u3phy->clks[clk] = of_clk_get(np, clk); ++ if (IS_ERR(u3phy->clks[clk])) { ++ ret = PTR_ERR(u3phy->clks[clk]); ++ if (ret == -EPROBE_DEFER) ++ goto err_put_clks; ++ dev_err(&pdev->dev, "failed to get clks, %i\n", ++ ret); ++ u3phy->clks[clk] = NULL; ++ break; ++ } ++ } ++ ++ for (i = 0; i < U3PHY_RESET_MAX; i++) { ++ u3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i)); ++ if (IS_ERR(u3phy->rsts[i])) { ++ dev_info(dev, "no %s reset control specified\n", ++ get_rest_name(i)); ++ u3phy->rsts[i] = NULL; ++ } ++ } ++ ++ return 0; ++ ++err_put_clks: ++ while (--clk >= 0) ++ clk_put(u3phy->clks[clk]); ++ return ret; ++} ++ ++static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ struct device_node *child_np) ++{ ++ struct resource res; ++ struct phy *phy; ++ int ret; ++ ++ dev_dbg(u3phy->dev, "u3phy port initialize\n"); ++ ++ mutex_init(&u3phy_port->mutex); ++ u3phy_port->suspended = true; /* initial status */ ++ ++ phy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops); ++ if (IS_ERR(phy)) { ++ dev_err(u3phy->dev, "failed to create phy\n"); ++ return PTR_ERR(phy); ++ } ++ ++ u3phy_port->phy = phy; ++ ++ ret = of_address_to_resource(child_np, 0, &res); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to get address resource(np-%s)\n", ++ child_np->name); ++ return ret; ++ } ++ ++ u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res); ++ if (IS_ERR(u3phy_port->base)) { ++ dev_err(u3phy->dev, "failed to remap phy regs\n"); ++ return PTR_ERR(u3phy_port->base); ++ } ++ ++ if (!of_node_cmp(child_np->name, "pipe")) { ++ u3phy_port->type = U3PHY_TYPE_PIPE; ++ u3phy_port->refclk_25m_quirk = ++ of_property_read_bool(child_np, ++ "rockchip,refclk-25m-quirk"); ++ } else { ++ u3phy_port->type = U3PHY_TYPE_UTMI; ++ INIT_DELAYED_WORK(&u3phy_port->um_sm_work, ++ rockchip_u3phy_um_sm_work); ++ ++ ret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq, ++ NULL, rockchip_u3phy_um_ls_irq, ++ IRQF_ONESHOT, "rockchip_u3phy", ++ u3phy_port); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to request utmi linestate irq handle\n"); ++ return ret; ++ } ++ } ++ ++ if (u3phy->cfgs->phy_tuning) { ++ dev_dbg(u3phy->dev, "do u3phy tuning\n"); ++ ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np); ++ if (ret) ++ return ret; ++ } ++ ++ phy_set_drvdata(u3phy_port->phy, u3phy_port); ++ return 0; ++} ++ ++static int rockchip_u3phy_on_init(struct usb_phy *usb_phy) ++{ ++ struct rockchip_u3phy *u3phy = ++ container_of(usb_phy, struct rockchip_u3phy, usb_phy); ++ ++ rockchip_u3phy_rest_deassert(u3phy, U3PHY_POR_RST | U3PHY_MAC_RST); ++ return 0; ++} ++ ++static void rockchip_u3phy_on_shutdown(struct usb_phy *usb_phy) ++{ ++ struct rockchip_u3phy *u3phy = ++ container_of(usb_phy, struct rockchip_u3phy, usb_phy); ++ int rst; ++ ++ for (rst = 0; rst < U3PHY_RESET_MAX; rst++) ++ if (u3phy->rsts[rst] && rst != UTMI_APB_RSTN && ++ rst != PIPE_APB_RSTN) ++ reset_control_assert(u3phy->rsts[rst]); ++ udelay(1); ++} ++ ++static int rockchip_u3phy_on_disconnect(struct usb_phy *usb_phy, ++ enum usb_device_speed speed) ++{ ++ struct rockchip_u3phy *u3phy = ++ container_of(usb_phy, struct rockchip_u3phy, usb_phy); ++ ++ dev_info(u3phy->dev, "%s device has disconnected\n", ++ (speed == USB_SPEED_SUPER) ? "U3" : "UW/U2/U1.1/U1"); ++ ++ if (speed == USB_SPEED_SUPER) ++ atomic_notifier_call_chain(&usb_phy->notifier, 0, NULL); ++ ++ return 0; ++} ++ ++static int rockchip_u3phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct device_node *child_np; ++ struct phy_provider *provider; ++ struct rockchip_u3phy *u3phy; ++ const struct rockchip_u3phy_cfg *phy_cfgs; ++ const struct of_device_id *match; ++ unsigned int reg[2]; ++ int index, ret; ++ ++ match = of_match_device(dev->driver->of_match_table, dev); ++ if (!match || !match->data) { ++ dev_err(dev, "phy-cfgs are not assigned!\n"); ++ return -EINVAL; ++ } ++ ++ u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL); ++ if (!u3phy) ++ return -ENOMEM; ++ ++ u3phy->u3phy_grf = ++ syscon_regmap_lookup_by_phandle(np, "rockchip,u3phygrf"); ++ if (IS_ERR(u3phy->u3phy_grf)) ++ return PTR_ERR(u3phy->u3phy_grf); ++ ++ u3phy->grf = ++ syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); ++ if (IS_ERR(u3phy->grf)) { ++ dev_err(dev, "Missing rockchip,grf property\n"); ++ return PTR_ERR(u3phy->grf); ++ } ++ ++ if (of_property_read_u32_array(np, "reg", reg, 2)) { ++ dev_err(dev, "the reg property is not assigned in %s node\n", ++ np->name); ++ return -EINVAL; ++ } ++ ++ u3phy->dev = dev; ++ phy_cfgs = match->data; ++ platform_set_drvdata(pdev, u3phy); ++ ++ /* find out a proper config which can be matched with dt. */ ++ index = 0; ++ while (phy_cfgs[index].reg) { ++ if (phy_cfgs[index].reg == reg[1]) { ++ u3phy->cfgs = &phy_cfgs[index]; ++ break; ++ } ++ ++ ++index; ++ } ++ ++ if (!u3phy->cfgs) { ++ dev_err(dev, "no phy-cfgs can be matched with %s node\n", ++ np->name); ++ return -EINVAL; ++ } ++ ++ ret = rockchip_u3phy_parse_dt(u3phy, pdev); ++ if (ret) { ++ dev_err(dev, "parse dt failed, ret(%d)\n", ret); ++ return ret; ++ } ++ ++ ret = rockchip_u3phy_clk_enable(u3phy); ++ if (ret) { ++ dev_err(dev, "clk enable failed, ret(%d)\n", ret); ++ return ret; ++ } ++ ++ rockchip_u3phy_rest_assert(u3phy); ++ rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST); ++ ++ index = 0; ++ for_each_available_child_of_node(np, child_np) { ++ struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index]; ++ ++ u3phy_port->index = index; ++ ret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np); ++ if (ret) { ++ dev_err(dev, "u3phy port init failed,ret(%d)\n", ret); ++ goto put_child; ++ } ++ ++ /* to prevent out of boundary */ ++ if (++index >= U3PHY_PORT_NUM) ++ break; ++ } ++ ++ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (IS_ERR_OR_NULL(provider)) ++ goto put_child; ++ ++ rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST); ++ rockchip_u3phy_clk_disable(u3phy); ++ ++ u3phy->usb_phy.dev = dev; ++ u3phy->usb_phy.init = rockchip_u3phy_on_init; ++ u3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown; ++ u3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect; ++ usb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3); ++ ATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier); ++ ++ rockchip_u3phy_debugfs_init(u3phy); ++ ++ dev_info(dev, "Rockchip u3phy initialized successfully\n"); ++ return 0; ++ ++put_child: ++ of_node_put(child_np); ++ return ret; ++} ++ ++static int rk3328_u3phy_pipe_power(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ bool on) ++{ ++ unsigned int reg; ++ ++ if (on) { ++ reg = readl(u3phy_port->base + 0x1a8); ++ reg &= ~BIT(4); /* ldo power up */ ++ writel(reg, u3phy_port->base + 0x1a8); ++ ++ reg = readl(u3phy_port->base + 0x044); ++ reg &= ~BIT(4); /* bg power on */ ++ writel(reg, u3phy_port->base + 0x044); ++ ++ reg = readl(u3phy_port->base + 0x150); ++ reg |= BIT(6); /* tx bias enable */ ++ writel(reg, u3phy_port->base + 0x150); ++ ++ reg = readl(u3phy_port->base + 0x080); ++ reg &= ~BIT(2); /* tx cm power up */ ++ writel(reg, u3phy_port->base + 0x080); ++ ++ reg = readl(u3phy_port->base + 0x0c0); ++ /* tx obs enable and rx cm enable */ ++ reg |= (BIT(3) | BIT(4)); ++ writel(reg, u3phy_port->base + 0x0c0); ++ ++ udelay(1); ++ } else { ++ reg = readl(u3phy_port->base + 0x1a8); ++ reg |= BIT(4); /* ldo power down */ ++ writel(reg, u3phy_port->base + 0x1a8); ++ ++ reg = readl(u3phy_port->base + 0x044); ++ reg |= BIT(4); /* bg power down */ ++ writel(reg, u3phy_port->base + 0x044); ++ ++ reg = readl(u3phy_port->base + 0x150); ++ reg &= ~BIT(6); /* tx bias disable */ ++ writel(reg, u3phy_port->base + 0x150); ++ ++ reg = readl(u3phy_port->base + 0x080); ++ reg |= BIT(2); /* tx cm power down */ ++ writel(reg, u3phy_port->base + 0x080); ++ ++ reg = readl(u3phy_port->base + 0x0c0); ++ /* tx obs disable and rx cm disable */ ++ reg &= ~(BIT(3) | BIT(4)); ++ writel(reg, u3phy_port->base + 0x0c0); ++ } ++ ++ return 0; ++} ++ ++static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy, ++ struct rockchip_u3phy_port *u3phy_port, ++ struct device_node *child_np) ++{ ++ if (u3phy_port->type == U3PHY_TYPE_UTMI) { ++ /* ++ * For rk3328 SoC, pre-emphasis and pre-emphasis strength must ++ * be written as one fixed value as below. ++ * ++ * Dissimilarly, the odt 45ohm value should be flexibly tuninged ++ * for the different boards to adjust HS eye height, so its ++ * value can be assigned in DT in code design. ++ */ ++ ++ /* {bits[2:0]=111}: always enable pre-emphasis */ ++ u3phy->apbcfg.u2_pre_emp = 0x0f; ++ ++ /* {bits[5:3]=000}: pre-emphasis strength as the weakest */ ++ u3phy->apbcfg.u2_pre_emp_sth = 0x41; ++ ++ /* {bits[4:0]=10101}: odt 45ohm tuning */ ++ u3phy->apbcfg.u2_odt_tuning = 0xb5; ++ /* optional override of the odt 45ohm tuning */ ++ of_property_read_u32(child_np, "rockchip,odt-val-tuning", ++ &u3phy->apbcfg.u2_odt_tuning); ++ ++ writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030); ++ writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040); ++ writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c); ++ } else if (u3phy_port->type == U3PHY_TYPE_PIPE) { ++ if (u3phy_port->refclk_25m_quirk) { ++ dev_dbg(u3phy->dev, "switch to 25m refclk\n"); ++ /* ref clk switch to 25M */ ++ writel(0x64, u3phy_port->base + 0x11c); ++ writel(0x64, u3phy_port->base + 0x028); ++ writel(0x01, u3phy_port->base + 0x020); ++ writel(0x21, u3phy_port->base + 0x030); ++ writel(0x06, u3phy_port->base + 0x108); ++ writel(0x00, u3phy_port->base + 0x118); ++ } else { ++ /* configure for 24M ref clk */ ++ writel(0x80, u3phy_port->base + 0x10c); ++ writel(0x01, u3phy_port->base + 0x118); ++ writel(0x38, u3phy_port->base + 0x11c); ++ writel(0x83, u3phy_port->base + 0x020); ++ writel(0x02, u3phy_port->base + 0x108); ++ } ++ ++ /* Enable SSC */ ++ udelay(3); ++ writel(0x08, u3phy_port->base + 0x000); ++ writel(0x0c, u3phy_port->base + 0x120); ++ ++ /* Tuning Rx for compliance RJTL test */ ++ writel(0x70, u3phy_port->base + 0x150); ++ writel(0x12, u3phy_port->base + 0x0c8); ++ writel(0x05, u3phy_port->base + 0x148); ++ writel(0x08, u3phy_port->base + 0x068); ++ writel(0xf0, u3phy_port->base + 0x1c4); ++ writel(0xff, u3phy_port->base + 0x070); ++ writel(0x0f, u3phy_port->base + 0x06c); ++ writel(0xe0, u3phy_port->base + 0x060); ++ ++ /* ++ * Tuning Tx to increase the bias current ++ * used in TX driver and RX EQ, it can ++ * also increase the voltage of LFPS. ++ */ ++ writel(0x08, u3phy_port->base + 0x180); ++ } else { ++ dev_err(u3phy->dev, "invalid u3phy port type\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct rockchip_u3phy_cfg rk3328_u3phy_cfgs[] = { ++ { ++ .reg = 0xff470000, ++ .grfcfg = { ++ .um_suspend = { 0x0004, 15, 0, 0x1452, 0x15d1 }, ++ .u2_only_ctrl = { 0x0020, 15, 15, 0, 1 }, ++ .um_ls = { 0x0030, 5, 4, 0, 1 }, ++ .um_hstdct = { 0x0030, 7, 7, 0, 1 }, ++ .ls_det_en = { 0x0040, 0, 0, 0, 1 }, ++ .ls_det_st = { 0x0044, 0, 0, 0, 1 }, ++ .pp_pwr_st = { 0x0034, 14, 13, 0, 0}, ++ .pp_pwr_en = { {0x0020, 14, 0, 0x0014, 0x0005}, ++ {0x0020, 14, 0, 0x0014, 0x000d}, ++ {0x0020, 14, 0, 0x0014, 0x0015}, ++ {0x0020, 14, 0, 0x0014, 0x001d} }, ++ .u3_disable = { 0x04c4, 15, 0, 0x1100, 0x101}, ++ }, ++ .phy_pipe_power = rk3328_u3phy_pipe_power, ++ .phy_tuning = rk3328_u3phy_tuning, ++ }, ++ { /* sentinel */ } ++}; ++ ++static const struct of_device_id rockchip_u3phy_dt_match[] = { ++ { .compatible = "rockchip,rk3328-u3phy", .data = &rk3328_u3phy_cfgs }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, rockchip_u3phy_dt_match); ++ ++static struct platform_driver rockchip_u3phy_driver = { ++ .probe = rockchip_u3phy_probe, ++ .driver = { ++ .name = "rockchip-u3phy", ++ .of_match_table = rockchip_u3phy_dt_match, ++ }, ++}; ++module_platform_driver(rockchip_u3phy_driver); ++ ++MODULE_AUTHOR("Frank Wang "); ++MODULE_AUTHOR("William Wu "); ++MODULE_DESCRIPTION("Rockchip USB 3.0 PHY driver"); ++MODULE_LICENSE("GPL v2"); + +diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml +new file mode 100644 +index 000000000000..f4f28625173a +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml +@@ -0,0 +1,157 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: "http://devicetree.org/schemas/phy/phy-rockchip-inno-usb3.yaml#" ++$schema: "http://devicetree.org/meta-schemas/core.yaml#" ++ ++title: ROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK ++ ++maintainers: ++ ++properties: ++ compatible: ++ enum: ++ - rockchip,rk3328-u3phy ++ ++ reg: ++ - description: the base address of the USB 3.0 PHY ++ ++ interrupts: ++ maxItems: 1 ++ ++ interrupt-names: ++ items: ++ - const: linestate ++ description: host/otg linestate interrupt ++ ++ clocks: ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: u3phy-otg ++ description: USB 3.0 PHY UTMI ++ - const: u3phy-pipe ++ description: USB 3.0 PHY Pipe ++ ++ resets: ++ maxItems: 6 ++ ++ reset-names: ++ items: ++ - const: u3phy-u2-por ++ description: USB 2.0 logic of USB 3.0 PHY ++ - const: u3phy-u3-por ++ description: USB 3.0 logic of USB 3.0 PHY ++ - const: u3phy-pipe-mac ++ description: USB 3.0 PHY pipe MAC ++ - const: u3phy-utmi-mac ++ description: USB 3.0 PHY utmi MAC ++ - const: u3phy-utmi-apb ++ description: USB 3.0 PHY utmi apb ++ - const: u3phy-pipe-apb ++ description: USB 3.0 PHY pipe apb ++ ++ "#phy-cells": ++ const: 1 ++ ++ rockchip,u3phygrf: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ type: array ++ - description: phandle to the syscon managing the ++ "USB 3.0 PHY general register files". ++ ++ vbus-drv-gpios: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ type: array ++ - description: phandle for gpio vbus supply ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - interrupt-names ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - "#phy-cells" ++ - rockchip,u3phygrf ++ ++patternProperties: ++ "^u3phy_utmi@[0-9a-f]+$": ++ type: object ++ ++ properties: ++ - description: USB 2.0 utmi phy. ++ ++ rockchip,odt-val-tuning: ++ type: boolean ++ - description: specify 45ohm ODT tuning value. ++ ++ "phy-cells": ++ const: 0 ++ ++ required: ++ - reg ++ - "#phy-cells" ++ ++patternProperties: ++ "^u3phy_pipe@[0-9a-f]+$": ++ type: object ++ ++ properties: ++ - description: USB 3.0 pipe phy. ++ ++ rockchip,refclk-25m-quirk : ++ ++ - description: phy reference clock changed to 25m quirk. ++ ++ "phy-cells": ++ const: 0 ++ ++ required: ++ - reg ++ - "#phy-cells" ++ ++examples: ++ ++usb3phy_grf: syscon@ff460000 { ++ compatible = "rockchip,usb3phy-grf", "syscon"; ++ reg = <0x0 0xff460000 0x0 0x1000>; ++}; ++ ++... ++ ++u3phy: usb3-phy@ff470000 { ++ compatible = "rockchip,rk3328-u3phy"; ++ reg = <0x0 0xff470000 0x0 0x0>; ++ rockchip,u3phygrf = <&usb3phy_grf>; ++ interrupts = ; ++ interrupt-names = "linestate"; ++ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; ++ clock-names = "u3phy-otg", "u3phy-pipe"; ++ resets = <&cru SRST_USB3PHY_U2>, ++ <&cru SRST_USB3PHY_U3>, ++ <&cru SRST_USB3PHY_PIPE>, ++ <&cru SRST_USB3OTG_UTMI>, ++ <&cru SRST_USB3PHY_OTG_P>, ++ <&cru SRST_USB3PHY_PIPE_P>; ++ reset-names = "u3phy-u2-por", "u3phy-u3-por", ++ "u3phy-pipe-mac", "u3phy-utmi-mac", ++ "u3phy-utmi-apb", "u3phy-pipe-apb"; ++ vbus-drv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ u3phy_utmi: utmi@ff470000 { ++ reg = <0x0 0xff470000 0x0 0x8000>; ++ #phy-cells = <0>; ++ }; ++ ++ u3phy_pipe: pipe@ff478000 { ++ reg = <0x0 0xff478000 0x0 0x8000>; ++ #phy-cells = <0>; ++ }; ++}; +diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +index ada5435ce2c3..5f2f19344cc7 100644 +--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml ++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +@@ -34,6 +34,7 @@ + - rockchip,rk3308-usb2phy-grf + - rockchip,rk3328-grf + - rockchip,rk3328-usb2phy-grf ++ - rockchip,rk3328-u3phy-grf + - rockchip,rk3368-grf + - rockchip,rk3368-pmugrf + - rockchip,rk3399-grf +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 31cc1541f1f5..072e988ad655 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -805,6 +805,47 @@ + }; + }; + ++ usb3phy_grf: syscon@ff460000 { ++ compatible = "rockchip,usb3phy-grf", "syscon"; ++ reg = <0x0 0xff460000 0x0 0x1000>; ++ }; ++ ++ u3phy: usb3-phy@ff470000 { ++ compatible = "rockchip,rk3328-u3phy"; ++ reg = <0x0 0xff470000 0x0 0x0>; ++ rockchip,u3phygrf = <&usb3phy_grf>; ++ rockchip,grf = <&grf>; ++ interrupts = ; ++ interrupt-names = "linestate"; ++ clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; ++ clock-names = "u3phy-otg", "u3phy-pipe"; ++ resets = <&cru SRST_USB3PHY_U2>, ++ <&cru SRST_USB3PHY_U3>, ++ <&cru SRST_USB3PHY_PIPE>, ++ <&cru SRST_USB3OTG_UTMI>, ++ <&cru SRST_USB3PHY_OTG_P>, ++ <&cru SRST_USB3PHY_PIPE_P>; ++ reset-names = "u3phy-u2-por", "u3phy-u3-por", ++ "u3phy-pipe-mac", "u3phy-utmi-mac", ++ "u3phy-utmi-apb", "u3phy-pipe-apb"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ u3phy_utmi: utmi@ff470000 { ++ reg = <0x0 0xff470000 0x0 0x8000>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ u3phy_pipe: pipe@ff478000 { ++ reg = <0x0 0xff478000 0x0 0x8000>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ + sdmmc: mmc@ff500000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff500000 0x0 0x4000>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +index bb40c163b05d..f300f3d0f02e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -328,6 +328,18 @@ + status = "okay"; + }; + ++&u3phy { ++ status = "okay"; ++}; ++ ++&u3phy_utmi { ++ status = "okay"; ++}; ++ ++&u3phy_pipe { ++ status = "okay"; ++}; ++ + &uart2 { + status = "okay"; + }; +@@ -344,6 +356,11 @@ + status = "okay"; + }; + ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index 62936b432..f97446924 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -383,6 +383,18 @@ + status = "okay"; + }; + ++&u3phy { ++ status = "okay"; ++}; ++ ++&u3phy_utmi { ++ status = "okay"; ++}; ++ ++&u3phy_pipe { ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + }; +@@ -391,6 +403,11 @@ + status = "okay"; + }; + ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; diff --git a/patch/kernel/archive/station-p2-5.19/320-add-rockchip-iep-driver.patch b/patch/kernel/archive/station-p2-5.19/320-add-rockchip-iep-driver.patch new file mode 100644 index 000000000..06434ec8b --- /dev/null +++ b/patch/kernel/archive/station-p2-5.19/320-add-rockchip-iep-driver.patch @@ -0,0 +1,1736 @@ +diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml +new file mode 100644 +index 000000000..a9efcda13 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml +@@ -0,0 +1,73 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/rockchip-iep.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip Image Enhancement Processor (IEP) ++ ++description: ++ Rockchip IEP supports various image enhancement operations for YUV and RGB domains. ++ Deinterlacing, spatial and temporal sampling noise reduction are supported by the ++ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in ++ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for ++ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB. ++ ++maintainers: ++ - Heiko Stuebner ++ ++properties: ++ compatible: ++ oneOf: ++ - const: rockchip,rk3228-iep ++ - items: ++ - enum: ++ - rockchip,rk3288-iep ++ - rockchip,rk3328-iep ++ - rockchip,rk3368-iep ++ - rockchip,rk3399-iep ++ - const: rockchip,rk3228-iep ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: axi ++ - const: ahb ++ ++ power-domains: ++ maxItems: 1 ++ ++ iommus: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ iep: iep@20070000 { ++ compatible = "rockchip,rk3228-iep"; ++ reg = <0x20070000 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ iommus = <&iep_mmu>; ++ power-domains = <&power RK3228_PD_VIO>; ++ }; +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 9c5a7791a..13db2ac6b 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -983,6 +983,17 @@ crypto: cypto-controller@ff8a0000 { + status = "okay"; + }; + ++ iep: iep@ff90000 { ++ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff900000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3288_PD_VIO>; ++ iommus = <&iep_mmu>; ++ }; ++ + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x40>; +@@ -990,8 +1001,8 @@ iep_mmu: iommu@ff900800 { + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3288_PD_VIO>; + #iommu-cells = <0>; +- status = "disabled"; + }; + + isp_mmu: iommu@ff914000 { +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 8c0bca75e..162e57936 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -829,6 +829,28 @@ vop_mmu: iommu@ff373f00 { + status = "disabled"; + }; + ++ iep: iep@ff3a0000 { ++ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff3a0000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3328_PD_VIDEO>; ++ iommus = <&iep_mmu>; ++ }; ++ ++ iep_mmu: iommu@ff3a0800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff3a0800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "iep_mmu"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3328_PD_VIDEO>; ++ #iommu-cells = <0>; ++ }; ++ + hdmi: hdmi@ff3c0000 { + compatible = "rockchip,rk3328-dw-hdmi"; + reg = <0x0 0xff3c0000 0x0 0x20000>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index c39408ccc..f35211810 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1283,6 +1283,18 @@ vdec_mmu: iommu@ff660480 { + #iommu-cells = <0>; + }; + ++ ++ iep: iep@ff670000 { ++ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff670000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3399_PD_IEP>; ++ iommus = <&iep_mmu>; ++ }; ++ + iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; +@@ -1290,6 +1302,7 @@ iep_mmu: iommu@ff670800 { + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3399_PD_IEP>; + #iommu-cells = <0>; + status = "disabled"; + }; +diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile +new file mode 100644 +index 000000000..5c89b3277 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++rockchip-iep-objs := iep.o ++ ++obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o +diff --git a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/platform/rockchip/iep/iep-regs.h +new file mode 100644 +index 000000000..a68685ef3 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep-regs.h +@@ -0,0 +1,291 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ */ ++ ++#ifndef __IEP_REGS_H__ ++#define __IEP_REGS_H__ ++ ++/* IEP Registers addresses */ ++#define IEP_CONFIG0 0x000 /* Configuration register0 */ ++#define IEP_VOP_DIRECT_PATH BIT(0) ++#define IEP_DEIN_HIGH_FREQ_SHFT 1 ++#define IEP_DEIN_HIGH_FREQ_MASK (0x7f << IEP_DEIN_HIGH_FREQ_SHFT) ++#define IEP_DEIN_MODE_SHFT 8 ++#define IEP_DEIN_MODE_MASK (7 << IEP_DEIN_MODE_SHFT) ++#define IEP_DEIN_HIGH_FREQ_EN BIT(11) ++#define IEP_DEIN_EDGE_INTPOL_EN BIT(12) ++#define IEP_YUV_DENOISE_EN BIT(13) ++#define IEP_YUV_ENHNC_EN BIT(14) ++#define IEP_DEIN_EDGE_INTPOL_SMTH_EN BIT(15) ++#define IEP_RGB_CLR_ENHNC_EN BIT(16) ++#define IEP_RGB_CNTRST_ENHNC_EN BIT(17) ++#define IEP_RGB_ENHNC_MODE_BYPASS (0 << 18) ++#define IEP_RGB_ENHNC_MODE_DNS BIT(18) ++#define IEP_RGB_ENHNC_MODE_DTL (2 << 18) ++#define IEP_RGB_ENHNC_MODE_EDG (3 << 18) ++#define IEP_RGB_ENHNC_MODE_MASK (3 << 18) ++#define IEP_RGB_CNTRST_ENHNC_DDE_FRST BIT(20) ++#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT 21 ++#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK (3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) ++#define IEP_DEIN_EDGE_INTPOL_SELECT BIT(23) ++ ++#define IEP_CONFIG1 0x004 /* Configuration register1 */ ++#define IEP_SRC_FMT_SHFT 0 ++#define IEP_SRC_FMT_MASK (3 << IEP_SRC_FMT_SHFT) ++#define IEP_SRC_RGB_SWP_SHFT 2 ++#define IEP_SRC_RGB_SWP_MASK (2 << IEP_SRC_RGB_SWP_SHFT) ++#define IEP_SRC_YUV_SWP_SHFT 4 ++#define IEP_SRC_YUV_SWP_MASK (3 << IEP_SRC_YUV_SWP_SHFT) ++#define IEP_DST_FMT_SHFT 8 ++#define IEP_DST_FMT_MASK (3 << IEP_DST_FMT_SHFT) ++#define IEP_DST_RGB_SWP_SHFT 10 ++#define IEP_DST_RGB_SWP_MASK (2 << IEP_DST_RGB_SWP_SHFT) ++#define IEP_DST_YUV_SWP_SHFT 12 ++#define IEP_DST_YUV_SWP_MASK (3 << IEP_DST_YUV_SWP_SHFT) ++#define IEP_DTH_UP_EN BIT(14) ++#define IEP_DTH_DWN_EN BIT(15) ++#define IEP_YUV2RGB_COE_BT601_1 (0 << 16) ++#define IEP_YUV2RGB_COE_BT601_F BIT(16) ++#define IEP_YUV2RGB_COE_BT709_1 (2 << 16) ++#define IEP_YUV2RGB_COE_BT709_F (3 << 16) ++#define IEP_YUV2RGB_COE_MASK (3 << 16) ++#define IEP_RGB2YUV_COE_BT601_1 (0 << 18) ++#define IEP_RGB2YUV_COE_BT601_F BIT(18) ++#define IEP_RGB2YUV_COE_BT709_1 (2 << 18) ++#define IEP_RGB2YUV_COE_BT709_F (3 << 18) ++#define IEP_RGB2YUV_COE_MASK (3 << 18) ++#define IEP_YUV2RGB_EN BIT(20) ++#define IEP_RGB2YUV_EN BIT(21) ++#define IEP_YUV2RGB_CLIP_EN BIT(22) ++#define IEP_RGB2YUV_CLIP_EN BIT(23) ++#define IEP_GLB_ALPHA_SHFT 24 ++#define IEP_GLB_ALPHA_MASK (0x7f << IEP_GLB_ALPHA_SHFT) ++ ++#define IEP_STATUS 0x008 /* Status register */ ++#define IEP_STATUS_YUV_DNS BIT(0) ++#define IEP_STATUS_SCL BIT(1) ++#define IEP_STATUS_DIL BIT(2) ++#define IEP_STATUS_DDE BIT(3) ++#define IEP_STATUS_DMA_WR_YUV BIT(4) ++#define IEP_STATUS_DMA_RE_YUV BIT(5) ++#define IEP_STATUS_DMA_WR_RGB BIT(6) ++#define IEP_STATUS_DMA_RE_RGB BIT(7) ++#define IEP_STATUS_VOP_DIRECT_PATH BIT(8) ++#define IEP_STATUS_DMA_IA_WR_YUV BIT(16) ++#define IEP_STATUS_DMA_IA_RE_YUV BIT(17) ++#define IEP_STATUS_DMA_IA_WR_RGB BIT(18) ++#define IEP_STATUS_DMA_IA_RE_RGB BIT(19) ++ ++#define IEP_INT 0x00c /* Interrupt register*/ ++#define IEP_INT_FRAME_DONE BIT(0) /* Frame process done interrupt */ ++#define IEP_INT_FRAME_DONE_EN BIT(8) /* Frame process done interrupt enable */ ++#define IEP_INT_FRAME_DONE_CLR BIT(16) /* Frame process done interrupt clear */ ++ ++#define IEP_FRM_START 0x010 /* Frame start */ ++#define IEP_SRST 0x014 /* Soft reset */ ++#define IEP_CONFIG_DONE 0x018 /* Configuration done */ ++#define IEP_FRM_CNT 0x01c /* Frame counter */ ++ ++#define IEP_VIR_IMG_WIDTH 0x020 /* Image virtual width */ ++#define IEP_IMG_SCL_FCT 0x024 /* Scaling factor */ ++#define IEP_SRC_IMG_SIZE 0x028 /* src image width/height */ ++#define IEP_DST_IMG_SIZE 0x02c /* dst image width/height */ ++#define IEP_DST_IMG_WIDTH_TILE0 0x030 /* dst image tile0 width */ ++#define IEP_DST_IMG_WIDTH_TILE1 0x034 /* dst image tile1 width */ ++#define IEP_DST_IMG_WIDTH_TILE2 0x038 /* dst image tile2 width */ ++#define IEP_DST_IMG_WIDTH_TILE3 0x03c /* dst image tile3 width */ ++ ++#define IEP_ENH_YUV_CNFG_0 0x040 /* Brightness, contrast, saturation adjustment */ ++#define IEP_YUV_BRIGHTNESS_SHFT 0 ++#define IEP_YUV_BRIGHTNESS_MASK (0x3f << IEP_YUV_BRIGHTNESS_SHFT) ++#define IEP_YUV_CONTRAST_SHFT 8 ++#define IEP_YUV_CONTRAST_MASK (0xff << IEP_YUV_CONTRAST_SHFT) ++#define IEP_YUV_SATURATION_SHFT 16 ++#define IEP_YUV_SATURATION_MASK (0x1ff << IEP_YUV_SATURATION_SHFT) ++ ++#define IEP_ENH_YUV_CNFG_1 0x044 /* Hue configuration */ ++#define IEP_YUV_COS_HUE_SHFT 0 ++#define IEP_YUV_COS_HUE_MASK (0xff << IEP_YUV_COS_HUE_SHFT) ++#define IEP_YUV_SIN_HUE_SHFT 8 ++#define IEP_YUV_SIN_HUE_MASK (0xff << IEP_YUV_SIN_HUE_SHFT) ++ ++#define IEP_ENH_YUV_CNFG_2 0x048 /* Color bar configuration */ ++#define IEP_YUV_COLOR_BAR_Y_SHFT 0 ++#define IEP_YUV_COLOR_BAR_Y_MASK (0xff << IEP_YUV_COLOR_BAR_Y_SHFT) ++#define IEP_YUV_COLOR_BAR_U_SHFT 8 ++#define IEP_YUV_COLOR_BAR_U_MASK (0xff << IEP_YUV_COLOR_BAR_U_SHFT) ++#define IEP_YUV_COLOR_BAR_V_SHFT 16 ++#define IEP_YUV_COLOR_BAR_V_MASK (0xff << IEP_YUV_COLOR_BAR_V_SHFT) ++#define IEP_YUV_VIDEO_MODE_SHFT 24 ++#define IEP_YUV_VIDEO_MODE_MASK (3 << IEP_YUV_VIDEO_MODE_SHFT) ++ ++#define IEP_ENH_RGB_CNFG 0x04c /* RGB enhancement configuration */ ++#define IEP_ENH_RGB_C_COE 0x050 /* RGB color enhancement coefficient */ ++ ++#define IEP_RAW_CONFIG0 0x058 /* Raw configuration register0 */ ++#define IEP_RAW_CONFIG1 0x05c /* Raw configuration register1 */ ++#define IEP_RAW_VIR_IMG_WIDTH 0x060 /* Raw image virtual width */ ++#define IEP_RAW_IMG_SCL_FCT 0x064 /* Raw scaling factor */ ++#define IEP_RAW_SRC_IMG_SIZE 0x068 /* Raw src image width/height */ ++#define IEP_RAW_DST_IMG_SIZE 0x06c /* Raw src image width/height */ ++#define IEP_RAW_ENH_YUV_CNFG_0 0x070 /* Raw brightness,contrast,saturation adjustment */ ++#define IEP_RAW_ENH_YUV_CNFG_1 0x074 /* Raw hue configuration */ ++#define IEP_RAW_ENH_YUV_CNFG_2 0x078 /* Raw color bar configuration */ ++#define IEP_RAW_ENH_RGB_CNFG 0x07c /* Raw RGB enhancement configuration */ ++ ++#define IEP_SRC_ADDR_Y_RGB 0x080 /* Start addr. of src image 0 (Y/RGB) */ ++#define IEP_SRC_ADDR_CBCR 0x084 /* Start addr. of src image 0 (Cb/Cr) */ ++#define IEP_SRC_ADDR_CR 0x088 /* Start addr. of src image 0 (Cr) */ ++#define IEP_SRC_ADDR_Y1 0x08c /* Start addr. of src image 1 (Y) */ ++#define IEP_SRC_ADDR_CBCR1 0x090 /* Start addr. of src image 1 (Cb/Cr) */ ++#define IEP_SRC_ADDR_CR1 0x094 /* Start addr. of src image 1 (Cr) */ ++#define IEP_SRC_ADDR_Y_ITEMP 0x098 /* Start addr. of src image(Y int part) */ ++#define IEP_SRC_ADDR_CBCR_ITEMP 0x09c /* Start addr. of src image(CBCR int part) */ ++#define IEP_SRC_ADDR_CR_ITEMP 0x0a0 /* Start addr. of src image(CR int part) */ ++#define IEP_SRC_ADDR_Y_FTEMP 0x0a4 /* Start addr. of src image(Y frac part) */ ++#define IEP_SRC_ADDR_CBCR_FTEMP 0x0a8 /* Start addr. of src image(CBCR frac part) */ ++#define IEP_SRC_ADDR_CR_FTEMP 0x0ac /* Start addr. of src image(CR frac part) */ ++ ++#define IEP_DST_ADDR_Y_RGB 0x0b0 /* Start addr. of dst image 0 (Y/RGB) */ ++#define IEP_DST_ADDR_CBCR 0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */ ++#define IEP_DST_ADDR_CR 0x0b8 /* Start addr. of dst image 0 (Cr) */ ++#define IEP_DST_ADDR_Y1 0x0bc /* Start addr. of dst image 1 (Y) */ ++#define IEP_DST_ADDR_CBCR1 0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */ ++#define IEP_DST_ADDR_CR1 0x0c4 /* Start addr. of dst image 1 (Cr) */ ++#define IEP_DST_ADDR_Y_ITEMP 0x0c8 /* Start addr. of dst image(Y int part) */ ++#define IEP_DST_ADDR_CBCR_ITEMP 0x0cc /* Start addr. of dst image(CBCR int part)*/ ++#define IEP_DST_ADDR_CR_ITEMP 0x0d0 /* Start addr. of dst image(CR int part) */ ++#define IEP_DST_ADDR_Y_FTEMP 0x0d4 /* Start addr. of dst image(Y frac part) */ ++#define IEP_DST_ADDR_CBCR_FTEMP 0x0d8 /* Start addr. of dst image(CBCR frac part) */ ++#define IEP_DST_ADDR_CR_FTEMP 0x0dc /* Start addr. of dst image(CR frac part)*/ ++ ++#define IEP_DEIN_MTN_TAB0 0x0e0 /* Deinterlace motion table0 */ ++#define IEP_DEIN_MTN_TAB1 0x0e4 /* Deinterlace motion table1 */ ++#define IEP_DEIN_MTN_TAB2 0x0e8 /* Deinterlace motion table2 */ ++#define IEP_DEIN_MTN_TAB3 0x0ec /* Deinterlace motion table3 */ ++#define IEP_DEIN_MTN_TAB4 0x0f0 /* Deinterlace motion table4 */ ++#define IEP_DEIN_MTN_TAB5 0x0f4 /* Deinterlace motion table5 */ ++#define IEP_DEIN_MTN_TAB6 0x0f8 /* Deinterlace motion table6 */ ++#define IEP_DEIN_MTN_TAB7 0x0fc /* Deinterlace motion table7 */ ++ ++#define IEP_ENH_CG_TAB 0x100 /* Contrast and gamma enhancement table */ ++#define IEP_ENH_DDE_COE0 0x400 /* Denoise,detail and edge enhancement coefficient */ ++#define IEP_ENH_DDE_COE1 0x500 /* Denoise,detail and edge enhancement coefficient1 */ ++ ++#define IEP_INT_MASK (IEP_INT_FRAME_DONE) ++ ++/* IEP colorformats */ ++#define IEP_COLOR_FMT_XRGB 0U ++#define IEP_COLOR_FMT_RGB565 1U ++#define IEP_COLOR_FMT_YUV422 2U ++#define IEP_COLOR_FMT_YUV420 3U ++ ++/* IEP YUV color swaps */ ++#define IEP_YUV_SWP_SP_UV 0U ++#define IEP_YUV_SWP_SP_VU 1U ++#define IEP_YUV_SWP_P 2U ++ ++/* IEP XRGB color swaps */ ++#define XRGB_SWP_XRGB 0U ++#define XRGB_SWP_XBGR 1U ++#define XRGB_SWP_BGRX 2U ++ ++/* IEP RGB565 color swaps */ ++#define RGB565_SWP_RGB 0U ++#define RGB565_SWP_BGR 1U ++ ++#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1) ++ ++#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \ ++ ((h - 1) & 0x1fff) << 16) ++ ++#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \ ++ ((dst_w / 4) & 0x1fff) << 16) ++ ++#define IEP_Y_STRIDE(w, h) (w * h) ++#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac) ++ ++#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK) ++#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK) ++ ++#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \ ++ (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT))) ++#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \ ++ (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT))) ++ ++/* IEP DEINTERLACE MODES */ ++#define IEP_DEIN_MODE_YUV 0U ++#define IEP_DEIN_MODE_I4O2 1U ++#define IEP_DEIN_MODE_I4O1B 2U ++#define IEP_DEIN_MODE_I4O1T 3U ++#define IEP_DEIN_MODE_I2O1B 4U ++#define IEP_DEIN_MODE_I2O1T 5U ++#define IEP_DEIN_MODE_BYPASS 6U ++ ++#define IEP_DEIN_IN_FIELDS_2 2U ++#define IEP_DEIN_IN_FIELDS_4 4U ++ ++#define IEP_DEIN_OUT_FRAMES_1 1U ++#define IEP_DEIN_OUT_FRAMES_2 2U ++ ++/* values taken from BSP driver */ ++static const u32 default_dein_motion_tbl[][2] = { ++ { IEP_DEIN_MTN_TAB0, 0x40404040 }, ++ { IEP_DEIN_MTN_TAB1, 0x3c3e3f3f }, ++ { IEP_DEIN_MTN_TAB2, 0x3336393b }, ++ { IEP_DEIN_MTN_TAB3, 0x272a2d31 }, ++ { IEP_DEIN_MTN_TAB4, 0x181c2023 }, ++ { IEP_DEIN_MTN_TAB5, 0x0c0e1215 }, ++ { IEP_DEIN_MTN_TAB6, 0x03040609 }, ++ { IEP_DEIN_MTN_TAB7, 0x00000001 }, ++ ++}; ++ ++#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1) ++#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1) ++#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1) ++#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff)) ++#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff)) ++#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff)) ++ ++#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB) ++#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR) ++#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR) ++#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff)) ++#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff)) ++#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff)) ++ ++#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT) ++ ++#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \ ++ || m == IEP_DEIN_MODE_I4O2) \ ++ ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2) ++ ++#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \ ++ ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1) ++ ++#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \ ++ ? 1 : 0) ++ ++#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) ++ ++#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT) ++ ++/* YUV Enhance video modes */ ++#define VIDEO_MODE_BLACK_SCREEN 0U ++#define VIDEO_MODE_BLUE_SCREEN 1U ++#define VIDEO_MODE_COLOR_BARS 2U ++#define VIDEO_MODE_NORMAL_VIDEO 3U ++ ++#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK) ++#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK) ++#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK) ++#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK) ++#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK) ++#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK) ++ ++#endif +diff --git a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c +new file mode 100644 +index 000000000..f4b932073 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep.c +@@ -0,0 +1,1089 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ * Based on Allwinner sun8i deinterlacer with scaler driver ++ * Copyright (C) 2019 Jernej Skrabec ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "iep-regs.h" ++#include "iep.h" ++ ++static struct iep_fmt formats[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_NV12, ++ .color_swap = IEP_YUV_SWP_SP_UV, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV21, ++ .color_swap = IEP_YUV_SWP_SP_VU, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV16, ++ .color_swap = IEP_YUV_SWP_SP_UV, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV61, ++ .color_swap = IEP_YUV_SWP_SP_VU, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV420, ++ .color_swap = IEP_YUV_SWP_P, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV422P, ++ .color_swap = IEP_YUV_SWP_P, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++}; ++ ++static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) { ++ if (formats[i].fourcc == pix_fmt->pixelformat) ++ return &formats[i]; ++ } ++ ++ return NULL; ++} ++ ++static bool iep_check_pix_format(u32 pixelformat) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) ++ if (formats[i].fourcc == pixelformat) ++ return true; ++ ++ return false; ++} ++ ++static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx) ++{ ++ struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); ++ ++ /* application has set a dst sequence: take it as start point */ ++ if (ctx->dst_sequence == 0 && dst_buf->sequence > 0) ++ ctx->dst_sequence = dst_buf->sequence; ++ ++ dst_buf->sequence = ctx->dst_sequence++; ++ ++ return dst_buf; ++} ++ ++static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state) ++{ ++ if (ctx->dst0_buf) { ++ v4l2_m2m_buf_done(ctx->dst0_buf, state); ++ ctx->dst_buffs_done++; ++ ctx->dst0_buf = NULL; ++ } ++ ++ if (ctx->dst1_buf) { ++ v4l2_m2m_buf_done(ctx->dst1_buf, state); ++ ctx->dst_buffs_done++; ++ ctx->dst1_buf = NULL; ++ } ++} ++ ++static void iep_setup_formats(struct iep_ctx *ctx) ++{ ++ /* setup src dimensions */ ++ iep_write(ctx->iep, IEP_SRC_IMG_SIZE, ++ IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height)); ++ ++ /* setup dst dimensions */ ++ iep_write(ctx->iep, IEP_DST_IMG_SIZE, ++ IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height)); ++ ++ /* setup virtual width */ ++ iep_write(ctx->iep, IEP_VIR_IMG_WIDTH, ++ IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width)); ++ ++ /* setup src format */ ++ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, ++ IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format), ++ IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format, ++ ctx->src_fmt.hw_fmt->color_swap)); ++ /* setup dst format */ ++ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, ++ IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format), ++ IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format, ++ ctx->dst_fmt.hw_fmt->color_swap)); ++ ++ ctx->fmt_changed = false; ++} ++ ++static void iep_dein_init(struct rockchip_iep *iep) ++{ ++ unsigned int i; ++ ++ /* values taken from BSP driver */ ++ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, ++ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | ++ IEP_DEIN_EDGE_INTPOL_RADIUS_MASK | ++ IEP_DEIN_HIGH_FREQ_EN | ++ IEP_DEIN_HIGH_FREQ_MASK), ++ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | ++ IEP_DEIN_EDGE_INTPOL_RADIUS(3) | ++ IEP_DEIN_HIGH_FREQ_EN | ++ IEP_DEIN_HIGH_FREQ(64))); ++ ++ for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++) ++ iep_write(iep, default_dein_motion_tbl[i][0], ++ default_dein_motion_tbl[i][1]); ++} ++ ++static void iep_init(struct rockchip_iep *iep) ++{ ++ iep_write(iep, IEP_CONFIG0, ++ IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // | ++ //IEP_YUV_ENHNC_EN ++ ); ++ ++ /* TODO: B/S/C/H works ++ * only in 1-frame-out modes ++ iep_write(iep, IEP_ENH_YUV_CNFG_0, ++ YUV_BRIGHTNESS(0) | ++ YUV_CONTRAST(128) | ++ YUV_SATURATION(128)); ++ ++ iep_write(iep, IEP_ENH_YUV_CNFG_1, ++ YUV_COS_HUE(255) | ++ YUV_SIN_HUE(255)); ++ ++ iep_write(iep, IEP_ENH_YUV_CNFG_2, ++ YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO)); ++ ++ */ ++ ++ /* reset frame counter */ ++ iep_write(iep, IEP_FRM_CNT, 0); ++} ++ ++static void iep_device_run(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ struct rockchip_iep *iep = ctx->iep; ++ struct vb2_v4l2_buffer *src, *dst; ++ unsigned int dein_mode; ++ dma_addr_t addr; ++ ++ if (ctx->fmt_changed) ++ iep_setup_formats(ctx); ++ ++ if (ctx->prev_src_buf) ++ dein_mode = IEP_DEIN_MODE_I4O2; ++ else ++ dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T; ++ ++ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, ++ IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode)); ++ ++ /* sync RAW_xxx registers with actual used */ ++ iep_write(iep, IEP_CONFIG_DONE, 1); ++ ++ /* setup src buff(s)/addresses */ ++ src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff), ++ addr + ctx->src_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff), ++ addr + ctx->src_fmt.uv_stride); ++ ++ if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4) ++ addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff), ++ addr + ctx->src_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff), ++ addr + ctx->src_fmt.uv_stride); ++ ++ /* setup dst buff(s)/addresses */ ++ dst = iep_m2m_next_dst_buf(ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); ++ ++ if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) { ++ v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff), ++ addr + ctx->dst_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff), ++ addr + ctx->dst_fmt.uv_stride); ++ ++ ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ dst = iep_m2m_next_dst_buf(ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); ++ } ++ ++ v4l2_m2m_buf_copy_metadata(src, dst, true); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff), ++ addr + ctx->dst_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff), ++ addr + ctx->dst_fmt.uv_stride); ++ ++ ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN, ++ IEP_INT_FRAME_DONE_EN); ++ ++ /* start HW */ ++ iep_write(iep, IEP_FRM_START, 1); ++} ++ ++static int iep_job_ready(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ ++ return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 && ++ v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1; ++} ++ ++static void iep_job_abort(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ ++ /* Will cancel the transaction in the next interrupt handler */ ++ ctx->job_abort = true; ++} ++ ++static const struct v4l2_m2m_ops iep_m2m_ops = { ++ .device_run = iep_device_run, ++ .job_ready = iep_job_ready, ++ .job_abort = iep_job_abort, ++}; ++ ++static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, ++ unsigned int *nplanes, unsigned int sizes[], ++ struct device *alloc_devs[]) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt.pix; ++ else ++ pix_fmt = &ctx->dst_fmt.pix; ++ ++ if (*nplanes) { ++ if (sizes[0] < pix_fmt->sizeimage) ++ return -EINVAL; ++ } else { ++ sizes[0] = pix_fmt->sizeimage; ++ *nplanes = 1; ++ } ++ ++ return 0; ++} ++ ++static int iep_buf_prepare(struct vb2_buffer *vb) ++{ ++ struct vb2_queue *vq = vb->vb2_queue; ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt.pix; ++ else ++ pix_fmt = &ctx->dst_fmt.pix; ++ ++ if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage) ++ return -EINVAL; ++ ++ /* set bytesused for capture buffers */ ++ if (!V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage); ++ ++ return 0; ++} ++ ++static void iep_buf_queue(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); ++ ++ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); ++} ++ ++static void iep_queue_cleanup(struct vb2_queue *vq, u32 state) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct vb2_v4l2_buffer *vbuf; ++ ++ do { ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ else ++ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ if (vbuf) ++ v4l2_m2m_buf_done(vbuf, state); ++ } while (vbuf); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf) ++ v4l2_m2m_buf_done(ctx->prev_src_buf, state); ++ else ++ iep_m2m_dst_bufs_done(ctx, state); ++} ++ ++static int iep_start_streaming(struct vb2_queue *vq, unsigned int count) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct device *dev = ctx->iep->dev; ++ int ret; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ ret = pm_runtime_get_sync(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to enable module\n"); ++ goto err_runtime_get; ++ } ++ ++ ctx->field_order_bff = ++ ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT; ++ ctx->field_bff = ctx->field_order_bff; ++ ++ ctx->src_sequence = 0; ++ ctx->dst_sequence = 0; ++ ++ ctx->prev_src_buf = NULL; ++ ++ ctx->dst0_buf = NULL; ++ ctx->dst1_buf = NULL; ++ ctx->dst_buffs_done = 0; ++ ++ ctx->job_abort = false; ++ ++ iep_init(ctx->iep); ++ //if (ctx->src_fmt.pix.field != ctx->dst_fmt.pix.field) ++ iep_dein_init(ctx->iep); ++ } ++ ++ return 0; ++ ++err_runtime_get: ++ iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED); ++ ++ return ret; ++} ++ ++static void iep_stop_streaming(struct vb2_queue *vq) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ pm_runtime_mark_last_busy(ctx->iep->dev); ++ pm_runtime_put_autosuspend(ctx->iep->dev); ++ } ++ ++ iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR); ++} ++ ++static const struct vb2_ops iep_qops = { ++ .queue_setup = iep_queue_setup, ++ .buf_prepare = iep_buf_prepare, ++ .buf_queue = iep_buf_queue, ++ .start_streaming = iep_start_streaming, ++ .stop_streaming = iep_stop_streaming, ++ .wait_prepare = vb2_ops_wait_prepare, ++ .wait_finish = vb2_ops_wait_finish, ++}; ++ ++static int iep_queue_init(void *priv, struct vb2_queue *src_vq, ++ struct vb2_queue *dst_vq) ++{ ++ struct iep_ctx *ctx = priv; ++ int ret; ++ ++ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; ++ src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | ++ DMA_ATTR_NO_KERNEL_MAPPING; ++ src_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ src_vq->drv_priv = ctx; ++ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ src_vq->min_buffers_needed = 1; ++ src_vq->ops = &iep_qops; ++ src_vq->mem_ops = &vb2_dma_contig_memops; ++ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ src_vq->lock = &ctx->iep->mutex; ++ src_vq->dev = ctx->iep->v4l2_dev.dev; ++ ++ ret = vb2_queue_init(src_vq); ++ if (ret) ++ return ret; ++ ++ dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | ++ DMA_ATTR_NO_KERNEL_MAPPING; ++ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ dst_vq->drv_priv = ctx; ++ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ dst_vq->min_buffers_needed = 2; ++ dst_vq->ops = &iep_qops; ++ dst_vq->mem_ops = &vb2_dma_contig_memops; ++ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ dst_vq->lock = &ctx->iep->mutex; ++ dst_vq->dev = ctx->iep->v4l2_dev.dev; ++ ++ ret = vb2_queue_init(dst_vq); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void iep_prepare_format(struct v4l2_pix_format *pix_fmt) ++{ ++ unsigned int height = pix_fmt->height; ++ unsigned int width = pix_fmt->width; ++ unsigned int sizeimage, bytesperline; ++ ++ struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt); ++ ++ if (!hw_fmt) { ++ hw_fmt = &formats[0]; ++ pix_fmt->pixelformat = hw_fmt->fourcc; ++ } ++ ++ width = ALIGN(clamp(width, IEP_MIN_WIDTH, ++ IEP_MAX_WIDTH), 16); ++ height = ALIGN(clamp(height, IEP_MIN_HEIGHT, ++ IEP_MAX_HEIGHT), 16); ++ ++ bytesperline = FMT_IS_YUV(hw_fmt->hw_format) ++ ? width : (width * hw_fmt->depth) >> 3; ++ ++ sizeimage = height * (width * hw_fmt->depth) >> 3; ++ ++ pix_fmt->width = width; ++ pix_fmt->height = height; ++ pix_fmt->bytesperline = bytesperline; ++ pix_fmt->sizeimage = sizeimage; ++} ++ ++static int iep_open(struct file *file) ++{ ++ struct rockchip_iep *iep = video_drvdata(file); ++ struct iep_ctx *ctx = NULL; ++ ++ int ret; ++ ++ if (mutex_lock_interruptible(&iep->mutex)) ++ return -ERESTARTSYS; ++ ++ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); ++ if (!ctx) { ++ mutex_unlock(&iep->mutex); ++ return -ENOMEM; ++ } ++ ++ /* default output format */ ++ ctx->src_fmt.pix.pixelformat = formats[0].fourcc; ++ ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED; ++ ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH; ++ ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT; ++ iep_prepare_format(&ctx->src_fmt.pix); ++ ctx->src_fmt.hw_fmt = &formats[0]; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height, ++ ctx->src_fmt.hw_fmt->uv_factor); ++ ++ /* default capture format */ ++ ctx->dst_fmt.pix.pixelformat = formats[0].fourcc; ++ ctx->dst_fmt.pix.field = V4L2_FIELD_NONE; ++ ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH; ++ ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT; ++ iep_prepare_format(&ctx->dst_fmt.pix); ++ ctx->dst_fmt.hw_fmt = &formats[0]; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ /* ensure fmts are written to HW */ ++ ctx->fmt_changed = true; ++ ++ v4l2_fh_init(&ctx->fh, video_devdata(file)); ++ file->private_data = &ctx->fh; ++ ctx->iep = iep; ++ ++ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx, ++ &iep_queue_init); ++ ++ if (IS_ERR(ctx->fh.m2m_ctx)) { ++ ret = PTR_ERR(ctx->fh.m2m_ctx); ++ goto err_free; ++ } ++ ++ v4l2_fh_add(&ctx->fh); ++ ++ mutex_unlock(&iep->mutex); ++ ++ return 0; ++ ++err_free: ++ kfree(ctx); ++ mutex_unlock(&iep->mutex); ++ ++ return ret; ++} ++ ++static int iep_release(struct file *file) ++{ ++ struct rockchip_iep *iep = video_drvdata(file); ++ struct iep_ctx *ctx = container_of(file->private_data, ++ struct iep_ctx, fh); ++ ++ mutex_lock(&iep->mutex); ++ ++ v4l2_fh_del(&ctx->fh); ++ v4l2_fh_exit(&ctx->fh); ++ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); ++ kfree(ctx); ++ ++ mutex_unlock(&iep->mutex); ++ return 0; ++} ++ ++static const struct v4l2_file_operations iep_fops = { ++ .owner = THIS_MODULE, ++ .open = iep_open, ++ .release = iep_release, ++ .poll = v4l2_m2m_fop_poll, ++ .unlocked_ioctl = video_ioctl2, ++ .mmap = v4l2_m2m_fop_mmap, ++}; ++ ++static int iep_querycap(struct file *file, void *priv, ++ struct v4l2_capability *cap) ++{ ++ strscpy(cap->driver, IEP_NAME, sizeof(cap->driver)); ++ strscpy(cap->card, IEP_NAME, sizeof(cap->card)); ++ snprintf(cap->bus_info, sizeof(cap->bus_info), ++ "platform:%s", IEP_NAME); ++ ++ return 0; ++} ++ ++static int iep_enum_fmt(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ struct iep_fmt *fmt; ++ ++ if (f->index < ARRAY_SIZE(formats)) { ++ fmt = &formats[f->index]; ++ f->pixelformat = fmt->fourcc; ++ ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int iep_enum_framesizes(struct file *file, void *priv, ++ struct v4l2_frmsizeenum *fsize) ++{ ++ if (fsize->index != 0) ++ return -EINVAL; ++ ++ if (!iep_check_pix_format(fsize->pixel_format)) ++ return -EINVAL; ++ ++ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; ++ ++ fsize->stepwise.min_width = IEP_MIN_WIDTH; ++ fsize->stepwise.max_width = IEP_MAX_WIDTH; ++ fsize->stepwise.step_width = 16; ++ ++ fsize->stepwise.min_height = IEP_MIN_HEIGHT; ++ fsize->stepwise.max_height = IEP_MAX_HEIGHT; ++ fsize->stepwise.step_height = 16; ++ ++ return 0; ++} ++ ++static inline struct iep_ctx *iep_file2ctx(struct file *file) ++{ ++ return container_of(file->private_data, struct iep_ctx, fh); ++} ++ ++static int iep_g_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ ++ f->fmt.pix = ctx->dst_fmt.pix; ++ ++ return 0; ++} ++ ++static int iep_g_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ ++ f->fmt.pix = ctx->src_fmt.pix; ++ ++ return 0; ++} ++ ++static int iep_try_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ f->fmt.pix.field = V4L2_FIELD_NONE; ++ iep_prepare_format(&f->fmt.pix); ++ ++ return 0; ++} ++ ++static int iep_try_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED) ++ f->fmt.pix.field = V4L2_FIELD_INTERLACED; ++ ++ iep_prepare_format(&f->fmt.pix); ++ ++ return 0; ++} ++ ++static int iep_s_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ struct vb2_queue *vq; ++ ++ int ret; ++ ++ ret = iep_try_fmt_vid_out(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ ctx->src_fmt.pix = f->fmt.pix; ++ ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); ++ ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->src_fmt.hw_fmt->uv_factor); ++ ++ /* Propagate colorspace information to capture. */ ++ ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace; ++ ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func; ++ ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc; ++ ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization; ++ ++ /* scaling is not supported */ ++ ctx->dst_fmt.pix.width = f->fmt.pix.width; ++ ctx->dst_fmt.pix.height = f->fmt.pix.height; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ ++ ctx->fmt_changed = true; ++ ++ return 0; ++} ++ ++static int iep_s_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ struct vb2_queue *vq; ++ int ret; ++ ++ ret = iep_try_fmt_vid_cap(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ /* scaling is not supported */ ++ f->fmt.pix.width = ctx->src_fmt.pix.width; ++ f->fmt.pix.height = ctx->src_fmt.pix.height; ++ ++ ctx->dst_fmt.pix = f->fmt.pix; ++ ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); ++ ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ ++ ctx->fmt_changed = true; ++ ++ return 0; ++} ++ ++static const struct v4l2_ioctl_ops iep_ioctl_ops = { ++ .vidioc_querycap = iep_querycap, ++ ++ .vidioc_enum_framesizes = iep_enum_framesizes, ++ ++ .vidioc_enum_fmt_vid_cap = iep_enum_fmt, ++ .vidioc_g_fmt_vid_cap = iep_g_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = iep_try_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = iep_s_fmt_vid_cap, ++ ++ .vidioc_enum_fmt_vid_out = iep_enum_fmt, ++ .vidioc_g_fmt_vid_out = iep_g_fmt_vid_out, ++ .vidioc_try_fmt_vid_out = iep_try_fmt_vid_out, ++ .vidioc_s_fmt_vid_out = iep_s_fmt_vid_out, ++ ++ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, ++ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, ++ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, ++ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, ++ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, ++ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, ++ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, ++ ++ .vidioc_streamon = v4l2_m2m_ioctl_streamon, ++ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, ++}; ++ ++static const struct video_device iep_video_device = { ++ .name = IEP_NAME, ++ .vfl_dir = VFL_DIR_M2M, ++ .fops = &iep_fops, ++ .ioctl_ops = &iep_ioctl_ops, ++ .minor = -1, ++ .release = video_device_release_empty, ++ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, ++}; ++ ++static int iep_parse_dt(struct rockchip_iep *iep) ++{ ++ int ret = 0; ++ ++ iep->axi_clk = devm_clk_get(iep->dev, "axi"); ++ if (IS_ERR(iep->axi_clk)) { ++ dev_err(iep->dev, "failed to get aclk clock\n"); ++ return PTR_ERR(iep->axi_clk); ++ } ++ ++ iep->ahb_clk = devm_clk_get(iep->dev, "ahb"); ++ if (IS_ERR(iep->ahb_clk)) { ++ dev_err(iep->dev, "failed to get hclk clock\n"); ++ return PTR_ERR(iep->ahb_clk); ++ } ++ ++ ret = clk_set_rate(iep->axi_clk, 300000000); ++ ++ if (ret) ++ dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n"); ++ ++ return ret; ++} ++ ++static irqreturn_t iep_isr(int irq, void *prv) ++{ ++ struct rockchip_iep *iep = prv; ++ struct iep_ctx *ctx; ++ u32 val; ++ enum vb2_buffer_state state = VB2_BUF_STATE_DONE; ++ ++ ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev); ++ if (!ctx) { ++ v4l2_err(&iep->v4l2_dev, ++ "Instance released before the end of transaction\n"); ++ return IRQ_NONE; ++ } ++ ++ /* ++ * The irq is shared with the iommu. If the runtime-pm state of the ++ * iep-device is disabled or the interrupt status doesn't match the ++ * expeceted mask the irq has been targeted to the iommu. ++ */ ++ ++ if (!pm_runtime_active(iep->dev) || ++ !(iep_read(iep, IEP_INT) & IEP_INT_MASK)) ++ return IRQ_NONE; ++ ++ /* disable interrupt - will be re-enabled at next iep_device_run */ ++ iep_mod(ctx->iep, IEP_INT, ++ IEP_INT_FRAME_DONE_EN, 0); ++ ++ iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR, ++ IEP_INT_FRAME_DONE_CLR); ++ ++ /* wait for all status regs to show "idle" */ ++ val = readl_poll_timeout(iep->regs + IEP_STATUS, val, ++ (val == 0), 100, IEP_TIMEOUT); ++ ++ if (val) { ++ dev_err(iep->dev, ++ "Failed to wait for job to finish: status: %u\n", val); ++ state = VB2_BUF_STATE_ERROR; ++ ctx->job_abort = true; ++ } ++ ++ iep_m2m_dst_bufs_done(ctx, state); ++ ++ ctx->field_bff = (ctx->dst_buffs_done % 2 == 0) ++ ? ctx->field_order_bff : !ctx->field_order_bff; ++ ++ if (ctx->dst_buffs_done == 2 || ctx->job_abort) { ++ if (ctx->prev_src_buf) ++ v4l2_m2m_buf_done(ctx->prev_src_buf, state); ++ ++ /* current src buff will be next prev */ ++ ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ ++ v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx); ++ ctx->dst_buffs_done = 0; ++ ++ } else { ++ iep_device_run(ctx); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int iep_probe(struct platform_device *pdev) ++{ ++ struct rockchip_iep *iep; ++ struct video_device *vfd; ++ struct resource *res; ++ int ret = 0; ++ int irq; ++ ++ if (!pdev->dev.of_node) ++ return -ENODEV; ++ ++ iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL); ++ if (!iep) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, iep); ++ iep->dev = &pdev->dev; ++ iep->vfd = iep_video_device; ++ ++ ret = iep_parse_dt(iep); ++ if (ret) ++ dev_err(&pdev->dev, "Unable to parse OF data\n"); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ iep->regs = devm_ioremap_resource(iep->dev, res); ++ if (IS_ERR(iep->regs)) { ++ ret = PTR_ERR(iep->regs); ++ goto err_put_clk; ++ } ++ ++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n"); ++ goto err_put_clk; ++ } ++ ++ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ ret = irq; ++ goto err_put_clk; ++ } ++ ++ /* IRQ is shared with IOMMU */ ++ ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED, ++ dev_name(iep->dev), iep); ++ if (ret < 0) { ++ dev_err(iep->dev, "failed to request irq\n"); ++ goto err_put_clk; ++ } ++ ++ mutex_init(&iep->mutex); ++ ++ ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev); ++ if (ret) { ++ dev_err(iep->dev, "Failed to register V4L2 device\n"); ++ ++ return ret; ++ } ++ ++ vfd = &iep->vfd; ++ vfd->lock = &iep->mutex; ++ vfd->v4l2_dev = &iep->v4l2_dev; ++ ++ snprintf(vfd->name, sizeof(vfd->name), "%s", ++ iep_video_device.name); ++ ++ video_set_drvdata(vfd, iep); ++ ++ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); ++ if (ret) { ++ v4l2_err(&iep->v4l2_dev, "Failed to register video device\n"); ++ ++ goto err_v4l2; ++ } ++ ++ v4l2_info(&iep->v4l2_dev, ++ "Device %s registered as /dev/video%d\n", vfd->name, vfd->num); ++ ++ iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops); ++ if (IS_ERR(iep->m2m_dev)) { ++ v4l2_err(&iep->v4l2_dev, ++ "Failed to initialize V4L2 M2M device\n"); ++ ret = PTR_ERR(iep->m2m_dev); ++ ++ goto err_video; ++ } ++ ++ pm_runtime_set_autosuspend_delay(iep->dev, 100); ++ pm_runtime_use_autosuspend(iep->dev); ++ pm_runtime_enable(iep->dev); ++ ++ return ret; ++ ++err_video: ++ video_unregister_device(&iep->vfd); ++err_v4l2: ++ v4l2_device_unregister(&iep->v4l2_dev); ++err_put_clk: ++ pm_runtime_dont_use_autosuspend(iep->dev); ++ pm_runtime_disable(iep->dev); ++ ++return ret; ++} ++ ++static int iep_remove(struct platform_device *pdev) ++{ ++ struct rockchip_iep *iep = platform_get_drvdata(pdev); ++ ++ pm_runtime_dont_use_autosuspend(iep->dev); ++ pm_runtime_disable(iep->dev); ++ ++ v4l2_m2m_release(iep->m2m_dev); ++ video_unregister_device(&iep->vfd); ++ v4l2_device_unregister(&iep->v4l2_dev); ++ ++ return 0; ++} ++ ++static int __maybe_unused iep_runtime_suspend(struct device *dev) ++{ ++ struct rockchip_iep *iep = dev_get_drvdata(dev); ++ ++ clk_disable_unprepare(iep->ahb_clk); ++ clk_disable_unprepare(iep->axi_clk); ++ ++ return 0; ++} ++ ++static int __maybe_unused iep_runtime_resume(struct device *dev) ++{ ++ struct rockchip_iep *iep; ++ int ret = 0; ++ ++ iep = dev_get_drvdata(dev); ++ ++ ret = clk_prepare_enable(iep->axi_clk); ++ if (ret) { ++ dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(iep->ahb_clk); ++ if (ret) { ++ dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret); ++ goto err_disable_axi_clk; ++ } ++ ++ return ret; ++ ++err_disable_axi_clk: ++ clk_disable_unprepare(iep->axi_clk); ++ return ret; ++} ++ ++static const struct dev_pm_ops iep_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++ SET_RUNTIME_PM_OPS(iep_runtime_suspend, ++ iep_runtime_resume, NULL) ++}; ++ ++static const struct of_device_id rockchip_iep_match[] = { ++ { ++ .compatible = "rockchip,rk3228-iep", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, rockchip_iep_match); ++ ++static struct platform_driver iep_pdrv = { ++ .probe = iep_probe, ++ .remove = iep_remove, ++ .driver = { ++ .name = IEP_NAME, ++ .pm = &iep_pm_ops, ++ .of_match_table = rockchip_iep_match, ++ }, ++}; ++ ++module_platform_driver(iep_pdrv); ++ ++MODULE_AUTHOR("Alex Bee "); ++MODULE_DESCRIPTION("Rockchip Image Enhancement Processor"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/media/platform/rockchip/iep/iep.h b/drivers/media/platform/rockchip/iep/iep.h +new file mode 100644 +index 000000000..7d9fc6162 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep.h +@@ -0,0 +1,112 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ */ ++#ifndef __IEP_H__ ++#define __IEP_H__ ++ ++#include ++#include ++#include ++#include ++ ++#define IEP_NAME "rockchip-iep" ++ ++/* Hardware limits */ ++#define IEP_MIN_WIDTH 320U ++#define IEP_MAX_WIDTH 1920U ++ ++#define IEP_MIN_HEIGHT 240U ++#define IEP_MAX_HEIGHT 1088U ++ ++/* Hardware defaults */ ++#define IEP_DEFAULT_WIDTH 320U ++#define IEP_DEFAULT_HEIGHT 240U ++ ++//ns ++#define IEP_TIMEOUT 250000 ++ ++struct iep_fmt { ++ u32 fourcc; ++ u8 depth; ++ u8 uv_factor; ++ u8 color_swap; ++ u8 hw_format; ++}; ++ ++struct iep_frm_fmt { ++ struct iep_fmt *hw_fmt; ++ struct v4l2_pix_format pix; ++ ++ unsigned int y_stride; ++ unsigned int uv_stride; ++}; ++ ++struct iep_ctx { ++ struct v4l2_fh fh; ++ struct rockchip_iep *iep; ++ ++ struct iep_frm_fmt src_fmt; ++ struct iep_frm_fmt dst_fmt; ++ ++ struct vb2_v4l2_buffer *prev_src_buf; ++ struct vb2_v4l2_buffer *dst0_buf; ++ struct vb2_v4l2_buffer *dst1_buf; ++ ++ u32 dst_sequence; ++ u32 src_sequence; ++ ++ /* bff = bottom field first */ ++ bool field_order_bff; ++ bool field_bff; ++ ++ unsigned int dst_buffs_done; ++ ++ bool fmt_changed; ++ bool job_abort; ++}; ++ ++struct rockchip_iep { ++ struct v4l2_device v4l2_dev; ++ struct v4l2_m2m_dev *m2m_dev; ++ struct video_device vfd; ++ ++ struct device *dev; ++ ++ void __iomem *regs; ++ ++ struct clk *axi_clk; ++ struct clk *ahb_clk; ++ ++ /* vfd lock */ ++ struct mutex mutex; ++}; ++ ++static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value) ++{ ++ writel(value, iep->regs + reg); ++}; ++ ++static inline u32 iep_read(struct rockchip_iep *iep, u32 reg) ++{ ++ return readl(iep->regs + reg); ++}; ++ ++static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg, ++ u32 shadow_reg, u32 mask, u32 val) ++{ ++ u32 temp = iep_read(iep, shadow_reg) & ~(mask); ++ ++ temp |= val & mask; ++ iep_write(iep, reg, temp); ++}; ++ ++static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val) ++{ ++ iep_shadow_mod(iep, reg, reg, mask, val); ++}; ++ ++#endif +-- +2.30.2 + +diff --git a/drivers/media/platform/rockchip/iep/Kconfig b/drivers/media/platform/rockchip/iep/Kconfig +new file mode 100644 +index 00000000000..e513fa7f45f +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/Kconfig +@@ -0,0 +1,13 @@ ++config VIDEO_ROCKCHIP_IEP ++ tristate "Rockchip Image Enhancement Processor" ++ depends on VIDEO_DEV && VIDEO_V4L2 ++ depends on ARCH_ROCKCHIP || COMPILE_TEST ++ select VIDEOBUF2_DMA_CONTIG ++ select V4L2_MEM2MEM_DEV ++ help ++ This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP) ++ found in most Rockchip RK3xxx SoCs. ++ Rockchip IEP supports various enhancement operations for RGB and YUV ++ images. The driver currently implements YUV deinterlacing only. ++ To compile this driver as a module, choose M here: the module ++ will be called rockchip-iep +diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig +index b41d3960c1b..862590be791 100644 +--- a/drivers/media/platform/rockchip/Kconfig ++++ b/drivers/media/platform/rockchip/Kconfig +@@ -4,3 +4,4 @@ comment "Rockchip media platform drivers" + + source "drivers/media/platform/rockchip/rga/Kconfig" + source "drivers/media/platform/rockchip/rkisp1/Kconfig" ++source "drivers/media/platform/rockchip/iep/Kconfig" +diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile +index 4f782b876ac..be8015c6d9e 100644 +--- a/drivers/media/platform/rockchip/Makefile ++++ b/drivers/media/platform/rockchip/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-y += rga/ + obj-y += rkisp1/ ++obj-y += iep/ diff --git a/patch/kernel/archive/station-p2-5.18/0650-board-roc-rk3399-pc-fix-fusb302-compatible.patch b/patch/kernel/archive/station-p2-5.19/330-board-roc-rk3399-pc-fix-fusb302-compatible.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0650-board-roc-rk3399-pc-fix-fusb302-compatible.patch rename to patch/kernel/archive/station-p2-5.19/330-board-roc-rk3399-pc-fix-fusb302-compatible.patch diff --git a/patch/kernel/archive/station-p2-5.18/0660-general-add-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/archive/station-p2-5.19/340-general-add-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0660-general-add-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/archive/station-p2-5.19/340-general-add-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/station-p2-5.19/350-general-add-miniDP-dt-doc.patch b/patch/kernel/archive/station-p2-5.19/350-general-add-miniDP-dt-doc.patch new file mode 100644 index 000000000..58b1a9a7a --- /dev/null +++ b/patch/kernel/archive/station-p2-5.19/350-general-add-miniDP-dt-doc.patch @@ -0,0 +1,73 @@ +diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml +new file mode 100644 +index 000000000000..8110fbe2ddc2 +--- /dev/null ++++ b/Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml +@@ -0,0 +1,66 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/extcon/extcon-usbc-virtual-pd.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Type-C Virtual PD extcon ++ ++maintainers: ++ - Jagan Teki ++ ++description: | ++ USB Type-C protocol supports various modes of operations includes PD, ++ USB3, and Altmode. If the platform design supports a Type-C connector ++ then configuring these modes can be done via enumeration. ++ ++ However, there are some platforms that design these modes as separate ++ protocol connectors like design Display Port from on-chip USB3 controller. ++ So we can access Type-C Altmode Display Port via onboard Display Port ++ connector instead of a Type-C connector. These kinds of platforms require ++ an explicit extcon driver in order to handle Power Delivery and ++ Port Detection. ++ ++properties: ++ compatible: ++ const: linux,extcon-usbc-virtual-pd ++ ++ det-gpios: ++ description: Detect GPIO pin. Pin can be Display Port Detect or USB ID. ++ maxItems: 1 ++ ++ vpd-polarity: ++ description: USB Type-C Polarity. false for Normal and true for Flip. ++ type: boolean ++ ++ vpd-super-speed: ++ description: USB Super Speed. false for USB2 and true for USB3. ++ type: boolean ++ ++ vpd-data-role: ++ description: USB Data roles for Virtual Type-C. ++ $ref: /schemas/types.yaml#definitions/string ++ ++ enum: ++ - host ++ - device ++ - display-port ++ ++required: ++ - compatible ++ - det-gpios ++ - vpd-data-role ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ virtual_pd: virtual-pd { ++ compatible = "linux,extcon-usbc-virtual-pd"; ++ det-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; ++ vpd-data-role = "display-port"; ++ vpd-super-speed; ++ }; + diff --git a/patch/kernel/archive/station-p2-5.19/360-general-add-miniDP-virtual-extcon.patch b/patch/kernel/archive/station-p2-5.19/360-general-add-miniDP-virtual-extcon.patch new file mode 100644 index 000000000..07adbb503 --- /dev/null +++ b/patch/kernel/archive/station-p2-5.19/360-general-add-miniDP-virtual-extcon.patch @@ -0,0 +1,337 @@ +diff --git a/MAINTAINERS b/MAINTAINERS +index 68f21d46614c..aeb161b19dae 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -6466,6 +6466,12 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git + F: Documentation/filesystems/ext4/ + F: fs/ext4/ + ++EXTCON DRIVER FOR TYPE-C VIRTUAL PD ++M: Jagan Teki ++S: Maintained ++F: Documentation/devicetree/bindings/extcon/extcon-usbc-virtual-pd.yaml ++F: drivers/extcon/extcon-usbc-virtual-pd.c ++ + Extended Verification Module (EVM) + M: Mimi Zohar + L: linux-integrity@vger.kernel.org +diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig +index aac507bff135..edd6c3c52699 100644 +--- a/drivers/extcon/Kconfig ++++ b/drivers/extcon/Kconfig +@@ -186,4 +186,14 @@ config EXTCON_USBC_CROS_EC + Say Y here to enable USB Type C cable detection extcon support when + using Chrome OS EC based USB Type-C ports. + ++config EXTCON_USBC_VIRTUAL_PD ++ tristate "Virtual Type-C PD EXTCON support" ++ depends on GPIOLIB || COMPILE_TEST ++ help ++ Say Y here to enable Virtual Type-C PD extcon driver support, if ++ hardware platform designed Type-C modes separately. ++ ++ Example, of designing Display Port separately from Type-C Altmode ++ instead of accessing Altmode Display Port in Type-C connector. ++ + endif +diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile +index 52096fd8a216..c35191eef0e1 100644 +--- a/drivers/extcon/Makefile ++++ b/drivers/extcon/Makefile +@@ -25,3 +25,4 @@ obj-$(CONFIG_EXTCON_RT8973A) += extcon-rt8973a.o + obj-$(CONFIG_EXTCON_USB_GPIO) += extcon-usb-gpio.o + obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o + obj-$(CONFIG_EXTCON_USBC_TUSB320) += extcon-usbc-tusb320.o ++obj-$(CONFIG_EXTCON_USBC_VIRTUAL_PD) += extcon-usbc-virtual-pd.o +diff --git a/drivers/extcon/extcon-usbc-virtual-pd.c b/drivers/extcon/extcon-usbc-virtual-pd.c +new file mode 100644 +index 000000000000..e0713670e33d +--- /dev/null ++++ b/drivers/extcon/extcon-usbc-virtual-pd.c +@@ -0,0 +1,285 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Type-C Virtual PD Extcon driver ++ * ++ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2019 Radxa Limited ++ * Copyright (c) 2019 Amarula Solutions(India) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const unsigned int vpd_cable[] = { ++ EXTCON_USB, ++ EXTCON_USB_HOST, ++ EXTCON_DISP_DP, ++ EXTCON_NONE, ++}; ++ ++enum vpd_data_role { ++ DR_NONE, ++ DR_HOST, ++ DR_DEVICE, ++ DR_DISPLAY_PORT, ++}; ++ ++enum vpd_polarity { ++ POLARITY_NORMAL, ++ POLARITY_FLIP, ++}; ++ ++enum vpd_usb_ss { ++ USB_SS_USB2, ++ USB_SS_USB3, ++}; ++ ++struct vpd_extcon { ++ struct device *dev; ++ struct extcon_dev *extcon; ++ struct gpio_desc *det_gpio; ++ ++ u8 polarity; ++ u8 usb_ss; ++ enum vpd_data_role data_role; ++ ++ int irq; ++ bool enable_irq; ++ struct work_struct work; ++ struct delayed_work irq_work; ++}; ++ ++static void vpd_extcon_irq_work(struct work_struct *work) ++{ ++ struct vpd_extcon *vpd = container_of(work, struct vpd_extcon, irq_work.work); ++ bool host_connected = false, device_connected = false, dp_connected = false; ++ union extcon_property_value property; ++ int det; ++ ++ det = vpd->det_gpio ? gpiod_get_raw_value(vpd->det_gpio) : 0; ++ if (det) { ++ device_connected = (vpd->data_role == DR_DEVICE) ? true : false; ++ host_connected = (vpd->data_role == DR_HOST) ? true : false; ++ dp_connected = (vpd->data_role == DR_DISPLAY_PORT) ? true : false; ++ } ++ ++ extcon_set_state(vpd->extcon, EXTCON_USB, host_connected); ++ extcon_set_state(vpd->extcon, EXTCON_USB_HOST, device_connected); ++ extcon_set_state(vpd->extcon, EXTCON_DISP_DP, dp_connected); ++ ++ property.intval = vpd->polarity; ++ extcon_set_property(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ extcon_set_property(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ extcon_set_property(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY, property); ++ ++ property.intval = vpd->usb_ss; ++ extcon_set_property(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS, property); ++ extcon_set_property(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS, property); ++ extcon_set_property(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS, property); ++ ++ extcon_sync(vpd->extcon, EXTCON_USB); ++ extcon_sync(vpd->extcon, EXTCON_USB_HOST); ++ extcon_sync(vpd->extcon, EXTCON_DISP_DP); ++} ++ ++static irqreturn_t vpd_extcon_irq_handler(int irq, void *dev_id) ++{ ++ struct vpd_extcon *vpd = dev_id; ++ ++ schedule_delayed_work(&vpd->irq_work, msecs_to_jiffies(10)); ++ ++ return IRQ_HANDLED; ++} ++ ++static enum vpd_data_role vpd_extcon_data_role(struct vpd_extcon *vpd) ++{ ++ const char *const data_roles[] = { ++ [DR_NONE] = "NONE", ++ [DR_HOST] = "host", ++ [DR_DEVICE] = "device", ++ [DR_DISPLAY_PORT] = "display-port", ++ }; ++ struct device *dev = vpd->dev; ++ int ret; ++ const char *dr; ++ ++ ret = device_property_read_string(dev, "vpd-data-role", &dr); ++ if (ret < 0) ++ return DR_NONE; ++ ++ ret = match_string(data_roles, ARRAY_SIZE(data_roles), dr); ++ ++ return (ret < 0) ? DR_NONE : ret; ++} ++ ++static int vpd_extcon_parse_dts(struct vpd_extcon *vpd) ++{ ++ struct device *dev = vpd->dev; ++ bool val = false; ++ int ret; ++ ++ val = device_property_read_bool(dev, "vpd-polarity"); ++ if (val) ++ vpd->polarity = POLARITY_FLIP; ++ else ++ vpd->polarity = POLARITY_NORMAL; ++ ++ val = device_property_read_bool(dev, "vpd-super-speed"); ++ if (val) ++ vpd->usb_ss = USB_SS_USB3; ++ else ++ vpd->usb_ss = USB_SS_USB2; ++ ++ vpd->data_role = vpd_extcon_data_role(vpd); ++ ++ vpd->det_gpio = devm_gpiod_get_optional(dev, "det", GPIOD_OUT_LOW); ++ if (IS_ERR(vpd->det_gpio)) { ++ ret = PTR_ERR(vpd->det_gpio); ++ dev_warn(dev, "failed to get det gpio: %d\n", ret); ++ return ret; ++ } ++ ++ vpd->irq = gpiod_to_irq(vpd->det_gpio); ++ if (vpd->irq < 0) { ++ dev_err(dev, "failed to get irq for gpio: %d\n", vpd->irq); ++ return vpd->irq; ++ } ++ ++ ret = devm_request_threaded_irq(dev, vpd->irq, NULL, ++ vpd_extcon_irq_handler, ++ IRQF_TRIGGER_FALLING | ++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, ++ NULL, vpd); ++ if (ret) ++ dev_err(dev, "failed to request gpio irq\n"); ++ ++ return ret; ++} ++ ++static int vpd_extcon_probe(struct platform_device *pdev) ++{ ++ struct vpd_extcon *vpd; ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ vpd = devm_kzalloc(dev, sizeof(*vpd), GFP_KERNEL); ++ if (!vpd) ++ return -ENOMEM; ++ ++ vpd->dev = dev; ++ ret = vpd_extcon_parse_dts(vpd); ++ if (ret) ++ return ret; ++ ++ INIT_DELAYED_WORK(&vpd->irq_work, vpd_extcon_irq_work); ++ ++ vpd->extcon = devm_extcon_dev_allocate(dev, vpd_cable); ++ if (IS_ERR(vpd->extcon)) { ++ dev_err(dev, "allocat extcon failed\n"); ++ return PTR_ERR(vpd->extcon); ++ } ++ ++ ret = devm_extcon_dev_register(dev, vpd->extcon); ++ if (ret) { ++ dev_err(dev, "register extcon failed: %d\n", ret); ++ return ret; ++ } ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_VBUS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_VBUS); ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_USB_HOST, ++ EXTCON_PROP_USB_SS); ++ ++ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_SS); ++ extcon_set_property_capability(vpd->extcon, EXTCON_DISP_DP, ++ EXTCON_PROP_USB_TYPEC_POLARITY); ++ ++ platform_set_drvdata(pdev, vpd); ++ ++ vpd_extcon_irq_work(&vpd->irq_work.work); ++ ++ return 0; ++} ++ ++static int vpd_extcon_remove(struct platform_device *pdev) ++{ ++ struct vpd_extcon *vpd = platform_get_drvdata(pdev); ++ ++ cancel_delayed_work_sync(&vpd->irq_work); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int vpd_extcon_suspend(struct device *dev) ++{ ++ struct vpd_extcon *vpd = dev_get_drvdata(dev); ++ ++ if (!vpd->enable_irq) { ++ disable_irq_nosync(vpd->irq); ++ vpd->enable_irq = true; ++ } ++ ++ return 0; ++} ++ ++static int vpd_extcon_resume(struct device *dev) ++{ ++ struct vpd_extcon *vpd = dev_get_drvdata(dev); ++ ++ if (vpd->enable_irq) { ++ enable_irq(vpd->irq); ++ vpd->enable_irq = false; ++ } ++ ++ return 0; ++} ++#endif ++ ++static SIMPLE_DEV_PM_OPS(vpd_extcon_pm_ops, ++ vpd_extcon_suspend, vpd_extcon_resume); ++ ++static const struct of_device_id vpd_extcon_dt_match[] = { ++ { .compatible = "linux,extcon-usbc-virtual-pd", }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver vpd_extcon_driver = { ++ .probe = vpd_extcon_probe, ++ .remove = vpd_extcon_remove, ++ .driver = { ++ .name = "extcon-usbc-virtual-pd", ++ .pm = &vpd_extcon_pm_ops, ++ .of_match_table = vpd_extcon_dt_match, ++ }, ++}; ++ ++module_platform_driver(vpd_extcon_driver); ++ ++MODULE_AUTHOR("Jagan Teki "); ++MODULE_DESCRIPTION("Type-C Virtual PD extcon driver"); ++MODULE_LICENSE("GPL v2"); + diff --git a/patch/kernel/archive/station-p2-5.18/0670-general-add-overlay-compilation-support.patch b/patch/kernel/archive/station-p2-5.19/370-general-add-overlay-compilation-support.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0670-general-add-overlay-compilation-support.patch rename to patch/kernel/archive/station-p2-5.19/370-general-add-overlay-compilation-support.patch diff --git a/patch/kernel/archive/station-p2-5.18/0680-general-add-overlay-configfs.patch b/patch/kernel/archive/station-p2-5.19/380-general-add-overlay-configfs.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0680-general-add-overlay-configfs.patch rename to patch/kernel/archive/station-p2-5.19/380-general-add-overlay-configfs.patch diff --git a/patch/kernel/archive/station-p2-5.19/390-general-add-pll-hdmi-timings.patch b/patch/kernel/archive/station-p2-5.19/390-general-add-pll-hdmi-timings.patch new file mode 100644 index 000000000..deb39113c --- /dev/null +++ b/patch/kernel/archive/station-p2-5.19/390-general-add-pll-hdmi-timings.patch @@ -0,0 +1,82 @@ +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 9ca20c947..ca91a01f3 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -316,6 +316,77 @@ static const struct pre_pll_config pre_pll_cfg_table[] = { + {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0}, + {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B}, + {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0}, ++ { 25175000, 25175000, 30, 1007, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ { 31500000, 31500000, 1, 21, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ { 33750000, 33750000, 1, 45, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ { 35500000, 35500000, 3, 71, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ { 36000000, 36000000, 1, 12, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ { 49500000, 49500000, 1, 33, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ { 50000000, 50000000, 3, 50, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ { 56250000, 56250000, 1, 75, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ { 65000000, 65000000, 3, 65, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ { 68250000, 68250000, 1, 91, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ { 71000000, 71000000, 3, 71, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ { 72000000, 72000000, 1, 24, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ { 73250000, 73250000, 3, 293, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ { 75000000, 75000000, 1, 25, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ { 78750000, 78750000, 1, 105, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ { 79500000, 79500000, 1, 53, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ { 83500000, 83500000, 3, 167, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ { 85500000, 85500000, 1, 57, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ { 88750000, 88750000, 3, 355, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ { 94500000, 94500000, 1, 63, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {101000000, 101000000, 3, 101, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {102250000, 102250000, 3, 409, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {106500000, 106500000, 1, 71, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {108000000, 108000000, 1, 36, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {115500000, 115500000, 1, 77, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {117500000, 117500000, 3, 235, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {119000000, 119000000, 3, 119, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {121750000, 121750000, 3, 487, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {122500000, 122500000, 3, 245, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {135000000, 135000000, 1, 45, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {136750000, 136750000, 3, 547, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {140250000, 140250000, 1, 187, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {146250000, 146250000, 1, 195, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {148250000, 148250000, 3, 593, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {154000000, 154000000, 3, 154, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {156000000, 156000000, 1, 52, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {156750000, 156750000, 1, 209, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {157000000, 157000000, 3, 157, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {157500000, 157500000, 1, 105, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {162000000, 162000000, 1, 54, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {175500000, 175500000, 1, 117, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {179500000, 179500000, 3, 359, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {182750000, 182750000, 3, 731, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {187000000, 187000000, 3, 187, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {187250000, 187250000, 3, 749, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {189000000, 189000000, 1, 63, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {193250000, 193250000, 3, 773, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {202500000, 202500000, 1, 135, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {204750000, 204750000, 1, 273, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {208000000, 208000000, 3, 208, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {214750000, 214750000, 3, 859, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {218250000, 218250000, 1, 291, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {229500000, 229500000, 1, 153, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {234000000, 234000000, 1, 78, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {241500000, 241500000, 1, 161, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {245250000, 245250000, 1, 327, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {245500000, 245500000, 3, 491, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {261000000, 261000000, 1, 87, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {268250000, 268250000, 3, 1073, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {268500000, 268500000, 1, 179, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {281250000, 281250000, 1, 375, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {288000000, 288000000, 1, 96, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {312250000, 312250000, 3, 1249, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {317000000, 317000000, 3, 317, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {333250000, 333250000, 3, 1333, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {348500000, 348500000, 3, 697, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {356500000, 356500000, 3, 713, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {380500000, 380500000, 3, 761, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {443250000, 443250000, 1, 591, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {505250000, 505250000, 3, 2021, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ {552750000, 552750000, 1, 737, 1, 2, 2, 1, 2, 3, 4, 0, 0}, + { /* sentinel */ } + }; + diff --git a/patch/kernel/archive/station-p2-5.19/400-general-bluetooth-02-add-support-for-RTL8723CS.patch b/patch/kernel/archive/station-p2-5.19/400-general-bluetooth-02-add-support-for-RTL8723CS.patch new file mode 100644 index 000000000..afe31fb10 --- /dev/null +++ b/patch/kernel/archive/station-p2-5.19/400-general-bluetooth-02-add-support-for-RTL8723CS.patch @@ -0,0 +1,266 @@ +From 26e61cffb09c1f5519a4eeb9d9e99239d58b6c2d Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Thu, 1 Jul 2021 11:22:23 +0200 +Subject: [PATCH 302/467] Bluetooth: btrtl: add support for the RTL8723CS + +The Realtek RTL8723CS is SDIO WiFi chip. It also contains a Bluetooth +module which is connected via UART to the host. + +It shares lmp subversion with 8703B, so Realtek's userspace +initialization tool (rtk_hciattach) differentiates varieties of RTL8723CS +(CG, VF, XX) with RTL8703B using vendor's command to read chip type. + +Also this chip declares support for some features it doesn't support +so add a quirk to indicate that these features are broken. + +Signed-off-by: Vasily Khoruzhick +Signed-off-by: Ondrej Jirman +--- + drivers/bluetooth/btrtl.c | 119 +++++++++++++++++++++++++++++++++++++- + drivers/bluetooth/btrtl.h | 5 ++ + 2 files changed, 121 insertions(+), 3 deletions(-) + +diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c +index 1f8afa024..fd293a9c4 100644 +--- a/drivers/bluetooth/btrtl.c ++++ b/drivers/bluetooth/btrtl.c +@@ -17,7 +17,12 @@ + + #define VERSION "0.1" + ++#define RTL_CHIP_8723CS_CG 3 ++#define RTL_CHIP_8723CS_VF 4 ++#define RTL_CHIP_8723CS_XX 5 + #define RTL_EPATCH_SIGNATURE "Realtech" ++#define RTL_ROM_LMP_3499 0x3499 ++#define RTL_ROM_LMP_8703B 0x8703 + #define RTL_ROM_LMP_8723A 0x1200 + #define RTL_ROM_LMP_8723B 0x8723 + #define RTL_ROM_LMP_8821A 0x8821 +@@ -30,6 +35,7 @@ + #define IC_MATCH_FL_HCIREV (1 << 1) + #define IC_MATCH_FL_HCIVER (1 << 2) + #define IC_MATCH_FL_HCIBUS (1 << 3) ++#define IC_MATCH_FL_CHIP_TYPE (1 << 4) + #define IC_INFO(lmps, hcir, hciv, bus) \ + .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV | \ + IC_MATCH_FL_HCIVER | IC_MATCH_FL_HCIBUS, \ +@@ -57,6 +63,7 @@ struct id_table { + __u16 hci_rev; + __u8 hci_ver; + __u8 hci_bus; ++ __u8 chip_type; + bool config_needed; + bool has_rom_version; + char *fw_name; +@@ -96,6 +103,39 @@ static const struct id_table ic_id_table[] = { + .fw_name = "rtl_bt/rtl8723b_fw.bin", + .cfg_name = "rtl_bt/rtl8723b_config" }, + ++ /* 8723CS-CG */ ++ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | ++ IC_MATCH_FL_HCIBUS, ++ .lmp_subver = RTL_ROM_LMP_8703B, ++ .chip_type = RTL_CHIP_8723CS_CG, ++ .hci_bus = HCI_UART, ++ .config_needed = true, ++ .has_rom_version = true, ++ .fw_name = "rtl_bt/rtl8723cs_cg_fw.bin", ++ .cfg_name = "rtl_bt/rtl8723cs_cg_config" }, ++ ++ /* 8723CS-VF */ ++ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | ++ IC_MATCH_FL_HCIBUS, ++ .lmp_subver = RTL_ROM_LMP_8703B, ++ .chip_type = RTL_CHIP_8723CS_VF, ++ .hci_bus = HCI_UART, ++ .config_needed = true, ++ .has_rom_version = true, ++ .fw_name = "rtl_bt/rtl8723cs_vf_fw.bin", ++ .cfg_name = "rtl_bt/rtl8723cs_vf_config" }, ++ ++ /* 8723CS-XX */ ++ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | ++ IC_MATCH_FL_HCIBUS, ++ .lmp_subver = RTL_ROM_LMP_8703B, ++ .chip_type = RTL_CHIP_8723CS_XX, ++ .hci_bus = HCI_UART, ++ .config_needed = true, ++ .has_rom_version = true, ++ .fw_name = "rtl_bt/rtl8723cs_xx_fw.bin", ++ .cfg_name = "rtl_bt/rtl8723cs_xx_config" }, ++ + /* 8723D */ + { IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_USB), + .config_needed = true, +@@ -175,7 +215,8 @@ static const struct id_table ic_id_table[] = { + }; + + static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev, +- u8 hci_ver, u8 hci_bus) ++ u8 hci_ver, u8 hci_bus, ++ u8 chip_type) + { + int i; + +@@ -192,6 +233,9 @@ static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev, + if ((ic_id_table[i].match_flags & IC_MATCH_FL_HCIBUS) && + (ic_id_table[i].hci_bus != hci_bus)) + continue; ++ if ((ic_id_table[i].match_flags & IC_MATCH_FL_CHIP_TYPE) && ++ (ic_id_table[i].chip_type != chip_type)) ++ continue; + + break; + } +@@ -274,6 +318,7 @@ static int rtlbt_parse_firmware(struct hci_dev *hdev, + { RTL_ROM_LMP_8723B, 1 }, + { RTL_ROM_LMP_8821A, 2 }, + { RTL_ROM_LMP_8761A, 3 }, ++ { RTL_ROM_LMP_8703B, 7 }, + { RTL_ROM_LMP_8822B, 8 }, + { RTL_ROM_LMP_8723B, 9 }, /* 8723D */ + { RTL_ROM_LMP_8821A, 10 }, /* 8821C */ +@@ -552,6 +597,48 @@ static int btrtl_setup_rtl8723b(struct hci_dev *hdev, + return ret; + } + ++static bool rtl_has_chip_type(u16 lmp_subver) ++{ ++ switch (lmp_subver) { ++ case RTL_ROM_LMP_8703B: ++ return true; ++ default: ++ break; ++ } ++ ++ return false; ++} ++ ++static int rtl_read_chip_type(struct hci_dev *hdev, u8 *type) ++{ ++ struct rtl_chip_type_evt *chip_type; ++ struct sk_buff *skb; ++ const unsigned char cmd_buf[] = {0x00, 0x94, 0xa0, 0x00, 0xb0}; ++ ++ /* Read RTL chip type command */ ++ skb = __hci_cmd_sync(hdev, 0xfc61, 5, cmd_buf, HCI_INIT_TIMEOUT); ++ if (IS_ERR(skb)) { ++ rtl_dev_err(hdev, "Read chip type failed (%ld)", ++ PTR_ERR(skb)); ++ return PTR_ERR(skb); ++ } ++ ++ if (skb->len != sizeof(*chip_type)) { ++ rtl_dev_err(hdev, "RTL chip type event length mismatch"); ++ kfree_skb(skb); ++ return -EIO; ++ } ++ ++ chip_type = (struct rtl_chip_type_evt *)skb->data; ++ rtl_dev_info(hdev, "chip_type status=%x type=%x", ++ chip_type->status, chip_type->type); ++ ++ *type = chip_type->type & 0x0f; ++ ++ kfree_skb(skb); ++ return 0; ++} ++ + void btrtl_free(struct btrtl_device_info *btrtl_dev) + { + kvfree(btrtl_dev->fw_data); +@@ -568,7 +655,7 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev, + struct hci_rp_read_local_version *resp; + char cfg_name[40]; + u16 hci_rev, lmp_subver; +- u8 hci_ver; ++ u8 hci_ver, chip_type = 0; + int ret; + u16 opcode; + u8 cmd[2]; +@@ -638,8 +725,14 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev, + out_free: + kfree_skb(skb); + ++ if (rtl_has_chip_type(lmp_subver)) { ++ ret = rtl_read_chip_type(hdev, &chip_type); ++ if (ret) ++ goto err_free; ++ } ++ + btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver, +- hdev->bus); ++ hdev->bus, chip_type); + + if (!btrtl_dev->ic_info) { + rtl_dev_info(hdev, "unknown IC info, lmp subver %04x, hci rev %04x, hci ver %04x", +@@ -757,7 +757,7 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev, + lmp_subver = le16_to_cpu(resp->lmp_subver); + + btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver, +- hdev->bus); ++ hdev->bus, chip_type); + } + out_free: + kfree_skb(skb); +@@ -722,6 +815,7 @@ int btrtl_download_firmware(struct hci_dev *hdev, + case RTL_ROM_LMP_8761A: + case RTL_ROM_LMP_8822B: + case RTL_ROM_LMP_8852A: ++ case RTL_ROM_LMP_8703B: + return btrtl_setup_rtl8723b(hdev, btrtl_dev); + default: + rtl_dev_info(hdev, "assuming no firmware upload needed"); +@@ -752,6 +846,19 @@ void btrtl_set_quirks(struct hci_dev *hdev, struct btrtl_device_info *btrtl_dev) + rtl_dev_dbg(hdev, "WBS supported not enabled."); + break; + } ++ ++ switch (btrtl_dev->ic_info->lmp_subver) { ++ case RTL_ROM_LMP_8703B: ++ /* 8723CS reports two pages for local ext features, ++ * but it doesn't support any features from page 2 - ++ * it either responds with garbage or with error status ++ */ ++ set_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE, ++ &hdev->quirks); ++ break; ++ default: ++ break; ++ } + } + EXPORT_SYMBOL_GPL(btrtl_set_quirks); + +@@ -910,6 +1017,12 @@ MODULE_FIRMWARE("rtl_bt/rtl8723b_fw.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723b_config.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723bs_fw.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723bs_config.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_fw.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_config.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_fw.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_config.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_fw.bin"); ++MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_config.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723ds_fw.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8723ds_config.bin"); + MODULE_FIRMWARE("rtl_bt/rtl8761a_fw.bin"); +diff --git a/drivers/bluetooth/btrtl.h b/drivers/bluetooth/btrtl.h +index 2c441bda3..1c6282241 100644 +--- a/drivers/bluetooth/btrtl.h ++++ b/drivers/bluetooth/btrtl.h +@@ -14,6 +14,11 @@ + + struct btrtl_device_info; + ++struct rtl_chip_type_evt { ++ __u8 status; ++ __u8 type; ++} __packed; ++ + struct rtl_download_cmd { + __u8 index; + __u8 data[RTL_FRAG_LEN]; +-- +2.34.0 + diff --git a/patch/kernel/archive/station-p2-5.19/410-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch b/patch/kernel/archive/station-p2-5.19/410-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch new file mode 100644 index 000000000..058ea2c39 --- /dev/null +++ b/patch/kernel/archive/station-p2-5.19/410-general-bluetooth-03-hci_h5-add-binding-RTL8723CS.patch @@ -0,0 +1,31 @@ +From 8fc0422773dc5274fa32e2a5a6ce2e1f0a96d78c Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Wed, 31 Oct 2018 20:07:41 -0700 +Subject: [PATCH 304/467] Bluetooth: hci_h5: Add support for binding RTL8723CS + with device tree + +RTL8723CS is often used in ARM boards, so add ability to bind it +using device tree. + +Signed-off-by: Vasily Khoruzhick +Signed-off-by: Ondrej Jirman +--- + drivers/bluetooth/hci_h5.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c +index d49a39d17..c9b54335a 100644 +--- a/drivers/bluetooth/hci_h5.c ++++ b/drivers/bluetooth/hci_h5.c +@@ -1100,6 +1100,8 @@ static const struct of_device_id rtl_bluetooth_of_match[] = { + .data = (const void *)&h5_data_rtl8723bs }, + { .compatible = "realtek,rtl8723ds-bt", + .data = (const void *)&h5_data_rtl8723bs }, ++ { .compatible = "realtek,rtl8723cs-bt", ++ .data = (const void *)&h5_data_rtl8723bs }, + #endif + { }, + }; +-- +2.34.0 + diff --git a/patch/kernel/archive/station-p2-5.19/420-general-bluetooth-04-add-rtl8703bs.patch b/patch/kernel/archive/station-p2-5.19/420-general-bluetooth-04-add-rtl8703bs.patch new file mode 100644 index 000000000..474db44ec --- /dev/null +++ b/patch/kernel/archive/station-p2-5.19/420-general-bluetooth-04-add-rtl8703bs.patch @@ -0,0 +1,42 @@ +From f0c05140b92cca447cd55a93ad4de141d0f117f1 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Thu, 9 Dec 2021 22:47:36 +0000 +Subject: [PATCH] rtl8703bs: add chip type to list and info block + +--- + drivers/bluetooth/btrtl.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c +index ad4085eede4..2c227bf4e00 100644 +--- a/drivers/bluetooth/btrtl.c ++++ b/drivers/bluetooth/btrtl.c +@@ -20,6 +20,7 @@ + #define RTL_CHIP_8723CS_CG 3 + #define RTL_CHIP_8723CS_VF 4 + #define RTL_CHIP_8723CS_XX 5 ++#define RTL_CHIP_8703BS 7 + #define RTL_EPATCH_SIGNATURE "Realtech" + #define RTL_ROM_LMP_3499 0x3499 + #define RTL_ROM_LMP_8703B 0x8703 +@@ -136,6 +137,17 @@ static const struct id_table ic_id_table[] = { + .fw_name = "rtl_bt/rtl8723cs_xx_fw.bin", + .cfg_name = "rtl_bt/rtl8723cs_xx_config" }, + ++ /* 8703BS */ ++ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | ++ IC_MATCH_FL_HCIBUS, ++ .lmp_subver = RTL_ROM_LMP_8703B, ++ .chip_type = RTL_CHIP_8703BS, ++ .hci_bus = HCI_UART, ++ .config_needed = true, ++ .has_rom_version = true, ++ .fw_name = "rtl_bt/rtl8723cs_xx_fw.bin", ++ .cfg_name = "rtl_bt/rtl8723cs_xx_config" }, ++ + /* 8723D */ + { IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_USB), + .config_needed = true, +-- +2.30.2 + diff --git a/patch/kernel/archive/station-p2-5.19/430-general-bluetooth-add-new-quirk.patch b/patch/kernel/archive/station-p2-5.19/430-general-bluetooth-add-new-quirk.patch new file mode 100644 index 000000000..a4614e12b --- /dev/null +++ b/patch/kernel/archive/station-p2-5.19/430-general-bluetooth-add-new-quirk.patch @@ -0,0 +1,53 @@ +From f60f1605f5056d543e49fc625ffeeb05621f2ad3 Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Wed, 31 Oct 2018 19:40:18 -0700 +Subject: Bluetooth: Add new quirk for broken local ext features max_page + +Some adapters (e.g. RTL8723CS) advertise that they have more than +2 pages for local ext features, but they don't support any features +declared in these pages. RTL8723CS reports max_page = 2 and declares +support for sync train and secure connection, but it responds with +either garbage or with error in status on corresponding commands. + +Signed-off-by: Vasily Khoruzhick +--- + include/net/bluetooth/hci.h | 7 +++++++ + net/bluetooth/hci_event.c | 4 +++- + 2 files changed, 10 insertions(+), 1 deletion(-) + +diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h +index 16ab6ce87883..8e4c16210d18 100644 +--- a/include/net/bluetooth/hci.h ++++ b/include/net/bluetooth/hci.h +@@ -238,6 +238,13 @@ enum { + * HCI after resume. + */ + HCI_QUIRK_NO_SUSPEND_NOTIFIER, ++ ++ /* When this quirk is set, max_page for local extended features ++ * is set to 1, even if controller reports higher number. Some ++ * controllers (e.g. RTL8723CS) report more pages, but they ++ * don't actually support features declared there. ++ */ ++ HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE, + + /* + * When this quirk is set, LE tx power is not queried on startup +diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c +index cfeaee347db3..df3232828978 100644 +--- a/net/bluetooth/hci_event.c ++++ b/net/bluetooth/hci_event.c +@@ -700,7 +700,9 @@ static void hci_cc_read_local_ext_features(struct hci_dev *hdev, + if (rp->status) + return; + +- if (hdev->max_page < rp->max_page) ++ if (!test_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE, ++ &hdev->quirks) && ++ hdev->max_page < rp->max_page) + hdev->max_page = rp->max_page; + + if (rp->page < HCI_MAX_PAGES) +-- +cgit v1.2.3 + diff --git a/patch/kernel/archive/media-5.18/220-general-disable-mtu-validation.patch b/patch/kernel/archive/station-p2-5.19/440-general-disable-mtu-validation.patch similarity index 100% rename from patch/kernel/archive/media-5.18/220-general-disable-mtu-validation.patch rename to patch/kernel/archive/station-p2-5.19/440-general-disable-mtu-validation.patch diff --git a/patch/kernel/archive/station-p2-5.18/0700-general-fix-es8316-kernel-panic.patch b/patch/kernel/archive/station-p2-5.19/450-general-fix-es8316-kernel-panic.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0700-general-fix-es8316-kernel-panic.patch rename to patch/kernel/archive/station-p2-5.19/450-general-fix-es8316-kernel-panic.patch diff --git a/patch/kernel/archive/station-p2-5.18/0710-general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/archive/station-p2-5.19/470-general-increasing_DMA_block_memory_allocation_to_2048.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0710-general-increasing_DMA_block_memory_allocation_to_2048.patch rename to patch/kernel/archive/station-p2-5.19/470-general-increasing_DMA_block_memory_allocation_to_2048.patch diff --git a/patch/kernel/archive/station-p2-5.18/0720-general-possibility-of-disabling-rk808-rtc.patch b/patch/kernel/archive/station-p2-5.19/480-general-possibility-of-disabling-rk808-rtc.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0720-general-possibility-of-disabling-rk808-rtc.patch rename to patch/kernel/archive/station-p2-5.19/480-general-possibility-of-disabling-rk808-rtc.patch diff --git a/patch/kernel/archive/station-p2-5.18/0730-general-rk808-configurable-switch-voltage-steps.patch b/patch/kernel/archive/station-p2-5.19/490-general-rk808-configurable-switch-voltage-steps.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0730-general-rk808-configurable-switch-voltage-steps.patch rename to patch/kernel/archive/station-p2-5.19/490-general-rk808-configurable-switch-voltage-steps.patch diff --git a/patch/kernel/archive/station-p2-5.18/0740-general-workaround-broadcom-bt-serdev.patch b/patch/kernel/archive/station-p2-5.19/500-general-workaround-broadcom-bt-serdev.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0740-general-workaround-broadcom-bt-serdev.patch rename to patch/kernel/archive/station-p2-5.19/500-general-workaround-broadcom-bt-serdev.patch diff --git a/patch/kernel/archive/station-p2-5.18/0750-rk3328-dtsi-usb3-reset-properties.patch b/patch/kernel/archive/station-p2-5.19/510-rk3328-dtsi-usb3-reset-properties.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0750-rk3328-dtsi-usb3-reset-properties.patch rename to patch/kernel/archive/station-p2-5.19/510-rk3328-dtsi-usb3-reset-properties.patch diff --git a/patch/kernel/archive/station-p2-5.18/0760-rk3328-roc-pc-bt.patch b/patch/kernel/archive/station-p2-5.19/520-rk3328-roc-pc-bt.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0760-rk3328-roc-pc-bt.patch rename to patch/kernel/archive/station-p2-5.19/520-rk3328-roc-pc-bt.patch diff --git a/patch/kernel/archive/station-p2-5.18/0770-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/archive/station-p2-5.19/530-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0770-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/archive/station-p2-5.19/530-rk3399-enable-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/station-p2-5.18/0780-rk3399-nanopc-t4-emmc.patch b/patch/kernel/archive/station-p2-5.19/540-rk3399-nanopc-t4-emmc.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0780-rk3399-nanopc-t4-emmc.patch rename to patch/kernel/archive/station-p2-5.19/540-rk3399-nanopc-t4-emmc.patch diff --git a/patch/kernel/archive/station-p2-5.18/0790-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch b/patch/kernel/archive/station-p2-5.19/550-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0790-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch rename to patch/kernel/archive/station-p2-5.19/550-rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch diff --git a/patch/kernel/archive/station-p2-5.18/0800-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch b/patch/kernel/archive/station-p2-5.19/560-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0800-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch rename to patch/kernel/archive/station-p2-5.19/560-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch diff --git a/patch/kernel/archive/station-p2-5.18/0810-rk3399-sd-drive-level-8ma.patch b/patch/kernel/archive/station-p2-5.19/570-rk3399-sd-drive-level-8ma.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0810-rk3399-sd-drive-level-8ma.patch rename to patch/kernel/archive/station-p2-5.19/570-rk3399-sd-drive-level-8ma.patch diff --git a/patch/kernel/archive/station-p2-5.18/0820-rk3399-unlock-temperature.patch b/patch/kernel/archive/station-p2-5.19/580-rk3399-unlock-temperature.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0820-rk3399-unlock-temperature.patch rename to patch/kernel/archive/station-p2-5.19/580-rk3399-unlock-temperature.patch diff --git a/patch/kernel/archive/station-p2-5.18/0830-v2-net-dsa-tag_mtk-add-padding-for-tx-packets.patch b/patch/kernel/archive/station-p2-5.19/590-v2-net-dsa-tag_mtk-add-padding-for-tx-packets.patch similarity index 100% rename from patch/kernel/archive/station-p2-5.18/0830-v2-net-dsa-tag_mtk-add-padding-for-tx-packets.patch rename to patch/kernel/archive/station-p2-5.19/590-v2-net-dsa-tag_mtk-add-padding-for-tx-packets.patch diff --git a/patch/kernel/media-current b/patch/kernel/media-current index cdae8e3bf..f492a3f25 120000 --- a/patch/kernel/media-current +++ b/patch/kernel/media-current @@ -1 +1 @@ -archive/media-5.18 \ No newline at end of file +archive/media-5.19 \ No newline at end of file diff --git a/patch/kernel/media-edge b/patch/kernel/media-edge index f492a3f25..2879dd064 120000 --- a/patch/kernel/media-edge +++ b/patch/kernel/media-edge @@ -1 +1 @@ -archive/media-5.19 \ No newline at end of file +archive/media-6.0 \ No newline at end of file diff --git a/patch/kernel/station-p2-current b/patch/kernel/station-p2-current index 82cbcfa41..01b2ae6d6 120000 --- a/patch/kernel/station-p2-current +++ b/patch/kernel/station-p2-current @@ -1 +1 @@ -archive/station-p2-5.18 \ No newline at end of file +archive/station-p2-5.19 \ No newline at end of file