Upgrade Allwinner boot loader to 2022.08 (#4168)

* Bump sunxi u-boot to 2022.07

* Clean configs

config/boards/beelinkx2.tvb

@@ -3,4 +3,3 @@ BOARD_NAME="Beelink X2"
 BOARDFAMILY="sun8i"
 BOOTCONFIG="beelink_x2_defconfig"
 KERNEL_TARGET="legacy,current,edge"
-BOOTBRANCH='tag:v2022.07'

config/boards/orangepi3-lts.conf

@@ -6,4 +6,3 @@ KERNEL_TARGET="current,edge"
 MODULES="sprdbt_tty sprdwl_ng"
 MODULES_BLACKLIST_LEGACY="bcmdhd"
 ATFBRANCH="tag:v2.2"
-BOOTBRANCH="tag:v2022.07"

config/sources/arm64.conf

@@ -42,7 +42,7 @@ fi
 [[ -z $UBOOT_USE_GCC ]]	&& UBOOT_USE_GCC='> 8.0'
 [[ -z $BOOTSOURCE ]]		&& BOOTSOURCE=$MAINLINE_UBOOT_SOURCE
 [[ -z $BOOTDIR ]]		&& BOOTDIR=$MAINLINE_UBOOT_DIR
-[[ -z $BOOTBRANCH ]]		&& BOOTBRANCH='tag:v2021.10'
+[[ -z $BOOTBRANCH ]]		&& BOOTBRANCH='tag:v2022.07'
 
 [[ -z $KERNELDIR ]]		&& KERNELDIR=$MAINLINE_KERNEL_DIR
 [[ -z $KERNELSOURCE ]]		&& KERNELSOURCE=$MAINLINE_KERNEL_SOURCE

config/sources/armhf.conf

@@ -28,7 +28,7 @@ fi
 [[ -z $UBOOT_USE_GCC ]]	&& UBOOT_USE_GCC='> 8.0'
 [[ -z $BOOTSOURCE ]]		&& BOOTSOURCE=$MAINLINE_UBOOT_SOURCE
 [[ -z $BOOTDIR ]]		&& BOOTDIR=$MAINLINE_UBOOT_DIR
-[[ -z $BOOTBRANCH ]]		&& BOOTBRANCH='tag:v2021.10'
+[[ -z $BOOTBRANCH ]]		&& BOOTBRANCH='tag:v2022.07'
 
 if [ "$(uname -m)" = "aarch64" ]; then
 	[[ -z $KERNEL_COMPILER ]]	&& KERNEL_COMPILER="arm-linux-gnueabihf-"

patch/u-boot/u-boot-sunxi/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch

@@ -1,42 +0,0 @@
-From 55d3cc28b37000d1a3d7224c0ba4a808274e0b33 Mon Sep 17 00:00:00 2001
-From: Icenowy Zheng <icenowy@aosc.io>
-Date: Fri, 27 Oct 2017 17:25:00 +0800
-Subject: [PATCH 20/20] sunxi: call fdt_fixup_ethernet again to set macaddr for
- more aliases
-
-Sometimes some ethernet aliases do not exist in U-Boot FDT but they
-exist in the FDT used to boot the system. In this situation
-setup_environment is called again in ft_board_setup to generate macaddr
-environment variable for them. However now the call to
-fdt_fixup_ethernet is moved before the call of ft_board_setup.
-
-Call fdt_fixup_ethernet again to add MAC addresses for the extra
-ethernet aliases.
-
-Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
----
- board/sunxi/board.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/board/sunxi/board.c b/board/sunxi/board.c
-index 192cf8ca45..0fe70f47cb 100644
---- a/board/sunxi/board.c
-+++ b/board/sunxi/board.c
-@@ -751,10 +751,12 @@ int ft_board_setup(void *blob, bd_t *bd)
- 	int __maybe_unused r;
- 
- 	/*
--	 * Call setup_environment again in case the boot fdt has
--	 * ethernet aliases the u-boot copy does not have.
-+	 * Call setup_environment and fdt_fixup_ethernet again
-+	 * in case the boot fdt has ethernet aliases the u-boot
-+	 * copy does not have.
- 	 */
- 	setup_environment(blob);
-+	fdt_fixup_ethernet(blob);
- 
- #ifdef CONFIG_VIDEO_DT_SIMPLEFB
- 	r = sunxi_simplefb_setup(blob);
--- 
-2.13.6
-

patch/u-boot/u-boot-sunxi/add-nanopi-r1-and-duo2.patch

@@ -1,279 +0,0 @@
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index d17045a..9e1be8b 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -446,5 +446,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
- 	sun8i-h3-nanopi-m1-plus.dtb \
- 	sun8i-h3-nanopi-neo.dtb \
- 	sun8i-h3-nanopi-neo-air.dtb \
-+	sun8i-h3-nanopi-r1.dtb \
-+	sun8i-h3-nanopi-duo2.dtb \
- 	sun8i-h3-orangepi-2.dtb \
- 	sun8i-h3-orangepi-lite.dtb \
-diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
-new file mode 100644
-index 0000000..9f33f6f
---- /dev/null
-+++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
-@@ -0,0 +1,102 @@
-+/*
-+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This file is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This file is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#include "sun8i-h3-nanopi.dtsi"
-+
-+/ {
-+	model = "FriendlyARM NanoPi R1";
-+	compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
-+
-+	reg_gmac_3v3: gmac-3v3 {
-+		compatible = "regulator-fixed";
-+		pinctrl-names = "default";
-+		regulator-name = "gmac-3v3";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		startup-delay-us = <100000>;
-+		enable-active-high;
-+		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
-+	};
-+
-+};
-+
-+&ehci0 {
-+	status = "okay";
-+};
-+
-+&pio {
-+	gmac_power_pin_nanopi: gmac_power_pin@0 {
-+		pins = "PD6";
-+		function = "gpio_out";
-+	};
-+};
-+
-+&ohci0 {
-+	status = "okay";
-+};
-+
-+&mmc2 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc2_8bit_pins>;
-+	vmmc-supply = <&reg_vcc3v3>;
-+	bus-width = <8>;
-+	non-removable;
-+	cap-mmc-hw-reset;
-+	status = "okay";
-+};
-+
-+&emac {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emac_rgmii_pins>;
-+	phy-supply = <&reg_gmac_3v3>;
-+	phy-handle = <&ext_rgmii_phy>;
-+	phy-mode = "rgmii";
-+
-+	status = "okay";
-+};
-+
-+&external_mdio {
-+	ext_rgmii_phy: ethernet-phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <7>;
-+	};
-+};
-diff --git a/configs/nanopi_r1_defconfig b/configs/nanopi_r1_defconfig
-new file mode 100644
-index 0000000..dee7d9d
---- /dev/null
-+++ b/configs/nanopi_r1_defconfig
-@@ -0,0 +1,22 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_SPL=y
-+CONFIG_MACH_SUN8I_H3=y
-+CONFIG_DRAM_CLK=408
-+CONFIG_DRAM_ZQ=3881979
-+CONFIG_DRAM_ODT_EN=y
-+CONFIG_MACPWR="PD6"
-+# CONFIG_VIDEO_DE2 is not set
-+CONFIG_NR_DRAM_BANKS=1
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_CONSOLE_MUX=y
-+CONFIG_SYS_CLK_FREQ=480000000
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_SPL_DOS_PARTITION is not set
-+# CONFIG_SPL_EFI_PARTITION is not set
-+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1"
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-diff --git a/configs/nanopi_duo2_defconfig b/configs/nanopi_duo2_defconfig
-new file mode 100644
-index 0000000..1e51018
---- /dev/null
-+++ b/configs/nanopi_duo2_defconfig
-@@ -0,0 +1,21 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_SYS_TEXT_BASE=0x4a000000
-+CONFIG_SPL_SPI_FLASH_SUPPORT=y
-+CONFIG_MACH_SUN8I_H3=y
-+CONFIG_DRAM_CLK=408
-+CONFIG_DRAM_ZQ=3881979
-+CONFIG_DRAM_ODT_EN=y
-+# CONFIG_VIDEO_DE2 is not set
-+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-duo2"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_CONSOLE_MUX=y
-+CONFIG_SPL=y
-+CONFIG_SYS_CLK_FREQ=480000000
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+CONFIG_SPL_SPI_SUNXI=y
-+CONFIG_SUN8I_EMAC=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-diff --git a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts
-new file mode 100644
-index 0000000..b6afe20
---- /dev/null
-+++ b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts
-@@ -0,0 +1,98 @@
-+/*
-+ * adapted by Igor Pecovnik igor@armbian.com
-+ * Copyright (C) 2017 Jelle van der Waa <jelle@vdwaa.nl>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This file is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This file is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/dts-v1/;
-+#include "sun8i-h3.dtsi"
-+#include "sunxi-common-regulators.dtsi"
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/pinctrl/sun4i-a10.h>
-+
-+/ {
-+	model = "FriendlyARM NanoPi DUO 2";
-+	compatible = "friendlyarm,nanopi-duo2", "allwinner,sun8i-h3";
-+
-+	aliases {
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		pwr {
-+			label = "nanopi:green:pwr";
-+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
-+			default-state = "on";
-+		};
-+
-+		status {
-+			label = "nanopi:blue:status";
-+			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
-+		};
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc0_pins>;
-+	vmmc-supply = <&reg_vcc3v3>;
-+	bus-width = <4>;
-+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-+	cd-inverted;
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_pa_pins>;
-+	status = "okay";
-+};
-+
-+&usbphy {
-+	/* USB VBUS is always on */
-+	status = "okay";
-+};

patch/u-boot/u-boot-sunxi/add-pineh64-model-b.patch

@@ -1,46 +0,0 @@
-diff --git a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
-new file mode 120000
-index 00000000..76280222
---- /dev/null
-+++ b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
-@@ -0,0 +1 @@
-+sun50i-h6-pine-h64.dts
-\ No newline at end of file
-diff --git a/configs/pine_h64-model-b_defconfig b/configs/pine_h64-model-b_defconfig
-new file mode 100644
-index 00000000..ace3e84e
---- /dev/null
-+++ b/configs/pine_h64-model-b_defconfig
-@@ -0,0 +1,18 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_SPL=y
-+CONFIG_MACH_SUN50I_H6=y
-+CONFIG_SUNXI_DRAM_H6_LPDDR3=y
-+CONFIG_MMC0_CD_PIN="PF6"
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-+CONFIG_USB3_VBUS_PIN="PL5"
-+# CONFIG_PSCI_RESET is not set
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_USE_PREBOOT=y
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_SPL_DOS_PARTITION is not set
-+# CONFIG_SPL_EFI_PARTITION is not set
-+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64-model-b"
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_OHCI_HCD=y
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index 7a791cba..e74adc94 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -525,7 +525,8 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
- 	sun50i-h6-beelink-gs1.dtb \
- 	sun50i-h6-orangepi-lite2.dtb \
- 	sun50i-h6-orangepi-one-plus.dtb \
--	sun50i-h6-pine-h64.dtb \
-+	sun50i-h6-pine-h64.dtb \
-+	sun50i-h6-pine-h64-model-b.dtb \
- 	sun50i-h6-tanix-tx6.dtb
- dtb-$(CONFIG_MACH_SUN50I) += \
- 	sun50i-a64-amarula-relic.dtb \

patch/u-boot/u-boot-sunxi/add-xx-nanopineocore2.patch

@@ -1,18 +1,15 @@
 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index d36447d..7311063
+index 6f6e92eb..231d4966 100644
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -388,8 +393,9 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+@@ -690,6 +690,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
- dtb-$(CONFIG_MACH_SUN50I_H5) += \
+ 	sun50i-h5-libretech-all-h5-cc.dtb \
- 	sun50i-h5-libretech-all-h3-cc.dtb \
  	sun50i-h5-nanopi-m1-plus2.dtb \
  	sun50i-h5-nanopi-neo2.dtb \
 +	sun50i-h5-nanopi-neo-core2.dtb \
  	sun50i-h5-nanopi-neo-plus2.dtb \
+ 	sun50i-h5-nanopi-r1s-h5.dtb \
  	sun50i-h5-orangepi-zero-plus.dtb \
- 	sun50i-h5-orangepi-pc2.dtb \
- 	sun50i-h5-nanopi-k1-plus.dtb \
- dtb-$(CONFIG_MACH_SUN50I_H6) += \
 diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts
 new file mode 100644
 index 0000000..dd25549

patch/u-boot/u-boot-sunxi/adjust-small-boards-cpufreq.patch

@@ -30,6 +30,6 @@ index f8dda05..739a5f4 100644
  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 +CONFIG_SYS_CLK_FREQ=480000000
  CONFIG_CONSOLE_MUX=y
+ CONFIG_SPI_FLASH_WINBOND=y
  CONFIG_SUN8I_EMAC=y
- CONFIG_USB_EHCI_HCD=y
+ CONFIG_SPI=y
- CONFIG_USB_OHCI_HCD=y

patch/u-boot/u-boot-sunxi/board_orangepi3/add-orangepi3.patch

@@ -1,222 +0,0 @@
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index dda4e59..6d3cca2 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -403,7 +403,8 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
- 	sun50i-h5-orangepi-prime.dtb \
- 	sun50i-h5-orangepi-zero-plus2.dtb
- dtb-$(CONFIG_MACH_SUN50I_H6) += \
- 	sun50i-h6-beelink-gs1.dtb \
-+	sun50i-h6-orangepi-3.dtb \
- 	sun50i-h6-orangepi-lite2.dtb \
- 	sun50i-h6-orangepi-one-plus.dtb \
- 	sun50i-h6-pine-h64.dtb
-diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts
-new file mode 100644
-index 0000000..dffd648
---- /dev/null
-+++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts
-@@ -0,0 +1,179 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+/*
-+ * Copyright (C) 2018 Amarula Solutions
-+ * Author: Jagan Teki <jagan@amarulasolutions.com>
-+ */
-+
-+/dts-v1/;
-+
-+#include "sun50i-h6.dtsi"
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	model = "OrangePi 3";
-+	compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6";
-+
-+	aliases {
-+		serial0 = &uart0;
-+		ethernet0 = &emac;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+};
-+
-+&emac {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&ext_rgmii_pins>;
-+	phy-mode = "rgmii";
-+	phy-handle = <&ext_rgmii_phy>;
-+	phy-supply = <&reg_aldo2>;
-+	allwinner,rx-delay-ps = <200>;
-+	allwinner,tx-delay-ps = <200>;
-+	status = "okay";
-+};
-+
-+&mdio {
-+	ext_rgmii_phy: ethernet-phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <1>;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc0_pins>;
-+	vmmc-supply = <&reg_cldo1>;
-+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
-+	bus-width = <4>;
-+	status = "okay";
-+};
-+
-+&mmc2 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mmc2_pins>;
-+	vmmc-supply = <&reg_cldo1>;
-+	non-removable;
-+	cap-mmc-hw-reset;
-+	bus-width = <8>;
-+	status = "okay";
-+};
-+
-+&r_i2c {
-+	status = "okay";
-+
-+	axp805: pmic@36 {
-+		compatible = "x-powers,axp805", "x-powers,axp806";
-+		reg = <0x36>;
-+		interrupt-parent = <&r_intc>;
-+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-controller;
-+		#interrupt-cells = <1>;
-+		x-powers,self-working-mode;
-+
-+		regulators {
-+			reg_aldo1: aldo1 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-name = "vcc-pl";
-+			};
-+
-+			reg_aldo2: aldo2 {
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-name = "vcc-ac200";
-+			};
-+
-+			reg_aldo3: aldo3 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-name = "vcc25-dram";
-+			};
-+
-+			reg_bldo1: bldo1 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc-bias-pll";
-+			};
-+
-+			reg_bldo2: bldo2 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc-efuse-pcie-hdmi-io";
-+			};
-+
-+			reg_bldo3: bldo3 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc-dcxoio";
-+			};
-+
-+			bldo4 {
-+				/* unused */
-+			};
-+
-+			reg_cldo1: cldo1 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-name = "vcc-3v3";
-+			};
-+
-+			reg_cldo2: cldo2 {
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-name = "vcc-wifi-1";
-+			};
-+
-+			reg_cldo3: cldo3 {
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-name = "vcc-wifi-2";
-+			};
-+
-+			reg_dcdca: dcdca {
-+				regulator-always-on;
-+				regulator-min-microvolt = <810000>;
-+				regulator-max-microvolt = <1080000>;
-+				regulator-name = "vdd-cpu";
-+			};
-+
-+			reg_dcdcc: dcdcc {
-+				regulator-min-microvolt = <810000>;
-+				regulator-max-microvolt = <1080000>;
-+				regulator-name = "vdd-gpu";
-+			};
-+
-+			reg_dcdcd: dcdcd {
-+				regulator-always-on;
-+				regulator-min-microvolt = <960000>;
-+				regulator-max-microvolt = <960000>;
-+				regulator-name = "vdd-sys";
-+			};
-+
-+			reg_dcdce: dcdce {
-+				regulator-always-on;
-+				regulator-min-microvolt = <1200000>;
-+				regulator-max-microvolt = <1200000>;
-+				regulator-name = "vcc-dram";
-+			};
-+
-+			sw {
-+				/* unused */
-+			};
-+		};
-+	};
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_ph_pins>;
-+	status = "okay";
-+};
-diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig
-new file mode 100644
-index 0000000..187818e
---- /dev/null
-+++ b/configs/orangepi_3_defconfig
-@@ -0,0 +1,18 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_SUNXI=y
-+CONFIG_MACH_SUN50I_H6=y
-+CONFIG_SUNXI_DRAM_H6_LPDDR3=y
-+CONFIG_SUNXI_DRAM_DDR3=n
-+CONFIG_DRAM_ODT_EN=y
-+CONFIG_MMC0_CD_PIN="PF6"
-+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-+CONFIG_HDMI_DDC_EN="PH2"
-+# CONFIG_PSCI_RESET is not set
-+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3"
-+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-+CONFIG_SPL=y
-+# CONFIG_CMD_FLASH is not set
-+# CONFIG_CMD_FPGA is not set
-+# CONFIG_SPL_DOS_PARTITION is not set
-+# CONFIG_SPL_ISO_PARTITION is not set
-+# CONFIG_SPL_EFI_PARTITION is not set

patch/u-boot/u-boot-sunxi/h3-set-safe-axi_apb-clock-dividers.patch

@@ -1,18 +1,18 @@
 diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
-index 15272c9..cedddc2 100644
+index ad3f8365..aec9e562 100644
 --- a/arch/arm/mach-sunxi/clock_sun6i.c
 +++ b/arch/arm/mach-sunxi/clock_sun6i.c
-@@ -117,8 +117,8 @@ void clock_set_pll1(unsigned int clk)
+@@ -167,8 +167,8 @@ void clock_set_pll1(unsigned int clk)
- 	sdelay(200);
+ 		writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
- 
+ 		       &ccm->cpu_axi_cfg);
- 	/* Switch CPU to PLL1 */
+ 	} else {
--	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+-		writel(AXI_DIV_3 << AXI_DIV_SHIFT |
--	       ATB_DIV_2 << ATB_DIV_SHIFT |
+-		       ATB_DIV_2 << ATB_DIV_SHIFT |
-+	writel(AXI_DIV_4 << AXI_DIV_SHIFT |
++		writel(AXI_DIV_4 << AXI_DIV_SHIFT |
-+	       ATB_DIV_4 << ATB_DIV_SHIFT |
++		       ATB_DIV_4 << ATB_DIV_SHIFT |
- 	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ 		       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
- 	       &ccm->cpu_axi_cfg);
+ 		       &ccm->cpu_axi_cfg);
- }
+ 	}
 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
 index f2990db..b3a8575 100644
 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h

patch/u-boot/u-boot-sunxi/sunxi_H616_GPU_enable_hack.patch

@@ -9,19 +9,15 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
  1 file changed, 4 insertions(+), 1 deletion(-)
 
 diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
-index a947463e0a..b97a09c382 100644
+index 7926394c..f12f9625 100644
 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
 +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
-@@ -11,8 +11,11 @@ void clock_init_safe(void)
+@@ -16,6 +16,8 @@ void clock_init_safe(void)
- 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ 		/* this seems to enable PLLs on H616 */
- 
+ 		setbits_le32(&prcm->sys_pwroff_gating, 0x10);
- 	/* this seems to enable PLLs on H616 */
+ 		setbits_le32(&prcm->res_cal_ctrl, 2);
--	if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
-+	if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) {
- 		setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
 +		/* enable GPU */
 +		writel(0, 0x7010254);
-+	}
+ 	}
- 
- 	clock_set_pll1(408000000);
  
+ 	clrbits_le32(&prcm->res_cal_ctrl, 1);