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Main: adjust broken patches on Meson and Rockchip64

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This commit is contained in:
Igor Pecovnik
2025-06-21 12:08:32 +02:00
committed by Igor
parent fc8fef06b2
commit 3844ef919f
2 changed files with 6 additions and 8 deletions
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2
patch/kernel/archive/meson-6.12/0052-drm-meson-Describe-the-HDMI-PHY-frequency-limits-of-.patch
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@@ -43,7 +43,7 @@ index 111111111111..222222222222 100644
+ */
{
.limits = {
.max_hdmi_phy_freq = 1650000,
.max_hdmi_phy_freq = 1650000000,
},
.attrs = (const struct soc_device_attribute []) {
{ .soc_id = "GXL (S805*)", },

12
patch/kernel/archive/rockchip64-6.12/rk3588-0132-phy-phy-rockchip-samsung-hdptx-Add-FRL-EARC-support.patch
View File

@@ -21,9 +21,10 @@ diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/roc
index 111111111111..222222222222 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -193,6 +193,10 @@
@@ -193,7 +193,11 @@
#define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
#define HDMI14_MAX_RATE 340000000
#define HDMI20_MAX_RATE 600000000
+#define DATA_RATE_MASK 0xFFFFFFF
+#define COLOR_DEPTH_MASK BIT(31)
@@ -346,20 +347,17 @@ index 111111111111..222222222222 100644
static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
struct ropll_config *cfg)
{
@@ -765,9 +1034,13 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
@@ -765,7 +1034,11 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
unsigned int rate)
{
+ int i, bus_width = phy_get_bus_width(hdptx->phy);
+ int bus_width = phy_get_bus_width(hdptx->phy);
+ u8 color_depth = (bus_width & COLOR_DEPTH_MASK) ? 1 : 0;
const struct ropll_config *cfg = NULL;
struct ropll_config rc = {0};
- int i;
+
+ if (color_depth)
+ rate = rate * 10 / 8;
hdptx->rate = rate * 100;
int ret, i;
@@ -825,6 +1098,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,