diff --git a/patch/kernel/archive/rockchip-6.4/01-linux-1000-drm-rockchip.patch b/patch/kernel/archive/rockchip-6.4/01-linux-1000-drm-rockchip.patch index 4587a9484..3f9e60350 100644 --- a/patch/kernel/archive/rockchip-6.4/01-linux-1000-drm-rockchip.patch +++ b/patch/kernel/archive/rockchip-6.4/01-linux-1000-drm-rockchip.patch @@ -83,7 +83,7 @@ index dbe4d411b30f..fac23d370ee0 100644 + */ +#define CLOCK_TOLERANCE_PER_MILLE 5 + -+static enum drm_mode_status vop_crtc_mode_valid5(struct drm_crtc *crtc, ++static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + struct vop *vop = to_vop(crtc); @@ -140,6 +140,67 @@ index fac23d370ee0..9f7326c5b1f5 100644 if (rounded_rate < 0) return MODE_NOCLOCK; +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +index 16e6aa01e400..9b25b8ffd0ce 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +@@ -743,6 +743,7 @@ static const struct vop_intr rk3288_vop_intr = { + static const struct vop_data rk3288_vop = { + .version = VOP_VERSION(3, 1), + .feature = VOP_FEATURE_OUTPUT_RGB10, ++ .max_output = { 3840, 2160 }, + .intr = &rk3288_vop_intr, + .common = &rk3288_common, + .modeset = &rk3288_modeset, +@@ -845,6 +846,7 @@ static const struct vop_misc rk3368_misc = { + + static const struct vop_data rk3368_vop = { + .version = VOP_VERSION(3, 2), ++ .max_output = { 4096, 2160 }, + .intr = &rk3368_vop_intr, + .common = &rk3288_common, + .modeset = &rk3288_modeset, +@@ -866,6 +868,7 @@ static const struct vop_intr rk3366_vop_intr = { + + static const struct vop_data rk3366_vop = { + .version = VOP_VERSION(3, 4), ++ .max_output = { 4096, 2160 }, + .intr = &rk3366_vop_intr, + .common = &rk3288_common, + .modeset = &rk3288_modeset, +@@ -994,6 +997,7 @@ static const struct vop_afbc rk3399_vop_afbc = { + static const struct vop_data rk3399_vop_big = { + .version = VOP_VERSION(3, 5), + .feature = VOP_FEATURE_OUTPUT_RGB10, ++ .max_output = { 4096, 2160 }, + .intr = &rk3366_vop_intr, + .common = &rk3399_common, + .modeset = &rk3288_modeset, +@@ -1021,6 +1025,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { + + static const struct vop_data rk3399_vop_lit = { + .version = VOP_VERSION(3, 6), ++ .max_output = { 2560, 1600 }, + .intr = &rk3366_vop_intr, + .common = &rk3399_common, + .modeset = &rk3288_modeset, +@@ -1042,6 +1047,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { + static const struct vop_data rk3228_vop = { + .version = VOP_VERSION(3, 7), + .feature = VOP_FEATURE_OUTPUT_RGB10, ++ .max_output = { 4096, 2160 }, + .intr = &rk3366_vop_intr, + .common = &rk3288_common, + .modeset = &rk3288_modeset, +@@ -1113,6 +1119,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { + static const struct vop_data rk3328_vop = { + .version = VOP_VERSION(3, 8), + .feature = VOP_FEATURE_OUTPUT_RGB10, ++ .max_output = { 4096, 2160 }, + .intr = &rk3328_vop_intr, + .common = &rk3328_common, + .modeset = &rk3328_modeset, + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 20 Jul 2020 11:46:16 +0000 @@ -333,7 +394,7 @@ diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockc index bec381cde0bc..72c1d65c7b75 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -172,20 +172,6 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { +@@ -262,20 +264,6 @@ static const struct dw_hdmi_mpll_config rockchip_rk3288w_mpll_cfg_420[] = { static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { /* pixelclk bpp8 bpp10 bpp12 */ { @@ -352,7 +413,7 @@ index bec381cde0bc..72c1d65c7b75 100644 - 148500000, { 0x0000, 0x0038, 0x0038 }, - }, { 600000000, { 0x0000, 0x0000, 0x0000 }, - }, { + }, { ~0UL, { 0x0000, 0x0000, 0x0000}, From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 @@ -389,7 +450,7 @@ diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockc index 72c1d65c7b75..0370bb247fcb 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -95,86 +95,88 @@ +@@ -95,86 +95,88 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { { @@ -403,111 +464,91 @@ index 72c1d65c7b75..0370bb247fcb 100644 - { 0x00b3, 0x0000}, - { 0x2153, 0x0000}, - { 0x40f3, 0x0000} -- }, ++ 30666000, { ++ { 0x00b3, 0x0000 }, ++ { 0x2153, 0x0000 }, ++ { 0x40f3, 0x0000 }, + }, - }, { - 40000000, { - { 0x00b3, 0x0000}, - { 0x2153, 0x0000}, - { 0x40f3, 0x0000} -- }, -- }, { -- 54000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -- }, -- }, { -- 65000000, { -- { 0x0072, 0x0001}, -- { 0x2142, 0x0001}, -- { 0x40a2, 0x0001}, -- }, -- }, { -- 66000000, { -- { 0x013e, 0x0003}, -- { 0x217e, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 74250000, { -- { 0x0072, 0x0001}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 83500000, { -- { 0x0072, 0x0001}, -- }, -- }, { -- 108000000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 106500000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 146250000, { -- { 0x0051, 0x0002}, -- { 0x2145, 0x0002}, -- { 0x4061, 0x0002} -- }, -- }, { -- 148500000, { -- { 0x0051, 0x0003}, -- { 0x214c, 0x0003}, -- { 0x4064, 0x0003} -+ 30666000, { -+ { 0x00b3, 0x0000 }, -+ { 0x2153, 0x0000 }, -+ { 0x40f3, 0x0000 }, -+ }, + }, { + 36800000, { + { 0x00b3, 0x0000 }, + { 0x2153, 0x0000 }, + { 0x40a2, 0x0001 }, -+ }, + }, +- }, { +- 54000000, { +- { 0x0072, 0x0001}, +- { 0x2142, 0x0001}, +- { 0x40a2, 0x0001}, + }, { + 46000000, { + { 0x00b3, 0x0000 }, + { 0x2142, 0x0001 }, + { 0x40a2, 0x0001 }, -+ }, + }, +- }, { +- 65000000, { +- { 0x0072, 0x0001}, +- { 0x2142, 0x0001}, +- { 0x40a2, 0x0001}, + }, { + 61333000, { + { 0x0072, 0x0001 }, + { 0x2142, 0x0001 }, + { 0x40a2, 0x0001 }, -+ }, + }, +- }, { +- 66000000, { +- { 0x013e, 0x0003}, +- { 0x217e, 0x0002}, +- { 0x4061, 0x0002} + }, { + 73600000, { + { 0x0072, 0x0001 }, + { 0x2142, 0x0001 }, + { 0x4061, 0x0002 }, -+ }, + }, +- }, { +- 74250000, { +- { 0x0072, 0x0001}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} + }, { + 92000000, { + { 0x0072, 0x0001 }, + { 0x2145, 0x0002 }, + { 0x4061, 0x0002 }, -+ }, + }, +- }, { +- 83500000, { +- { 0x0072, 0x0001}, + }, { + 122666000, { + { 0x0051, 0x0002 }, + { 0x2145, 0x0002 }, + { 0x4061, 0x0002 }, -+ }, + }, +- }, { +- 108000000, { +- { 0x0051, 0x0002}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} + }, { + 147200000, { + { 0x0051, 0x0002 }, + { 0x2145, 0x0002 }, + { 0x4064, 0x0003 }, -+ }, + }, +- }, { +- 106500000, { +- { 0x0051, 0x0002}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} + }, { + 184000000, { + { 0x0051, 0x0002 }, @@ -515,18 +556,28 @@ index 72c1d65c7b75..0370bb247fcb 100644 + { 0x4064, 0x0003 }, }, - }, { +- 146250000, { +- { 0x0051, 0x0002}, +- { 0x2145, 0x0002}, +- { 0x4061, 0x0002} + }, { + 226666000, { + { 0x0040, 0x0003 }, + { 0x214c, 0x0003 }, + { 0x4064, 0x0003 }, -+ }, + }, +- }, { +- 148500000, { +- { 0x0051, 0x0003}, +- { 0x214c, 0x0003}, +- { 0x4064, 0x0003} + }, { + 272000000, { + { 0x0040, 0x0003 }, + { 0x214c, 0x0003 }, + { 0x5a64, 0x0003 }, -+ }, + }, +- }, { + }, { 340000000, { { 0x0040, 0x0003 }, @@ -552,6 +603,86 @@ index 72c1d65c7b75..0370bb247fcb 100644 } }; +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Wed, 8 Jan 2020 21:07:52 +0000 +Subject: [PATCH] drm/rockchip: dw-hdmi: limit tmds to 340mhz + +RK3228/RK3328 does not provide a stable hdmi signal at TMDS rates +above 371.25MHz (340MHz pixel clock). + +Limit the pixel clock rate to 340MHz to provide a stable signal. +Also limit the pixel clock to the display reported max tmds clock. + +This also enables use of pixel clocks up to 340MHz on RK3288/RK3399. + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++------------ + 1 file changed, 4 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index 0370bb247fcb..55c0b8dddad5 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -338,35 +326,32 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data, + const struct drm_display_info *info, + const struct drm_display_mode *mode) + { +- struct rockchip_hdmi *hdmi = data; +- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; +- int pclk = mode->clock * 1000; +- bool exact_match = hdmi->plat_data->phy_force_vendor; +- int i; ++ struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; ++ struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)hdmi->plat_data; ++ const struct dw_hdmi_mpll_config *mpll_cfg = pdata->mpll_cfg; ++ int clock = mode->clock; ++ unsigned int i = 0; ++ ++ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) && ++ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) { ++ clock /= 2; ++ mpll_cfg = pdata->mpll_cfg_420; ++ } + +- if (hdmi->ref_clk) { +- int rpclk = clk_round_rate(hdmi->ref_clk, pclk); ++ if ((!mpll_cfg && clock > 340000) || ++ (info->max_tmds_clock && clock > info->max_tmds_clock)) ++ return MODE_CLOCK_HIGH; + +- if (abs(rpclk - pclk) > pclk / 1000) +- return MODE_NOCLOCK; +- } ++ if (mpll_cfg) { ++ while ((clock * 1000) < mpll_cfg[i].mpixelclock && ++ mpll_cfg[i].mpixelclock != (~0UL)) ++ i++; + +- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { +- /* +- * For vendor specific phys force an exact match of the pixelclock +- * to preserve the original behaviour of the driver. +- */ +- if (exact_match && pclk == mpll_cfg[i].mpixelclock) +- return MODE_OK; +- /* +- * The Synopsys phy can work with pixelclocks up to the value given +- * in the corresponding mpll_cfg entry. +- */ +- if (!exact_match && pclk <= mpll_cfg[i].mpixelclock) +- return MODE_OK; ++ if (mpll_cfg[i].mpixelclock == (~0UL)) ++ return MODE_CLOCK_HIGH; + } + +- return MODE_BAD; ++ return MODE_OK; + } + static void + dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 8 Jan 2020 21:07:49 +0000 @@ -1315,7 +1446,7 @@ index 66fee351f4a7..d6d8f3335813 100644 err_bind: drm_encoder_cleanup(encoder); err_disable_clk: -@@ -719,7 +763,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, +@@ -639,7 +870,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, { struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); @@ -1913,14 +2044,13 @@ index a2d101ebf7a7..7f6ffbc3e7b2 100644 } /* -@@ -2732,40 +2744,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2749,42 +2749,53 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + * if supported. In any case the default RGB888 format is added */ - /* Default 8bit RGB fallback */ +- /* Default 8bit RGB fallback */ - output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24)) -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; - +- if (max_bpc >= 16 && info->bpc == 16) { - if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) + if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && @@ -1974,8 +2104,13 @@ index a2d101ebf7a7..7f6ffbc3e7b2 100644 + is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV8_1X24)) output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; ++ /* Default 8bit RGB fallback */ ++ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24)) ++ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; ++ *num_output_fmts = i; + return output_fmts; @@ -2946,11 +2969,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, struct dw_hdmi *hdmi = bridge->driver_private; const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; @@ -3275,3 +3410,37 @@ index 49619f794061..9915bf124374 100644 } port = of_get_child_by_name(dev->of_node, "port"); +From deaa583fd87acdca3976ad997ff9b949e234fb3e Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sat, 8 Jul 2023 12:10:14 +0200 +Subject: [PATCH] remove duplicate function + +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 11 ----------- + 1 file changed, 11 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 5351eb68f44f..929bc38b2629 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -1438,17 +1438,6 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) + spin_unlock_irqrestore(&vop->irq_lock, flags); + } + +-static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +- const struct drm_display_mode *mode) +-{ +- struct vop *vop = to_vop(crtc); +- +- if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width) +- return MODE_BAD_HVALUE; +- +- return MODE_OK; +-} +- + static bool vop_crtc_is_tmds(struct drm_crtc *crtc) + { + struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); +-- +2.34.1 + diff --git a/patch/kernel/archive/rockchip-6.4/01-linux-1003-temp-dw_hdmi-rockchip.patch b/patch/kernel/archive/rockchip-6.4/01-linux-1003-temp-dw_hdmi-rockchip.patch deleted file mode 100644 index 649732ddb..000000000 --- a/patch/kernel/archive/rockchip-6.4/01-linux-1003-temp-dw_hdmi-rockchip.patch +++ /dev/null @@ -1,63 +0,0 @@ -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 0370bb247fcb..55c0b8dddad5 100644 ---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2023-06-25 03:23:55.724209412 +0000 -+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2023-06-25 04:16:27.469899470 +0000 -@@ -254,35 +245,31 @@ - const struct drm_display_info *info, - const struct drm_display_mode *mode) - { -- struct rockchip_hdmi *hdmi = data; -- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; -- int pclk = mode->clock * 1000; -- bool exact_match = hdmi->plat_data->phy_force_vendor; -- int i; -- -- if (hdmi->ref_clk) { -- int rpclk = clk_round_rate(hdmi->ref_clk, pclk); -- -- if (abs(rpclk - pclk) > pclk / 1000) -- return MODE_NOCLOCK; -- } -- -- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { -- /* -- * For vendor specific phys force an exact match of the pixelclock -- * to preserve the original behaviour of the driver. -- */ -- if (exact_match && pclk == mpll_cfg[i].mpixelclock) -- return MODE_OK; -- /* -- * The Synopsys phy can work with pixelclocks up to the value given -- * in the corresponding mpll_cfg entry. -- */ -- if (!exact_match && pclk <= mpll_cfg[i].mpixelclock) -- return MODE_OK; -+ struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data; -+ const struct dw_hdmi_mpll_config *mpll_cfg = pdata->mpll_cfg; -+ int clock = mode->clock; -+ unsigned int i = 0; -+ -+ if (pdata->ycbcr_420_allowed && drm_mode_is_420(info, mode) && -+ (info->color_formats & DRM_COLOR_FORMAT_YCBCR420)) { -+ clock /= 2; -+ mpll_cfg = pdata->mpll_cfg_420; -+ } -+ -+ if ((!mpll_cfg && clock > 340000) || -+ (info->max_tmds_clock && clock > info->max_tmds_clock)) -+ return MODE_CLOCK_HIGH; -+ -+ if (mpll_cfg) { -+ while ((clock * 1000) < mpll_cfg[i].mpixelclock && -+ mpll_cfg[i].mpixelclock != (~0UL)) -+ i++; -+ -+ if (mpll_cfg[i].mpixelclock == (~0UL)) -+ return MODE_CLOCK_HIGH; - } - -- return MODE_BAD; -+ return MODE_OK; - } - - static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) diff --git a/patch/kernel/archive/rockchip-6.4/5002-prefer-8-bit-RGB-over-YCbCr.patch b/patch/kernel/archive/rockchip-6.4/5002-prefer-8-bit-RGB-over-YCbCr.patch index b7f6ae7dd..961381a5c 100644 --- a/patch/kernel/archive/rockchip-6.4/5002-prefer-8-bit-RGB-over-YCbCr.patch +++ b/patch/kernel/archive/rockchip-6.4/5002-prefer-8-bit-RGB-over-YCbCr.patch @@ -1,6 +1,6 @@ -From 3c0fe31689c380b1ebaaf7327a2585248eacecad Mon Sep 17 00:00:00 2001 +From b50d1c7f698c88b790aa3d13a40fd67292b15c16 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino -Date: Fri, 7 Jul 2023 16:00:15 +0200 +Date: Sun, 29 May 2022 10:57:59 +0000 Subject: [PATCH] prefer 8-bit RGB over YCbCr --- @@ -8,21 +8,10 @@ Subject: [PATCH] prefer 8-bit RGB over YCbCr 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 36c8dc302de1..2944fc0a236e 100644 +index 115d610c5c3..975e4ef6ef4 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2749,10 +2749,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, - * if supported. In any case the default RGB888 format is added - */ - -- /* Default 8bit RGB fallback */ -- if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24)) -- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -- - if (max_bpc >= 16 && info->bpc == 16) { - if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) && - is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV16_1X48)) -@@ -2788,6 +2784,10 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2658,6 +2658,10 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; } @@ -33,6 +22,17 @@ index 36c8dc302de1..2944fc0a236e 100644 if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) && is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY8_1X16)) output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; +@@ -2666,10 +2670,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV8_1X24)) + output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; + +- /* Default 8bit RGB fallback */ +- if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24)) +- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; +- + *num_output_fmts = i; + + return output_fmts; -- -2.34.1 +2.30.2