Rockchip atf 2.5 (#2998)

* bump rockchip64 ATF to 2.5

v2.5 includes our patches and some other RK3399 improvements

* Delete power domains patch

included in ATF v2.5

* Delete fix-reset-in-v2.2.patch

Included in v2.5

* disable logging patch

&console.console is causing a compile error with ATF v2.5.  I haven't looked into it yet, disable for now.

* Add experimental suspend support for PBP

Co-authored-by: Igor Pecovnik <igor.pecovnik@gmail.com>

patch/atf/atf-rk3399/enable-suspend-on-pbpro.patch

@@ -0,0 +1,127 @@
+fix(rk3399/suspend): correct LPDDR4 resume sequence
+
+This change adds 208 bytes to PMUSRAM, pushing the end of text from
+0xff3b0de0 to 0xff3b0eb0, which is still shy of the maximum
+0xff3b1000.
+
+Further, this skips enabling the watchdog when it's not being used
+elsewhere, as you can't turn the watchdog off.
+
+Unofficial patch made from:
+
+Change-Id: I2e6fa3c7e01f2be6b32ce04ce479edf64e278554
+Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
+---
+ plat/rockchip/rk3399/drivers/dram/suspend.c | 57 ++++++++++++++++++---
+ 1 file changed, 51 insertions(+), 6 deletions(-)
+
+diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c
+index 7f9fad1..dc2c16b 100644
+--- a/plat/rockchip/rk3399/drivers/dram/suspend.c
++++ b/plat/rockchip/rk3399/drivers/dram/suspend.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
++ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -562,8 +562,14 @@ static __pmusramfunc int dram_switch_to_next_index(
+ 
+ 	/* LPDDR4 f2 cann't do training, all training will fail */
+ 	for (ch = 0; ch < ch_count; ch++) {
+-		mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
+-				   fn << 8);
++		/*
++		 * Without this disabled for LPDDR4 we end up writing 0's in place
++		 * of real data in an interesting pattern.
++		 */
++		if (sdram_params->dramtype != LPDDR4) {
++			mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
++					fn << 8);
++		}
+ 
+ 		/* data_training failed */
+ 		if (data_training(ch, sdram_params, PI_FULL_TRAINING))
+@@ -660,6 +666,7 @@ __pmusramfunc static void pmusram_restore_pll(int pll_id, uint32_t *src)
+ 		;
+ }
+ 
++__attribute__((unused))
+ __pmusramfunc static void pmusram_enable_watchdog(void)
+ {
+ 	/* Make the watchdog use the first global reset. */
+@@ -748,13 +755,40 @@ void dmc_suspend(void)
+ 	phy_regs->phy896[0] &= ~(0x3 << 8);
+ }
+ 
++__pmusramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t freq) {
++	if (freq <= (125 * 1000 * 1000)) {
++		/* Set master mode to SW for slices*/
++		mmio_setbits_32(PHY_REG(ch, 86), 3 << 10);
++		mmio_setbits_32(PHY_REG(ch, 214), 3 << 10);
++		mmio_setbits_32(PHY_REG(ch, 342), 3 << 10);
++		mmio_setbits_32(PHY_REG(ch, 470), 3 << 10);
++		/* Set master mode to SW for address slices*/
++		mmio_setbits_32(PHY_REG(ch, 547), 3 << 18);
++		mmio_setbits_32(PHY_REG(ch, 675), 3 << 18);
++		mmio_setbits_32(PHY_REG(ch, 803), 3 << 18);
++	} else {
++		/* Clear SW master mode for slices*/
++		mmio_clrbits_32(PHY_REG(ch, 86), 3 << 10);
++		mmio_clrbits_32(PHY_REG(ch, 214), 3 << 10);
++		mmio_clrbits_32(PHY_REG(ch, 342), 3 << 10);
++		mmio_clrbits_32(PHY_REG(ch, 470), 3 << 10);
++		/* Clear SW master mode for address slices*/
++		mmio_clrbits_32(PHY_REG(ch, 547), 3 << 18);
++		mmio_clrbits_32(PHY_REG(ch, 675), 3 << 18);
++		mmio_clrbits_32(PHY_REG(ch, 803), 3 << 18);
++	}
++}
++
+ __pmusramfunc void dmc_resume(void)
+ {
+ 	struct rk3399_sdram_params *sdram_params = &sdram_config;
+ 	uint32_t channel_mask = 0;
+ 	uint32_t channel;
+ 
+-	pmusram_enable_watchdog();
++	/*
++	 * Note: I would love to enable the watchdog, but as it turns out,
++	 * resume with LPDDR4 crashes, because of the watchdog ATM.
++	 */
+ 	pmu_sgrf_rst_hld_release();
+ 	restore_pmu_rsthold();
+ 	sram_secure_timer_init();
+@@ -772,6 +806,13 @@ __pmusramfunc void dmc_resume(void)
+ retry:
+ 	for (channel = 0; channel < sdram_params->num_channels; channel++) {
+ 		phy_pctrl_reset(channel);
++		/*
++		 * Without this, LPDDR4 will write 0's in place of real data
++		 * in a strange pattern.
++		 */
++		if (sdram_params->dramtype == LPDDR4) {
++			phy_dll_bypass_set(channel, sdram_params->ddr_freq);
++		}
+ 		pctl_cfg(channel, sdram_params);
+ 	}
+ 
+@@ -788,8 +829,12 @@ retry:
+ 		if (sdram_params->dramtype == LPDDR3)
+ 			sram_udelay(10);
+ 
+-		/* If traning fail, retry to do it again. */
+-		if (data_training(channel, sdram_params, PI_FULL_TRAINING))
++		/*
++		 * Training here will always fail for LPDDR4, so skip it
++		 * If traning fail, retry to do it again.
++		 */
++		if (sdram_params->dramtype != LPDDR4 &&
++		    data_training(channel, sdram_params, PI_FULL_TRAINING))
+ 			goto retry;
+ 
+ 		set_ddrconfig(sdram_params, channel,
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+

patch/atf/atf-rk3399/fix-reset-in-v2.2.patch

@@ -1,56 +0,0 @@
-From f4707a3c40bfc752a24c427263f7cbe8d7adfcd6 Mon Sep 17 00:00:00 2001
-From: Vasily Khoruzhick <anarsoul@gmail.com>
-Date: Fri, 15 Nov 2019 08:25:02 -0800
-Subject: [PATCH] plat/rockchip: initialize reset and poweroff GPIOs with known
- invalid value
-
-And return NULL if we didn't get them in bl aux params otherwise reset and poweroff
-will be broken on platforms that do not have reset and poweroff GPIOs.
-
-Fixes: c1185ffde17c ("plat/rockchip: Switch to use new common BL aux parameter library")
-Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
----
- plat/rockchip/common/params_setup.c | 11 +++++++++--
- 1 file changed, 9 insertions(+), 2 deletions(-)
-
-diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
-index 8c2e5e911b..b2fd2011e4 100644
---- a/plat/rockchip/common/params_setup.c
-+++ b/plat/rockchip/common/params_setup.c
-@@ -6,6 +6,7 @@
- 
- #include <assert.h>
- #include <errno.h>
-+#include <limits.h>
- #include <string.h>
- 
- #include <lib/bl_aux_params/bl_aux_params.h>
-@@ -21,8 +22,8 @@
- #include <plat_params.h>
- #include <plat_private.h>
- 
--static struct bl_aux_gpio_info rst_gpio;
--static struct bl_aux_gpio_info poweroff_gpio;
-+static struct bl_aux_gpio_info rst_gpio = { .index = UINT_MAX } ;
-+static struct bl_aux_gpio_info poweroff_gpio = { .index = UINT_MAX };
- static struct bl_aux_gpio_info suspend_gpio[10];
- uint32_t suspend_gpio_cnt;
- static struct bl_aux_rk_apio_info suspend_apio;
-@@ -174,11 +175,17 @@ uint32_t rockchip_get_uart_clock(void)
- 
- struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void)
- {
-+	if (rst_gpio.index == UINT_MAX)
-+		return NULL;
-+
- 	return &rst_gpio;
- }
- 
- struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void)
- {
-+	if (poweroff_gpio.index == UINT_MAX)
-+		return NULL;
-+
- 	return &poweroff_gpio;
- }
- 

patch/atf/atf-rk3399/switch-power-domains-on-before-reset.patch

@@ -1,63 +0,0 @@
-diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
-index 42589b9..8f2a419 100644
---- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
-+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
-@@ -400,7 +400,26 @@ static void pmu_power_domains_resume(void)
- 	clk_gate_con_restore();
- }
- 
--void rk3399_flush_l2_b(void)
-+void pmu_power_domains_on(void)
-+{
-+	clk_gate_con_disable();
-+	pmu_set_power_domain(PD_VDU, pmu_pd_on);
-+	pmu_set_power_domain(PD_VCODEC, pmu_pd_on);
-+	pmu_set_power_domain(PD_RGA, pmu_pd_on);
-+	pmu_set_power_domain(PD_IEP, pmu_pd_on);
-+	pmu_set_power_domain(PD_EDP, pmu_pd_on);
-+	pmu_set_power_domain(PD_GMAC, pmu_pd_on);
-+	pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on);
-+	pmu_set_power_domain(PD_HDCP, pmu_pd_on);
-+	pmu_set_power_domain(PD_ISP1, pmu_pd_on);
-+	pmu_set_power_domain(PD_ISP0, pmu_pd_on);
-+	pmu_set_power_domain(PD_VO, pmu_pd_on);
-+	pmu_set_power_domain(PD_TCPD1, pmu_pd_on);
-+	pmu_set_power_domain(PD_TCPD0, pmu_pd_on);
-+	pmu_set_power_domain(PD_GPU, pmu_pd_on);
-+}
-+
-+void rk3399_flush_l2_b(void)
- {
- 	uint32_t wait_cnt = 0;
- 
-diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
-index e1ba410..27a453b 100644
---- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
-+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
-@@ -136,5 +136,6 @@ struct pmu_slpdata_s {
- extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT];
- 
- extern void sram_func_set_ddrctl_pll(uint32_t pll_src);
-+void pmu_power_domains_on(void);
- 
- #endif /* PMU_H */
-diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
-index c877dbd..98b5ad6 100644
---- a/plat/rockchip/rk3399/drivers/soc/soc.c
-+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
-@@ -17,6 +17,7 @@
- #include <dram.h>
- #include <m0_ctl.h>
- #include <plat_private.h>
-+#include <pmu.h>
- #include <rk3399_def.h>
- #include <secure.h>
- #include <soc.h>
-@@ -327,6 +328,7 @@ void soc_global_soft_reset_init(void)
- 
- void __dead2 soc_global_soft_reset(void)
- {
-+	pmu_power_domains_on();
- 	set_pll_slow_mode(VPLL_ID);
- 	set_pll_slow_mode(NPLL_ID);
- 	set_pll_slow_mode(GPLL_ID);