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https://github.com/LibreELEC/LibreELEC.tv
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67 lines
2.2 KiB
Diff
67 lines
2.2 KiB
Diff
From 809dafc9a1ec60907dd77324a8193fb06c5218b7 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Fri, 1 Aug 2025 17:10:15 +0300
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Subject: [PATCH 090/113] FROMLIST(v4): phy: rockchip: samsung-hdptx: Drop
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hw_rate driver data
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The ->hw_rate member of struct rk_hdptx_phy was mainly used to keep
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track of the clock rate programmed in hardware and support implementing
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the ->recalc_rate() callback in hdptx_phy_clk_ops.
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Computing the clock rate from the actual PHY PLL configuration seems to
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work reliably, hence remove the now redundant struct member.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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---
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drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 13 ++-----------
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1 file changed, 2 insertions(+), 11 deletions(-)
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diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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index 6e2443f78968..4195387108d8 100644
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--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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@@ -401,7 +401,6 @@ struct rk_hdptx_phy {
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/* clk provider */
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struct clk_hw hw;
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- unsigned long hw_rate;
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bool restrict_rate_change;
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atomic_t usage_count;
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@@ -964,7 +963,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
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{
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const struct ropll_config *cfg = NULL;
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struct ropll_config rc = {0};
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- int ret, i;
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+ int i;
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if (!hdptx->hdmi_cfg.tmds_char_rate)
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return 0;
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@@ -1026,12 +1025,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
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regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK,
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FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1));
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- ret = rk_hdptx_post_enable_pll(hdptx);
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- if (!ret)
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- hdptx->hw_rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8,
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- hdptx->hdmi_cfg.bpc);
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-
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- return ret;
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+ return rk_hdptx_post_enable_pll(hdptx);
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}
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static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
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@@ -1936,9 +1930,6 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
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u64 rate;
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int ret;
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- if (hdptx->hw_rate)
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- return hdptx->hw_rate;
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-
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ret = regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status);
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if (ret || !(status & HDPTX_I_PLL_EN))
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return 0;
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--
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2.34.1
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