mirror of
https://github.com/LibreELEC/LibreELEC.tv
synced 2025-09-24 19:46:01 +07:00
71 lines
2.8 KiB
Diff
71 lines
2.8 KiB
Diff
From 41e5fedc7c85557b5530b346db9f90b73658be20 Mon Sep 17 00:00:00 2001
|
|
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
|
Date: Mon, 28 Jul 2025 22:52:42 +0300
|
|
Subject: [PATCH 080/113] FROMLIST(v1): phy: rockchip: samsung-hdptx: Fix
|
|
reported clock rate in high bpc mode
|
|
|
|
When making use of the clock provider functionality, the output clock
|
|
does normally match the TMDS character rate, which is what the PHY PLL
|
|
gets configured to.
|
|
|
|
However, this is only applicable for default color depth of 8 bpc. For
|
|
higher depths, the output clock is further divided by the hardware
|
|
according to the formula:
|
|
|
|
output_clock_rate = tmds_char_rate * 8 / bpc
|
|
|
|
Since the existence of the clock divider wasn't taken into account when
|
|
support for high bpc has been introduced, make the necessary adjustments
|
|
to report the correct clock rate.
|
|
|
|
Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management")
|
|
Reported-by: Andy Yan <andy.yan@rock-chips.com>
|
|
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
|
---
|
|
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 14 ++++++++------
|
|
1 file changed, 8 insertions(+), 6 deletions(-)
|
|
|
|
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
|
|
index 79db57ee90d1..8adf6e84fc0b 100644
|
|
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
|
|
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
|
|
@@ -1038,7 +1038,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
|
|
|
|
ret = rk_hdptx_post_enable_pll(hdptx);
|
|
if (!ret)
|
|
- hdptx->hw_rate = hdptx->hdmi_cfg.tmds_char_rate;
|
|
+ hdptx->hw_rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8,
|
|
+ hdptx->hdmi_cfg.bpc);
|
|
|
|
return ret;
|
|
}
|
|
@@ -1896,19 +1897,20 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
* hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with
|
|
* a different rate argument.
|
|
*/
|
|
- return hdptx->hdmi_cfg.tmds_char_rate;
|
|
+ return DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, hdptx->hdmi_cfg.bpc);
|
|
}
|
|
|
|
static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
|
|
+ unsigned long long tmds_rate = DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8);
|
|
|
|
/* Revert any unlikely TMDS char rate change since round_rate() */
|
|
- if (hdptx->hdmi_cfg.tmds_char_rate != rate) {
|
|
- dev_warn(hdptx->dev, "Reverting unexpected rate change from %lu to %llu\n",
|
|
- rate, hdptx->hdmi_cfg.tmds_char_rate);
|
|
- hdptx->hdmi_cfg.tmds_char_rate = rate;
|
|
+ if (hdptx->hdmi_cfg.tmds_char_rate != tmds_rate) {
|
|
+ dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu\n",
|
|
+ tmds_rate, hdptx->hdmi_cfg.tmds_char_rate);
|
|
+ hdptx->hdmi_cfg.tmds_char_rate = tmds_rate;
|
|
}
|
|
|
|
/*
|
|
--
|
|
2.34.1
|
|
|