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https://github.com/LibreELEC/LibreELEC.tv
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114 lines
3.7 KiB
Diff
114 lines
3.7 KiB
Diff
From e929fb875b5f8e89b18ef46936f60004ea69b2bf Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Mon, 25 Aug 2025 13:08:32 +0300
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Subject: [PATCH 058/113] FROMLIST(v2): drm/rockchip: vop2: Check bpc before
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switching DCLK source
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When making use of the HDMI PHY PLL as a VOP2 DCLK source, it's output
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rate does normally match the mode clock. But this is only applicable
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for default color depth of 8 bpc. For higher depths, the output clock
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is further divided by the hardware according to the formula:
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output rate = PHY PLL rate * 8 / bpc
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Hence there is no need for VOP2 to compensate for bpc when adjusting
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DCLK, but it is required to do so when computing its maximum operating
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frequency.
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Take color depth into consideration before deciding to switch DCLK
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source.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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---
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drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 60 ++++++++++++--------
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1 file changed, 36 insertions(+), 24 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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index b50927a824b4..977ccbf16344 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -101,7 +101,7 @@ enum vop2_afbc_format {
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VOP2_AFBC_FMT_INVALID = -1,
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};
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-#define VOP2_MAX_DCLK_RATE 600000000
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+#define VOP2_MAX_DCLK_RATE 600000000UL
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/*
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* bus-format types.
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@@ -1737,36 +1737,48 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
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* Switch to HDMI PHY PLL as DCLK source for display modes up
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* to 4K@60Hz, if available, otherwise keep using the system CRU.
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*/
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- if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <= VOP2_MAX_DCLK_RATE) {
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- drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
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- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
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+ if (vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) {
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+ unsigned long max_dclk;
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- if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) {
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- if (!vop2->pll_hdmiphy0)
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- break;
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+ if (vcstate->output_bpc > 8)
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+ max_dclk = DIV_ROUND_CLOSEST_ULL(VOP2_MAX_DCLK_RATE * 8,
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+ vcstate->output_bpc);
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+ else
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+ max_dclk = VOP2_MAX_DCLK_RATE;
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- if (!vp->dclk_src)
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- vp->dclk_src = clk_get_parent(vp->dclk);
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+ if (clock <= max_dclk) {
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+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
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+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
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- ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0);
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- if (ret < 0)
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- drm_warn(vop2->drm,
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- "Could not switch to HDMI0 PHY PLL: %d\n", ret);
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- break;
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- }
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+ if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) {
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+ if (!vop2->pll_hdmiphy0)
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+ break;
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+
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+ if (!vp->dclk_src)
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+ vp->dclk_src = clk_get_parent(vp->dclk);
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- if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI1) {
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- if (!vop2->pll_hdmiphy1)
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+ ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0);
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+ if (ret < 0)
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+ drm_warn(vop2->drm,
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+ "Could not switch to HDMI0 PHY PLL: %d\n",
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+ ret);
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break;
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+ }
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- if (!vp->dclk_src)
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- vp->dclk_src = clk_get_parent(vp->dclk);
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+ if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI1) {
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+ if (!vop2->pll_hdmiphy1)
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+ break;
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- ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1);
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- if (ret < 0)
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- drm_warn(vop2->drm,
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- "Could not switch to HDMI1 PHY PLL: %d\n", ret);
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- break;
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+ if (!vp->dclk_src)
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+ vp->dclk_src = clk_get_parent(vp->dclk);
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+
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+ ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1);
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+ if (ret < 0)
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+ drm_warn(vop2->drm,
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+ "Could not switch to HDMI1 PHY PLL: %d\n",
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+ ret);
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+ break;
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+ }
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}
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}
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}
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--
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2.34.1
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