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https://github.com/LibreELEC/LibreELEC.tv
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113 lines
3.2 KiB
Diff
113 lines
3.2 KiB
Diff
From a77b197930d1b8c2890c12b9d128eba23361c067 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Wed, 2 Sep 2020 19:52:02 +0200
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Subject: [PATCH 36/59] WIP/1002: arm64: dts: rockchip: add gpu powerdomain,
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gpu opp-table and cooling cell for RK3328
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Note: since the regulator that supplies the GPU usually also supplies
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other SoC components, we have to make sure voltage is never lower then
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1075 mV - also disable 500 MHz for now, since it will crash if rkvdec
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is running at the same time (voltage too high)
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Signed-off-by: Alex Bee <knaerzche@gmail.com>
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---
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arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 4 +++
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.../arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 +++
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arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 +++++++++++++++++++
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3 files changed, 43 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
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index b5bd5e7d5748..7eef6f7f108f 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
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@@ -160,6 +160,10 @@ &gmac2io {
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status = "okay";
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};
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+&gpu {
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+ mali-supply = <&vdd_logic>;
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+};
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+
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&hdmi {
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status = "okay";
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};
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
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index 5367e5fa9232..592fd8ca21df 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
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@@ -152,6 +152,10 @@ &gmac2io {
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status = "okay";
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};
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+&gpu {
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+ mali-supply = <&vdd_logic>;
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+};
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+
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&hdmi {
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avdd-0v9-supply = <&vdd_10>;
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avdd-1v8-supply = <&vcc_18>;
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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index 48d1a6292818..e3beadde6c07 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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@@ -331,6 +331,11 @@ power: power-controller {
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#address-cells = <1>;
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#size-cells = <0>;
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+ power-domain@RK3328_PD_GPU {
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+ reg = <RK3328_PD_GPU>;
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+ clocks = <&cru ACLK_GPU>;
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+ #power-domain-cells = <0>;
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+ };
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power-domain@RK3328_PD_HEVC {
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reg = <RK3328_PD_HEVC>;
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clocks = <&cru SCLK_VENC_CORE>;
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@@ -570,6 +575,11 @@ map0 {
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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contribution = <4096>;
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};
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+ map1 {
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+ trip = <&target>;
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+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ contribution = <4096>;
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+ };
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};
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};
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@@ -651,7 +661,32 @@ gpu: gpu@ff300000 {
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"ppmmu1";
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clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
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clock-names = "bus", "core";
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+ operating-points-v2 = <&gpu_opp_table>;
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+ power-domains = <&power RK3328_PD_GPU>;
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resets = <&cru SRST_GPU_A>;
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+ #cooling-cells = <2>;
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+ };
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+
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+ gpu_opp_table: gpu-opp-table {
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+ compatible = "operating-points-v2";
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+
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+ opp-200000000 {
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+ opp-hz = /bits/ 64 <200000000>;
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+ opp-microvolt = <1075000>;
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+ };
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+ opp-300000000 {
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+ opp-hz = /bits/ 64 <300000000>;
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+ opp-microvolt = <1075000>;
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+ };
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+ opp-400000000 {
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+ opp-hz = /bits/ 64 <400000000>;
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+ opp-microvolt = <1075000>;
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+ };
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+ opp-500000000 {
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+ opp-hz = /bits/ 64 <500000000>;
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+ opp-microvolt = <1150000>;
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+ status = "disabled";
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+ };
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};
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h265e_mmu: iommu@ff330200 {
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--
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2.34.1
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