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https://github.com/LibreELEC/LibreELEC.tv
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45 lines
1.6 KiB
Diff
45 lines
1.6 KiB
Diff
From 51babedd158973b9b578fda731177705b453e339 Mon Sep 17 00:00:00 2001
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From: Christian Hewitt <christianshewitt@gmail.com>
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Date: Sun, 13 Feb 2022 08:53:39 +0000
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Subject: [PATCH 51/75] WIP: drm/meson/meson_vclk: fix VIC alternate timings
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4K VP9 media with 59.94 fractional refresh rate refuses to play with
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the screen going blank (no sync) and the following error reported in
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system logs:
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[ 89.610280] Fatal Error, invalid HDMI vclk freq 593406
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Modetest shows the following:
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3840x2160 59.94 3840 4016 4104 4400 2160 2168 2178 2250 593407 flags: phsync, pvsync; type: driver
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calculated value -----------------------------------------^
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Tweaking DIV_ROUND_CLOSEST to use 1002 in calculations allows 593406
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to match and 4K 59.94 media now plays correctly.
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Unfortunately this is not a proper fix and it's not guaranteed to
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work for everyone. It points and issue with clocks/precision somewhere.
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Fixes: ff217bc710e0 ("drm/meson: Add support for VIC alternate timings")
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Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
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---
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drivers/gpu/drm/meson/meson_vclk.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
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index 2a82119eb58e..3fc7d9cb9953 100644
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--- a/drivers/gpu/drm/meson/meson_vclk.c
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+++ b/drivers/gpu/drm/meson/meson_vclk.c
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@@ -110,7 +110,7 @@
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#define HDMI_PLL_LOCK BIT(31)
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#define HDMI_PLL_LOCK_G12A (3 << 30)
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-#define FREQ_1000_1001(_freq) DIV_ROUND_CLOSEST(_freq * 1000, 1001)
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+#define FREQ_1000_1001(_freq) DIV_ROUND_CLOSEST(_freq * 1000, 1002)
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/* VID PLL Dividers */
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enum {
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--
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2.17.1
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