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63 lines
1.7 KiB
Diff
63 lines
1.7 KiB
Diff
From 00dc3a05e11e2930fa13bac35765a3ce6c596808 Mon Sep 17 00:00:00 2001
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From: Dongjin Kim <tobetter@gmail.com>
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Date: Thu, 10 Sep 2020 11:01:33 +0900
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Subject: [PATCH 28/54] WIP: drm/meson: add support for 2560x1440 resolution
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output
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Add support for Quad HD (QHD) 2560x1440 resolution output. Timings
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have been adapted from the vendor kernel.
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Signed-off-by: Joy Cho <joy.cho@hardkernel.com>
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Signed-off-by: Dongjin Kim <tobetter@gmail.com>
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Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
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---
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drivers/gpu/drm/meson/meson_vclk.c | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
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index dfe0c28a0f05..f5385b3e3796 100644
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--- a/drivers/gpu/drm/meson/meson_vclk.c
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+++ b/drivers/gpu/drm/meson/meson_vclk.c
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@@ -357,6 +357,8 @@ enum {
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MESON_VCLK_HDMI_594000,
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/* 2970 /1 /1 /1 /5 /1 => /1 /2 */
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MESON_VCLK_HDMI_594000_YUV420,
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+/* 4830 /2 /1 /2 /5 /1 => /1 /1 */
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+ MESON_VCLK_HDMI_241500,
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};
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struct meson_vclk_params {
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@@ -467,6 +469,18 @@ struct meson_vclk_params {
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.vid_pll_div = VID_PLL_DIV_5,
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.vclk_div = 1,
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},
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+ [MESON_VCLK_HDMI_241500] = {
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+ .pll_freq = 4830000000,
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+ .phy_freq = 2415000000,
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+ .venc_freq = 241500000,
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+ .vclk_freq = 241500000,
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+ .pixel_freq = 241500000,
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+ .pll_od1 = 2,
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+ .pll_od2 = 1,
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+ .pll_od3 = 2,
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+ .vid_pll_div = VID_PLL_DIV_5,
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+ .vclk_div = 1,
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+ },
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{ /* sentinel */ },
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};
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@@ -894,6 +908,10 @@ static void meson_vclk_set(struct meson_drm *priv,
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m = 0xf7;
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frac = vic_alternate_clock ? 0x8148 : 0x10000;
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break;
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+ case 4830000:
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+ m = 0xc9;
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+ frac = 0xd560;
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+ break;
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}
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meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
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--
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2.34.1
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