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https://github.com/LibreELEC/LibreELEC.tv
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143 lines
3.9 KiB
Diff
143 lines
3.9 KiB
Diff
From fd85ad679733c0affc0fa89606a3c6f7e7d1280f Mon Sep 17 00:00:00 2001
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From: Anand Moon <linux.amoon@gmail.com>
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Date: Mon, 25 Aug 2025 12:21:50 +0530
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Subject: [PATCH 15/54] FROMGIT(6.18): arm64: dts: amlogic: Add cache
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information to the Amlogic S922X SoC
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As per S922X datasheet add missing cache information to the Amlogic
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S922X SoC.
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- Each Cortex-A53 core has 32 KB of instruction cache and
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32 KB of L1 data cache available.
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- Each Cortex-A73 core has 64 KB of L1 instruction cache and
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64 KB of L1 data cache available.
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- The little (A53) cluster has 256 KB of unified L2 cache available.
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- The big (A73) cluster has 1 MB of unified L2 cache available.
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Cache memory significantly reduces the time it takes for the CPU
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to access data and instructions, leading to faster program execution
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and overall system responsiveness.
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Signed-off-by: Anand Moon <linux.amoon@gmail.com>
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---
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arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 62 ++++++++++++++++++---
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1 file changed, 55 insertions(+), 7 deletions(-)
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diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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index 86e6ceb31d5e..f04efa828256 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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@@ -49,7 +49,13 @@ cpu0: cpu@0 {
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reg = <0x0 0x0>;
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enable-method = "psci";
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capacity-dmips-mhz = <592>;
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- next-level-cache = <&l2>;
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+ d-cache-line-size = <32>;
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+ d-cache-size = <0x8000>;
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+ d-cache-sets = <32>;
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+ i-cache-line-size = <32>;
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+ i-cache-size = <0x8000>;
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+ i-cache-sets = <32>;
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+ next-level-cache = <&l2_cache_l>;
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#cooling-cells = <2>;
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};
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@@ -59,7 +65,13 @@ cpu1: cpu@1 {
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reg = <0x0 0x1>;
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enable-method = "psci";
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capacity-dmips-mhz = <592>;
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- next-level-cache = <&l2>;
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+ d-cache-line-size = <32>;
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+ d-cache-size = <0x8000>;
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+ d-cache-sets = <32>;
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+ i-cache-line-size = <32>;
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+ i-cache-size = <0x8000>;
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+ i-cache-sets = <32>;
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+ next-level-cache = <&l2_cache_l>;
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#cooling-cells = <2>;
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};
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@@ -69,7 +81,13 @@ cpu100: cpu@100 {
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reg = <0x0 0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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- next-level-cache = <&l2>;
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+ d-cache-line-size = <32>;
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+ d-cache-size = <0x8000>;
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+ d-cache-sets = <32>;
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+ i-cache-line-size = <32>;
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+ i-cache-size = <0x8000>;
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+ i-cache-sets = <32>;
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+ next-level-cache = <&l2_cache_l>;
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#cooling-cells = <2>;
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};
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@@ -79,7 +97,13 @@ cpu101: cpu@101 {
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reg = <0x0 0x101>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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- next-level-cache = <&l2>;
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+ d-cache-line-size = <32>;
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+ d-cache-size = <0x8000>;
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+ d-cache-sets = <32>;
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+ i-cache-line-size = <32>;
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+ i-cache-size = <0x8000>;
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+ i-cache-sets = <32>;
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+ next-level-cache = <&l2_cache_l>;
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#cooling-cells = <2>;
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};
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@@ -89,7 +113,13 @@ cpu102: cpu@102 {
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reg = <0x0 0x102>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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- next-level-cache = <&l2>;
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+ d-cache-line-size = <64>;
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+ d-cache-size = <0x10000>;
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+ d-cache-sets = <64>;
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+ i-cache-line-size = <64>;
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+ i-cache-size = <0x10000>;
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+ i-cache-sets = <64>;
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+ next-level-cache = <&l2_cache_b>;
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#cooling-cells = <2>;
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};
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@@ -99,14 +129,32 @@ cpu103: cpu@103 {
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reg = <0x0 0x103>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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- next-level-cache = <&l2>;
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+ d-cache-line-size = <64>;
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+ d-cache-size = <0x10000>;
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+ d-cache-sets = <64>;
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+ i-cache-line-size = <64>;
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+ i-cache-size = <0x10000>;
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+ i-cache-sets = <64>;
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+ next-level-cache = <&l2_cache_b>;
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#cooling-cells = <2>;
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};
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- l2: l2-cache0 {
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+ l2_cache_l: l2-cache-cluster0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ cache-size = <0x40000>; /* L2. 256 KB */
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+ cache-line-size = <64>;
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+ cache-sets = <512>;
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+ };
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+
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+ l2_cache_b: l2-cache-cluster1 {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ cache-unified;
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+ cache-size = <0x100000>; /* L2. 1MB */
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+ cache-line-size = <64>;
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+ cache-sets = <512>;
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};
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};
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};
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--
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2.34.1
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