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92 lines
2.6 KiB
Diff
92 lines
2.6 KiB
Diff
From 8f6a387b7ad84170a309872f72b586f4c8a38d31 Mon Sep 17 00:00:00 2001
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From: Anand Moon <linux.amoon@gmail.com>
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Date: Mon, 25 Aug 2025 12:21:43 +0530
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Subject: [PATCH 14/54] FROMGIT(6.18): arm64: dts: amlogic: Add cache
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information to the Amlogic G12A SoCS
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As per the S905X2 datasheet add missing cache information to the Amlogic
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G12A SoC.
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- Each Cortex-A53 core has 32KB of L1 instruction cache available and
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32KB of L1 data cache available.
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- Along with 512KB Unified L2 cache.
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Cache memory significantly reduces the time it takes for the CPU
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to access data and instructions, leading to faster program execution
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and overall system responsiveness.
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Signed-off-by: Anand Moon <linux.amoon@gmail.com>
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---
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arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
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1 file changed, 27 insertions(+)
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diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
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index deee61dbe074..1321ad95923d 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
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@@ -17,6 +17,12 @@ cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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+ d-cache-line-size = <32>;
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+ d-cache-size = <0x8000>;
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+ d-cache-sets = <32>;
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+ i-cache-line-size = <32>;
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+ i-cache-size = <0x8000>;
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+ i-cache-sets = <32>;
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next-level-cache = <&l2>;
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#cooling-cells = <2>;
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};
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@@ -26,6 +32,12 @@ cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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+ d-cache-line-size = <32>;
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+ d-cache-size = <0x8000>;
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+ d-cache-sets = <32>;
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+ i-cache-line-size = <32>;
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+ i-cache-size = <0x8000>;
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+ i-cache-sets = <32>;
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next-level-cache = <&l2>;
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#cooling-cells = <2>;
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};
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@@ -35,6 +47,12 @@ cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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+ d-cache-line-size = <32>;
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+ d-cache-size = <0x8000>;
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+ d-cache-sets = <32>;
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+ i-cache-line-size = <32>;
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+ i-cache-size = <0x8000>;
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+ i-cache-sets = <32>;
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next-level-cache = <&l2>;
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#cooling-cells = <2>;
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};
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@@ -44,6 +62,12 @@ cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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+ d-cache-line-size = <32>;
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+ d-cache-size = <0x8000>;
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+ d-cache-sets = <32>;
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+ i-cache-line-size = <32>;
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+ i-cache-size = <0x8000>;
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+ i-cache-sets = <32>;
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next-level-cache = <&l2>;
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#cooling-cells = <2>;
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};
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@@ -52,6 +76,9 @@ l2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ cache-size = <0x80000>; /* L2. 512 KB */
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+ cache-line-size = <64>;
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+ cache-sets = <512>;
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};
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};
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--
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2.34.1
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