mirror of
https://github.com/LibreELEC/LibreELEC.tv
synced 2025-09-24 19:46:01 +07:00
82 lines
2.5 KiB
Diff
82 lines
2.5 KiB
Diff
From 16c9fa28fcb4a8193fedd2841b317d1384c5be63 Mon Sep 17 00:00:00 2001
|
|
From: Anand Moon <linux.amoon@gmail.com>
|
|
Date: Mon, 25 Aug 2025 12:21:45 +0530
|
|
Subject: [PATCH 13/54] FROMGIT(6.18): arm64: dts: amlogic: Add cache
|
|
information to the Amlogic GXM SoCS
|
|
|
|
As per the GXM datasheet add missing cache information to the Amlogic GXM
|
|
SoC.
|
|
|
|
- Each Cortex-A53 core has 32KB of L1 instruction cache available and
|
|
32KB of L1 data cache available.
|
|
- Along with 512KB Unified L2 cache.
|
|
|
|
Cache memory significantly reduces the time it takes for the CPU
|
|
to access data and instructions, leading to faster program execution
|
|
and overall system responsiveness.
|
|
|
|
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
|
|
---
|
|
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 24 ++++++++++++++++++++++
|
|
1 file changed, 24 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
|
|
index 411cc312fc62..514c9bea6423 100644
|
|
--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
|
|
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
|
|
@@ -64,6 +64,12 @@ cpu4: cpu@100 {
|
|
reg = <0x0 0x100>;
|
|
enable-method = "psci";
|
|
capacity-dmips-mhz = <1024>;
|
|
+ d-cache-line-size = <32>;
|
|
+ d-cache-size = <0x8000>;
|
|
+ d-cache-sets = <32>;
|
|
+ i-cache-line-size = <32>;
|
|
+ i-cache-size = <0x8000>;
|
|
+ i-cache-sets = <32>;
|
|
next-level-cache = <&l2>;
|
|
clocks = <&scpi_dvfs 1>;
|
|
#cooling-cells = <2>;
|
|
@@ -75,6 +81,12 @@ cpu5: cpu@101 {
|
|
reg = <0x0 0x101>;
|
|
enable-method = "psci";
|
|
capacity-dmips-mhz = <1024>;
|
|
+ d-cache-line-size = <32>;
|
|
+ d-cache-size = <0x8000>;
|
|
+ d-cache-sets = <32>;
|
|
+ i-cache-line-size = <32>;
|
|
+ i-cache-size = <0x8000>;
|
|
+ i-cache-sets = <32>;
|
|
next-level-cache = <&l2>;
|
|
clocks = <&scpi_dvfs 1>;
|
|
#cooling-cells = <2>;
|
|
@@ -86,6 +98,12 @@ cpu6: cpu@102 {
|
|
reg = <0x0 0x102>;
|
|
enable-method = "psci";
|
|
capacity-dmips-mhz = <1024>;
|
|
+ d-cache-line-size = <32>;
|
|
+ d-cache-size = <0x8000>;
|
|
+ d-cache-sets = <32>;
|
|
+ i-cache-line-size = <32>;
|
|
+ i-cache-size = <0x8000>;
|
|
+ i-cache-sets = <32>;
|
|
next-level-cache = <&l2>;
|
|
clocks = <&scpi_dvfs 1>;
|
|
#cooling-cells = <2>;
|
|
@@ -97,6 +115,12 @@ cpu7: cpu@103 {
|
|
reg = <0x0 0x103>;
|
|
enable-method = "psci";
|
|
capacity-dmips-mhz = <1024>;
|
|
+ d-cache-line-size = <32>;
|
|
+ d-cache-size = <0x8000>;
|
|
+ d-cache-sets = <32>;
|
|
+ i-cache-line-size = <32>;
|
|
+ i-cache-size = <0x8000>;
|
|
+ i-cache-sets = <32>;
|
|
next-level-cache = <&l2>;
|
|
clocks = <&scpi_dvfs 1>;
|
|
#cooling-cells = <2>;
|
|
--
|
|
2.34.1
|
|
|