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https://github.com/LibreELEC/LibreELEC.tv
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50 lines
2.0 KiB
Diff
50 lines
2.0 KiB
Diff
From 32431fd81d65259d490e53e3cfc7e1a2ad781fe3 Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Tue, 16 Dec 2014 08:44:31 +0000
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Subject: [PATCH] drm/i915: Invalidate media caches on gen7
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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In the gen7 pipe control there is an extra bit to flush the media
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caches, so let's set it during cache invalidation flushes.
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v2: Rename to MEDIA_STATE_CLEAR to be more inline with spec.
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Cc: Simon Farnsworth <simon@farnz.org.uk>
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Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Cc: stable@vger.kernel.org
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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---
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drivers/gpu/drm/i915/i915_reg.h | 1 +
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drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
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2 files changed, 2 insertions(+)
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index c01e5f3..d9780e2 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -370,6 +370,7 @@
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#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
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#define PIPE_CONTROL_CS_STALL (1<<20)
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#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
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+#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
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#define PIPE_CONTROL_QW_WRITE (1<<14)
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#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
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#define PIPE_CONTROL_DEPTH_STALL (1<<13)
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diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
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index 0a80e41..b02cf69 100644
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--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
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+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
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@@ -362,6 +362,7 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
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flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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+ flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
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/*
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* TLB invalidate requires a post-sync write.
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*/
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