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48 lines
2.0 KiB
Diff
48 lines
2.0 KiB
Diff
From 502427f80bfe0b3fa3536f6dea7904e84a45e3e9 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Wed, 4 Jun 2025 10:25:49 +0300
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Subject: [PATCH 086/110] FROMLIST(v4): phy: rockchip: samsung-hdptx: Enable
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lane output in common helper
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In preparation to support FRL mode, move the PHY lane output enablement
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from the TMDS specific configuration to the common *_post_enable_lane()
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helper and make sure it gets turned off in *_phy_disable().
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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---
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drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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index f2202b1195e7..3bb4ce993088 100644
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--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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@@ -830,6 +830,8 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
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HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
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regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
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+ regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
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+
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ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
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(val & HDPTX_O_PHY_RDY) &&
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(val & HDPTX_O_PLL_LOCK_DONE),
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@@ -883,6 +885,7 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
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usleep_range(20, 30);
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reset_control_deassert(hdptx->rsts[RST_APB].rstc);
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+ regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0);
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regmap_write(hdptx->regmap, LANE_REG(0300), 0x82);
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regmap_write(hdptx->regmap, SB_REG(010f), 0xc1);
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regmap_write(hdptx->regmap, SB_REG(0110), 0x1);
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@@ -1060,7 +1063,6 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
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}
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regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
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- regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
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rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq);
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rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq);
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--
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2.34.1
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