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https://github.com/LibreELEC/LibreELEC.tv
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84 lines
2.9 KiB
Diff
84 lines
2.9 KiB
Diff
From 767ba6b92dd6b409208540b8fe2e57361b20afb6 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Wed, 3 Sep 2025 21:51:00 +0300
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Subject: [PATCH 052/110] FROMLIST(v4): drm/bridge: dw-hdmi-qp: Fixup timer
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base setup
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Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed
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value as initially found in vendor driver code supporting the RK3588
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SoC. As a matter of fact the value matches the rate of the HDMI TX
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reference clock, which is roughly 428.57 MHz.
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However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and
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the incorrect register configuration breaks CEC functionality.
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Set the timer base according to the actual reference clock rate that
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shall be provided by the platform driver. Otherwise fallback to the
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vendor default.
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While at it, also drop the unnecessary empty lines in
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dw_hdmi_qp_init_hw().
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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---
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drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 12 +++++++++---
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include/drm/bridge/dw_hdmi_qp.h | 1 +
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2 files changed, 10 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
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index 1ab30dfaf988..a1fc3de58fb7 100644
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--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
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+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
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@@ -161,6 +161,7 @@ struct dw_hdmi_qp {
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void *data;
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} phy;
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+ unsigned long ref_clk_rate;
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struct regmap *regm;
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unsigned long tmds_char_rate;
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@@ -1209,13 +1210,11 @@ static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *hdmi)
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{
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dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N);
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dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N);
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- dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0);
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+ dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0);
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/* Software reset */
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dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
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-
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dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0);
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-
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dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0);
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/* Clear DONE and ERROR interrupts */
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@@ -1261,6 +1260,13 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
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hdmi->phy.ops = plat_data->phy_ops;
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hdmi->phy.data = plat_data->phy_data;
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+ if (plat_data->ref_clk_rate) {
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+ hdmi->ref_clk_rate = plat_data->ref_clk_rate;
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+ } else {
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+ hdmi->ref_clk_rate = 428571429;
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+ dev_warn(dev, "Set ref_clk_rate to vendor default\n");
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+ }
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+
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dw_hdmi_qp_init_hw(hdmi);
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ret = devm_request_threaded_irq(dev, plat_data->main_irq,
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diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_qp.h
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index b4a9b739734e..76ecf3130199 100644
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--- a/include/drm/bridge/dw_hdmi_qp.h
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+++ b/include/drm/bridge/dw_hdmi_qp.h
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@@ -24,6 +24,7 @@ struct dw_hdmi_qp_plat_data {
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void *phy_data;
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int main_irq;
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int cec_irq;
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+ unsigned long ref_clk_rate;
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};
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struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
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--
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2.34.1
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