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https://github.com/LibreELEC/LibreELEC.tv
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73 lines
2.6 KiB
Diff
73 lines
2.6 KiB
Diff
From d5f7dbd36b24426c2b826f25ebd1016ecc7ce066 Mon Sep 17 00:00:00 2001
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From: Detlev Casanova <detlev.casanova@collabora.com>
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Date: Mon, 23 Jun 2025 12:07:18 -0400
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Subject: [PATCH 007/110] FROMGIT(6.18): arm64: dts: rockchip: Add the vdpu383
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Video Decoder on rk3576
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Add the vdpu383 Video Decoder variant to the RK3576 device tree.
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Also allow using the dedicated SRAM as a pool.
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Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++
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1 file changed, 36 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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index c3cdae8a5494..b99f4bd4c9d9 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -1139,6 +1139,41 @@ gpu: gpu@27800000 {
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status = "disabled";
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};
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+ vdec: video-codec@27b00000 {
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+ compatible = "rockchip,rk3576-vdec";
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+ reg = <0x0 0x27b00100 0x0 0x500>,
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+ <0x0 0x27b00000 0x0 0x100>,
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+ <0x0 0x27b00600 0x0 0x100>;
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+ reg-names = "function", "link", "cache";
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+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>,
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+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>,
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+ <&cru CLK_RKVDEC_HEVC_CA>;
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+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>,
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+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>;
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+ assigned-clock-rates = <600000000>, <600000000>,
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+ <500000000>, <1000000000>;
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+ iommus = <&vdec_mmu>;
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+ power-domains = <&power RK3576_PD_VDEC>;
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+ resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>,
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+ <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>,
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+ <&cru SRST_RKVDEC_HEVC_CA>;
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+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ sram = <&rkvdec_sram>;
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+ };
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+
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+ vdec_mmu: iommu@27b00800 {
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+ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
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+ reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>;
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+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>;
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+ clock-names = "aclk", "iface";
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+ power-domains = <&power RK3576_PD_VDEC>;
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+ rockchip,disable-mmu-reset;
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+ #iommu-cells = <0>;
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+ };
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+
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vop: vop@27d00000 {
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compatible = "rockchip,rk3576-vop";
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reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
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@@ -2428,6 +2463,7 @@ sram: sram@3ff88000 {
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/* start address and size should be 4k align */
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rkvdec_sram: rkvdec-sram@0 {
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reg = <0x0 0x78000>;
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+ pool;
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};
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};
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--
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2.34.1
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