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53 lines
1.7 KiB
Diff
53 lines
1.7 KiB
Diff
From 5fed19731f3305ef99b80dc7f9d33f8f35918246 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Sat, 30 Jan 2021 18:27:30 +0100
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Subject: [PATCH 51/59] WIP/2000: ARM: dts: RK3288: add hevc node
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Signed-off-by: Alex Bee <knaerzche@gmail.com>
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---
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arch/arm/boot/dts/rockchip/rk3288.dtsi | 21 ++++++++++++++++++++-
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1 file changed, 20 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
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index 5f3e3cc8757c..64e9d757d712 100644
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--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
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@@ -1285,6 +1285,25 @@ vpu_mmu: iommu@ff9a0800 {
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power-domains = <&power RK3288_PD_VIDEO>;
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};
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+ hevc: hevc@ff9c0000 {
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+ compatible = "rockchip,rk3288-hevc";
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+ reg = <0x0 0xff9c0000 0x0 0x400>;
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+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "irq_dec";
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+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>,
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+ <&cru SCLK_HEVC_CORE>;
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+ clock-names = "axi", "ahb", "cabac", "core";
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+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
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+ <&cru SCLK_HEVC_CORE>,
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+ <&cru SCLK_HEVC_CABAC>;
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+ assigned-clock-rates = <400000000>, <100000000>,
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+ <300000000>, <300000000>;
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+ iommus = <&hevc_mmu>;
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+ power-domains = <&power RK3288_PD_HEVC>;
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+ resets = <&cru SRST_HEVC>;
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+ reset-names = "video_core";
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+ };
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+
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hevc_mmu: iommu@ff9c0440 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
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@@ -1292,7 +1311,7 @@ hevc_mmu: iommu@ff9c0440 {
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clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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- status = "disabled";
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+ power-domains = <&power RK3288_PD_HEVC>;
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};
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gpu: gpu@ffa30000 {
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--
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2.34.1
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