From 0845d9b5935ad8b3d450c2dfa62631c9c1df1bea Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Tue, 7 Mar 2023 21:21:57 -0800
Subject: [PATCH 4/4] PCI: imx: Provide a clock to the device for i.MX8MQ

When the internal PLL is configured as PCIe REF_CLK, we also have to
output a clock via CLK2_P/N pin to the connector/device to provide it.
Configure 100 MHz clock as its output.

Signed-off-by: Ryosuke Saito <rsaito@redhat.com>
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 841af6f55c7d..ac36c7035460 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -43,6 +43,11 @@ struct imx6_pcie {
 #define IMX8MQ_GPR_PCIE_VREG_BYPASS		BIT(12)
 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE	GENMASK(11, 8)
 #define IMX8MQ_PCIE2_BASE_ADDR			0x33c00000
+#define IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG	0x74
+#define IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK	GENMASK(3, 0)
+#define IMX8MQ_ANA_PLLOUT_MONITOR_CKE		BIT(4)
+#define IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG	0x7C
+#define IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK	GENMASK(2, 0)
 
 #define IMX95_PCIE_PHY_GEN_CTRL		0x0
 #define IMX95_PCIE_REF_USE_PAD			BIT(17)
@@ -370,6 +370,34 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 				   imx_pcie_grp_offset(imx_pcie),
 				   IMX8MQ_GPR_PCIE_REF_USE_PAD,
 				   IMX8MQ_GPR_PCIE_REF_USE_PAD);
+	} else {
+		/*
+		 * Use the internal PLL as REF clock and also
+		 * provide a clock to the device.
+		 */
+		struct regmap *anatop =
+			syscon_regmap_lookup_by_compatible("fsl,imx8mq-anatop");
+
+		if (IS_ERR(anatop)) {
+			dev_err(imx_pcie->pci->dev,
+				"Couldn't configure the internal PLL as REF clock\n");
+		} else {
+			/* Select SYSTEM_PLL1_CLK as the clock source */
+			regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG,
+					   IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK, 0xb);
+
+			/*
+			 * SYSTEM_PLL1_CLK is 800 MHz, so divided by 8
+			 * for generating 100 MHz as output.
+			 */
+			regmap_update_bits(anatop, IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG,
+					   IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK, 0x7);
+
+			/* Enable CLK2_P/N clock to provide it to the device */
+			regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG,
+					   IMX8MQ_ANA_PLLOUT_MONITOR_CKE,
+					   IMX8MQ_ANA_PLLOUT_MONITOR_CKE);
+		}
 	}
 	/*
 	 * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is
-- 
2.39.2

