From c789945d09e4c77eb30af1a8db1425cefab52080 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Fri, 28 Aug 2020 10:09:12 +0800
Subject: [PATCH 33/49] MLK-24601: drm: imx: mhdp: DP PHY support 1/2 lanes
 mode

All four lanes should be configurated for 1/2/4 lanes modes in driver.
The DP FW will power down unused PHY lanes after negotiation.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
 drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
index 5c75e7d40cc0..3d17840b0941 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
@@ -137,7 +137,7 @@ static void dp_aux_cfg(struct cdns_mhdp_device *mhdp)
 static void dp_phy_pma_cmn_cfg_24mhz(struct cdns_mhdp_device *mhdp)
 {
 	int k;
-	u32 num_lanes = mhdp->dp.num_lanes;
+	u32 num_lanes = 4;
 	u16 val;
 
 	val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1);
@@ -157,7 +157,7 @@ static void dp_phy_pma_cmn_cfg_24mhz(struct cdns_mhdp_device *mhdp)
 /* Valid for 24 MHz only */
 static void dp_phy_pma_cmn_pll0_24mhz(struct cdns_mhdp_device *mhdp)
 {
-	u32 num_lanes = mhdp->dp.num_lanes;
+	u32 num_lanes = 4;
 	u32 link_rate = mhdp->dp.rate;
 	u16 val;
 	int index, i, k;
@@ -228,7 +228,7 @@ static void dp_phy_pma_cmn_pll0_24mhz(struct cdns_mhdp_device *mhdp)
 /* PMA common configuration for 27MHz */
 static void dp_phy_pma_cmn_cfg_27mhz(struct cdns_mhdp_device *mhdp)
 {
-	u32 num_lanes = mhdp->dp.num_lanes;
+	u32 num_lanes = 4;
 	u16 val;
 	int k;
 
@@ -279,7 +279,7 @@ static void dp_phy_pma_cmn_cfg_27mhz(struct cdns_mhdp_device *mhdp)
 
 static void dp_phy_pma_cmn_pll0_27mhz(struct cdns_mhdp_device *mhdp)
 {
-	u32 num_lanes = mhdp->dp.num_lanes;
+	u32 num_lanes = 4;
 	u32 link_rate = mhdp->dp.rate;
 	u16 val;
 	int index, i, k;
-- 
2.29.2

